target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31
  32 #ifdef CONFIG_KVM_PARA
  33 #include <linux/kvm_para.h>
  34 #endif
  35 //
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
  66 static bool has_msr_async_pf_en;
  67 #endif
  68 static int lm_capable_kernel;
  69
  70 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  71 {
  72     struct kvm_cpuid2 *cpuid;
  73     int r, size;
  74
  75     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  76     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  77     cpuid->nent = max;
  78     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  79     if (r == 0 && cpuid->nent >= max) {
  80         r = -E2BIG;
  81     }
  82     if (r < 0) {
  83         if (r == -E2BIG) {
  84             qemu_free(cpuid);
  85             return NULL;
  86         } else {
  87             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  88                     strerror(-r));
  89             exit(1);
  90         }
  91     }
  92     return cpuid;
  93 }
  94
  95 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  96                                       uint32_t index, int reg)
  97 {
  98     struct kvm_cpuid2 *cpuid;
  99     int i, max;
 100     uint32_t ret = 0;
 101     uint32_t cpuid_1_edx;
 102
 103     max = 1;
 104     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 105         max *= 2;
 106     }
 107
 108     for (i = 0; i < cpuid->nent; ++i) {
 109         if (cpuid->entries[i].function == function &&
 110             cpuid->entries[i].index == index) {
 111             switch (reg) {
 112             case R_EAX:
 113                 ret = cpuid->entries[i].eax;
 114                 break;
 115             case R_EBX:
 116                 ret = cpuid->entries[i].ebx;
 117                 break;
 118             case R_ECX:
 119                 ret = cpuid->entries[i].ecx;
 120                 break;
 121             case R_EDX:
 122                 ret = cpuid->entries[i].edx;
 123                 switch (function) {
 124                 case 1:
 125                     /* KVM before 2.6.30 misreports the following features */
 126                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 127                     break;
 128                 case 0x80000001:
 129                     /* On Intel, kvm returns cpuid according to the Intel spec,
 130                      * so add missing bits according to the AMD spec:
 131                      */
 132                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 133                     ret |= cpuid_1_edx & 0x183f7ff;
 134                     break;
 135                 }
 136                 break;
 137             }
 138         }
 139     }
 140
 141     qemu_free(cpuid);
 142
 143     return ret;
 144 }
 145
 146 #ifdef CONFIG_KVM_PARA
 147 struct kvm_para_features {
 148     int cap;
 149     int feature;
 150 } para_features[] = {
 151     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 152     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 153     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 154 #ifdef KVM_CAP_ASYNC_PF
 155     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 156 #endif
 157     { -1, -1 }
 158 };
 159
 160 static int get_para_features(CPUState *env)
 161 {
 162     int i, features = 0;
 163
 164     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 165         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 166             features |= (1 << para_features[i].feature);
 167         }
 168     }
 169 #ifdef KVM_CAP_ASYNC_PF
 170     has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF);
 171 #endif
 172     return features;
 173 }
 174 #endif /* CONFIG_KVM_PARA */
 175
 176 typedef struct HWPoisonPage {
 177     ram_addr_t ram_addr;
 178     QLIST_ENTRY(HWPoisonPage) list;
 179 } HWPoisonPage;
 180
 181 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 182     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 183
 184 static void kvm_unpoison_all(void *param)
 185 {
 186     HWPoisonPage *page, *next_page;
 187
 188     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 189         QLIST_REMOVE(page, list);
 190         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 191         qemu_free(page);
 192     }
 193 }
 194
 195 #ifdef KVM_CAP_MCE
 196 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 197 {
 198     HWPoisonPage *page;
 199
 200     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 201         if (page->ram_addr == ram_addr) {
 202             return;
 203         }
 204     }
 205     page = qemu_malloc(sizeof(HWPoisonPage));
 206     page->ram_addr = ram_addr;
 207     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 208 }
 209
 210 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 211                                      int *max_banks)
 212 {
 213     int r;
 214
 215     r = kvm_check_extension(s, KVM_CAP_MCE);
 216     if (r > 0) {
 217         *max_banks = r;
 218         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 219     }
 220     return -ENOSYS;
 221 }
 222
 223 static void kvm_mce_inject(CPUState *env, target_phys_addr_t paddr, int code)
 224 {
 225     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 226                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 227     uint64_t mcg_status = MCG_STATUS_MCIP;
 228
 229     if (code == BUS_MCEERR_AR) {
 230         status |= MCI_STATUS_AR | 0x134;
 231         mcg_status |= MCG_STATUS_EIPV;
 232     } else {
 233         status |= 0xc0;
 234         mcg_status |= MCG_STATUS_RIPV;
 235     }
 236     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 237                        (MCM_ADDR_PHYS << 6) | 0xc,
 238                        cpu_x86_support_mca_broadcast(env) ?
 239                        MCE_INJECT_BROADCAST : 0);
 240 }
 241 #endif /* KVM_CAP_MCE */
 242
 243 static void hardware_memory_error(void)
 244 {
 245     fprintf(stderr, "Hardware memory error!\n");
 246     exit(1);
 247 }
 248
 249 int kvm_arch_on_sigbus_vcpu(CPUState *env, int code, void *addr)
 250 {
 251 #ifdef KVM_CAP_MCE
 252     ram_addr_t ram_addr;
 253     target_phys_addr_t paddr;
 254
 255     if ((env->mcg_cap & MCG_SER_P) && addr
 256         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 257         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 258             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr,
 259                                                &paddr)) {
 260             fprintf(stderr, "Hardware memory error for memory used by "
 261                     "QEMU itself instead of guest system!\n");
 262             /* Hope we are lucky for AO MCE */
 263             if (code == BUS_MCEERR_AO) {
 264                 return 0;
 265             } else {
 266                 hardware_memory_error();
 267             }
 268         }
 269         kvm_hwpoison_page_add(ram_addr);
 270         kvm_mce_inject(env, paddr, code);
 271     } else
 272 #endif /* KVM_CAP_MCE */
 273     {
 274         if (code == BUS_MCEERR_AO) {
 275             return 0;
 276         } else if (code == BUS_MCEERR_AR) {
 277             hardware_memory_error();
 278         } else {
 279             return 1;
 280         }
 281     }
 282     return 0;
 283 }
 284
 285 int kvm_arch_on_sigbus(int code, void *addr)
 286 {
 287 #ifdef KVM_CAP_MCE
 288     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 289         ram_addr_t ram_addr;
 290         target_phys_addr_t paddr;
 291
 292         /* Hope we are lucky for AO MCE */
 293         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 294             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr,
 295                                                &paddr)) {
 296             fprintf(stderr, "Hardware memory error for memory used by "
 297                     "QEMU itself instead of guest system!: %p\n", addr);
 298             return 0;
 299         }
 300         kvm_hwpoison_page_add(ram_addr);
 301         kvm_mce_inject(first_cpu, paddr, code);
 302     } else
 303 #endif /* KVM_CAP_MCE */
 304     {
 305         if (code == BUS_MCEERR_AO) {
 306             return 0;
 307         } else if (code == BUS_MCEERR_AR) {
 308             hardware_memory_error();
 309         } else {
 310             return 1;
 311         }
 312     }
 313     return 0;
 314 }
 315
 316 static int kvm_inject_mce_oldstyle(CPUState *env)
 317 {
 318 #ifdef KVM_CAP_MCE
 319     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 320         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 321         struct kvm_x86_mce mce;
 322
 323         env->exception_injected = -1;
 324
 325         /*
 326          * There must be at least one bank in use if an MCE is pending.
 327          * Find it and use its values for the event injection.
 328          */
 329         for (bank = 0; bank < bank_num; bank++) {
 330             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 331                 break;
 332             }
 333         }
 334         assert(bank < bank_num);
 335
 336         mce.bank = bank;
 337         mce.status = env->mce_banks[bank * 4 + 1];
 338         mce.mcg_status = env->mcg_status;
 339         mce.addr = env->mce_banks[bank * 4 + 2];
 340         mce.misc = env->mce_banks[bank * 4 + 3];
 341
 342         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 343     }
 344 #endif /* KVM_CAP_MCE */
 345     return 0;
 346 }
 347
 348 static void cpu_update_state(void *opaque, int running, int reason)
 349 {
 350     CPUState *env = opaque;
 351
 352     if (running) {
 353         env->tsc_valid = false;
 354     }
 355 }
 356
 357 int kvm_arch_init_vcpu(CPUState *env)
 358 {
 359     struct {
 360         struct kvm_cpuid2 cpuid;
 361         struct kvm_cpuid_entry2 entries[100];
 362     } __attribute__((packed)) cpuid_data;
 363     uint32_t limit, i, j, cpuid_i;
 364     uint32_t unused;
 365     struct kvm_cpuid_entry2 *c;
 366 #ifdef CONFIG_KVM_PARA
 367     uint32_t signature[3];
 368 #endif
 369
 370     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 371
 372     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 373     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 374     env->cpuid_ext_features |= i;
 375
 376     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 377                                                              0, R_EDX);
 378     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 379                                                              0, R_ECX);
 380     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 381                                                              0, R_EDX);
 382
 383
 384     cpuid_i = 0;
 385
 386 #ifdef CONFIG_KVM_PARA
 387     /* Paravirtualization CPUIDs */
 388     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 389     c = &cpuid_data.entries[cpuid_i++];
 390     memset(c, 0, sizeof(*c));
 391     c->function = KVM_CPUID_SIGNATURE;
 392     c->eax = 0;
 393     c->ebx = signature[0];
 394     c->ecx = signature[1];
 395     c->edx = signature[2];
 396
 397     c = &cpuid_data.entries[cpuid_i++];
 398     memset(c, 0, sizeof(*c));
 399     c->function = KVM_CPUID_FEATURES;
 400     c->eax = env->cpuid_kvm_features & get_para_features(env);
 401 #endif
 402
 403     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 404
 405     for (i = 0; i <= limit; i++) {
 406         c = &cpuid_data.entries[cpuid_i++];
 407
 408         switch (i) {
 409         case 2: {
 410             /* Keep reading function 2 till all the input is received */
 411             int times;
 412
 413             c->function = i;
 414             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 415                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 416             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 417             times = c->eax & 0xff;
 418
 419             for (j = 1; j < times; ++j) {
 420                 c = &cpuid_data.entries[cpuid_i++];
 421                 c->function = i;
 422                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 423                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 424             }
 425             break;
 426         }
 427         case 4:
 428         case 0xb:
 429         case 0xd:
 430             for (j = 0; ; j++) {
 431                 c->function = i;
 432                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 433                 c->index = j;
 434                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 435
 436                 if (i == 4 && c->eax == 0) {
 437                     break;
 438                 }
 439                 if (i == 0xb && !(c->ecx & 0xff00)) {
 440                     break;
 441                 }
 442                 if (i == 0xd && c->eax == 0) {
 443                     break;
 444                 }
 445                 c = &cpuid_data.entries[cpuid_i++];
 446             }
 447             break;
 448         default:
 449             c->function = i;
 450             c->flags = 0;
 451             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 452             break;
 453         }
 454     }
 455     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 456
 457     for (i = 0x80000000; i <= limit; i++) {
 458         c = &cpuid_data.entries[cpuid_i++];
 459
 460         c->function = i;
 461         c->flags = 0;
 462         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 463     }
 464
 465     cpuid_data.cpuid.nent = cpuid_i;
 466
 467 #ifdef KVM_CAP_MCE
 468     if (((env->cpuid_version >> 8)&0xF) >= 6
 469         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 470         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 471         uint64_t mcg_cap;
 472         int banks;
 473         int ret;
 474
 475         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 476         if (ret < 0) {
 477             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 478             return ret;
 479         }
 480
 481         if (banks > MCE_BANKS_DEF) {
 482             banks = MCE_BANKS_DEF;
 483         }
 484         mcg_cap &= MCE_CAP_DEF;
 485         mcg_cap |= banks;
 486         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 487         if (ret < 0) {
 488             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 489             return ret;
 490         }
 491
 492         env->mcg_cap = mcg_cap;
 493     }
 494 #endif
 495
 496     qemu_add_vm_change_state_handler(cpu_update_state, env);
 497
 498     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 499 }
 500
 501 void kvm_arch_reset_vcpu(CPUState *env)
 502 {
 503     env->exception_injected = -1;
 504     env->interrupt_injected = -1;
 505     env->xcr0 = 1;
 506     if (kvm_irqchip_in_kernel()) {
 507         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 508                                           KVM_MP_STATE_UNINITIALIZED;
 509     } else {
 510         env->mp_state = KVM_MP_STATE_RUNNABLE;
 511     }
 512 }
 513
 514 static int kvm_get_supported_msrs(KVMState *s)
 515 {
 516     static int kvm_supported_msrs;
 517     int ret = 0;
 518
 519     /* first time */
 520     if (kvm_supported_msrs == 0) {
 521         struct kvm_msr_list msr_list, *kvm_msr_list;
 522
 523         kvm_supported_msrs = -1;
 524
 525         /* Obtain MSR list from KVM.  These are the MSRs that we must
 526          * save/restore */
 527         msr_list.nmsrs = 0;
 528         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 529         if (ret < 0 && ret != -E2BIG) {
 530             return ret;
 531         }
 532         /* Old kernel modules had a bug and could write beyond the provided
 533            memory. Allocate at least a safe amount of 1K. */
 534         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 535                                               msr_list.nmsrs *
 536                                               sizeof(msr_list.indices[0])));
 537
 538         kvm_msr_list->nmsrs = msr_list.nmsrs;
 539         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 540         if (ret >= 0) {
 541             int i;
 542
 543             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 544                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 545                     has_msr_star = true;
 546                     continue;
 547                 }
 548                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 549                     has_msr_hsave_pa = true;
 550                     continue;
 551                 }
 552             }
 553         }
 554
 555         free(kvm_msr_list);
 556     }
 557
 558     return ret;
 559 }
 560
 561 int kvm_arch_init(KVMState *s)
 562 {
 563     uint64_t identity_base = 0xfffbc000;
 564     int ret;
 565     struct utsname utsname;
 566
 567     ret = kvm_get_supported_msrs(s);
 568     if (ret < 0) {
 569         return ret;
 570     }
 571
 572     uname(&utsname);
 573     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 574
 575     /*
 576      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 577      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 578      * Since these must be part of guest physical memory, we need to allocate
 579      * them, both by setting their start addresses in the kernel and by
 580      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 581      *
 582      * Older KVM versions may not support setting the identity map base. In
 583      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 584      * size.
 585      */
 586 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 587     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 588         /* Allows up to 16M BIOSes. */
 589         identity_base = 0xfeffc000;
 590
 591         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 592         if (ret < 0) {
 593             return ret;
 594         }
 595     }
 596 #endif
 597     /* Set TSS base one page after EPT identity map. */
 598     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 599     if (ret < 0) {
 600         return ret;
 601     }
 602
 603     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 604     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 605     if (ret < 0) {
 606         fprintf(stderr, "e820_add_entry() table is full\n");
 607         return ret;
 608     }
 609     qemu_register_reset(kvm_unpoison_all, NULL);
 610
 611     return 0;
 612 }
 613
 614 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 615 {
 616     lhs->selector = rhs->selector;
 617     lhs->base = rhs->base;
 618     lhs->limit = rhs->limit;
 619     lhs->type = 3;
 620     lhs->present = 1;
 621     lhs->dpl = 3;
 622     lhs->db = 0;
 623     lhs->s = 1;
 624     lhs->l = 0;
 625     lhs->g = 0;
 626     lhs->avl = 0;
 627     lhs->unusable = 0;
 628 }
 629
 630 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 631 {
 632     unsigned flags = rhs->flags;
 633     lhs->selector = rhs->selector;
 634     lhs->base = rhs->base;
 635     lhs->limit = rhs->limit;
 636     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 637     lhs->present = (flags & DESC_P_MASK) != 0;
 638     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 639     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 640     lhs->s = (flags & DESC_S_MASK) != 0;
 641     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 642     lhs->g = (flags & DESC_G_MASK) != 0;
 643     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 644     lhs->unusable = 0;
 645 }
 646
 647 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 648 {
 649     lhs->selector = rhs->selector;
 650     lhs->base = rhs->base;
 651     lhs->limit = rhs->limit;
 652     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 653                  (rhs->present * DESC_P_MASK) |
 654                  (rhs->dpl << DESC_DPL_SHIFT) |
 655                  (rhs->db << DESC_B_SHIFT) |
 656                  (rhs->s * DESC_S_MASK) |
 657                  (rhs->l << DESC_L_SHIFT) |
 658                  (rhs->g * DESC_G_MASK) |
 659                  (rhs->avl * DESC_AVL_MASK);
 660 }
 661
 662 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 663 {
 664     if (set) {
 665         *kvm_reg = *qemu_reg;
 666     } else {
 667         *qemu_reg = *kvm_reg;
 668     }
 669 }
 670
 671 static int kvm_getput_regs(CPUState *env, int set)
 672 {
 673     struct kvm_regs regs;
 674     int ret = 0;
 675
 676     if (!set) {
 677         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 678         if (ret < 0) {
 679             return ret;
 680         }
 681     }
 682
 683     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 684     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 685     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 686     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 687     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 688     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 689     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 690     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 691 #ifdef TARGET_X86_64
 692     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 693     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 694     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 695     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 696     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 697     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 698     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 699     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 700 #endif
 701
 702     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 703     kvm_getput_reg(&regs.rip, &env->eip, set);
 704
 705     if (set) {
 706         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 707     }
 708
 709     return ret;
 710 }
 711
 712 static int kvm_put_fpu(CPUState *env)
 713 {
 714     struct kvm_fpu fpu;
 715     int i;
 716
 717     memset(&fpu, 0, sizeof fpu);
 718     fpu.fsw = env->fpus & ~(7 << 11);
 719     fpu.fsw |= (env->fpstt & 7) << 11;
 720     fpu.fcw = env->fpuc;
 721     for (i = 0; i < 8; ++i) {
 722         fpu.ftwx |= (!env->fptags[i]) << i;
 723     }
 724     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 725     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 726     fpu.mxcsr = env->mxcsr;
 727
 728     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 729 }
 730
 731 #ifdef KVM_CAP_XSAVE
 732 #define XSAVE_CWD_RIP     2
 733 #define XSAVE_CWD_RDP     4
 734 #define XSAVE_MXCSR       6
 735 #define XSAVE_ST_SPACE    8
 736 #define XSAVE_XMM_SPACE   40
 737 #define XSAVE_XSTATE_BV   128
 738 #define XSAVE_YMMH_SPACE  144
 739 #endif
 740
 741 static int kvm_put_xsave(CPUState *env)
 742 {
 743 #ifdef KVM_CAP_XSAVE
 744     int i, r;
 745     struct kvm_xsave* xsave;
 746     uint16_t cwd, swd, twd, fop;
 747
 748     if (!kvm_has_xsave()) {
 749         return kvm_put_fpu(env);
 750     }
 751
 752     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 753     memset(xsave, 0, sizeof(struct kvm_xsave));
 754     cwd = swd = twd = fop = 0;
 755     swd = env->fpus & ~(7 << 11);
 756     swd |= (env->fpstt & 7) << 11;
 757     cwd = env->fpuc;
 758     for (i = 0; i < 8; ++i) {
 759         twd |= (!env->fptags[i]) << i;
 760     }
 761     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 762     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 763     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 764             sizeof env->fpregs);
 765     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 766             sizeof env->xmm_regs);
 767     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 768     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 769     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 770             sizeof env->ymmh_regs);
 771     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 772     qemu_free(xsave);
 773     return r;
 774 #else
 775     return kvm_put_fpu(env);
 776 #endif
 777 }
 778
 779 static int kvm_put_xcrs(CPUState *env)
 780 {
 781 #ifdef KVM_CAP_XCRS
 782     struct kvm_xcrs xcrs;
 783
 784     if (!kvm_has_xcrs()) {
 785         return 0;
 786     }
 787
 788     xcrs.nr_xcrs = 1;
 789     xcrs.flags = 0;
 790     xcrs.xcrs[0].xcr = 0;
 791     xcrs.xcrs[0].value = env->xcr0;
 792     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 793 #else
 794     return 0;
 795 #endif
 796 }
 797
 798 static int kvm_put_sregs(CPUState *env)
 799 {
 800     struct kvm_sregs sregs;
 801
 802     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 803     if (env->interrupt_injected >= 0) {
 804         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 805                 (uint64_t)1 << (env->interrupt_injected % 64);
 806     }
 807
 808     if ((env->eflags & VM_MASK)) {
 809         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 810         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 811         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 812         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 813         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 814         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 815     } else {
 816         set_seg(&sregs.cs, &env->segs[R_CS]);
 817         set_seg(&sregs.ds, &env->segs[R_DS]);
 818         set_seg(&sregs.es, &env->segs[R_ES]);
 819         set_seg(&sregs.fs, &env->segs[R_FS]);
 820         set_seg(&sregs.gs, &env->segs[R_GS]);
 821         set_seg(&sregs.ss, &env->segs[R_SS]);
 822     }
 823
 824     set_seg(&sregs.tr, &env->tr);
 825     set_seg(&sregs.ldt, &env->ldt);
 826
 827     sregs.idt.limit = env->idt.limit;
 828     sregs.idt.base = env->idt.base;
 829     sregs.gdt.limit = env->gdt.limit;
 830     sregs.gdt.base = env->gdt.base;
 831
 832     sregs.cr0 = env->cr[0];
 833     sregs.cr2 = env->cr[2];
 834     sregs.cr3 = env->cr[3];
 835     sregs.cr4 = env->cr[4];
 836
 837     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 838     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 839
 840     sregs.efer = env->efer;
 841
 842     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 843 }
 844
 845 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 846                               uint32_t index, uint64_t value)
 847 {
 848     entry->index = index;
 849     entry->data = value;
 850 }
 851
 852 static int kvm_put_msrs(CPUState *env, int level)
 853 {
 854     struct {
 855         struct kvm_msrs info;
 856         struct kvm_msr_entry entries[100];
 857     } msr_data;
 858     struct kvm_msr_entry *msrs = msr_data.entries;
 859     int n = 0;
 860
 861     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 862     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 863     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 864     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 865     if (has_msr_star) {
 866         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 867     }
 868     if (has_msr_hsave_pa) {
 869         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 870     }
 871 #ifdef TARGET_X86_64
 872     if (lm_capable_kernel) {
 873         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 874         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 875         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 876         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 877     }
 878 #endif
 879     if (level == KVM_PUT_FULL_STATE) {
 880         /*
 881          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 882          * writeback. Until this is fixed, we only write the offset to SMP
 883          * guests after migration, desynchronizing the VCPUs, but avoiding
 884          * huge jump-backs that would occur without any writeback at all.
 885          */
 886         if (smp_cpus == 1 || env->tsc != 0) {
 887             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 888         }
 889     }
 890     /*
 891      * The following paravirtual MSRs have side effects on the guest or are
 892      * too heavy for normal writeback. Limit them to reset or full state
 893      * updates.
 894      */
 895     if (level >= KVM_PUT_RESET_STATE) {
 896         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 897                           env->system_time_msr);
 898         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 899 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 900         if (has_msr_async_pf_en) {
 901             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 902                               env->async_pf_en_msr);
 903         }
 904 #endif
 905     }
 906 #ifdef KVM_CAP_MCE
 907     if (env->mcg_cap) {
 908         int i;
 909
 910         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 911         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 912         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 913             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 914         }
 915     }
 916 #endif
 917
 918     msr_data.info.nmsrs = n;
 919
 920     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 921
 922 }
 923
 924
 925 static int kvm_get_fpu(CPUState *env)
 926 {
 927     struct kvm_fpu fpu;
 928     int i, ret;
 929
 930     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 931     if (ret < 0) {
 932         return ret;
 933     }
 934
 935     env->fpstt = (fpu.fsw >> 11) & 7;
 936     env->fpus = fpu.fsw;
 937     env->fpuc = fpu.fcw;
 938     for (i = 0; i < 8; ++i) {
 939         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 940     }
 941     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 942     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 943     env->mxcsr = fpu.mxcsr;
 944
 945     return 0;
 946 }
 947
 948 static int kvm_get_xsave(CPUState *env)
 949 {
 950 #ifdef KVM_CAP_XSAVE
 951     struct kvm_xsave* xsave;
 952     int ret, i;
 953     uint16_t cwd, swd, twd, fop;
 954
 955     if (!kvm_has_xsave()) {
 956         return kvm_get_fpu(env);
 957     }
 958
 959     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 960     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 961     if (ret < 0) {
 962         qemu_free(xsave);
 963         return ret;
 964     }
 965
 966     cwd = (uint16_t)xsave->region[0];
 967     swd = (uint16_t)(xsave->region[0] >> 16);
 968     twd = (uint16_t)xsave->region[1];
 969     fop = (uint16_t)(xsave->region[1] >> 16);
 970     env->fpstt = (swd >> 11) & 7;
 971     env->fpus = swd;
 972     env->fpuc = cwd;
 973     for (i = 0; i < 8; ++i) {
 974         env->fptags[i] = !((twd >> i) & 1);
 975     }
 976     env->mxcsr = xsave->region[XSAVE_MXCSR];
 977     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 978             sizeof env->fpregs);
 979     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 980             sizeof env->xmm_regs);
 981     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 982     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 983             sizeof env->ymmh_regs);
 984     qemu_free(xsave);
 985     return 0;
 986 #else
 987     return kvm_get_fpu(env);
 988 #endif
 989 }
 990
 991 static int kvm_get_xcrs(CPUState *env)
 992 {
 993 #ifdef KVM_CAP_XCRS
 994     int i, ret;
 995     struct kvm_xcrs xcrs;
 996
 997     if (!kvm_has_xcrs()) {
 998         return 0;
 999     }
1000
1001     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1002     if (ret < 0) {
1003         return ret;
1004     }
1005
1006     for (i = 0; i < xcrs.nr_xcrs; i++) {
1007         /* Only support xcr0 now */
1008         if (xcrs.xcrs[0].xcr == 0) {
1009             env->xcr0 = xcrs.xcrs[0].value;
1010             break;
1011         }
1012     }
1013     return 0;
1014 #else
1015     return 0;
1016 #endif
1017 }
1018
1019 static int kvm_get_sregs(CPUState *env)
1020 {
1021     struct kvm_sregs sregs;
1022     uint32_t hflags;
1023     int bit, i, ret;
1024
1025     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1026     if (ret < 0) {
1027         return ret;
1028     }
1029
1030     /* There can only be one pending IRQ set in the bitmap at a time, so try
1031        to find it and save its number instead (-1 for none). */
1032     env->interrupt_injected = -1;
1033     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1034         if (sregs.interrupt_bitmap[i]) {
1035             bit = ctz64(sregs.interrupt_bitmap[i]);
1036             env->interrupt_injected = i * 64 + bit;
1037             break;
1038         }
1039     }
1040
1041     get_seg(&env->segs[R_CS], &sregs.cs);
1042     get_seg(&env->segs[R_DS], &sregs.ds);
1043     get_seg(&env->segs[R_ES], &sregs.es);
1044     get_seg(&env->segs[R_FS], &sregs.fs);
1045     get_seg(&env->segs[R_GS], &sregs.gs);
1046     get_seg(&env->segs[R_SS], &sregs.ss);
1047
1048     get_seg(&env->tr, &sregs.tr);
1049     get_seg(&env->ldt, &sregs.ldt);
1050
1051     env->idt.limit = sregs.idt.limit;
1052     env->idt.base = sregs.idt.base;
1053     env->gdt.limit = sregs.gdt.limit;
1054     env->gdt.base = sregs.gdt.base;
1055
1056     env->cr[0] = sregs.cr0;
1057     env->cr[2] = sregs.cr2;
1058     env->cr[3] = sregs.cr3;
1059     env->cr[4] = sregs.cr4;
1060
1061     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1062
1063     env->efer = sregs.efer;
1064     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1065
1066 #define HFLAG_COPY_MASK \
1067     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1068        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1069        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1070        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1071
1072     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1073     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1074     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1075                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1076     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1077     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1078                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1079
1080     if (env->efer & MSR_EFER_LMA) {
1081         hflags |= HF_LMA_MASK;
1082     }
1083
1084     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1085         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1086     } else {
1087         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1088                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1089         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1090                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1091         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1092             !(hflags & HF_CS32_MASK)) {
1093             hflags |= HF_ADDSEG_MASK;
1094         } else {
1095             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1096                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1097         }
1098     }
1099     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1100
1101     return 0;
1102 }
1103
1104 static int kvm_get_msrs(CPUState *env)
1105 {
1106     struct {
1107         struct kvm_msrs info;
1108         struct kvm_msr_entry entries[100];
1109     } msr_data;
1110     struct kvm_msr_entry *msrs = msr_data.entries;
1111     int ret, i, n;
1112
1113     n = 0;
1114     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1115     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1116     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1117     msrs[n++].index = MSR_PAT;
1118     if (has_msr_star) {
1119         msrs[n++].index = MSR_STAR;
1120     }
1121     if (has_msr_hsave_pa) {
1122         msrs[n++].index = MSR_VM_HSAVE_PA;
1123     }
1124
1125     if (!env->tsc_valid) {
1126         msrs[n++].index = MSR_IA32_TSC;
1127         env->tsc_valid = !vm_running;
1128     }
1129
1130 #ifdef TARGET_X86_64
1131     if (lm_capable_kernel) {
1132         msrs[n++].index = MSR_CSTAR;
1133         msrs[n++].index = MSR_KERNELGSBASE;
1134         msrs[n++].index = MSR_FMASK;
1135         msrs[n++].index = MSR_LSTAR;
1136     }
1137 #endif
1138     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1139     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1140 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1141     if (has_msr_async_pf_en) {
1142         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1143     }
1144 #endif
1145
1146 #ifdef KVM_CAP_MCE
1147     if (env->mcg_cap) {
1148         msrs[n++].index = MSR_MCG_STATUS;
1149         msrs[n++].index = MSR_MCG_CTL;
1150         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1151             msrs[n++].index = MSR_MC0_CTL + i;
1152         }
1153     }
1154 #endif
1155
1156     msr_data.info.nmsrs = n;
1157     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1158     if (ret < 0) {
1159         return ret;
1160     }
1161
1162     for (i = 0; i < ret; i++) {
1163         switch (msrs[i].index) {
1164         case MSR_IA32_SYSENTER_CS:
1165             env->sysenter_cs = msrs[i].data;
1166             break;
1167         case MSR_IA32_SYSENTER_ESP:
1168             env->sysenter_esp = msrs[i].data;
1169             break;
1170         case MSR_IA32_SYSENTER_EIP:
1171             env->sysenter_eip = msrs[i].data;
1172             break;
1173         case MSR_PAT:
1174             env->pat = msrs[i].data;
1175             break;
1176         case MSR_STAR:
1177             env->star = msrs[i].data;
1178             break;
1179 #ifdef TARGET_X86_64
1180         case MSR_CSTAR:
1181             env->cstar = msrs[i].data;
1182             break;
1183         case MSR_KERNELGSBASE:
1184             env->kernelgsbase = msrs[i].data;
1185             break;
1186         case MSR_FMASK:
1187             env->fmask = msrs[i].data;
1188             break;
1189         case MSR_LSTAR:
1190             env->lstar = msrs[i].data;
1191             break;
1192 #endif
1193         case MSR_IA32_TSC:
1194             env->tsc = msrs[i].data;
1195             break;
1196         case MSR_VM_HSAVE_PA:
1197             env->vm_hsave = msrs[i].data;
1198             break;
1199         case MSR_KVM_SYSTEM_TIME:
1200             env->system_time_msr = msrs[i].data;
1201             break;
1202         case MSR_KVM_WALL_CLOCK:
1203             env->wall_clock_msr = msrs[i].data;
1204             break;
1205 #ifdef KVM_CAP_MCE
1206         case MSR_MCG_STATUS:
1207             env->mcg_status = msrs[i].data;
1208             break;
1209         case MSR_MCG_CTL:
1210             env->mcg_ctl = msrs[i].data;
1211             break;
1212 #endif
1213         default:
1214 #ifdef KVM_CAP_MCE
1215             if (msrs[i].index >= MSR_MC0_CTL &&
1216                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1217                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1218             }
1219 #endif
1220             break;
1221 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1222         case MSR_KVM_ASYNC_PF_EN:
1223             env->async_pf_en_msr = msrs[i].data;
1224             break;
1225 #endif
1226         }
1227     }
1228
1229     return 0;
1230 }
1231
1232 static int kvm_put_mp_state(CPUState *env)
1233 {
1234     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1235
1236     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1237 }
1238
1239 static int kvm_get_mp_state(CPUState *env)
1240 {
1241     struct kvm_mp_state mp_state;
1242     int ret;
1243
1244     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1245     if (ret < 0) {
1246         return ret;
1247     }
1248     env->mp_state = mp_state.mp_state;
1249     if (kvm_irqchip_in_kernel()) {
1250         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1251     }
1252     return 0;
1253 }
1254
1255 static int kvm_put_vcpu_events(CPUState *env, int level)
1256 {
1257 #ifdef KVM_CAP_VCPU_EVENTS
1258     struct kvm_vcpu_events events;
1259
1260     if (!kvm_has_vcpu_events()) {
1261         return 0;
1262     }
1263
1264     events.exception.injected = (env->exception_injected >= 0);
1265     events.exception.nr = env->exception_injected;
1266     events.exception.has_error_code = env->has_error_code;
1267     events.exception.error_code = env->error_code;
1268
1269     events.interrupt.injected = (env->interrupt_injected >= 0);
1270     events.interrupt.nr = env->interrupt_injected;
1271     events.interrupt.soft = env->soft_interrupt;
1272
1273     events.nmi.injected = env->nmi_injected;
1274     events.nmi.pending = env->nmi_pending;
1275     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1276
1277     events.sipi_vector = env->sipi_vector;
1278
1279     events.flags = 0;
1280     if (level >= KVM_PUT_RESET_STATE) {
1281         events.flags |=
1282             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1283     }
1284
1285     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1286 #else
1287     return 0;
1288 #endif
1289 }
1290
1291 static int kvm_get_vcpu_events(CPUState *env)
1292 {
1293 #ifdef KVM_CAP_VCPU_EVENTS
1294     struct kvm_vcpu_events events;
1295     int ret;
1296
1297     if (!kvm_has_vcpu_events()) {
1298         return 0;
1299     }
1300
1301     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1302     if (ret < 0) {
1303        return ret;
1304     }
1305     env->exception_injected =
1306        events.exception.injected ? events.exception.nr : -1;
1307     env->has_error_code = events.exception.has_error_code;
1308     env->error_code = events.exception.error_code;
1309
1310     env->interrupt_injected =
1311         events.interrupt.injected ? events.interrupt.nr : -1;
1312     env->soft_interrupt = events.interrupt.soft;
1313
1314     env->nmi_injected = events.nmi.injected;
1315     env->nmi_pending = events.nmi.pending;
1316     if (events.nmi.masked) {
1317         env->hflags2 |= HF2_NMI_MASK;
1318     } else {
1319         env->hflags2 &= ~HF2_NMI_MASK;
1320     }
1321
1322     env->sipi_vector = events.sipi_vector;
1323 #endif
1324
1325     return 0;
1326 }
1327
1328 static int kvm_guest_debug_workarounds(CPUState *env)
1329 {
1330     int ret = 0;
1331 #ifdef KVM_CAP_SET_GUEST_DEBUG
1332     unsigned long reinject_trap = 0;
1333
1334     if (!kvm_has_vcpu_events()) {
1335         if (env->exception_injected == 1) {
1336             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1337         } else if (env->exception_injected == 3) {
1338             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1339         }
1340         env->exception_injected = -1;
1341     }
1342
1343     /*
1344      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1345      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1346      * by updating the debug state once again if single-stepping is on.
1347      * Another reason to call kvm_update_guest_debug here is a pending debug
1348      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1349      * reinject them via SET_GUEST_DEBUG.
1350      */
1351     if (reinject_trap ||
1352         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1353         ret = kvm_update_guest_debug(env, reinject_trap);
1354     }
1355 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1356     return ret;
1357 }
1358
1359 static int kvm_put_debugregs(CPUState *env)
1360 {
1361 #ifdef KVM_CAP_DEBUGREGS
1362     struct kvm_debugregs dbgregs;
1363     int i;
1364
1365     if (!kvm_has_debugregs()) {
1366         return 0;
1367     }
1368
1369     for (i = 0; i < 4; i++) {
1370         dbgregs.db[i] = env->dr[i];
1371     }
1372     dbgregs.dr6 = env->dr[6];
1373     dbgregs.dr7 = env->dr[7];
1374     dbgregs.flags = 0;
1375
1376     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1377 #else
1378     return 0;
1379 #endif
1380 }
1381
1382 static int kvm_get_debugregs(CPUState *env)
1383 {
1384 #ifdef KVM_CAP_DEBUGREGS
1385     struct kvm_debugregs dbgregs;
1386     int i, ret;
1387
1388     if (!kvm_has_debugregs()) {
1389         return 0;
1390     }
1391
1392     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1393     if (ret < 0) {
1394         return ret;
1395     }
1396     for (i = 0; i < 4; i++) {
1397         env->dr[i] = dbgregs.db[i];
1398     }
1399     env->dr[4] = env->dr[6] = dbgregs.dr6;
1400     env->dr[5] = env->dr[7] = dbgregs.dr7;
1401 #endif
1402
1403     return 0;
1404 }
1405
1406 int kvm_arch_put_registers(CPUState *env, int level)
1407 {
1408     int ret;
1409
1410     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1411
1412     ret = kvm_getput_regs(env, 1);
1413     if (ret < 0) {
1414         return ret;
1415     }
1416     ret = kvm_put_xsave(env);
1417     if (ret < 0) {
1418         return ret;
1419     }
1420     ret = kvm_put_xcrs(env);
1421     if (ret < 0) {
1422         return ret;
1423     }
1424     ret = kvm_put_sregs(env);
1425     if (ret < 0) {
1426         return ret;
1427     }
1428     /* must be before kvm_put_msrs */
1429     ret = kvm_inject_mce_oldstyle(env);
1430     if (ret < 0) {
1431         return ret;
1432     }
1433     ret = kvm_put_msrs(env, level);
1434     if (ret < 0) {
1435         return ret;
1436     }
1437     if (level >= KVM_PUT_RESET_STATE) {
1438         ret = kvm_put_mp_state(env);
1439         if (ret < 0) {
1440             return ret;
1441         }
1442     }
1443     ret = kvm_put_vcpu_events(env, level);
1444     if (ret < 0) {
1445         return ret;
1446     }
1447     ret = kvm_put_debugregs(env);
1448     if (ret < 0) {
1449         return ret;
1450     }
1451     /* must be last */
1452     ret = kvm_guest_debug_workarounds(env);
1453     if (ret < 0) {
1454         return ret;
1455     }
1456     return 0;
1457 }
1458
1459 int kvm_arch_get_registers(CPUState *env)
1460 {
1461     int ret;
1462
1463     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1464
1465     ret = kvm_getput_regs(env, 0);
1466     if (ret < 0) {
1467         return ret;
1468     }
1469     ret = kvm_get_xsave(env);
1470     if (ret < 0) {
1471         return ret;
1472     }
1473     ret = kvm_get_xcrs(env);
1474     if (ret < 0) {
1475         return ret;
1476     }
1477     ret = kvm_get_sregs(env);
1478     if (ret < 0) {
1479         return ret;
1480     }
1481     ret = kvm_get_msrs(env);
1482     if (ret < 0) {
1483         return ret;
1484     }
1485     ret = kvm_get_mp_state(env);
1486     if (ret < 0) {
1487         return ret;
1488     }
1489     ret = kvm_get_vcpu_events(env);
1490     if (ret < 0) {
1491         return ret;
1492     }
1493     ret = kvm_get_debugregs(env);
1494     if (ret < 0) {
1495         return ret;
1496     }
1497     return 0;
1498 }
1499
1500 void kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1501 {
1502     int ret;
1503
1504     /* Inject NMI */
1505     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1506         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1507         DPRINTF("injected NMI\n");
1508         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1509         if (ret < 0) {
1510             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1511                     strerror(-ret));
1512         }
1513     }
1514
1515     if (!kvm_irqchip_in_kernel()) {
1516         /* Force the VCPU out of its inner loop to process the INIT request */
1517         if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1518             env->exit_request = 1;
1519         }
1520
1521         /* Try to inject an interrupt if the guest can accept it */
1522         if (run->ready_for_interrupt_injection &&
1523             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1524             (env->eflags & IF_MASK)) {
1525             int irq;
1526
1527             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1528             irq = cpu_get_pic_interrupt(env);
1529             if (irq >= 0) {
1530                 struct kvm_interrupt intr;
1531
1532                 intr.irq = irq;
1533                 DPRINTF("injected interrupt %d\n", irq);
1534                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1535                 if (ret < 0) {
1536                     fprintf(stderr,
1537                             "KVM: injection failed, interrupt lost (%s)\n",
1538                             strerror(-ret));
1539                 }
1540             }
1541         }
1542
1543         /* If we have an interrupt but the guest is not ready to receive an
1544          * interrupt, request an interrupt window exit.  This will
1545          * cause a return to userspace as soon as the guest is ready to
1546          * receive interrupts. */
1547         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1548             run->request_interrupt_window = 1;
1549         } else {
1550             run->request_interrupt_window = 0;
1551         }
1552
1553         DPRINTF("setting tpr\n");
1554         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1555     }
1556 }
1557
1558 void kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1559 {
1560     if (run->if_flag) {
1561         env->eflags |= IF_MASK;
1562     } else {
1563         env->eflags &= ~IF_MASK;
1564     }
1565     cpu_set_apic_tpr(env->apic_state, run->cr8);
1566     cpu_set_apic_base(env->apic_state, run->apic_base);
1567 }
1568
1569 int kvm_arch_process_async_events(CPUState *env)
1570 {
1571     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1572         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1573         assert(env->mcg_cap);
1574
1575         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1576
1577         kvm_cpu_synchronize_state(env);
1578
1579         if (env->exception_injected == EXCP08_DBLE) {
1580             /* this means triple fault */
1581             qemu_system_reset_request();
1582             env->exit_request = 1;
1583             return 0;
1584         }
1585         env->exception_injected = EXCP12_MCHK;
1586         env->has_error_code = 0;
1587
1588         env->halted = 0;
1589         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1590             env->mp_state = KVM_MP_STATE_RUNNABLE;
1591         }
1592     }
1593
1594     if (kvm_irqchip_in_kernel()) {
1595         return 0;
1596     }
1597
1598     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1599          (env->eflags & IF_MASK)) ||
1600         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1601         env->halted = 0;
1602     }
1603     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1604         kvm_cpu_synchronize_state(env);
1605         do_cpu_init(env);
1606     }
1607     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1608         kvm_cpu_synchronize_state(env);
1609         do_cpu_sipi(env);
1610     }
1611
1612     return env->halted;
1613 }
1614
1615 static int kvm_handle_halt(CPUState *env)
1616 {
1617     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1618           (env->eflags & IF_MASK)) &&
1619         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1620         env->halted = 1;
1621         return 0;
1622     }
1623
1624     return 1;
1625 }
1626
1627 static bool host_supports_vmx(void)
1628 {
1629     uint32_t ecx, unused;
1630
1631     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1632     return ecx & CPUID_EXT_VMX;
1633 }
1634
1635 #define VMX_INVALID_GUEST_STATE 0x80000021
1636
1637 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1638 {
1639     uint64_t code;
1640     int ret = 0;
1641
1642     switch (run->exit_reason) {
1643     case KVM_EXIT_HLT:
1644         DPRINTF("handle_hlt\n");
1645         ret = kvm_handle_halt(env);
1646         break;
1647     case KVM_EXIT_SET_TPR:
1648         ret = 1;
1649         break;
1650     case KVM_EXIT_FAIL_ENTRY:
1651         code = run->fail_entry.hardware_entry_failure_reason;
1652         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1653                 code);
1654         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1655             fprintf(stderr,
1656                     "\nIf you're runnning a guest on an Intel machine without "
1657                         "unrestricted mode\n"
1658                     "support, the failure can be most likely due to the guest "
1659                         "entering an invalid\n"
1660                     "state for Intel VT. For example, the guest maybe running "
1661                         "in big real mode\n"
1662                     "which is not supported on less recent Intel processors."
1663                         "\n\n");
1664         }
1665         ret = -1;
1666         break;
1667     case KVM_EXIT_EXCEPTION:
1668         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1669                 run->ex.exception, run->ex.error_code);
1670         ret = -1;
1671         break;
1672     default:
1673         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1674         ret = -1;
1675         break;
1676     }
1677
1678     return ret;
1679 }
1680
1681 #ifdef KVM_CAP_SET_GUEST_DEBUG
1682 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1683 {
1684     static const uint8_t int3 = 0xcc;
1685
1686     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1687         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1688         return -EINVAL;
1689     }
1690     return 0;
1691 }
1692
1693 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1694 {
1695     uint8_t int3;
1696
1697     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1698         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1699         return -EINVAL;
1700     }
1701     return 0;
1702 }
1703
1704 static struct {
1705     target_ulong addr;
1706     int len;
1707     int type;
1708 } hw_breakpoint[4];
1709
1710 static int nb_hw_breakpoint;
1711
1712 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1713 {
1714     int n;
1715
1716     for (n = 0; n < nb_hw_breakpoint; n++) {
1717         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1718             (hw_breakpoint[n].len == len || len == -1)) {
1719             return n;
1720         }
1721     }
1722     return -1;
1723 }
1724
1725 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1726                                   target_ulong len, int type)
1727 {
1728     switch (type) {
1729     case GDB_BREAKPOINT_HW:
1730         len = 1;
1731         break;
1732     case GDB_WATCHPOINT_WRITE:
1733     case GDB_WATCHPOINT_ACCESS:
1734         switch (len) {
1735         case 1:
1736             break;
1737         case 2:
1738         case 4:
1739         case 8:
1740             if (addr & (len - 1)) {
1741                 return -EINVAL;
1742             }
1743             break;
1744         default:
1745             return -EINVAL;
1746         }
1747         break;
1748     default:
1749         return -ENOSYS;
1750     }
1751
1752     if (nb_hw_breakpoint == 4) {
1753         return -ENOBUFS;
1754     }
1755     if (find_hw_breakpoint(addr, len, type) >= 0) {
1756         return -EEXIST;
1757     }
1758     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1759     hw_breakpoint[nb_hw_breakpoint].len = len;
1760     hw_breakpoint[nb_hw_breakpoint].type = type;
1761     nb_hw_breakpoint++;
1762
1763     return 0;
1764 }
1765
1766 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1767                                   target_ulong len, int type)
1768 {
1769     int n;
1770
1771     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1772     if (n < 0) {
1773         return -ENOENT;
1774     }
1775     nb_hw_breakpoint--;
1776     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1777
1778     return 0;
1779 }
1780
1781 void kvm_arch_remove_all_hw_breakpoints(void)
1782 {
1783     nb_hw_breakpoint = 0;
1784 }
1785
1786 static CPUWatchpoint hw_watchpoint;
1787
1788 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1789 {
1790     int handle = 0;
1791     int n;
1792
1793     if (arch_info->exception == 1) {
1794         if (arch_info->dr6 & (1 << 14)) {
1795             if (cpu_single_env->singlestep_enabled) {
1796                 handle = 1;
1797             }
1798         } else {
1799             for (n = 0; n < 4; n++) {
1800                 if (arch_info->dr6 & (1 << n)) {
1801                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1802                     case 0x0:
1803                         handle = 1;
1804                         break;
1805                     case 0x1:
1806                         handle = 1;
1807                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1808                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1809                         hw_watchpoint.flags = BP_MEM_WRITE;
1810                         break;
1811                     case 0x3:
1812                         handle = 1;
1813                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1814                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1815                         hw_watchpoint.flags = BP_MEM_ACCESS;
1816                         break;
1817                     }
1818                 }
1819             }
1820         }
1821     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1822         handle = 1;
1823     }
1824     if (!handle) {
1825         cpu_synchronize_state(cpu_single_env);
1826         assert(cpu_single_env->exception_injected == -1);
1827
1828         cpu_single_env->exception_injected = arch_info->exception;
1829         cpu_single_env->has_error_code = 0;
1830     }
1831
1832     return handle;
1833 }
1834
1835 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1836 {
1837     const uint8_t type_code[] = {
1838         [GDB_BREAKPOINT_HW] = 0x0,
1839         [GDB_WATCHPOINT_WRITE] = 0x1,
1840         [GDB_WATCHPOINT_ACCESS] = 0x3
1841     };
1842     const uint8_t len_code[] = {
1843         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1844     };
1845     int n;
1846
1847     if (kvm_sw_breakpoints_active(env)) {
1848         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1849     }
1850     if (nb_hw_breakpoint > 0) {
1851         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1852         dbg->arch.debugreg[7] = 0x0600;
1853         for (n = 0; n < nb_hw_breakpoint; n++) {
1854             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1855             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1856                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1857                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1858         }
1859     }
1860 }
1861 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1862
1863 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1864 {
1865     return !(env->cr[0] & CR0_PE_MASK) ||
1866            ((env->segs[R_CS].selector  & 3) != 3);
1867 }