4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
19 #include <linux/kvm.h>
21 #include "qemu-common.h"
26 #include "host-utils.h"
31 #ifdef CONFIG_KVM_PARA
32 #include <linux/kvm_para.h>
38 #define DPRINTF(fmt, ...) \
39 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
41 #define DPRINTF(fmt, ...) \
45 #define MSR_KVM_WALL_CLOCK 0x11
46 #define MSR_KVM_SYSTEM_TIME 0x12
48 #ifdef KVM_CAP_EXT_CPUID
50 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
52 struct kvm_cpuid2
*cpuid
;
55 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
56 cpuid
= (struct kvm_cpuid2
*)qemu_mallocz(size
);
58 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
59 if (r
== 0 && cpuid
->nent
>= max
) {
67 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
75 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
76 uint32_t index
, int reg
)
78 struct kvm_cpuid2
*cpuid
;
83 if (!kvm_check_extension(env
->kvm_state
, KVM_CAP_EXT_CPUID
)) {
88 while ((cpuid
= try_get_cpuid(env
->kvm_state
, max
)) == NULL
) {
92 for (i
= 0; i
< cpuid
->nent
; ++i
) {
93 if (cpuid
->entries
[i
].function
== function
&&
94 cpuid
->entries
[i
].index
== index
) {
97 ret
= cpuid
->entries
[i
].eax
;
100 ret
= cpuid
->entries
[i
].ebx
;
103 ret
= cpuid
->entries
[i
].ecx
;
106 ret
= cpuid
->entries
[i
].edx
;
109 /* KVM before 2.6.30 misreports the following features */
110 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
113 /* On Intel, kvm returns cpuid according to the Intel spec,
114 * so add missing bits according to the AMD spec:
116 cpuid_1_edx
= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
117 ret
|= cpuid_1_edx
& 0x183f7ff;
132 uint32_t kvm_arch_get_supported_cpuid(CPUState
*env
, uint32_t function
,
133 uint32_t index
, int reg
)
140 #ifdef CONFIG_KVM_PARA
141 struct kvm_para_features
{
144 } para_features
[] = {
145 #ifdef KVM_CAP_CLOCKSOURCE
146 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
148 #ifdef KVM_CAP_NOP_IO_DELAY
149 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
151 #ifdef KVM_CAP_PV_MMU
152 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
157 static int get_para_features(CPUState
*env
)
161 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
162 if (kvm_check_extension(env
->kvm_state
, para_features
[i
].cap
))
163 features
|= (1 << para_features
[i
].feature
);
170 int kvm_arch_init_vcpu(CPUState
*env
)
173 struct kvm_cpuid2 cpuid
;
174 struct kvm_cpuid_entry2 entries
[100];
175 } __attribute__((packed
)) cpuid_data
;
176 uint32_t limit
, i
, j
, cpuid_i
;
178 struct kvm_cpuid_entry2
*c
;
179 #ifdef KVM_CPUID_SIGNATURE
180 uint32_t signature
[3];
183 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
185 env
->cpuid_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_EDX
);
187 i
= env
->cpuid_ext_features
& CPUID_EXT_HYPERVISOR
;
188 env
->cpuid_ext_features
&= kvm_arch_get_supported_cpuid(env
, 1, 0, R_ECX
);
189 env
->cpuid_ext_features
|= i
;
191 env
->cpuid_ext2_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
193 env
->cpuid_ext3_features
&= kvm_arch_get_supported_cpuid(env
, 0x80000001,
195 env
->cpuid_svm_features
&= kvm_arch_get_supported_cpuid(env
, 0x8000000A,
201 #ifdef CONFIG_KVM_PARA
202 /* Paravirtualization CPUIDs */
203 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
204 c
= &cpuid_data
.entries
[cpuid_i
++];
205 memset(c
, 0, sizeof(*c
));
206 c
->function
= KVM_CPUID_SIGNATURE
;
208 c
->ebx
= signature
[0];
209 c
->ecx
= signature
[1];
210 c
->edx
= signature
[2];
212 c
= &cpuid_data
.entries
[cpuid_i
++];
213 memset(c
, 0, sizeof(*c
));
214 c
->function
= KVM_CPUID_FEATURES
;
215 c
->eax
= env
->cpuid_kvm_features
& get_para_features(env
);
218 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
220 for (i
= 0; i
<= limit
; i
++) {
221 c
= &cpuid_data
.entries
[cpuid_i
++];
225 /* Keep reading function 2 till all the input is received */
229 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
230 KVM_CPUID_FLAG_STATE_READ_NEXT
;
231 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
232 times
= c
->eax
& 0xff;
234 for (j
= 1; j
< times
; ++j
) {
235 c
= &cpuid_data
.entries
[cpuid_i
++];
237 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
238 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
247 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
249 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
251 if (i
== 4 && c
->eax
== 0)
253 if (i
== 0xb && !(c
->ecx
& 0xff00))
255 if (i
== 0xd && c
->eax
== 0)
258 c
= &cpuid_data
.entries
[cpuid_i
++];
264 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
268 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
270 for (i
= 0x80000000; i
<= limit
; i
++) {
271 c
= &cpuid_data
.entries
[cpuid_i
++];
275 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
278 cpuid_data
.cpuid
.nent
= cpuid_i
;
280 return kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
283 void kvm_arch_reset_vcpu(CPUState
*env
)
285 env
->exception_injected
= -1;
286 env
->interrupt_injected
= -1;
287 env
->nmi_injected
= 0;
288 env
->nmi_pending
= 0;
289 if (kvm_irqchip_in_kernel()) {
290 env
->mp_state
= cpu_is_bsp(env
) ? KVM_MP_STATE_RUNNABLE
:
291 KVM_MP_STATE_UNINITIALIZED
;
293 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
297 static int kvm_has_msr_star(CPUState
*env
)
299 static int has_msr_star
;
303 if (has_msr_star
== 0) {
304 struct kvm_msr_list msr_list
, *kvm_msr_list
;
308 /* Obtain MSR list from KVM. These are the MSRs that we must
311 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
312 if (ret
< 0 && ret
!= -E2BIG
) {
315 /* Old kernel modules had a bug and could write beyond the provided
316 memory. Allocate at least a safe amount of 1K. */
317 kvm_msr_list
= qemu_mallocz(MAX(1024, sizeof(msr_list
) +
319 sizeof(msr_list
.indices
[0])));
321 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
322 ret
= kvm_ioctl(env
->kvm_state
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
326 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
327 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
337 if (has_msr_star
== 1)
342 static int kvm_init_identity_map_page(KVMState
*s
)
344 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
346 uint64_t addr
= 0xfffbc000;
348 if (!kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
352 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &addr
);
354 fprintf(stderr
, "kvm_set_identity_map_addr: %s\n", strerror(ret
));
361 int kvm_arch_init(KVMState
*s
, int smp_cpus
)
365 /* create vm86 tss. KVM uses vm86 mode to emulate 16-bit code
366 * directly. In order to use vm86 mode, a TSS is needed. Since this
367 * must be part of guest physical memory, we need to allocate it. Older
368 * versions of KVM just assumed that it would be at the end of physical
369 * memory but that doesn't work with more than 4GB of memory. We simply
370 * refuse to work with those older versions of KVM. */
371 ret
= kvm_ioctl(s
, KVM_CHECK_EXTENSION
, KVM_CAP_SET_TSS_ADDR
);
373 fprintf(stderr
, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
377 /* this address is 3 pages before the bios, and the bios should present
378 * as unavaible memory. FIXME, need to ensure the e820 map deals with
382 * Tell fw_cfg to notify the BIOS to reserve the range.
384 if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED
) < 0) {
385 perror("e820_add_entry() table is full");
388 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, 0xfffbd000);
393 return kvm_init_identity_map_page(s
);
396 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
398 lhs
->selector
= rhs
->selector
;
399 lhs
->base
= rhs
->base
;
400 lhs
->limit
= rhs
->limit
;
412 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
414 unsigned flags
= rhs
->flags
;
415 lhs
->selector
= rhs
->selector
;
416 lhs
->base
= rhs
->base
;
417 lhs
->limit
= rhs
->limit
;
418 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
419 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
420 lhs
->dpl
= rhs
->selector
& 3;
421 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
422 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
423 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
424 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
425 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
429 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
431 lhs
->selector
= rhs
->selector
;
432 lhs
->base
= rhs
->base
;
433 lhs
->limit
= rhs
->limit
;
435 (rhs
->type
<< DESC_TYPE_SHIFT
)
436 | (rhs
->present
* DESC_P_MASK
)
437 | (rhs
->dpl
<< DESC_DPL_SHIFT
)
438 | (rhs
->db
<< DESC_B_SHIFT
)
439 | (rhs
->s
* DESC_S_MASK
)
440 | (rhs
->l
<< DESC_L_SHIFT
)
441 | (rhs
->g
* DESC_G_MASK
)
442 | (rhs
->avl
* DESC_AVL_MASK
);
445 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
448 *kvm_reg
= *qemu_reg
;
450 *qemu_reg
= *kvm_reg
;
453 static int kvm_getput_regs(CPUState
*env
, int set
)
455 struct kvm_regs regs
;
459 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
464 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
465 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
466 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
467 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
468 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
469 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
470 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
471 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
473 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
474 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
475 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
476 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
477 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
478 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
479 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
480 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
483 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
484 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
487 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
492 static int kvm_put_fpu(CPUState
*env
)
497 memset(&fpu
, 0, sizeof fpu
);
498 fpu
.fsw
= env
->fpus
& ~(7 << 11);
499 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
501 for (i
= 0; i
< 8; ++i
)
502 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
503 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
504 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
505 fpu
.mxcsr
= env
->mxcsr
;
507 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
511 #define XSAVE_CWD_RIP 2
512 #define XSAVE_CWD_RDP 4
513 #define XSAVE_MXCSR 6
514 #define XSAVE_ST_SPACE 8
515 #define XSAVE_XMM_SPACE 40
516 #define XSAVE_XSTATE_BV 128
517 #define XSAVE_YMMH_SPACE 144
520 static int kvm_put_xsave(CPUState
*env
)
524 struct kvm_xsave
* xsave
;
525 uint16_t cwd
, swd
, twd
, fop
;
527 if (!kvm_has_xsave())
528 return kvm_put_fpu(env
);
530 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
531 memset(xsave
, 0, sizeof(struct kvm_xsave
));
532 cwd
= swd
= twd
= fop
= 0;
533 swd
= env
->fpus
& ~(7 << 11);
534 swd
|= (env
->fpstt
& 7) << 11;
536 for (i
= 0; i
< 8; ++i
)
537 twd
|= (!env
->fptags
[i
]) << i
;
538 xsave
->region
[0] = (uint32_t)(swd
<< 16) + cwd
;
539 xsave
->region
[1] = (uint32_t)(fop
<< 16) + twd
;
540 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
542 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
543 sizeof env
->xmm_regs
);
544 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
545 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
546 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
547 sizeof env
->ymmh_regs
);
548 return kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
550 return kvm_put_fpu(env
);
554 static int kvm_put_xcrs(CPUState
*env
)
557 struct kvm_xcrs xcrs
;
564 xcrs
.xcrs
[0].xcr
= 0;
565 xcrs
.xcrs
[0].value
= env
->xcr0
;
566 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
572 static int kvm_put_sregs(CPUState
*env
)
574 struct kvm_sregs sregs
;
576 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
577 if (env
->interrupt_injected
>= 0) {
578 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
579 (uint64_t)1 << (env
->interrupt_injected
% 64);
582 if ((env
->eflags
& VM_MASK
)) {
583 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
584 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
585 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
586 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
587 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
588 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
590 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
591 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
592 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
593 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
594 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
595 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
597 if (env
->cr
[0] & CR0_PE_MASK
) {
598 /* force ss cpl to cs cpl */
599 sregs
.ss
.selector
= (sregs
.ss
.selector
& ~3) |
600 (sregs
.cs
.selector
& 3);
601 sregs
.ss
.dpl
= sregs
.ss
.selector
& 3;
605 set_seg(&sregs
.tr
, &env
->tr
);
606 set_seg(&sregs
.ldt
, &env
->ldt
);
608 sregs
.idt
.limit
= env
->idt
.limit
;
609 sregs
.idt
.base
= env
->idt
.base
;
610 sregs
.gdt
.limit
= env
->gdt
.limit
;
611 sregs
.gdt
.base
= env
->gdt
.base
;
613 sregs
.cr0
= env
->cr
[0];
614 sregs
.cr2
= env
->cr
[2];
615 sregs
.cr3
= env
->cr
[3];
616 sregs
.cr4
= env
->cr
[4];
618 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
619 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
621 sregs
.efer
= env
->efer
;
623 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
626 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
627 uint32_t index
, uint64_t value
)
629 entry
->index
= index
;
633 static int kvm_put_msrs(CPUState
*env
, int level
)
636 struct kvm_msrs info
;
637 struct kvm_msr_entry entries
[100];
639 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
642 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
643 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
644 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
645 if (kvm_has_msr_star(env
))
646 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
648 /* FIXME if lm capable */
649 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
650 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
651 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
652 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
654 if (level
== KVM_PUT_FULL_STATE
) {
655 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
656 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
657 env
->system_time_msr
);
658 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
661 msr_data
.info
.nmsrs
= n
;
663 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
668 static int kvm_get_fpu(CPUState
*env
)
673 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
677 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
680 for (i
= 0; i
< 8; ++i
)
681 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
682 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
683 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
684 env
->mxcsr
= fpu
.mxcsr
;
689 static int kvm_get_xsave(CPUState
*env
)
692 struct kvm_xsave
* xsave
;
694 uint16_t cwd
, swd
, twd
, fop
;
696 if (!kvm_has_xsave())
697 return kvm_get_fpu(env
);
699 xsave
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
700 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
704 cwd
= (uint16_t)xsave
->region
[0];
705 swd
= (uint16_t)(xsave
->region
[0] >> 16);
706 twd
= (uint16_t)xsave
->region
[1];
707 fop
= (uint16_t)(xsave
->region
[1] >> 16);
708 env
->fpstt
= (swd
>> 11) & 7;
711 for (i
= 0; i
< 8; ++i
)
712 env
->fptags
[i
] = !((twd
>> i
) & 1);
713 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
714 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
716 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
717 sizeof env
->xmm_regs
);
718 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
719 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
720 sizeof env
->ymmh_regs
);
723 return kvm_get_fpu(env
);
727 static int kvm_get_xcrs(CPUState
*env
)
731 struct kvm_xcrs xcrs
;
736 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
740 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++)
741 /* Only support xcr0 now */
742 if (xcrs
.xcrs
[0].xcr
== 0) {
743 env
->xcr0
= xcrs
.xcrs
[0].value
;
752 static int kvm_get_sregs(CPUState
*env
)
754 struct kvm_sregs sregs
;
758 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
762 /* There can only be one pending IRQ set in the bitmap at a time, so try
763 to find it and save its number instead (-1 for none). */
764 env
->interrupt_injected
= -1;
765 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
766 if (sregs
.interrupt_bitmap
[i
]) {
767 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
768 env
->interrupt_injected
= i
* 64 + bit
;
773 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
774 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
775 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
776 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
777 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
778 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
780 get_seg(&env
->tr
, &sregs
.tr
);
781 get_seg(&env
->ldt
, &sregs
.ldt
);
783 env
->idt
.limit
= sregs
.idt
.limit
;
784 env
->idt
.base
= sregs
.idt
.base
;
785 env
->gdt
.limit
= sregs
.gdt
.limit
;
786 env
->gdt
.base
= sregs
.gdt
.base
;
788 env
->cr
[0] = sregs
.cr0
;
789 env
->cr
[2] = sregs
.cr2
;
790 env
->cr
[3] = sregs
.cr3
;
791 env
->cr
[4] = sregs
.cr4
;
793 cpu_set_apic_base(env
->apic_state
, sregs
.apic_base
);
795 env
->efer
= sregs
.efer
;
796 //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
798 #define HFLAG_COPY_MASK ~( \
799 HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
800 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
801 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
802 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
806 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
807 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
808 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
809 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
810 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
811 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
812 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
814 if (env
->efer
& MSR_EFER_LMA
) {
815 hflags
|= HF_LMA_MASK
;
818 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
819 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
821 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
822 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
823 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
824 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
825 if (!(env
->cr
[0] & CR0_PE_MASK
) ||
826 (env
->eflags
& VM_MASK
) ||
827 !(hflags
& HF_CS32_MASK
)) {
828 hflags
|= HF_ADDSEG_MASK
;
830 hflags
|= ((env
->segs
[R_DS
].base
|
831 env
->segs
[R_ES
].base
|
832 env
->segs
[R_SS
].base
) != 0) <<
836 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
841 static int kvm_get_msrs(CPUState
*env
)
844 struct kvm_msrs info
;
845 struct kvm_msr_entry entries
[100];
847 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
851 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
852 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
853 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
854 if (kvm_has_msr_star(env
))
855 msrs
[n
++].index
= MSR_STAR
;
856 msrs
[n
++].index
= MSR_IA32_TSC
;
858 /* FIXME lm_capable_kernel */
859 msrs
[n
++].index
= MSR_CSTAR
;
860 msrs
[n
++].index
= MSR_KERNELGSBASE
;
861 msrs
[n
++].index
= MSR_FMASK
;
862 msrs
[n
++].index
= MSR_LSTAR
;
864 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
865 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
867 msr_data
.info
.nmsrs
= n
;
868 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
872 for (i
= 0; i
< ret
; i
++) {
873 switch (msrs
[i
].index
) {
874 case MSR_IA32_SYSENTER_CS
:
875 env
->sysenter_cs
= msrs
[i
].data
;
877 case MSR_IA32_SYSENTER_ESP
:
878 env
->sysenter_esp
= msrs
[i
].data
;
880 case MSR_IA32_SYSENTER_EIP
:
881 env
->sysenter_eip
= msrs
[i
].data
;
884 env
->star
= msrs
[i
].data
;
888 env
->cstar
= msrs
[i
].data
;
890 case MSR_KERNELGSBASE
:
891 env
->kernelgsbase
= msrs
[i
].data
;
894 env
->fmask
= msrs
[i
].data
;
897 env
->lstar
= msrs
[i
].data
;
901 env
->tsc
= msrs
[i
].data
;
903 case MSR_KVM_SYSTEM_TIME
:
904 env
->system_time_msr
= msrs
[i
].data
;
906 case MSR_KVM_WALL_CLOCK
:
907 env
->wall_clock_msr
= msrs
[i
].data
;
915 static int kvm_put_mp_state(CPUState
*env
)
917 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
919 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
922 static int kvm_get_mp_state(CPUState
*env
)
924 struct kvm_mp_state mp_state
;
927 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
931 env
->mp_state
= mp_state
.mp_state
;
935 static int kvm_put_vcpu_events(CPUState
*env
, int level
)
937 #ifdef KVM_CAP_VCPU_EVENTS
938 struct kvm_vcpu_events events
;
940 if (!kvm_has_vcpu_events()) {
944 events
.exception
.injected
= (env
->exception_injected
>= 0);
945 events
.exception
.nr
= env
->exception_injected
;
946 events
.exception
.has_error_code
= env
->has_error_code
;
947 events
.exception
.error_code
= env
->error_code
;
949 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
950 events
.interrupt
.nr
= env
->interrupt_injected
;
951 events
.interrupt
.soft
= env
->soft_interrupt
;
953 events
.nmi
.injected
= env
->nmi_injected
;
954 events
.nmi
.pending
= env
->nmi_pending
;
955 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
957 events
.sipi_vector
= env
->sipi_vector
;
960 if (level
>= KVM_PUT_RESET_STATE
) {
962 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
965 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
971 static int kvm_get_vcpu_events(CPUState
*env
)
973 #ifdef KVM_CAP_VCPU_EVENTS
974 struct kvm_vcpu_events events
;
977 if (!kvm_has_vcpu_events()) {
981 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
985 env
->exception_injected
=
986 events
.exception
.injected
? events
.exception
.nr
: -1;
987 env
->has_error_code
= events
.exception
.has_error_code
;
988 env
->error_code
= events
.exception
.error_code
;
990 env
->interrupt_injected
=
991 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
992 env
->soft_interrupt
= events
.interrupt
.soft
;
994 env
->nmi_injected
= events
.nmi
.injected
;
995 env
->nmi_pending
= events
.nmi
.pending
;
996 if (events
.nmi
.masked
) {
997 env
->hflags2
|= HF2_NMI_MASK
;
999 env
->hflags2
&= ~HF2_NMI_MASK
;
1002 env
->sipi_vector
= events
.sipi_vector
;
1008 static int kvm_guest_debug_workarounds(CPUState
*env
)
1011 #ifdef KVM_CAP_SET_GUEST_DEBUG
1012 unsigned long reinject_trap
= 0;
1014 if (!kvm_has_vcpu_events()) {
1015 if (env
->exception_injected
== 1) {
1016 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1017 } else if (env
->exception_injected
== 3) {
1018 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1020 env
->exception_injected
= -1;
1024 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1025 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1026 * by updating the debug state once again if single-stepping is on.
1027 * Another reason to call kvm_update_guest_debug here is a pending debug
1028 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1029 * reinject them via SET_GUEST_DEBUG.
1031 if (reinject_trap
||
1032 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1033 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1035 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1039 static int kvm_put_debugregs(CPUState
*env
)
1041 #ifdef KVM_CAP_DEBUGREGS
1042 struct kvm_debugregs dbgregs
;
1045 if (!kvm_has_debugregs()) {
1049 for (i
= 0; i
< 4; i
++) {
1050 dbgregs
.db
[i
] = env
->dr
[i
];
1052 dbgregs
.dr6
= env
->dr
[6];
1053 dbgregs
.dr7
= env
->dr
[7];
1056 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1062 static int kvm_get_debugregs(CPUState
*env
)
1064 #ifdef KVM_CAP_DEBUGREGS
1065 struct kvm_debugregs dbgregs
;
1068 if (!kvm_has_debugregs()) {
1072 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1076 for (i
= 0; i
< 4; i
++) {
1077 env
->dr
[i
] = dbgregs
.db
[i
];
1079 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1080 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1086 int kvm_arch_put_registers(CPUState
*env
, int level
)
1090 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1092 ret
= kvm_getput_regs(env
, 1);
1096 ret
= kvm_put_xsave(env
);
1100 ret
= kvm_put_xcrs(env
);
1104 ret
= kvm_put_sregs(env
);
1108 ret
= kvm_put_msrs(env
, level
);
1112 if (level
>= KVM_PUT_RESET_STATE
) {
1113 ret
= kvm_put_mp_state(env
);
1118 ret
= kvm_put_vcpu_events(env
, level
);
1123 ret
= kvm_guest_debug_workarounds(env
);
1127 ret
= kvm_put_debugregs(env
);
1134 int kvm_arch_get_registers(CPUState
*env
)
1138 assert(cpu_is_stopped(env
) || qemu_cpu_self(env
));
1140 ret
= kvm_getput_regs(env
, 0);
1144 ret
= kvm_get_xsave(env
);
1148 ret
= kvm_get_xcrs(env
);
1152 ret
= kvm_get_sregs(env
);
1156 ret
= kvm_get_msrs(env
);
1160 ret
= kvm_get_mp_state(env
);
1164 ret
= kvm_get_vcpu_events(env
);
1168 ret
= kvm_get_debugregs(env
);
1175 int kvm_arch_pre_run(CPUState
*env
, struct kvm_run
*run
)
1177 /* Try to inject an interrupt if the guest can accept it */
1178 if (run
->ready_for_interrupt_injection
&&
1179 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1180 (env
->eflags
& IF_MASK
)) {
1183 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1184 irq
= cpu_get_pic_interrupt(env
);
1186 struct kvm_interrupt intr
;
1189 DPRINTF("injected interrupt %d\n", irq
);
1190 kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1194 /* If we have an interrupt but the guest is not ready to receive an
1195 * interrupt, request an interrupt window exit. This will
1196 * cause a return to userspace as soon as the guest is ready to
1197 * receive interrupts. */
1198 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
))
1199 run
->request_interrupt_window
= 1;
1201 run
->request_interrupt_window
= 0;
1203 DPRINTF("setting tpr\n");
1204 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1209 int kvm_arch_post_run(CPUState
*env
, struct kvm_run
*run
)
1212 env
->eflags
|= IF_MASK
;
1214 env
->eflags
&= ~IF_MASK
;
1216 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1217 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1222 int kvm_arch_process_irqchip_events(CPUState
*env
)
1224 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1225 kvm_cpu_synchronize_state(env
);
1227 env
->exception_index
= EXCP_HALTED
;
1230 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1231 kvm_cpu_synchronize_state(env
);
1238 static int kvm_handle_halt(CPUState
*env
)
1240 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1241 (env
->eflags
& IF_MASK
)) &&
1242 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1244 env
->exception_index
= EXCP_HLT
;
1251 int kvm_arch_handle_exit(CPUState
*env
, struct kvm_run
*run
)
1255 switch (run
->exit_reason
) {
1257 DPRINTF("handle_hlt\n");
1258 ret
= kvm_handle_halt(env
);
1265 #ifdef KVM_CAP_SET_GUEST_DEBUG
1266 int kvm_arch_insert_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1268 static const uint8_t int3
= 0xcc;
1270 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1271 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1))
1276 int kvm_arch_remove_sw_breakpoint(CPUState
*env
, struct kvm_sw_breakpoint
*bp
)
1280 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1281 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1))
1292 static int nb_hw_breakpoint
;
1294 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1298 for (n
= 0; n
< nb_hw_breakpoint
; n
++)
1299 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1300 (hw_breakpoint
[n
].len
== len
|| len
== -1))
1305 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1306 target_ulong len
, int type
)
1309 case GDB_BREAKPOINT_HW
:
1312 case GDB_WATCHPOINT_WRITE
:
1313 case GDB_WATCHPOINT_ACCESS
:
1320 if (addr
& (len
- 1))
1331 if (nb_hw_breakpoint
== 4)
1334 if (find_hw_breakpoint(addr
, len
, type
) >= 0)
1337 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1338 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1339 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1345 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1346 target_ulong len
, int type
)
1350 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1355 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1360 void kvm_arch_remove_all_hw_breakpoints(void)
1362 nb_hw_breakpoint
= 0;
1365 static CPUWatchpoint hw_watchpoint
;
1367 int kvm_arch_debug(struct kvm_debug_exit_arch
*arch_info
)
1372 if (arch_info
->exception
== 1) {
1373 if (arch_info
->dr6
& (1 << 14)) {
1374 if (cpu_single_env
->singlestep_enabled
)
1377 for (n
= 0; n
< 4; n
++)
1378 if (arch_info
->dr6
& (1 << n
))
1379 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1385 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1386 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1387 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1391 cpu_single_env
->watchpoint_hit
= &hw_watchpoint
;
1392 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1393 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1397 } else if (kvm_find_sw_breakpoint(cpu_single_env
, arch_info
->pc
))
1401 cpu_synchronize_state(cpu_single_env
);
1402 assert(cpu_single_env
->exception_injected
== -1);
1404 cpu_single_env
->exception_injected
= arch_info
->exception
;
1405 cpu_single_env
->has_error_code
= 0;
1411 void kvm_arch_update_guest_debug(CPUState
*env
, struct kvm_guest_debug
*dbg
)
1413 const uint8_t type_code
[] = {
1414 [GDB_BREAKPOINT_HW
] = 0x0,
1415 [GDB_WATCHPOINT_WRITE
] = 0x1,
1416 [GDB_WATCHPOINT_ACCESS
] = 0x3
1418 const uint8_t len_code
[] = {
1419 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1423 if (kvm_sw_breakpoints_active(env
))
1424 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
1426 if (nb_hw_breakpoint
> 0) {
1427 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
1428 dbg
->arch
.debugreg
[7] = 0x0600;
1429 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1430 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
1431 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
1432 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
1433 (len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
1436 /* Legal xcr0 for loading */
1439 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1441 bool kvm_arch_stop_on_emulation_error(CPUState
*env
)
1443 return !(env
->cr
[0] & CR0_PE_MASK
) ||
1444 ((env
->segs
[R_CS
].selector
& 3) != 3);