target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34 #include "hw/pci.h"
  35
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 static bool has_msr_tsc_deadline;
  66 static bool has_msr_async_pf_en;
  67 static bool has_msr_pv_eoi_en;
  68 static bool has_msr_misc_enable;
  69 static int lm_capable_kernel;
  70
  71 bool kvm_allows_irq0_override(void)
  72 {
  73     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  74 }
  75
  76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int r, size;
  80
  81     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  82     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  83     cpuid->nent = max;
  84     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  85     if (r == 0 && cpuid->nent >= max) {
  86         r = -E2BIG;
  87     }
  88     if (r < 0) {
  89         if (r == -E2BIG) {
  90             g_free(cpuid);
  91             return NULL;
  92         } else {
  93             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  94                     strerror(-r));
  95             exit(1);
  96         }
  97     }
  98     return cpuid;
  99 }
 100
 101 struct kvm_para_features {
 102     int cap;
 103     int feature;
 104 } para_features[] = {
 105     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 106     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 107     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 108     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 109     { -1, -1 }
 110 };
 111
 112 static int get_para_features(KVMState *s)
 113 {
 114     int i, features = 0;
 115
 116     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 117         if (kvm_check_extension(s, para_features[i].cap)) {
 118             features |= (1 << para_features[i].feature);
 119         }
 120     }
 121
 122     return features;
 123 }
 124
 125
 126 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 127                                       uint32_t index, int reg)
 128 {
 129     struct kvm_cpuid2 *cpuid;
 130     int i, max;
 131     uint32_t ret = 0;
 132     uint32_t cpuid_1_edx;
 133     bool found = false;
 134
 135     max = 1;
 136     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 137         max *= 2;
 138     }
 139
 140     for (i = 0; i < cpuid->nent; ++i) {
 141         if (cpuid->entries[i].function == function &&
 142             cpuid->entries[i].index == index) {
 143             struct kvm_cpuid_entry2 *entry = &cpuid->entries[i];
 144             found = true;
 145             switch (reg) {
 146             case R_EAX:
 147                 ret = entry->eax;
 148                 break;
 149             case R_EBX:
 150                 ret = entry->ebx;
 151                 break;
 152             case R_ECX:
 153                 ret = entry->ecx;
 154                 break;
 155             case R_EDX:
 156                 ret = entry->edx;
 157                 break;
 158             }
 159         }
 160     }
 161
 162     /* Fixups for the data returned by KVM, below */
 163
 164     if (reg == R_EDX) {
 165         switch (function) {
 166         case 1:
 167             /* KVM before 2.6.30 misreports the following features */
 168             ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 169             break;
 170         case 0x80000001:
 171             /* On Intel, kvm returns cpuid according to the Intel spec,
 172              * so add missing bits according to the AMD spec:
 173              */
 174             cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 175             ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 176             break;
 177         }
 178     }
 179
 180     g_free(cpuid);
 181
 182     /* fallback for older kernels */
 183     if ((function == KVM_CPUID_FEATURES) && !found) {
 184         ret = get_para_features(s);
 185     }
 186
 187     return ret;
 188 }
 189
 190 typedef struct HWPoisonPage {
 191     ram_addr_t ram_addr;
 192     QLIST_ENTRY(HWPoisonPage) list;
 193 } HWPoisonPage;
 194
 195 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 196     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 197
 198 static void kvm_unpoison_all(void *param)
 199 {
 200     HWPoisonPage *page, *next_page;
 201
 202     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 203         QLIST_REMOVE(page, list);
 204         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 205         g_free(page);
 206     }
 207 }
 208
 209 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 210 {
 211     HWPoisonPage *page;
 212
 213     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 214         if (page->ram_addr == ram_addr) {
 215             return;
 216         }
 217     }
 218     page = g_malloc(sizeof(HWPoisonPage));
 219     page->ram_addr = ram_addr;
 220     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 221 }
 222
 223 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 224                                      int *max_banks)
 225 {
 226     int r;
 227
 228     r = kvm_check_extension(s, KVM_CAP_MCE);
 229     if (r > 0) {
 230         *max_banks = r;
 231         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 232     }
 233     return -ENOSYS;
 234 }
 235
 236 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
 237 {
 238     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 239                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 240     uint64_t mcg_status = MCG_STATUS_MCIP;
 241
 242     if (code == BUS_MCEERR_AR) {
 243         status |= MCI_STATUS_AR | 0x134;
 244         mcg_status |= MCG_STATUS_EIPV;
 245     } else {
 246         status |= 0xc0;
 247         mcg_status |= MCG_STATUS_RIPV;
 248     }
 249     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 250                        (MCM_ADDR_PHYS << 6) | 0xc,
 251                        cpu_x86_support_mca_broadcast(env) ?
 252                        MCE_INJECT_BROADCAST : 0);
 253 }
 254
 255 static void hardware_memory_error(void)
 256 {
 257     fprintf(stderr, "Hardware memory error!\n");
 258     exit(1);
 259 }
 260
 261 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 262 {
 263     ram_addr_t ram_addr;
 264     hwaddr paddr;
 265
 266     if ((env->mcg_cap & MCG_SER_P) && addr
 267         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 268         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 269             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 270             fprintf(stderr, "Hardware memory error for memory used by "
 271                     "QEMU itself instead of guest system!\n");
 272             /* Hope we are lucky for AO MCE */
 273             if (code == BUS_MCEERR_AO) {
 274                 return 0;
 275             } else {
 276                 hardware_memory_error();
 277             }
 278         }
 279         kvm_hwpoison_page_add(ram_addr);
 280         kvm_mce_inject(env, paddr, code);
 281     } else {
 282         if (code == BUS_MCEERR_AO) {
 283             return 0;
 284         } else if (code == BUS_MCEERR_AR) {
 285             hardware_memory_error();
 286         } else {
 287             return 1;
 288         }
 289     }
 290     return 0;
 291 }
 292
 293 int kvm_arch_on_sigbus(int code, void *addr)
 294 {
 295     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 296         ram_addr_t ram_addr;
 297         hwaddr paddr;
 298
 299         /* Hope we are lucky for AO MCE */
 300         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 301             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 302                                                 &paddr)) {
 303             fprintf(stderr, "Hardware memory error for memory used by "
 304                     "QEMU itself instead of guest system!: %p\n", addr);
 305             return 0;
 306         }
 307         kvm_hwpoison_page_add(ram_addr);
 308         kvm_mce_inject(first_cpu, paddr, code);
 309     } else {
 310         if (code == BUS_MCEERR_AO) {
 311             return 0;
 312         } else if (code == BUS_MCEERR_AR) {
 313             hardware_memory_error();
 314         } else {
 315             return 1;
 316         }
 317     }
 318     return 0;
 319 }
 320
 321 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 322 {
 323     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 324         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 325         struct kvm_x86_mce mce;
 326
 327         env->exception_injected = -1;
 328
 329         /*
 330          * There must be at least one bank in use if an MCE is pending.
 331          * Find it and use its values for the event injection.
 332          */
 333         for (bank = 0; bank < bank_num; bank++) {
 334             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 335                 break;
 336             }
 337         }
 338         assert(bank < bank_num);
 339
 340         mce.bank = bank;
 341         mce.status = env->mce_banks[bank * 4 + 1];
 342         mce.mcg_status = env->mcg_status;
 343         mce.addr = env->mce_banks[bank * 4 + 2];
 344         mce.misc = env->mce_banks[bank * 4 + 3];
 345
 346         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 347     }
 348     return 0;
 349 }
 350
 351 static void cpu_update_state(void *opaque, int running, RunState state)
 352 {
 353     CPUX86State *env = opaque;
 354
 355     if (running) {
 356         env->tsc_valid = false;
 357     }
 358 }
 359
 360 int kvm_arch_init_vcpu(CPUX86State *env)
 361 {
 362     struct {
 363         struct kvm_cpuid2 cpuid;
 364         struct kvm_cpuid_entry2 entries[100];
 365     } QEMU_PACKED cpuid_data;
 366     KVMState *s = env->kvm_state;
 367     uint32_t limit, i, j, cpuid_i;
 368     uint32_t unused;
 369     struct kvm_cpuid_entry2 *c;
 370     uint32_t signature[3];
 371     int r;
 372
 373     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 374
 375     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 376     j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER;
 377     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 378     env->cpuid_ext_features |= i;
 379     if (j && kvm_irqchip_in_kernel() &&
 380         kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 381         env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER;
 382     }
 383
 384     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 385                                                              0, R_EDX);
 386     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 387                                                              0, R_ECX);
 388     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 389                                                              0, R_EDX);
 390
 391     cpuid_i = 0;
 392
 393     /* Paravirtualization CPUIDs */
 394     c = &cpuid_data.entries[cpuid_i++];
 395     memset(c, 0, sizeof(*c));
 396     c->function = KVM_CPUID_SIGNATURE;
 397     if (!hyperv_enabled()) {
 398         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 399         c->eax = 0;
 400     } else {
 401         memcpy(signature, "Microsoft Hv", 12);
 402         c->eax = HYPERV_CPUID_MIN;
 403     }
 404     c->ebx = signature[0];
 405     c->ecx = signature[1];
 406     c->edx = signature[2];
 407
 408     c = &cpuid_data.entries[cpuid_i++];
 409     memset(c, 0, sizeof(*c));
 410     c->function = KVM_CPUID_FEATURES;
 411     c->eax = env->cpuid_kvm_features &
 412         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 413
 414     if (hyperv_enabled()) {
 415         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 416         c->eax = signature[0];
 417
 418         c = &cpuid_data.entries[cpuid_i++];
 419         memset(c, 0, sizeof(*c));
 420         c->function = HYPERV_CPUID_VERSION;
 421         c->eax = 0x00001bbc;
 422         c->ebx = 0x00060001;
 423
 424         c = &cpuid_data.entries[cpuid_i++];
 425         memset(c, 0, sizeof(*c));
 426         c->function = HYPERV_CPUID_FEATURES;
 427         if (hyperv_relaxed_timing_enabled()) {
 428             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 429         }
 430         if (hyperv_vapic_recommended()) {
 431             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 432             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 433         }
 434
 435         c = &cpuid_data.entries[cpuid_i++];
 436         memset(c, 0, sizeof(*c));
 437         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 438         if (hyperv_relaxed_timing_enabled()) {
 439             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 440         }
 441         if (hyperv_vapic_recommended()) {
 442             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 443         }
 444         c->ebx = hyperv_get_spinlock_retries();
 445
 446         c = &cpuid_data.entries[cpuid_i++];
 447         memset(c, 0, sizeof(*c));
 448         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 449         c->eax = 0x40;
 450         c->ebx = 0x40;
 451
 452         c = &cpuid_data.entries[cpuid_i++];
 453         memset(c, 0, sizeof(*c));
 454         c->function = KVM_CPUID_SIGNATURE_NEXT;
 455         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 456         c->eax = 0;
 457         c->ebx = signature[0];
 458         c->ecx = signature[1];
 459         c->edx = signature[2];
 460     }
 461
 462     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 463
 464     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 465
 466     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 467
 468     for (i = 0; i <= limit; i++) {
 469         c = &cpuid_data.entries[cpuid_i++];
 470
 471         switch (i) {
 472         case 2: {
 473             /* Keep reading function 2 till all the input is received */
 474             int times;
 475
 476             c->function = i;
 477             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 478                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 479             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 480             times = c->eax & 0xff;
 481
 482             for (j = 1; j < times; ++j) {
 483                 c = &cpuid_data.entries[cpuid_i++];
 484                 c->function = i;
 485                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 486                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 487             }
 488             break;
 489         }
 490         case 4:
 491         case 0xb:
 492         case 0xd:
 493             for (j = 0; ; j++) {
 494                 if (i == 0xd && j == 64) {
 495                     break;
 496                 }
 497                 c->function = i;
 498                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 499                 c->index = j;
 500                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 501
 502                 if (i == 4 && c->eax == 0) {
 503                     break;
 504                 }
 505                 if (i == 0xb && !(c->ecx & 0xff00)) {
 506                     break;
 507                 }
 508                 if (i == 0xd && c->eax == 0) {
 509                     continue;
 510                 }
 511                 c = &cpuid_data.entries[cpuid_i++];
 512             }
 513             break;
 514         default:
 515             c->function = i;
 516             c->flags = 0;
 517             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 518             break;
 519         }
 520     }
 521     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 522
 523     for (i = 0x80000000; i <= limit; i++) {
 524         c = &cpuid_data.entries[cpuid_i++];
 525
 526         c->function = i;
 527         c->flags = 0;
 528         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 529     }
 530
 531     /* Call Centaur's CPUID instructions they are supported. */
 532     if (env->cpuid_xlevel2 > 0) {
 533         env->cpuid_ext4_features &=
 534             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 535         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 536
 537         for (i = 0xC0000000; i <= limit; i++) {
 538             c = &cpuid_data.entries[cpuid_i++];
 539
 540             c->function = i;
 541             c->flags = 0;
 542             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 543         }
 544     }
 545
 546     cpuid_data.cpuid.nent = cpuid_i;
 547
 548     if (((env->cpuid_version >> 8)&0xF) >= 6
 549         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 550         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 551         uint64_t mcg_cap;
 552         int banks;
 553         int ret;
 554
 555         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 556         if (ret < 0) {
 557             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 558             return ret;
 559         }
 560
 561         if (banks > MCE_BANKS_DEF) {
 562             banks = MCE_BANKS_DEF;
 563         }
 564         mcg_cap &= MCE_CAP_DEF;
 565         mcg_cap |= banks;
 566         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 567         if (ret < 0) {
 568             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 569             return ret;
 570         }
 571
 572         env->mcg_cap = mcg_cap;
 573     }
 574
 575     qemu_add_vm_change_state_handler(cpu_update_state, env);
 576
 577     cpuid_data.cpuid.padding = 0;
 578     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 579     if (r) {
 580         return r;
 581     }
 582
 583     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 584     if (r && env->tsc_khz) {
 585         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 586         if (r < 0) {
 587             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 588             return r;
 589         }
 590     }
 591
 592     if (kvm_has_xsave()) {
 593         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 594     }
 595
 596     return 0;
 597 }
 598
 599 void kvm_arch_reset_vcpu(CPUX86State *env)
 600 {
 601     X86CPU *cpu = x86_env_get_cpu(env);
 602
 603     env->exception_injected = -1;
 604     env->interrupt_injected = -1;
 605     env->xcr0 = 1;
 606     if (kvm_irqchip_in_kernel()) {
 607         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 608                                           KVM_MP_STATE_UNINITIALIZED;
 609     } else {
 610         env->mp_state = KVM_MP_STATE_RUNNABLE;
 611     }
 612 }
 613
 614 static int kvm_get_supported_msrs(KVMState *s)
 615 {
 616     static int kvm_supported_msrs;
 617     int ret = 0;
 618
 619     /* first time */
 620     if (kvm_supported_msrs == 0) {
 621         struct kvm_msr_list msr_list, *kvm_msr_list;
 622
 623         kvm_supported_msrs = -1;
 624
 625         /* Obtain MSR list from KVM.  These are the MSRs that we must
 626          * save/restore */
 627         msr_list.nmsrs = 0;
 628         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 629         if (ret < 0 && ret != -E2BIG) {
 630             return ret;
 631         }
 632         /* Old kernel modules had a bug and could write beyond the provided
 633            memory. Allocate at least a safe amount of 1K. */
 634         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 635                                               msr_list.nmsrs *
 636                                               sizeof(msr_list.indices[0])));
 637
 638         kvm_msr_list->nmsrs = msr_list.nmsrs;
 639         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 640         if (ret >= 0) {
 641             int i;
 642
 643             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 644                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 645                     has_msr_star = true;
 646                     continue;
 647                 }
 648                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 649                     has_msr_hsave_pa = true;
 650                     continue;
 651                 }
 652                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 653                     has_msr_tsc_deadline = true;
 654                     continue;
 655                 }
 656                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 657                     has_msr_misc_enable = true;
 658                     continue;
 659                 }
 660             }
 661         }
 662
 663         g_free(kvm_msr_list);
 664     }
 665
 666     return ret;
 667 }
 668
 669 int kvm_arch_init(KVMState *s)
 670 {
 671     QemuOptsList *list = qemu_find_opts("machine");
 672     uint64_t identity_base = 0xfffbc000;
 673     uint64_t shadow_mem;
 674     int ret;
 675     struct utsname utsname;
 676
 677     ret = kvm_get_supported_msrs(s);
 678     if (ret < 0) {
 679         return ret;
 680     }
 681
 682     uname(&utsname);
 683     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 684
 685     /*
 686      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 687      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 688      * Since these must be part of guest physical memory, we need to allocate
 689      * them, both by setting their start addresses in the kernel and by
 690      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 691      *
 692      * Older KVM versions may not support setting the identity map base. In
 693      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 694      * size.
 695      */
 696     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 697         /* Allows up to 16M BIOSes. */
 698         identity_base = 0xfeffc000;
 699
 700         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 701         if (ret < 0) {
 702             return ret;
 703         }
 704     }
 705
 706     /* Set TSS base one page after EPT identity map. */
 707     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 708     if (ret < 0) {
 709         return ret;
 710     }
 711
 712     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 713     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 714     if (ret < 0) {
 715         fprintf(stderr, "e820_add_entry() table is full\n");
 716         return ret;
 717     }
 718     qemu_register_reset(kvm_unpoison_all, NULL);
 719
 720     if (!QTAILQ_EMPTY(&list->head)) {
 721         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 722                                        "kvm_shadow_mem", -1);
 723         if (shadow_mem != -1) {
 724             shadow_mem /= 4096;
 725             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 726             if (ret < 0) {
 727                 return ret;
 728             }
 729         }
 730     }
 731     return 0;
 732 }
 733
 734 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 735 {
 736     lhs->selector = rhs->selector;
 737     lhs->base = rhs->base;
 738     lhs->limit = rhs->limit;
 739     lhs->type = 3;
 740     lhs->present = 1;
 741     lhs->dpl = 3;
 742     lhs->db = 0;
 743     lhs->s = 1;
 744     lhs->l = 0;
 745     lhs->g = 0;
 746     lhs->avl = 0;
 747     lhs->unusable = 0;
 748 }
 749
 750 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 751 {
 752     unsigned flags = rhs->flags;
 753     lhs->selector = rhs->selector;
 754     lhs->base = rhs->base;
 755     lhs->limit = rhs->limit;
 756     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 757     lhs->present = (flags & DESC_P_MASK) != 0;
 758     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 759     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 760     lhs->s = (flags & DESC_S_MASK) != 0;
 761     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 762     lhs->g = (flags & DESC_G_MASK) != 0;
 763     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 764     lhs->unusable = 0;
 765     lhs->padding = 0;
 766 }
 767
 768 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 769 {
 770     lhs->selector = rhs->selector;
 771     lhs->base = rhs->base;
 772     lhs->limit = rhs->limit;
 773     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 774                  (rhs->present * DESC_P_MASK) |
 775                  (rhs->dpl << DESC_DPL_SHIFT) |
 776                  (rhs->db << DESC_B_SHIFT) |
 777                  (rhs->s * DESC_S_MASK) |
 778                  (rhs->l << DESC_L_SHIFT) |
 779                  (rhs->g * DESC_G_MASK) |
 780                  (rhs->avl * DESC_AVL_MASK);
 781 }
 782
 783 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 784 {
 785     if (set) {
 786         *kvm_reg = *qemu_reg;
 787     } else {
 788         *qemu_reg = *kvm_reg;
 789     }
 790 }
 791
 792 static int kvm_getput_regs(CPUX86State *env, int set)
 793 {
 794     struct kvm_regs regs;
 795     int ret = 0;
 796
 797     if (!set) {
 798         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 799         if (ret < 0) {
 800             return ret;
 801         }
 802     }
 803
 804     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 805     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 806     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 807     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 808     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 809     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 810     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 811     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 812 #ifdef TARGET_X86_64
 813     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 814     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 815     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 816     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 817     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 818     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 819     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 820     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 821 #endif
 822
 823     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 824     kvm_getput_reg(&regs.rip, &env->eip, set);
 825
 826     if (set) {
 827         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 828     }
 829
 830     return ret;
 831 }
 832
 833 static int kvm_put_fpu(CPUX86State *env)
 834 {
 835     struct kvm_fpu fpu;
 836     int i;
 837
 838     memset(&fpu, 0, sizeof fpu);
 839     fpu.fsw = env->fpus & ~(7 << 11);
 840     fpu.fsw |= (env->fpstt & 7) << 11;
 841     fpu.fcw = env->fpuc;
 842     fpu.last_opcode = env->fpop;
 843     fpu.last_ip = env->fpip;
 844     fpu.last_dp = env->fpdp;
 845     for (i = 0; i < 8; ++i) {
 846         fpu.ftwx |= (!env->fptags[i]) << i;
 847     }
 848     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 849     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 850     fpu.mxcsr = env->mxcsr;
 851
 852     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 853 }
 854
 855 #define XSAVE_FCW_FSW     0
 856 #define XSAVE_FTW_FOP     1
 857 #define XSAVE_CWD_RIP     2
 858 #define XSAVE_CWD_RDP     4
 859 #define XSAVE_MXCSR       6
 860 #define XSAVE_ST_SPACE    8
 861 #define XSAVE_XMM_SPACE   40
 862 #define XSAVE_XSTATE_BV   128
 863 #define XSAVE_YMMH_SPACE  144
 864
 865 static int kvm_put_xsave(CPUX86State *env)
 866 {
 867     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 868     uint16_t cwd, swd, twd;
 869     int i, r;
 870
 871     if (!kvm_has_xsave()) {
 872         return kvm_put_fpu(env);
 873     }
 874
 875     memset(xsave, 0, sizeof(struct kvm_xsave));
 876     twd = 0;
 877     swd = env->fpus & ~(7 << 11);
 878     swd |= (env->fpstt & 7) << 11;
 879     cwd = env->fpuc;
 880     for (i = 0; i < 8; ++i) {
 881         twd |= (!env->fptags[i]) << i;
 882     }
 883     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 884     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 885     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 886     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 887     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 888             sizeof env->fpregs);
 889     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 890             sizeof env->xmm_regs);
 891     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 892     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 893     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 894             sizeof env->ymmh_regs);
 895     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 896     return r;
 897 }
 898
 899 static int kvm_put_xcrs(CPUX86State *env)
 900 {
 901     struct kvm_xcrs xcrs;
 902
 903     if (!kvm_has_xcrs()) {
 904         return 0;
 905     }
 906
 907     xcrs.nr_xcrs = 1;
 908     xcrs.flags = 0;
 909     xcrs.xcrs[0].xcr = 0;
 910     xcrs.xcrs[0].value = env->xcr0;
 911     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 912 }
 913
 914 static int kvm_put_sregs(CPUX86State *env)
 915 {
 916     struct kvm_sregs sregs;
 917
 918     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 919     if (env->interrupt_injected >= 0) {
 920         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 921                 (uint64_t)1 << (env->interrupt_injected % 64);
 922     }
 923
 924     if ((env->eflags & VM_MASK)) {
 925         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 926         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 927         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 928         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 929         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 930         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 931     } else {
 932         set_seg(&sregs.cs, &env->segs[R_CS]);
 933         set_seg(&sregs.ds, &env->segs[R_DS]);
 934         set_seg(&sregs.es, &env->segs[R_ES]);
 935         set_seg(&sregs.fs, &env->segs[R_FS]);
 936         set_seg(&sregs.gs, &env->segs[R_GS]);
 937         set_seg(&sregs.ss, &env->segs[R_SS]);
 938     }
 939
 940     set_seg(&sregs.tr, &env->tr);
 941     set_seg(&sregs.ldt, &env->ldt);
 942
 943     sregs.idt.limit = env->idt.limit;
 944     sregs.idt.base = env->idt.base;
 945     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 946     sregs.gdt.limit = env->gdt.limit;
 947     sregs.gdt.base = env->gdt.base;
 948     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 949
 950     sregs.cr0 = env->cr[0];
 951     sregs.cr2 = env->cr[2];
 952     sregs.cr3 = env->cr[3];
 953     sregs.cr4 = env->cr[4];
 954
 955     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 956     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 957
 958     sregs.efer = env->efer;
 959
 960     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 961 }
 962
 963 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 964                               uint32_t index, uint64_t value)
 965 {
 966     entry->index = index;
 967     entry->data = value;
 968 }
 969
 970 static int kvm_put_msrs(CPUX86State *env, int level)
 971 {
 972     struct {
 973         struct kvm_msrs info;
 974         struct kvm_msr_entry entries[100];
 975     } msr_data;
 976     struct kvm_msr_entry *msrs = msr_data.entries;
 977     int n = 0;
 978
 979     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 980     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 981     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 982     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 983     if (has_msr_star) {
 984         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 985     }
 986     if (has_msr_hsave_pa) {
 987         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 988     }
 989     if (has_msr_tsc_deadline) {
 990         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 991     }
 992     if (has_msr_misc_enable) {
 993         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 994                           env->msr_ia32_misc_enable);
 995     }
 996 #ifdef TARGET_X86_64
 997     if (lm_capable_kernel) {
 998         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 999         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1000         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1001         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1002     }
1003 #endif
1004     if (level == KVM_PUT_FULL_STATE) {
1005         /*
1006          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1007          * writeback. Until this is fixed, we only write the offset to SMP
1008          * guests after migration, desynchronizing the VCPUs, but avoiding
1009          * huge jump-backs that would occur without any writeback at all.
1010          */
1011         if (smp_cpus == 1 || env->tsc != 0) {
1012             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1013         }
1014     }
1015     /*
1016      * The following paravirtual MSRs have side effects on the guest or are
1017      * too heavy for normal writeback. Limit them to reset or full state
1018      * updates.
1019      */
1020     if (level >= KVM_PUT_RESET_STATE) {
1021         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1022                           env->system_time_msr);
1023         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1024         if (has_msr_async_pf_en) {
1025             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1026                               env->async_pf_en_msr);
1027         }
1028         if (has_msr_pv_eoi_en) {
1029             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1030                               env->pv_eoi_en_msr);
1031         }
1032         if (hyperv_hypercall_available()) {
1033             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1034             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1035         }
1036         if (hyperv_vapic_recommended()) {
1037             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1038         }
1039     }
1040     if (env->mcg_cap) {
1041         int i;
1042
1043         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1044         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1045         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1046             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1047         }
1048     }
1049
1050     msr_data.info.nmsrs = n;
1051
1052     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1053
1054 }
1055
1056
1057 static int kvm_get_fpu(CPUX86State *env)
1058 {
1059     struct kvm_fpu fpu;
1060     int i, ret;
1061
1062     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1063     if (ret < 0) {
1064         return ret;
1065     }
1066
1067     env->fpstt = (fpu.fsw >> 11) & 7;
1068     env->fpus = fpu.fsw;
1069     env->fpuc = fpu.fcw;
1070     env->fpop = fpu.last_opcode;
1071     env->fpip = fpu.last_ip;
1072     env->fpdp = fpu.last_dp;
1073     for (i = 0; i < 8; ++i) {
1074         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1075     }
1076     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1077     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1078     env->mxcsr = fpu.mxcsr;
1079
1080     return 0;
1081 }
1082
1083 static int kvm_get_xsave(CPUX86State *env)
1084 {
1085     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1086     int ret, i;
1087     uint16_t cwd, swd, twd;
1088
1089     if (!kvm_has_xsave()) {
1090         return kvm_get_fpu(env);
1091     }
1092
1093     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1094     if (ret < 0) {
1095         return ret;
1096     }
1097
1098     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1099     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1100     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1101     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1102     env->fpstt = (swd >> 11) & 7;
1103     env->fpus = swd;
1104     env->fpuc = cwd;
1105     for (i = 0; i < 8; ++i) {
1106         env->fptags[i] = !((twd >> i) & 1);
1107     }
1108     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1109     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1110     env->mxcsr = xsave->region[XSAVE_MXCSR];
1111     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1112             sizeof env->fpregs);
1113     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1114             sizeof env->xmm_regs);
1115     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1116     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1117             sizeof env->ymmh_regs);
1118     return 0;
1119 }
1120
1121 static int kvm_get_xcrs(CPUX86State *env)
1122 {
1123     int i, ret;
1124     struct kvm_xcrs xcrs;
1125
1126     if (!kvm_has_xcrs()) {
1127         return 0;
1128     }
1129
1130     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1131     if (ret < 0) {
1132         return ret;
1133     }
1134
1135     for (i = 0; i < xcrs.nr_xcrs; i++) {
1136         /* Only support xcr0 now */
1137         if (xcrs.xcrs[0].xcr == 0) {
1138             env->xcr0 = xcrs.xcrs[0].value;
1139             break;
1140         }
1141     }
1142     return 0;
1143 }
1144
1145 static int kvm_get_sregs(CPUX86State *env)
1146 {
1147     struct kvm_sregs sregs;
1148     uint32_t hflags;
1149     int bit, i, ret;
1150
1151     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1152     if (ret < 0) {
1153         return ret;
1154     }
1155
1156     /* There can only be one pending IRQ set in the bitmap at a time, so try
1157        to find it and save its number instead (-1 for none). */
1158     env->interrupt_injected = -1;
1159     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1160         if (sregs.interrupt_bitmap[i]) {
1161             bit = ctz64(sregs.interrupt_bitmap[i]);
1162             env->interrupt_injected = i * 64 + bit;
1163             break;
1164         }
1165     }
1166
1167     get_seg(&env->segs[R_CS], &sregs.cs);
1168     get_seg(&env->segs[R_DS], &sregs.ds);
1169     get_seg(&env->segs[R_ES], &sregs.es);
1170     get_seg(&env->segs[R_FS], &sregs.fs);
1171     get_seg(&env->segs[R_GS], &sregs.gs);
1172     get_seg(&env->segs[R_SS], &sregs.ss);
1173
1174     get_seg(&env->tr, &sregs.tr);
1175     get_seg(&env->ldt, &sregs.ldt);
1176
1177     env->idt.limit = sregs.idt.limit;
1178     env->idt.base = sregs.idt.base;
1179     env->gdt.limit = sregs.gdt.limit;
1180     env->gdt.base = sregs.gdt.base;
1181
1182     env->cr[0] = sregs.cr0;
1183     env->cr[2] = sregs.cr2;
1184     env->cr[3] = sregs.cr3;
1185     env->cr[4] = sregs.cr4;
1186
1187     env->efer = sregs.efer;
1188
1189     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1190
1191 #define HFLAG_COPY_MASK \
1192     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1193        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1194        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1195        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1196
1197     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1198     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1199     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1200                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1201     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1202     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1203                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1204
1205     if (env->efer & MSR_EFER_LMA) {
1206         hflags |= HF_LMA_MASK;
1207     }
1208
1209     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1210         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1211     } else {
1212         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1213                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1214         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1215                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1216         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1217             !(hflags & HF_CS32_MASK)) {
1218             hflags |= HF_ADDSEG_MASK;
1219         } else {
1220             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1221                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1222         }
1223     }
1224     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1225
1226     return 0;
1227 }
1228
1229 static int kvm_get_msrs(CPUX86State *env)
1230 {
1231     struct {
1232         struct kvm_msrs info;
1233         struct kvm_msr_entry entries[100];
1234     } msr_data;
1235     struct kvm_msr_entry *msrs = msr_data.entries;
1236     int ret, i, n;
1237
1238     n = 0;
1239     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1240     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1241     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1242     msrs[n++].index = MSR_PAT;
1243     if (has_msr_star) {
1244         msrs[n++].index = MSR_STAR;
1245     }
1246     if (has_msr_hsave_pa) {
1247         msrs[n++].index = MSR_VM_HSAVE_PA;
1248     }
1249     if (has_msr_tsc_deadline) {
1250         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1251     }
1252     if (has_msr_misc_enable) {
1253         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1254     }
1255
1256     if (!env->tsc_valid) {
1257         msrs[n++].index = MSR_IA32_TSC;
1258         env->tsc_valid = !runstate_is_running();
1259     }
1260
1261 #ifdef TARGET_X86_64
1262     if (lm_capable_kernel) {
1263         msrs[n++].index = MSR_CSTAR;
1264         msrs[n++].index = MSR_KERNELGSBASE;
1265         msrs[n++].index = MSR_FMASK;
1266         msrs[n++].index = MSR_LSTAR;
1267     }
1268 #endif
1269     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1270     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1271     if (has_msr_async_pf_en) {
1272         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1273     }
1274     if (has_msr_pv_eoi_en) {
1275         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1276     }
1277
1278     if (env->mcg_cap) {
1279         msrs[n++].index = MSR_MCG_STATUS;
1280         msrs[n++].index = MSR_MCG_CTL;
1281         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1282             msrs[n++].index = MSR_MC0_CTL + i;
1283         }
1284     }
1285
1286     msr_data.info.nmsrs = n;
1287     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1288     if (ret < 0) {
1289         return ret;
1290     }
1291
1292     for (i = 0; i < ret; i++) {
1293         switch (msrs[i].index) {
1294         case MSR_IA32_SYSENTER_CS:
1295             env->sysenter_cs = msrs[i].data;
1296             break;
1297         case MSR_IA32_SYSENTER_ESP:
1298             env->sysenter_esp = msrs[i].data;
1299             break;
1300         case MSR_IA32_SYSENTER_EIP:
1301             env->sysenter_eip = msrs[i].data;
1302             break;
1303         case MSR_PAT:
1304             env->pat = msrs[i].data;
1305             break;
1306         case MSR_STAR:
1307             env->star = msrs[i].data;
1308             break;
1309 #ifdef TARGET_X86_64
1310         case MSR_CSTAR:
1311             env->cstar = msrs[i].data;
1312             break;
1313         case MSR_KERNELGSBASE:
1314             env->kernelgsbase = msrs[i].data;
1315             break;
1316         case MSR_FMASK:
1317             env->fmask = msrs[i].data;
1318             break;
1319         case MSR_LSTAR:
1320             env->lstar = msrs[i].data;
1321             break;
1322 #endif
1323         case MSR_IA32_TSC:
1324             env->tsc = msrs[i].data;
1325             break;
1326         case MSR_IA32_TSCDEADLINE:
1327             env->tsc_deadline = msrs[i].data;
1328             break;
1329         case MSR_VM_HSAVE_PA:
1330             env->vm_hsave = msrs[i].data;
1331             break;
1332         case MSR_KVM_SYSTEM_TIME:
1333             env->system_time_msr = msrs[i].data;
1334             break;
1335         case MSR_KVM_WALL_CLOCK:
1336             env->wall_clock_msr = msrs[i].data;
1337             break;
1338         case MSR_MCG_STATUS:
1339             env->mcg_status = msrs[i].data;
1340             break;
1341         case MSR_MCG_CTL:
1342             env->mcg_ctl = msrs[i].data;
1343             break;
1344         case MSR_IA32_MISC_ENABLE:
1345             env->msr_ia32_misc_enable = msrs[i].data;
1346             break;
1347         default:
1348             if (msrs[i].index >= MSR_MC0_CTL &&
1349                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1350                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1351             }
1352             break;
1353         case MSR_KVM_ASYNC_PF_EN:
1354             env->async_pf_en_msr = msrs[i].data;
1355             break;
1356         case MSR_KVM_PV_EOI_EN:
1357             env->pv_eoi_en_msr = msrs[i].data;
1358             break;
1359         }
1360     }
1361
1362     return 0;
1363 }
1364
1365 static int kvm_put_mp_state(CPUX86State *env)
1366 {
1367     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1368
1369     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1370 }
1371
1372 static int kvm_get_mp_state(CPUX86State *env)
1373 {
1374     struct kvm_mp_state mp_state;
1375     int ret;
1376
1377     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1378     if (ret < 0) {
1379         return ret;
1380     }
1381     env->mp_state = mp_state.mp_state;
1382     if (kvm_irqchip_in_kernel()) {
1383         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1384     }
1385     return 0;
1386 }
1387
1388 static int kvm_get_apic(CPUX86State *env)
1389 {
1390     DeviceState *apic = env->apic_state;
1391     struct kvm_lapic_state kapic;
1392     int ret;
1393
1394     if (apic && kvm_irqchip_in_kernel()) {
1395         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1396         if (ret < 0) {
1397             return ret;
1398         }
1399
1400         kvm_get_apic_state(apic, &kapic);
1401     }
1402     return 0;
1403 }
1404
1405 static int kvm_put_apic(CPUX86State *env)
1406 {
1407     DeviceState *apic = env->apic_state;
1408     struct kvm_lapic_state kapic;
1409
1410     if (apic && kvm_irqchip_in_kernel()) {
1411         kvm_put_apic_state(apic, &kapic);
1412
1413         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1414     }
1415     return 0;
1416 }
1417
1418 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1419 {
1420     struct kvm_vcpu_events events;
1421
1422     if (!kvm_has_vcpu_events()) {
1423         return 0;
1424     }
1425
1426     events.exception.injected = (env->exception_injected >= 0);
1427     events.exception.nr = env->exception_injected;
1428     events.exception.has_error_code = env->has_error_code;
1429     events.exception.error_code = env->error_code;
1430     events.exception.pad = 0;
1431
1432     events.interrupt.injected = (env->interrupt_injected >= 0);
1433     events.interrupt.nr = env->interrupt_injected;
1434     events.interrupt.soft = env->soft_interrupt;
1435
1436     events.nmi.injected = env->nmi_injected;
1437     events.nmi.pending = env->nmi_pending;
1438     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1439     events.nmi.pad = 0;
1440
1441     events.sipi_vector = env->sipi_vector;
1442
1443     events.flags = 0;
1444     if (level >= KVM_PUT_RESET_STATE) {
1445         events.flags |=
1446             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1447     }
1448
1449     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1450 }
1451
1452 static int kvm_get_vcpu_events(CPUX86State *env)
1453 {
1454     struct kvm_vcpu_events events;
1455     int ret;
1456
1457     if (!kvm_has_vcpu_events()) {
1458         return 0;
1459     }
1460
1461     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1462     if (ret < 0) {
1463        return ret;
1464     }
1465     env->exception_injected =
1466        events.exception.injected ? events.exception.nr : -1;
1467     env->has_error_code = events.exception.has_error_code;
1468     env->error_code = events.exception.error_code;
1469
1470     env->interrupt_injected =
1471         events.interrupt.injected ? events.interrupt.nr : -1;
1472     env->soft_interrupt = events.interrupt.soft;
1473
1474     env->nmi_injected = events.nmi.injected;
1475     env->nmi_pending = events.nmi.pending;
1476     if (events.nmi.masked) {
1477         env->hflags2 |= HF2_NMI_MASK;
1478     } else {
1479         env->hflags2 &= ~HF2_NMI_MASK;
1480     }
1481
1482     env->sipi_vector = events.sipi_vector;
1483
1484     return 0;
1485 }
1486
1487 static int kvm_guest_debug_workarounds(CPUX86State *env)
1488 {
1489     int ret = 0;
1490     unsigned long reinject_trap = 0;
1491
1492     if (!kvm_has_vcpu_events()) {
1493         if (env->exception_injected == 1) {
1494             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1495         } else if (env->exception_injected == 3) {
1496             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1497         }
1498         env->exception_injected = -1;
1499     }
1500
1501     /*
1502      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1503      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1504      * by updating the debug state once again if single-stepping is on.
1505      * Another reason to call kvm_update_guest_debug here is a pending debug
1506      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1507      * reinject them via SET_GUEST_DEBUG.
1508      */
1509     if (reinject_trap ||
1510         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1511         ret = kvm_update_guest_debug(env, reinject_trap);
1512     }
1513     return ret;
1514 }
1515
1516 static int kvm_put_debugregs(CPUX86State *env)
1517 {
1518     struct kvm_debugregs dbgregs;
1519     int i;
1520
1521     if (!kvm_has_debugregs()) {
1522         return 0;
1523     }
1524
1525     for (i = 0; i < 4; i++) {
1526         dbgregs.db[i] = env->dr[i];
1527     }
1528     dbgregs.dr6 = env->dr[6];
1529     dbgregs.dr7 = env->dr[7];
1530     dbgregs.flags = 0;
1531
1532     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1533 }
1534
1535 static int kvm_get_debugregs(CPUX86State *env)
1536 {
1537     struct kvm_debugregs dbgregs;
1538     int i, ret;
1539
1540     if (!kvm_has_debugregs()) {
1541         return 0;
1542     }
1543
1544     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1545     if (ret < 0) {
1546         return ret;
1547     }
1548     for (i = 0; i < 4; i++) {
1549         env->dr[i] = dbgregs.db[i];
1550     }
1551     env->dr[4] = env->dr[6] = dbgregs.dr6;
1552     env->dr[5] = env->dr[7] = dbgregs.dr7;
1553
1554     return 0;
1555 }
1556
1557 int kvm_arch_put_registers(CPUX86State *env, int level)
1558 {
1559     int ret;
1560
1561     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1562
1563     ret = kvm_getput_regs(env, 1);
1564     if (ret < 0) {
1565         return ret;
1566     }
1567     ret = kvm_put_xsave(env);
1568     if (ret < 0) {
1569         return ret;
1570     }
1571     ret = kvm_put_xcrs(env);
1572     if (ret < 0) {
1573         return ret;
1574     }
1575     ret = kvm_put_sregs(env);
1576     if (ret < 0) {
1577         return ret;
1578     }
1579     /* must be before kvm_put_msrs */
1580     ret = kvm_inject_mce_oldstyle(env);
1581     if (ret < 0) {
1582         return ret;
1583     }
1584     ret = kvm_put_msrs(env, level);
1585     if (ret < 0) {
1586         return ret;
1587     }
1588     if (level >= KVM_PUT_RESET_STATE) {
1589         ret = kvm_put_mp_state(env);
1590         if (ret < 0) {
1591             return ret;
1592         }
1593         ret = kvm_put_apic(env);
1594         if (ret < 0) {
1595             return ret;
1596         }
1597     }
1598     ret = kvm_put_vcpu_events(env, level);
1599     if (ret < 0) {
1600         return ret;
1601     }
1602     ret = kvm_put_debugregs(env);
1603     if (ret < 0) {
1604         return ret;
1605     }
1606     /* must be last */
1607     ret = kvm_guest_debug_workarounds(env);
1608     if (ret < 0) {
1609         return ret;
1610     }
1611     return 0;
1612 }
1613
1614 int kvm_arch_get_registers(CPUX86State *env)
1615 {
1616     int ret;
1617
1618     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1619
1620     ret = kvm_getput_regs(env, 0);
1621     if (ret < 0) {
1622         return ret;
1623     }
1624     ret = kvm_get_xsave(env);
1625     if (ret < 0) {
1626         return ret;
1627     }
1628     ret = kvm_get_xcrs(env);
1629     if (ret < 0) {
1630         return ret;
1631     }
1632     ret = kvm_get_sregs(env);
1633     if (ret < 0) {
1634         return ret;
1635     }
1636     ret = kvm_get_msrs(env);
1637     if (ret < 0) {
1638         return ret;
1639     }
1640     ret = kvm_get_mp_state(env);
1641     if (ret < 0) {
1642         return ret;
1643     }
1644     ret = kvm_get_apic(env);
1645     if (ret < 0) {
1646         return ret;
1647     }
1648     ret = kvm_get_vcpu_events(env);
1649     if (ret < 0) {
1650         return ret;
1651     }
1652     ret = kvm_get_debugregs(env);
1653     if (ret < 0) {
1654         return ret;
1655     }
1656     return 0;
1657 }
1658
1659 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1660 {
1661     int ret;
1662
1663     /* Inject NMI */
1664     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1665         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1666         DPRINTF("injected NMI\n");
1667         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1668         if (ret < 0) {
1669             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1670                     strerror(-ret));
1671         }
1672     }
1673
1674     if (!kvm_irqchip_in_kernel()) {
1675         /* Force the VCPU out of its inner loop to process any INIT requests
1676          * or pending TPR access reports. */
1677         if (env->interrupt_request &
1678             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1679             env->exit_request = 1;
1680         }
1681
1682         /* Try to inject an interrupt if the guest can accept it */
1683         if (run->ready_for_interrupt_injection &&
1684             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1685             (env->eflags & IF_MASK)) {
1686             int irq;
1687
1688             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1689             irq = cpu_get_pic_interrupt(env);
1690             if (irq >= 0) {
1691                 struct kvm_interrupt intr;
1692
1693                 intr.irq = irq;
1694                 DPRINTF("injected interrupt %d\n", irq);
1695                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1696                 if (ret < 0) {
1697                     fprintf(stderr,
1698                             "KVM: injection failed, interrupt lost (%s)\n",
1699                             strerror(-ret));
1700                 }
1701             }
1702         }
1703
1704         /* If we have an interrupt but the guest is not ready to receive an
1705          * interrupt, request an interrupt window exit.  This will
1706          * cause a return to userspace as soon as the guest is ready to
1707          * receive interrupts. */
1708         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1709             run->request_interrupt_window = 1;
1710         } else {
1711             run->request_interrupt_window = 0;
1712         }
1713
1714         DPRINTF("setting tpr\n");
1715         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1716     }
1717 }
1718
1719 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1720 {
1721     if (run->if_flag) {
1722         env->eflags |= IF_MASK;
1723     } else {
1724         env->eflags &= ~IF_MASK;
1725     }
1726     cpu_set_apic_tpr(env->apic_state, run->cr8);
1727     cpu_set_apic_base(env->apic_state, run->apic_base);
1728 }
1729
1730 int kvm_arch_process_async_events(CPUX86State *env)
1731 {
1732     X86CPU *cpu = x86_env_get_cpu(env);
1733
1734     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1735         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1736         assert(env->mcg_cap);
1737
1738         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1739
1740         kvm_cpu_synchronize_state(env);
1741
1742         if (env->exception_injected == EXCP08_DBLE) {
1743             /* this means triple fault */
1744             qemu_system_reset_request();
1745             env->exit_request = 1;
1746             return 0;
1747         }
1748         env->exception_injected = EXCP12_MCHK;
1749         env->has_error_code = 0;
1750
1751         env->halted = 0;
1752         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1753             env->mp_state = KVM_MP_STATE_RUNNABLE;
1754         }
1755     }
1756
1757     if (kvm_irqchip_in_kernel()) {
1758         return 0;
1759     }
1760
1761     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1762         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1763         apic_poll_irq(env->apic_state);
1764     }
1765     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1766          (env->eflags & IF_MASK)) ||
1767         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1768         env->halted = 0;
1769     }
1770     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1771         kvm_cpu_synchronize_state(env);
1772         do_cpu_init(cpu);
1773     }
1774     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1775         kvm_cpu_synchronize_state(env);
1776         do_cpu_sipi(cpu);
1777     }
1778     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1779         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1780         kvm_cpu_synchronize_state(env);
1781         apic_handle_tpr_access_report(env->apic_state, env->eip,
1782                                       env->tpr_access_type);
1783     }
1784
1785     return env->halted;
1786 }
1787
1788 static int kvm_handle_halt(CPUX86State *env)
1789 {
1790     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1791           (env->eflags & IF_MASK)) &&
1792         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1793         env->halted = 1;
1794         return EXCP_HLT;
1795     }
1796
1797     return 0;
1798 }
1799
1800 static int kvm_handle_tpr_access(CPUX86State *env)
1801 {
1802     struct kvm_run *run = env->kvm_run;
1803
1804     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1805                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1806                                                            : TPR_ACCESS_READ);
1807     return 1;
1808 }
1809
1810 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1811 {
1812     static const uint8_t int3 = 0xcc;
1813
1814     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1815         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1816         return -EINVAL;
1817     }
1818     return 0;
1819 }
1820
1821 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1822 {
1823     uint8_t int3;
1824
1825     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1826         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1827         return -EINVAL;
1828     }
1829     return 0;
1830 }
1831
1832 static struct {
1833     target_ulong addr;
1834     int len;
1835     int type;
1836 } hw_breakpoint[4];
1837
1838 static int nb_hw_breakpoint;
1839
1840 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1841 {
1842     int n;
1843
1844     for (n = 0; n < nb_hw_breakpoint; n++) {
1845         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1846             (hw_breakpoint[n].len == len || len == -1)) {
1847             return n;
1848         }
1849     }
1850     return -1;
1851 }
1852
1853 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1854                                   target_ulong len, int type)
1855 {
1856     switch (type) {
1857     case GDB_BREAKPOINT_HW:
1858         len = 1;
1859         break;
1860     case GDB_WATCHPOINT_WRITE:
1861     case GDB_WATCHPOINT_ACCESS:
1862         switch (len) {
1863         case 1:
1864             break;
1865         case 2:
1866         case 4:
1867         case 8:
1868             if (addr & (len - 1)) {
1869                 return -EINVAL;
1870             }
1871             break;
1872         default:
1873             return -EINVAL;
1874         }
1875         break;
1876     default:
1877         return -ENOSYS;
1878     }
1879
1880     if (nb_hw_breakpoint == 4) {
1881         return -ENOBUFS;
1882     }
1883     if (find_hw_breakpoint(addr, len, type) >= 0) {
1884         return -EEXIST;
1885     }
1886     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1887     hw_breakpoint[nb_hw_breakpoint].len = len;
1888     hw_breakpoint[nb_hw_breakpoint].type = type;
1889     nb_hw_breakpoint++;
1890
1891     return 0;
1892 }
1893
1894 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1895                                   target_ulong len, int type)
1896 {
1897     int n;
1898
1899     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1900     if (n < 0) {
1901         return -ENOENT;
1902     }
1903     nb_hw_breakpoint--;
1904     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1905
1906     return 0;
1907 }
1908
1909 void kvm_arch_remove_all_hw_breakpoints(void)
1910 {
1911     nb_hw_breakpoint = 0;
1912 }
1913
1914 static CPUWatchpoint hw_watchpoint;
1915
1916 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1917 {
1918     int ret = 0;
1919     int n;
1920
1921     if (arch_info->exception == 1) {
1922         if (arch_info->dr6 & (1 << 14)) {
1923             if (cpu_single_env->singlestep_enabled) {
1924                 ret = EXCP_DEBUG;
1925             }
1926         } else {
1927             for (n = 0; n < 4; n++) {
1928                 if (arch_info->dr6 & (1 << n)) {
1929                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1930                     case 0x0:
1931                         ret = EXCP_DEBUG;
1932                         break;
1933                     case 0x1:
1934                         ret = EXCP_DEBUG;
1935                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1936                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1937                         hw_watchpoint.flags = BP_MEM_WRITE;
1938                         break;
1939                     case 0x3:
1940                         ret = EXCP_DEBUG;
1941                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1942                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1943                         hw_watchpoint.flags = BP_MEM_ACCESS;
1944                         break;
1945                     }
1946                 }
1947             }
1948         }
1949     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1950         ret = EXCP_DEBUG;
1951     }
1952     if (ret == 0) {
1953         cpu_synchronize_state(cpu_single_env);
1954         assert(cpu_single_env->exception_injected == -1);
1955
1956         /* pass to guest */
1957         cpu_single_env->exception_injected = arch_info->exception;
1958         cpu_single_env->has_error_code = 0;
1959     }
1960
1961     return ret;
1962 }
1963
1964 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1965 {
1966     const uint8_t type_code[] = {
1967         [GDB_BREAKPOINT_HW] = 0x0,
1968         [GDB_WATCHPOINT_WRITE] = 0x1,
1969         [GDB_WATCHPOINT_ACCESS] = 0x3
1970     };
1971     const uint8_t len_code[] = {
1972         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1973     };
1974     int n;
1975
1976     if (kvm_sw_breakpoints_active(env)) {
1977         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1978     }
1979     if (nb_hw_breakpoint > 0) {
1980         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1981         dbg->arch.debugreg[7] = 0x0600;
1982         for (n = 0; n < nb_hw_breakpoint; n++) {
1983             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1984             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1985                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1986                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1987         }
1988     }
1989 }
1990
1991 static bool host_supports_vmx(void)
1992 {
1993     uint32_t ecx, unused;
1994
1995     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1996     return ecx & CPUID_EXT_VMX;
1997 }
1998
1999 #define VMX_INVALID_GUEST_STATE 0x80000021
2000
2001 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2002 {
2003     uint64_t code;
2004     int ret;
2005
2006     switch (run->exit_reason) {
2007     case KVM_EXIT_HLT:
2008         DPRINTF("handle_hlt\n");
2009         ret = kvm_handle_halt(env);
2010         break;
2011     case KVM_EXIT_SET_TPR:
2012         ret = 0;
2013         break;
2014     case KVM_EXIT_TPR_ACCESS:
2015         ret = kvm_handle_tpr_access(env);
2016         break;
2017     case KVM_EXIT_FAIL_ENTRY:
2018         code = run->fail_entry.hardware_entry_failure_reason;
2019         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2020                 code);
2021         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2022             fprintf(stderr,
2023                     "\nIf you're running a guest on an Intel machine without "
2024                         "unrestricted mode\n"
2025                     "support, the failure can be most likely due to the guest "
2026                         "entering an invalid\n"
2027                     "state for Intel VT. For example, the guest maybe running "
2028                         "in big real mode\n"
2029                     "which is not supported on less recent Intel processors."
2030                         "\n\n");
2031         }
2032         ret = -1;
2033         break;
2034     case KVM_EXIT_EXCEPTION:
2035         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2036                 run->ex.exception, run->ex.error_code);
2037         ret = -1;
2038         break;
2039     case KVM_EXIT_DEBUG:
2040         DPRINTF("kvm_exit_debug\n");
2041         ret = kvm_handle_debug(&run->debug.arch);
2042         break;
2043     default:
2044         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2045         ret = -1;
2046         break;
2047     }
2048
2049     return ret;
2050 }
2051
2052 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2053 {
2054     kvm_cpu_synchronize_state(env);
2055     return !(env->cr[0] & CR0_PE_MASK) ||
2056            ((env->segs[R_CS].selector  & 3) != 3);
2057 }
2058
2059 void kvm_arch_init_irq_routing(KVMState *s)
2060 {
2061     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2062         /* If kernel can't do irq routing, interrupt source
2063          * override 0->2 cannot be set up as required by HPET.
2064          * So we have to disable it.
2065          */
2066         no_hpet = 1;
2067     }
2068     /* We know at this point that we're using the in-kernel
2069      * irqchip, so we can use irqfds, and on x86 we know
2070      * we can use msi via irqfd and GSI routing.
2071      */
2072     kvm_irqfds_allowed = true;
2073     kvm_msi_via_irqfd_allowed = true;
2074     kvm_gsi_routing_allowed = true;
2075 }
2076
2077 /* Classic KVM device assignment interface. Will remain x86 only. */
2078 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2079                           uint32_t flags, uint32_t *dev_id)
2080 {
2081     struct kvm_assigned_pci_dev dev_data = {
2082         .segnr = dev_addr->domain,
2083         .busnr = dev_addr->bus,
2084         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2085         .flags = flags,
2086     };
2087     int ret;
2088
2089     dev_data.assigned_dev_id =
2090         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2091
2092     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2093     if (ret < 0) {
2094         return ret;
2095     }
2096
2097     *dev_id = dev_data.assigned_dev_id;
2098
2099     return 0;
2100 }
2101
2102 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2103 {
2104     struct kvm_assigned_pci_dev dev_data = {
2105         .assigned_dev_id = dev_id,
2106     };
2107
2108     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2109 }
2110
2111 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2112                                    uint32_t irq_type, uint32_t guest_irq)
2113 {
2114     struct kvm_assigned_irq assigned_irq = {
2115         .assigned_dev_id = dev_id,
2116         .guest_irq = guest_irq,
2117         .flags = irq_type,
2118     };
2119
2120     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2121         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2122     } else {
2123         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2124     }
2125 }
2126
2127 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2128                            uint32_t guest_irq)
2129 {
2130     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2131         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2132
2133     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2134 }
2135
2136 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2137 {
2138     struct kvm_assigned_pci_dev dev_data = {
2139         .assigned_dev_id = dev_id,
2140         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2141     };
2142
2143     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2144 }
2145
2146 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2147                                      uint32_t type)
2148 {
2149     struct kvm_assigned_irq assigned_irq = {
2150         .assigned_dev_id = dev_id,
2151         .flags = type,
2152     };
2153
2154     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2155 }
2156
2157 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2158 {
2159     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2160         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2161 }
2162
2163 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2164 {
2165     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2166                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2167 }
2168
2169 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2170 {
2171     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2172                                                 KVM_DEV_IRQ_HOST_MSI);
2173 }
2174
2175 bool kvm_device_msix_supported(KVMState *s)
2176 {
2177     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2178      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2179     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2180 }
2181
2182 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2183                                  uint32_t nr_vectors)
2184 {
2185     struct kvm_assigned_msix_nr msix_nr = {
2186         .assigned_dev_id = dev_id,
2187         .entry_nr = nr_vectors,
2188     };
2189
2190     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2191 }
2192
2193 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2194                                int virq)
2195 {
2196     struct kvm_assigned_msix_entry msix_entry = {
2197         .assigned_dev_id = dev_id,
2198         .gsi = virq,
2199         .entry = vector,
2200     };
2201
2202     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2203 }
2204
2205 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2206 {
2207     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2208                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2209 }
2210
2211 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2212 {
2213     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2214                                                 KVM_DEV_IRQ_HOST_MSIX);
2215 }