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kvm: reset state from the CPU's reset method
[mirror_qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include <asm/hyperv.h>
35 #include "hw/pci/pci.h"
36
37 //#define DEBUG_KVM
38
39 #ifdef DEBUG_KVM
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF(fmt, ...) \
44 do { } while (0)
45 #endif
46
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
49
50 #ifndef BUS_MCEERR_AR
51 #define BUS_MCEERR_AR 4
52 #endif
53 #ifndef BUS_MCEERR_AO
54 #define BUS_MCEERR_AO 5
55 #endif
56
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR),
59 KVM_CAP_INFO(EXT_CPUID),
60 KVM_CAP_INFO(MP_STATE),
61 KVM_CAP_LAST_INFO
62 };
63
64 static bool has_msr_star;
65 static bool has_msr_hsave_pa;
66 static bool has_msr_tsc_adjust;
67 static bool has_msr_tsc_deadline;
68 static bool has_msr_feature_control;
69 static bool has_msr_async_pf_en;
70 static bool has_msr_pv_eoi_en;
71 static bool has_msr_misc_enable;
72 static bool has_msr_bndcfgs;
73 static bool has_msr_kvm_steal_time;
74 static int lm_capable_kernel;
75 static bool has_msr_hv_hypercall;
76 static bool has_msr_hv_vapic;
77 static bool has_msr_hv_tsc;
78
79 static bool has_msr_architectural_pmu;
80 static uint32_t num_architectural_pmu_counters;
81
82 bool kvm_allows_irq0_override(void)
83 {
84 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
85 }
86
87 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
88 {
89 struct kvm_cpuid2 *cpuid;
90 int r, size;
91
92 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
93 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
94 cpuid->nent = max;
95 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
96 if (r == 0 && cpuid->nent >= max) {
97 r = -E2BIG;
98 }
99 if (r < 0) {
100 if (r == -E2BIG) {
101 g_free(cpuid);
102 return NULL;
103 } else {
104 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
105 strerror(-r));
106 exit(1);
107 }
108 }
109 return cpuid;
110 }
111
112 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
113 * for all entries.
114 */
115 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
116 {
117 struct kvm_cpuid2 *cpuid;
118 int max = 1;
119 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
120 max *= 2;
121 }
122 return cpuid;
123 }
124
125 static const struct kvm_para_features {
126 int cap;
127 int feature;
128 } para_features[] = {
129 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
130 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
131 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
132 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
133 };
134
135 static int get_para_features(KVMState *s)
136 {
137 int i, features = 0;
138
139 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
140 if (kvm_check_extension(s, para_features[i].cap)) {
141 features |= (1 << para_features[i].feature);
142 }
143 }
144
145 return features;
146 }
147
148
149 /* Returns the value for a specific register on the cpuid entry
150 */
151 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
152 {
153 uint32_t ret = 0;
154 switch (reg) {
155 case R_EAX:
156 ret = entry->eax;
157 break;
158 case R_EBX:
159 ret = entry->ebx;
160 break;
161 case R_ECX:
162 ret = entry->ecx;
163 break;
164 case R_EDX:
165 ret = entry->edx;
166 break;
167 }
168 return ret;
169 }
170
171 /* Find matching entry for function/index on kvm_cpuid2 struct
172 */
173 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
174 uint32_t function,
175 uint32_t index)
176 {
177 int i;
178 for (i = 0; i < cpuid->nent; ++i) {
179 if (cpuid->entries[i].function == function &&
180 cpuid->entries[i].index == index) {
181 return &cpuid->entries[i];
182 }
183 }
184 /* not found: */
185 return NULL;
186 }
187
188 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
189 uint32_t index, int reg)
190 {
191 struct kvm_cpuid2 *cpuid;
192 uint32_t ret = 0;
193 uint32_t cpuid_1_edx;
194 bool found = false;
195
196 cpuid = get_supported_cpuid(s);
197
198 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
199 if (entry) {
200 found = true;
201 ret = cpuid_entry_get_reg(entry, reg);
202 }
203
204 /* Fixups for the data returned by KVM, below */
205
206 if (function == 1 && reg == R_EDX) {
207 /* KVM before 2.6.30 misreports the following features */
208 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
209 } else if (function == 1 && reg == R_ECX) {
210 /* We can set the hypervisor flag, even if KVM does not return it on
211 * GET_SUPPORTED_CPUID
212 */
213 ret |= CPUID_EXT_HYPERVISOR;
214 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
215 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
216 * and the irqchip is in the kernel.
217 */
218 if (kvm_irqchip_in_kernel() &&
219 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
220 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
221 }
222
223 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
224 * without the in-kernel irqchip
225 */
226 if (!kvm_irqchip_in_kernel()) {
227 ret &= ~CPUID_EXT_X2APIC;
228 }
229 } else if (function == 0x80000001 && reg == R_EDX) {
230 /* On Intel, kvm returns cpuid according to the Intel spec,
231 * so add missing bits according to the AMD spec:
232 */
233 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
234 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
235 }
236
237 g_free(cpuid);
238
239 /* fallback for older kernels */
240 if ((function == KVM_CPUID_FEATURES) && !found) {
241 ret = get_para_features(s);
242 }
243
244 return ret;
245 }
246
247 typedef struct HWPoisonPage {
248 ram_addr_t ram_addr;
249 QLIST_ENTRY(HWPoisonPage) list;
250 } HWPoisonPage;
251
252 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
253 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
254
255 static void kvm_unpoison_all(void *param)
256 {
257 HWPoisonPage *page, *next_page;
258
259 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
260 QLIST_REMOVE(page, list);
261 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
262 g_free(page);
263 }
264 }
265
266 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
267 {
268 HWPoisonPage *page;
269
270 QLIST_FOREACH(page, &hwpoison_page_list, list) {
271 if (page->ram_addr == ram_addr) {
272 return;
273 }
274 }
275 page = g_malloc(sizeof(HWPoisonPage));
276 page->ram_addr = ram_addr;
277 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
278 }
279
280 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
281 int *max_banks)
282 {
283 int r;
284
285 r = kvm_check_extension(s, KVM_CAP_MCE);
286 if (r > 0) {
287 *max_banks = r;
288 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
289 }
290 return -ENOSYS;
291 }
292
293 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
294 {
295 CPUX86State *env = &cpu->env;
296 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
297 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
298 uint64_t mcg_status = MCG_STATUS_MCIP;
299
300 if (code == BUS_MCEERR_AR) {
301 status |= MCI_STATUS_AR | 0x134;
302 mcg_status |= MCG_STATUS_EIPV;
303 } else {
304 status |= 0xc0;
305 mcg_status |= MCG_STATUS_RIPV;
306 }
307 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
308 (MCM_ADDR_PHYS << 6) | 0xc,
309 cpu_x86_support_mca_broadcast(env) ?
310 MCE_INJECT_BROADCAST : 0);
311 }
312
313 static void hardware_memory_error(void)
314 {
315 fprintf(stderr, "Hardware memory error!\n");
316 exit(1);
317 }
318
319 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
320 {
321 X86CPU *cpu = X86_CPU(c);
322 CPUX86State *env = &cpu->env;
323 ram_addr_t ram_addr;
324 hwaddr paddr;
325
326 if ((env->mcg_cap & MCG_SER_P) && addr
327 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
328 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
329 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
330 fprintf(stderr, "Hardware memory error for memory used by "
331 "QEMU itself instead of guest system!\n");
332 /* Hope we are lucky for AO MCE */
333 if (code == BUS_MCEERR_AO) {
334 return 0;
335 } else {
336 hardware_memory_error();
337 }
338 }
339 kvm_hwpoison_page_add(ram_addr);
340 kvm_mce_inject(cpu, paddr, code);
341 } else {
342 if (code == BUS_MCEERR_AO) {
343 return 0;
344 } else if (code == BUS_MCEERR_AR) {
345 hardware_memory_error();
346 } else {
347 return 1;
348 }
349 }
350 return 0;
351 }
352
353 int kvm_arch_on_sigbus(int code, void *addr)
354 {
355 X86CPU *cpu = X86_CPU(first_cpu);
356
357 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
358 ram_addr_t ram_addr;
359 hwaddr paddr;
360
361 /* Hope we are lucky for AO MCE */
362 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
363 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
364 addr, &paddr)) {
365 fprintf(stderr, "Hardware memory error for memory used by "
366 "QEMU itself instead of guest system!: %p\n", addr);
367 return 0;
368 }
369 kvm_hwpoison_page_add(ram_addr);
370 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
371 } else {
372 if (code == BUS_MCEERR_AO) {
373 return 0;
374 } else if (code == BUS_MCEERR_AR) {
375 hardware_memory_error();
376 } else {
377 return 1;
378 }
379 }
380 return 0;
381 }
382
383 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
384 {
385 CPUX86State *env = &cpu->env;
386
387 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
388 unsigned int bank, bank_num = env->mcg_cap & 0xff;
389 struct kvm_x86_mce mce;
390
391 env->exception_injected = -1;
392
393 /*
394 * There must be at least one bank in use if an MCE is pending.
395 * Find it and use its values for the event injection.
396 */
397 for (bank = 0; bank < bank_num; bank++) {
398 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
399 break;
400 }
401 }
402 assert(bank < bank_num);
403
404 mce.bank = bank;
405 mce.status = env->mce_banks[bank * 4 + 1];
406 mce.mcg_status = env->mcg_status;
407 mce.addr = env->mce_banks[bank * 4 + 2];
408 mce.misc = env->mce_banks[bank * 4 + 3];
409
410 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
411 }
412 return 0;
413 }
414
415 static void cpu_update_state(void *opaque, int running, RunState state)
416 {
417 CPUX86State *env = opaque;
418
419 if (running) {
420 env->tsc_valid = false;
421 }
422 }
423
424 unsigned long kvm_arch_vcpu_id(CPUState *cs)
425 {
426 X86CPU *cpu = X86_CPU(cs);
427 return cpu->env.cpuid_apic_id;
428 }
429
430 #ifndef KVM_CPUID_SIGNATURE_NEXT
431 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
432 #endif
433
434 static bool hyperv_hypercall_available(X86CPU *cpu)
435 {
436 return cpu->hyperv_vapic ||
437 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
438 }
439
440 static bool hyperv_enabled(X86CPU *cpu)
441 {
442 CPUState *cs = CPU(cpu);
443 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
444 (hyperv_hypercall_available(cpu) ||
445 cpu->hyperv_time ||
446 cpu->hyperv_relaxed_timing);
447 }
448
449 #define KVM_MAX_CPUID_ENTRIES 100
450
451 int kvm_arch_init_vcpu(CPUState *cs)
452 {
453 struct {
454 struct kvm_cpuid2 cpuid;
455 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
456 } QEMU_PACKED cpuid_data;
457 X86CPU *cpu = X86_CPU(cs);
458 CPUX86State *env = &cpu->env;
459 uint32_t limit, i, j, cpuid_i;
460 uint32_t unused;
461 struct kvm_cpuid_entry2 *c;
462 uint32_t signature[3];
463 int kvm_base = KVM_CPUID_SIGNATURE;
464 int r;
465
466 memset(&cpuid_data, 0, sizeof(cpuid_data));
467
468 cpuid_i = 0;
469
470 /* Paravirtualization CPUIDs */
471 if (hyperv_enabled(cpu)) {
472 c = &cpuid_data.entries[cpuid_i++];
473 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
474 memcpy(signature, "Microsoft Hv", 12);
475 c->eax = HYPERV_CPUID_MIN;
476 c->ebx = signature[0];
477 c->ecx = signature[1];
478 c->edx = signature[2];
479
480 c = &cpuid_data.entries[cpuid_i++];
481 c->function = HYPERV_CPUID_INTERFACE;
482 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
483 c->eax = signature[0];
484 c->ebx = 0;
485 c->ecx = 0;
486 c->edx = 0;
487
488 c = &cpuid_data.entries[cpuid_i++];
489 c->function = HYPERV_CPUID_VERSION;
490 c->eax = 0x00001bbc;
491 c->ebx = 0x00060001;
492
493 c = &cpuid_data.entries[cpuid_i++];
494 c->function = HYPERV_CPUID_FEATURES;
495 if (cpu->hyperv_relaxed_timing) {
496 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
497 }
498 if (cpu->hyperv_vapic) {
499 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
500 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
501 has_msr_hv_vapic = true;
502 }
503 if (cpu->hyperv_time &&
504 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
505 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
506 c->eax |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
507 c->eax |= 0x200;
508 has_msr_hv_tsc = true;
509 }
510 c = &cpuid_data.entries[cpuid_i++];
511 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
512 if (cpu->hyperv_relaxed_timing) {
513 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
514 }
515 if (has_msr_hv_vapic) {
516 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
517 }
518 c->ebx = cpu->hyperv_spinlock_attempts;
519
520 c = &cpuid_data.entries[cpuid_i++];
521 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
522 c->eax = 0x40;
523 c->ebx = 0x40;
524
525 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
526 has_msr_hv_hypercall = true;
527 }
528
529 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
530 c = &cpuid_data.entries[cpuid_i++];
531 c->function = KVM_CPUID_SIGNATURE | kvm_base;
532 c->eax = 0;
533 c->ebx = signature[0];
534 c->ecx = signature[1];
535 c->edx = signature[2];
536
537 c = &cpuid_data.entries[cpuid_i++];
538 c->function = KVM_CPUID_FEATURES | kvm_base;
539 c->eax = env->features[FEAT_KVM];
540
541 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
542
543 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
544
545 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
546
547 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
548
549 for (i = 0; i <= limit; i++) {
550 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
551 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
552 abort();
553 }
554 c = &cpuid_data.entries[cpuid_i++];
555
556 switch (i) {
557 case 2: {
558 /* Keep reading function 2 till all the input is received */
559 int times;
560
561 c->function = i;
562 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
563 KVM_CPUID_FLAG_STATE_READ_NEXT;
564 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
565 times = c->eax & 0xff;
566
567 for (j = 1; j < times; ++j) {
568 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
569 fprintf(stderr, "cpuid_data is full, no space for "
570 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
571 abort();
572 }
573 c = &cpuid_data.entries[cpuid_i++];
574 c->function = i;
575 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
576 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
577 }
578 break;
579 }
580 case 4:
581 case 0xb:
582 case 0xd:
583 for (j = 0; ; j++) {
584 if (i == 0xd && j == 64) {
585 break;
586 }
587 c->function = i;
588 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
589 c->index = j;
590 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
591
592 if (i == 4 && c->eax == 0) {
593 break;
594 }
595 if (i == 0xb && !(c->ecx & 0xff00)) {
596 break;
597 }
598 if (i == 0xd && c->eax == 0) {
599 continue;
600 }
601 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
602 fprintf(stderr, "cpuid_data is full, no space for "
603 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
604 abort();
605 }
606 c = &cpuid_data.entries[cpuid_i++];
607 }
608 break;
609 default:
610 c->function = i;
611 c->flags = 0;
612 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
613 break;
614 }
615 }
616
617 if (limit >= 0x0a) {
618 uint32_t ver;
619
620 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
621 if ((ver & 0xff) > 0) {
622 has_msr_architectural_pmu = true;
623 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
624
625 /* Shouldn't be more than 32, since that's the number of bits
626 * available in EBX to tell us _which_ counters are available.
627 * Play it safe.
628 */
629 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
630 num_architectural_pmu_counters = MAX_GP_COUNTERS;
631 }
632 }
633 }
634
635 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
636
637 for (i = 0x80000000; i <= limit; i++) {
638 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
639 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
640 abort();
641 }
642 c = &cpuid_data.entries[cpuid_i++];
643
644 c->function = i;
645 c->flags = 0;
646 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
647 }
648
649 /* Call Centaur's CPUID instructions they are supported. */
650 if (env->cpuid_xlevel2 > 0) {
651 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
652
653 for (i = 0xC0000000; i <= limit; i++) {
654 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
655 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
656 abort();
657 }
658 c = &cpuid_data.entries[cpuid_i++];
659
660 c->function = i;
661 c->flags = 0;
662 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
663 }
664 }
665
666 cpuid_data.cpuid.nent = cpuid_i;
667
668 if (((env->cpuid_version >> 8)&0xF) >= 6
669 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
670 (CPUID_MCE | CPUID_MCA)
671 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
672 uint64_t mcg_cap;
673 int banks;
674 int ret;
675
676 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
677 if (ret < 0) {
678 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
679 return ret;
680 }
681
682 if (banks > MCE_BANKS_DEF) {
683 banks = MCE_BANKS_DEF;
684 }
685 mcg_cap &= MCE_CAP_DEF;
686 mcg_cap |= banks;
687 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
688 if (ret < 0) {
689 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
690 return ret;
691 }
692
693 env->mcg_cap = mcg_cap;
694 }
695
696 qemu_add_vm_change_state_handler(cpu_update_state, env);
697
698 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
699 if (c) {
700 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
701 !!(c->ecx & CPUID_EXT_SMX);
702 }
703
704 cpuid_data.cpuid.padding = 0;
705 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
706 if (r) {
707 return r;
708 }
709
710 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
711 if (r && env->tsc_khz) {
712 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
713 if (r < 0) {
714 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
715 return r;
716 }
717 }
718
719 if (kvm_has_xsave()) {
720 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
721 }
722
723 return 0;
724 }
725
726 void kvm_arch_reset_vcpu(X86CPU *cpu)
727 {
728 CPUX86State *env = &cpu->env;
729
730 env->exception_injected = -1;
731 env->interrupt_injected = -1;
732 env->xcr0 = 1;
733 if (kvm_irqchip_in_kernel()) {
734 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
735 KVM_MP_STATE_UNINITIALIZED;
736 } else {
737 env->mp_state = KVM_MP_STATE_RUNNABLE;
738 }
739 }
740
741 static int kvm_get_supported_msrs(KVMState *s)
742 {
743 static int kvm_supported_msrs;
744 int ret = 0;
745
746 /* first time */
747 if (kvm_supported_msrs == 0) {
748 struct kvm_msr_list msr_list, *kvm_msr_list;
749
750 kvm_supported_msrs = -1;
751
752 /* Obtain MSR list from KVM. These are the MSRs that we must
753 * save/restore */
754 msr_list.nmsrs = 0;
755 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
756 if (ret < 0 && ret != -E2BIG) {
757 return ret;
758 }
759 /* Old kernel modules had a bug and could write beyond the provided
760 memory. Allocate at least a safe amount of 1K. */
761 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
762 msr_list.nmsrs *
763 sizeof(msr_list.indices[0])));
764
765 kvm_msr_list->nmsrs = msr_list.nmsrs;
766 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
767 if (ret >= 0) {
768 int i;
769
770 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
771 if (kvm_msr_list->indices[i] == MSR_STAR) {
772 has_msr_star = true;
773 continue;
774 }
775 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
776 has_msr_hsave_pa = true;
777 continue;
778 }
779 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
780 has_msr_tsc_adjust = true;
781 continue;
782 }
783 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
784 has_msr_tsc_deadline = true;
785 continue;
786 }
787 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
788 has_msr_misc_enable = true;
789 continue;
790 }
791 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
792 has_msr_bndcfgs = true;
793 continue;
794 }
795 }
796 }
797
798 g_free(kvm_msr_list);
799 }
800
801 return ret;
802 }
803
804 int kvm_arch_init(KVMState *s)
805 {
806 uint64_t identity_base = 0xfffbc000;
807 uint64_t shadow_mem;
808 int ret;
809 struct utsname utsname;
810
811 ret = kvm_get_supported_msrs(s);
812 if (ret < 0) {
813 return ret;
814 }
815
816 uname(&utsname);
817 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
818
819 /*
820 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
821 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
822 * Since these must be part of guest physical memory, we need to allocate
823 * them, both by setting their start addresses in the kernel and by
824 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
825 *
826 * Older KVM versions may not support setting the identity map base. In
827 * that case we need to stick with the default, i.e. a 256K maximum BIOS
828 * size.
829 */
830 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
831 /* Allows up to 16M BIOSes. */
832 identity_base = 0xfeffc000;
833
834 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
835 if (ret < 0) {
836 return ret;
837 }
838 }
839
840 /* Set TSS base one page after EPT identity map. */
841 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
842 if (ret < 0) {
843 return ret;
844 }
845
846 /* Tell fw_cfg to notify the BIOS to reserve the range. */
847 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
848 if (ret < 0) {
849 fprintf(stderr, "e820_add_entry() table is full\n");
850 return ret;
851 }
852 qemu_register_reset(kvm_unpoison_all, NULL);
853
854 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
855 "kvm_shadow_mem", -1);
856 if (shadow_mem != -1) {
857 shadow_mem /= 4096;
858 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
859 if (ret < 0) {
860 return ret;
861 }
862 }
863 return 0;
864 }
865
866 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
867 {
868 lhs->selector = rhs->selector;
869 lhs->base = rhs->base;
870 lhs->limit = rhs->limit;
871 lhs->type = 3;
872 lhs->present = 1;
873 lhs->dpl = 3;
874 lhs->db = 0;
875 lhs->s = 1;
876 lhs->l = 0;
877 lhs->g = 0;
878 lhs->avl = 0;
879 lhs->unusable = 0;
880 }
881
882 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
883 {
884 unsigned flags = rhs->flags;
885 lhs->selector = rhs->selector;
886 lhs->base = rhs->base;
887 lhs->limit = rhs->limit;
888 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
889 lhs->present = (flags & DESC_P_MASK) != 0;
890 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
891 lhs->db = (flags >> DESC_B_SHIFT) & 1;
892 lhs->s = (flags & DESC_S_MASK) != 0;
893 lhs->l = (flags >> DESC_L_SHIFT) & 1;
894 lhs->g = (flags & DESC_G_MASK) != 0;
895 lhs->avl = (flags & DESC_AVL_MASK) != 0;
896 lhs->unusable = 0;
897 lhs->padding = 0;
898 }
899
900 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
901 {
902 lhs->selector = rhs->selector;
903 lhs->base = rhs->base;
904 lhs->limit = rhs->limit;
905 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
906 (rhs->present * DESC_P_MASK) |
907 (rhs->dpl << DESC_DPL_SHIFT) |
908 (rhs->db << DESC_B_SHIFT) |
909 (rhs->s * DESC_S_MASK) |
910 (rhs->l << DESC_L_SHIFT) |
911 (rhs->g * DESC_G_MASK) |
912 (rhs->avl * DESC_AVL_MASK);
913 }
914
915 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
916 {
917 if (set) {
918 *kvm_reg = *qemu_reg;
919 } else {
920 *qemu_reg = *kvm_reg;
921 }
922 }
923
924 static int kvm_getput_regs(X86CPU *cpu, int set)
925 {
926 CPUX86State *env = &cpu->env;
927 struct kvm_regs regs;
928 int ret = 0;
929
930 if (!set) {
931 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
932 if (ret < 0) {
933 return ret;
934 }
935 }
936
937 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
938 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
939 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
940 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
941 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
942 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
943 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
944 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
945 #ifdef TARGET_X86_64
946 kvm_getput_reg(&regs.r8, &env->regs[8], set);
947 kvm_getput_reg(&regs.r9, &env->regs[9], set);
948 kvm_getput_reg(&regs.r10, &env->regs[10], set);
949 kvm_getput_reg(&regs.r11, &env->regs[11], set);
950 kvm_getput_reg(&regs.r12, &env->regs[12], set);
951 kvm_getput_reg(&regs.r13, &env->regs[13], set);
952 kvm_getput_reg(&regs.r14, &env->regs[14], set);
953 kvm_getput_reg(&regs.r15, &env->regs[15], set);
954 #endif
955
956 kvm_getput_reg(&regs.rflags, &env->eflags, set);
957 kvm_getput_reg(&regs.rip, &env->eip, set);
958
959 if (set) {
960 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
961 }
962
963 return ret;
964 }
965
966 static int kvm_put_fpu(X86CPU *cpu)
967 {
968 CPUX86State *env = &cpu->env;
969 struct kvm_fpu fpu;
970 int i;
971
972 memset(&fpu, 0, sizeof fpu);
973 fpu.fsw = env->fpus & ~(7 << 11);
974 fpu.fsw |= (env->fpstt & 7) << 11;
975 fpu.fcw = env->fpuc;
976 fpu.last_opcode = env->fpop;
977 fpu.last_ip = env->fpip;
978 fpu.last_dp = env->fpdp;
979 for (i = 0; i < 8; ++i) {
980 fpu.ftwx |= (!env->fptags[i]) << i;
981 }
982 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
983 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
984 fpu.mxcsr = env->mxcsr;
985
986 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
987 }
988
989 #define XSAVE_FCW_FSW 0
990 #define XSAVE_FTW_FOP 1
991 #define XSAVE_CWD_RIP 2
992 #define XSAVE_CWD_RDP 4
993 #define XSAVE_MXCSR 6
994 #define XSAVE_ST_SPACE 8
995 #define XSAVE_XMM_SPACE 40
996 #define XSAVE_XSTATE_BV 128
997 #define XSAVE_YMMH_SPACE 144
998 #define XSAVE_BNDREGS 240
999 #define XSAVE_BNDCSR 256
1000
1001 static int kvm_put_xsave(X86CPU *cpu)
1002 {
1003 CPUX86State *env = &cpu->env;
1004 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1005 uint16_t cwd, swd, twd;
1006 int i, r;
1007
1008 if (!kvm_has_xsave()) {
1009 return kvm_put_fpu(cpu);
1010 }
1011
1012 memset(xsave, 0, sizeof(struct kvm_xsave));
1013 twd = 0;
1014 swd = env->fpus & ~(7 << 11);
1015 swd |= (env->fpstt & 7) << 11;
1016 cwd = env->fpuc;
1017 for (i = 0; i < 8; ++i) {
1018 twd |= (!env->fptags[i]) << i;
1019 }
1020 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
1021 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
1022 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
1023 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
1024 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
1025 sizeof env->fpregs);
1026 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
1027 sizeof env->xmm_regs);
1028 xsave->region[XSAVE_MXCSR] = env->mxcsr;
1029 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
1030 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
1031 sizeof env->ymmh_regs);
1032 memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
1033 sizeof env->bnd_regs);
1034 memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
1035 sizeof(env->bndcs_regs));
1036 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1037 return r;
1038 }
1039
1040 static int kvm_put_xcrs(X86CPU *cpu)
1041 {
1042 CPUX86State *env = &cpu->env;
1043 struct kvm_xcrs xcrs;
1044
1045 if (!kvm_has_xcrs()) {
1046 return 0;
1047 }
1048
1049 xcrs.nr_xcrs = 1;
1050 xcrs.flags = 0;
1051 xcrs.xcrs[0].xcr = 0;
1052 xcrs.xcrs[0].value = env->xcr0;
1053 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1054 }
1055
1056 static int kvm_put_sregs(X86CPU *cpu)
1057 {
1058 CPUX86State *env = &cpu->env;
1059 struct kvm_sregs sregs;
1060
1061 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1062 if (env->interrupt_injected >= 0) {
1063 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1064 (uint64_t)1 << (env->interrupt_injected % 64);
1065 }
1066
1067 if ((env->eflags & VM_MASK)) {
1068 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1069 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1070 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1071 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1072 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1073 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1074 } else {
1075 set_seg(&sregs.cs, &env->segs[R_CS]);
1076 set_seg(&sregs.ds, &env->segs[R_DS]);
1077 set_seg(&sregs.es, &env->segs[R_ES]);
1078 set_seg(&sregs.fs, &env->segs[R_FS]);
1079 set_seg(&sregs.gs, &env->segs[R_GS]);
1080 set_seg(&sregs.ss, &env->segs[R_SS]);
1081 }
1082
1083 set_seg(&sregs.tr, &env->tr);
1084 set_seg(&sregs.ldt, &env->ldt);
1085
1086 sregs.idt.limit = env->idt.limit;
1087 sregs.idt.base = env->idt.base;
1088 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1089 sregs.gdt.limit = env->gdt.limit;
1090 sregs.gdt.base = env->gdt.base;
1091 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1092
1093 sregs.cr0 = env->cr[0];
1094 sregs.cr2 = env->cr[2];
1095 sregs.cr3 = env->cr[3];
1096 sregs.cr4 = env->cr[4];
1097
1098 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1099 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1100
1101 sregs.efer = env->efer;
1102
1103 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1104 }
1105
1106 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1107 uint32_t index, uint64_t value)
1108 {
1109 entry->index = index;
1110 entry->data = value;
1111 }
1112
1113 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1114 {
1115 CPUX86State *env = &cpu->env;
1116 struct {
1117 struct kvm_msrs info;
1118 struct kvm_msr_entry entries[1];
1119 } msr_data;
1120 struct kvm_msr_entry *msrs = msr_data.entries;
1121
1122 if (!has_msr_tsc_deadline) {
1123 return 0;
1124 }
1125
1126 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1127
1128 msr_data.info.nmsrs = 1;
1129
1130 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1131 }
1132
1133 /*
1134 * Provide a separate write service for the feature control MSR in order to
1135 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1136 * before writing any other state because forcibly leaving nested mode
1137 * invalidates the VCPU state.
1138 */
1139 static int kvm_put_msr_feature_control(X86CPU *cpu)
1140 {
1141 struct {
1142 struct kvm_msrs info;
1143 struct kvm_msr_entry entry;
1144 } msr_data;
1145
1146 kvm_msr_entry_set(&msr_data.entry, MSR_IA32_FEATURE_CONTROL,
1147 cpu->env.msr_ia32_feature_control);
1148 msr_data.info.nmsrs = 1;
1149 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1150 }
1151
1152 static int kvm_put_msrs(X86CPU *cpu, int level)
1153 {
1154 CPUX86State *env = &cpu->env;
1155 struct {
1156 struct kvm_msrs info;
1157 struct kvm_msr_entry entries[100];
1158 } msr_data;
1159 struct kvm_msr_entry *msrs = msr_data.entries;
1160 int n = 0, i;
1161
1162 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1163 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1164 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1165 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1166 if (has_msr_star) {
1167 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1168 }
1169 if (has_msr_hsave_pa) {
1170 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1171 }
1172 if (has_msr_tsc_adjust) {
1173 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1174 }
1175 if (has_msr_misc_enable) {
1176 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1177 env->msr_ia32_misc_enable);
1178 }
1179 if (has_msr_bndcfgs) {
1180 kvm_msr_entry_set(&msrs[n++], MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1181 }
1182 #ifdef TARGET_X86_64
1183 if (lm_capable_kernel) {
1184 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1185 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1186 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1187 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1188 }
1189 #endif
1190 /*
1191 * The following MSRs have side effects on the guest or are too heavy
1192 * for normal writeback. Limit them to reset or full state updates.
1193 */
1194 if (level >= KVM_PUT_RESET_STATE) {
1195 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1196 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1197 env->system_time_msr);
1198 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1199 if (has_msr_async_pf_en) {
1200 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1201 env->async_pf_en_msr);
1202 }
1203 if (has_msr_pv_eoi_en) {
1204 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1205 env->pv_eoi_en_msr);
1206 }
1207 if (has_msr_kvm_steal_time) {
1208 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1209 env->steal_time_msr);
1210 }
1211 if (has_msr_architectural_pmu) {
1212 /* Stop the counter. */
1213 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1214 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1215
1216 /* Set the counter values. */
1217 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1218 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1219 env->msr_fixed_counters[i]);
1220 }
1221 for (i = 0; i < num_architectural_pmu_counters; i++) {
1222 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1223 env->msr_gp_counters[i]);
1224 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1225 env->msr_gp_evtsel[i]);
1226 }
1227 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1228 env->msr_global_status);
1229 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1230 env->msr_global_ovf_ctrl);
1231
1232 /* Now start the PMU. */
1233 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1234 env->msr_fixed_ctr_ctrl);
1235 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1236 env->msr_global_ctrl);
1237 }
1238 if (has_msr_hv_hypercall) {
1239 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID,
1240 env->msr_hv_guest_os_id);
1241 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL,
1242 env->msr_hv_hypercall);
1243 }
1244 if (has_msr_hv_vapic) {
1245 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,
1246 env->msr_hv_vapic);
1247 }
1248 if (has_msr_hv_tsc) {
1249 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_REFERENCE_TSC,
1250 env->msr_hv_tsc);
1251 }
1252
1253 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1254 * kvm_put_msr_feature_control. */
1255 }
1256 if (env->mcg_cap) {
1257 int i;
1258
1259 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1260 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1261 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1262 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1263 }
1264 }
1265
1266 msr_data.info.nmsrs = n;
1267
1268 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1269
1270 }
1271
1272
1273 static int kvm_get_fpu(X86CPU *cpu)
1274 {
1275 CPUX86State *env = &cpu->env;
1276 struct kvm_fpu fpu;
1277 int i, ret;
1278
1279 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1280 if (ret < 0) {
1281 return ret;
1282 }
1283
1284 env->fpstt = (fpu.fsw >> 11) & 7;
1285 env->fpus = fpu.fsw;
1286 env->fpuc = fpu.fcw;
1287 env->fpop = fpu.last_opcode;
1288 env->fpip = fpu.last_ip;
1289 env->fpdp = fpu.last_dp;
1290 for (i = 0; i < 8; ++i) {
1291 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1292 }
1293 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1294 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1295 env->mxcsr = fpu.mxcsr;
1296
1297 return 0;
1298 }
1299
1300 static int kvm_get_xsave(X86CPU *cpu)
1301 {
1302 CPUX86State *env = &cpu->env;
1303 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1304 int ret, i;
1305 uint16_t cwd, swd, twd;
1306
1307 if (!kvm_has_xsave()) {
1308 return kvm_get_fpu(cpu);
1309 }
1310
1311 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1312 if (ret < 0) {
1313 return ret;
1314 }
1315
1316 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1317 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1318 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1319 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1320 env->fpstt = (swd >> 11) & 7;
1321 env->fpus = swd;
1322 env->fpuc = cwd;
1323 for (i = 0; i < 8; ++i) {
1324 env->fptags[i] = !((twd >> i) & 1);
1325 }
1326 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1327 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1328 env->mxcsr = xsave->region[XSAVE_MXCSR];
1329 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1330 sizeof env->fpregs);
1331 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1332 sizeof env->xmm_regs);
1333 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1334 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1335 sizeof env->ymmh_regs);
1336 memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
1337 sizeof env->bnd_regs);
1338 memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
1339 sizeof(env->bndcs_regs));
1340 return 0;
1341 }
1342
1343 static int kvm_get_xcrs(X86CPU *cpu)
1344 {
1345 CPUX86State *env = &cpu->env;
1346 int i, ret;
1347 struct kvm_xcrs xcrs;
1348
1349 if (!kvm_has_xcrs()) {
1350 return 0;
1351 }
1352
1353 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1354 if (ret < 0) {
1355 return ret;
1356 }
1357
1358 for (i = 0; i < xcrs.nr_xcrs; i++) {
1359 /* Only support xcr0 now */
1360 if (xcrs.xcrs[i].xcr == 0) {
1361 env->xcr0 = xcrs.xcrs[i].value;
1362 break;
1363 }
1364 }
1365 return 0;
1366 }
1367
1368 static int kvm_get_sregs(X86CPU *cpu)
1369 {
1370 CPUX86State *env = &cpu->env;
1371 struct kvm_sregs sregs;
1372 uint32_t hflags;
1373 int bit, i, ret;
1374
1375 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1376 if (ret < 0) {
1377 return ret;
1378 }
1379
1380 /* There can only be one pending IRQ set in the bitmap at a time, so try
1381 to find it and save its number instead (-1 for none). */
1382 env->interrupt_injected = -1;
1383 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1384 if (sregs.interrupt_bitmap[i]) {
1385 bit = ctz64(sregs.interrupt_bitmap[i]);
1386 env->interrupt_injected = i * 64 + bit;
1387 break;
1388 }
1389 }
1390
1391 get_seg(&env->segs[R_CS], &sregs.cs);
1392 get_seg(&env->segs[R_DS], &sregs.ds);
1393 get_seg(&env->segs[R_ES], &sregs.es);
1394 get_seg(&env->segs[R_FS], &sregs.fs);
1395 get_seg(&env->segs[R_GS], &sregs.gs);
1396 get_seg(&env->segs[R_SS], &sregs.ss);
1397
1398 get_seg(&env->tr, &sregs.tr);
1399 get_seg(&env->ldt, &sregs.ldt);
1400
1401 env->idt.limit = sregs.idt.limit;
1402 env->idt.base = sregs.idt.base;
1403 env->gdt.limit = sregs.gdt.limit;
1404 env->gdt.base = sregs.gdt.base;
1405
1406 env->cr[0] = sregs.cr0;
1407 env->cr[2] = sregs.cr2;
1408 env->cr[3] = sregs.cr3;
1409 env->cr[4] = sregs.cr4;
1410
1411 env->efer = sregs.efer;
1412
1413 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1414
1415 #define HFLAG_COPY_MASK \
1416 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1417 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1418 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1419 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1420
1421 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1422 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1423 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1424 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1425 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1426 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1427 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1428
1429 if (env->efer & MSR_EFER_LMA) {
1430 hflags |= HF_LMA_MASK;
1431 }
1432
1433 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1434 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1435 } else {
1436 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1437 (DESC_B_SHIFT - HF_CS32_SHIFT);
1438 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1439 (DESC_B_SHIFT - HF_SS32_SHIFT);
1440 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1441 !(hflags & HF_CS32_MASK)) {
1442 hflags |= HF_ADDSEG_MASK;
1443 } else {
1444 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1445 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1446 }
1447 }
1448 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1449
1450 return 0;
1451 }
1452
1453 static int kvm_get_msrs(X86CPU *cpu)
1454 {
1455 CPUX86State *env = &cpu->env;
1456 struct {
1457 struct kvm_msrs info;
1458 struct kvm_msr_entry entries[100];
1459 } msr_data;
1460 struct kvm_msr_entry *msrs = msr_data.entries;
1461 int ret, i, n;
1462
1463 n = 0;
1464 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1465 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1466 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1467 msrs[n++].index = MSR_PAT;
1468 if (has_msr_star) {
1469 msrs[n++].index = MSR_STAR;
1470 }
1471 if (has_msr_hsave_pa) {
1472 msrs[n++].index = MSR_VM_HSAVE_PA;
1473 }
1474 if (has_msr_tsc_adjust) {
1475 msrs[n++].index = MSR_TSC_ADJUST;
1476 }
1477 if (has_msr_tsc_deadline) {
1478 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1479 }
1480 if (has_msr_misc_enable) {
1481 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1482 }
1483 if (has_msr_feature_control) {
1484 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1485 }
1486 if (has_msr_bndcfgs) {
1487 msrs[n++].index = MSR_IA32_BNDCFGS;
1488 }
1489
1490 if (!env->tsc_valid) {
1491 msrs[n++].index = MSR_IA32_TSC;
1492 env->tsc_valid = !runstate_is_running();
1493 }
1494
1495 #ifdef TARGET_X86_64
1496 if (lm_capable_kernel) {
1497 msrs[n++].index = MSR_CSTAR;
1498 msrs[n++].index = MSR_KERNELGSBASE;
1499 msrs[n++].index = MSR_FMASK;
1500 msrs[n++].index = MSR_LSTAR;
1501 }
1502 #endif
1503 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1504 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1505 if (has_msr_async_pf_en) {
1506 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1507 }
1508 if (has_msr_pv_eoi_en) {
1509 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1510 }
1511 if (has_msr_kvm_steal_time) {
1512 msrs[n++].index = MSR_KVM_STEAL_TIME;
1513 }
1514 if (has_msr_architectural_pmu) {
1515 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1516 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1517 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1518 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1519 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1520 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1521 }
1522 for (i = 0; i < num_architectural_pmu_counters; i++) {
1523 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1524 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1525 }
1526 }
1527
1528 if (env->mcg_cap) {
1529 msrs[n++].index = MSR_MCG_STATUS;
1530 msrs[n++].index = MSR_MCG_CTL;
1531 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1532 msrs[n++].index = MSR_MC0_CTL + i;
1533 }
1534 }
1535
1536 if (has_msr_hv_hypercall) {
1537 msrs[n++].index = HV_X64_MSR_HYPERCALL;
1538 msrs[n++].index = HV_X64_MSR_GUEST_OS_ID;
1539 }
1540 if (has_msr_hv_vapic) {
1541 msrs[n++].index = HV_X64_MSR_APIC_ASSIST_PAGE;
1542 }
1543 if (has_msr_hv_tsc) {
1544 msrs[n++].index = HV_X64_MSR_REFERENCE_TSC;
1545 }
1546
1547 msr_data.info.nmsrs = n;
1548 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1549 if (ret < 0) {
1550 return ret;
1551 }
1552
1553 for (i = 0; i < ret; i++) {
1554 uint32_t index = msrs[i].index;
1555 switch (index) {
1556 case MSR_IA32_SYSENTER_CS:
1557 env->sysenter_cs = msrs[i].data;
1558 break;
1559 case MSR_IA32_SYSENTER_ESP:
1560 env->sysenter_esp = msrs[i].data;
1561 break;
1562 case MSR_IA32_SYSENTER_EIP:
1563 env->sysenter_eip = msrs[i].data;
1564 break;
1565 case MSR_PAT:
1566 env->pat = msrs[i].data;
1567 break;
1568 case MSR_STAR:
1569 env->star = msrs[i].data;
1570 break;
1571 #ifdef TARGET_X86_64
1572 case MSR_CSTAR:
1573 env->cstar = msrs[i].data;
1574 break;
1575 case MSR_KERNELGSBASE:
1576 env->kernelgsbase = msrs[i].data;
1577 break;
1578 case MSR_FMASK:
1579 env->fmask = msrs[i].data;
1580 break;
1581 case MSR_LSTAR:
1582 env->lstar = msrs[i].data;
1583 break;
1584 #endif
1585 case MSR_IA32_TSC:
1586 env->tsc = msrs[i].data;
1587 break;
1588 case MSR_TSC_ADJUST:
1589 env->tsc_adjust = msrs[i].data;
1590 break;
1591 case MSR_IA32_TSCDEADLINE:
1592 env->tsc_deadline = msrs[i].data;
1593 break;
1594 case MSR_VM_HSAVE_PA:
1595 env->vm_hsave = msrs[i].data;
1596 break;
1597 case MSR_KVM_SYSTEM_TIME:
1598 env->system_time_msr = msrs[i].data;
1599 break;
1600 case MSR_KVM_WALL_CLOCK:
1601 env->wall_clock_msr = msrs[i].data;
1602 break;
1603 case MSR_MCG_STATUS:
1604 env->mcg_status = msrs[i].data;
1605 break;
1606 case MSR_MCG_CTL:
1607 env->mcg_ctl = msrs[i].data;
1608 break;
1609 case MSR_IA32_MISC_ENABLE:
1610 env->msr_ia32_misc_enable = msrs[i].data;
1611 break;
1612 case MSR_IA32_FEATURE_CONTROL:
1613 env->msr_ia32_feature_control = msrs[i].data;
1614 break;
1615 case MSR_IA32_BNDCFGS:
1616 env->msr_bndcfgs = msrs[i].data;
1617 break;
1618 default:
1619 if (msrs[i].index >= MSR_MC0_CTL &&
1620 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1621 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1622 }
1623 break;
1624 case MSR_KVM_ASYNC_PF_EN:
1625 env->async_pf_en_msr = msrs[i].data;
1626 break;
1627 case MSR_KVM_PV_EOI_EN:
1628 env->pv_eoi_en_msr = msrs[i].data;
1629 break;
1630 case MSR_KVM_STEAL_TIME:
1631 env->steal_time_msr = msrs[i].data;
1632 break;
1633 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1634 env->msr_fixed_ctr_ctrl = msrs[i].data;
1635 break;
1636 case MSR_CORE_PERF_GLOBAL_CTRL:
1637 env->msr_global_ctrl = msrs[i].data;
1638 break;
1639 case MSR_CORE_PERF_GLOBAL_STATUS:
1640 env->msr_global_status = msrs[i].data;
1641 break;
1642 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1643 env->msr_global_ovf_ctrl = msrs[i].data;
1644 break;
1645 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1646 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1647 break;
1648 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1649 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1650 break;
1651 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1652 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1653 break;
1654 case HV_X64_MSR_HYPERCALL:
1655 env->msr_hv_hypercall = msrs[i].data;
1656 break;
1657 case HV_X64_MSR_GUEST_OS_ID:
1658 env->msr_hv_guest_os_id = msrs[i].data;
1659 break;
1660 case HV_X64_MSR_APIC_ASSIST_PAGE:
1661 env->msr_hv_vapic = msrs[i].data;
1662 break;
1663 case HV_X64_MSR_REFERENCE_TSC:
1664 env->msr_hv_tsc = msrs[i].data;
1665 break;
1666 }
1667 }
1668
1669 return 0;
1670 }
1671
1672 static int kvm_put_mp_state(X86CPU *cpu)
1673 {
1674 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1675
1676 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1677 }
1678
1679 static int kvm_get_mp_state(X86CPU *cpu)
1680 {
1681 CPUState *cs = CPU(cpu);
1682 CPUX86State *env = &cpu->env;
1683 struct kvm_mp_state mp_state;
1684 int ret;
1685
1686 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1687 if (ret < 0) {
1688 return ret;
1689 }
1690 env->mp_state = mp_state.mp_state;
1691 if (kvm_irqchip_in_kernel()) {
1692 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1693 }
1694 return 0;
1695 }
1696
1697 static int kvm_get_apic(X86CPU *cpu)
1698 {
1699 DeviceState *apic = cpu->apic_state;
1700 struct kvm_lapic_state kapic;
1701 int ret;
1702
1703 if (apic && kvm_irqchip_in_kernel()) {
1704 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1705 if (ret < 0) {
1706 return ret;
1707 }
1708
1709 kvm_get_apic_state(apic, &kapic);
1710 }
1711 return 0;
1712 }
1713
1714 static int kvm_put_apic(X86CPU *cpu)
1715 {
1716 DeviceState *apic = cpu->apic_state;
1717 struct kvm_lapic_state kapic;
1718
1719 if (apic && kvm_irqchip_in_kernel()) {
1720 kvm_put_apic_state(apic, &kapic);
1721
1722 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1723 }
1724 return 0;
1725 }
1726
1727 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1728 {
1729 CPUX86State *env = &cpu->env;
1730 struct kvm_vcpu_events events;
1731
1732 if (!kvm_has_vcpu_events()) {
1733 return 0;
1734 }
1735
1736 events.exception.injected = (env->exception_injected >= 0);
1737 events.exception.nr = env->exception_injected;
1738 events.exception.has_error_code = env->has_error_code;
1739 events.exception.error_code = env->error_code;
1740 events.exception.pad = 0;
1741
1742 events.interrupt.injected = (env->interrupt_injected >= 0);
1743 events.interrupt.nr = env->interrupt_injected;
1744 events.interrupt.soft = env->soft_interrupt;
1745
1746 events.nmi.injected = env->nmi_injected;
1747 events.nmi.pending = env->nmi_pending;
1748 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1749 events.nmi.pad = 0;
1750
1751 events.sipi_vector = env->sipi_vector;
1752
1753 events.flags = 0;
1754 if (level >= KVM_PUT_RESET_STATE) {
1755 events.flags |=
1756 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1757 }
1758
1759 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1760 }
1761
1762 static int kvm_get_vcpu_events(X86CPU *cpu)
1763 {
1764 CPUX86State *env = &cpu->env;
1765 struct kvm_vcpu_events events;
1766 int ret;
1767
1768 if (!kvm_has_vcpu_events()) {
1769 return 0;
1770 }
1771
1772 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1773 if (ret < 0) {
1774 return ret;
1775 }
1776 env->exception_injected =
1777 events.exception.injected ? events.exception.nr : -1;
1778 env->has_error_code = events.exception.has_error_code;
1779 env->error_code = events.exception.error_code;
1780
1781 env->interrupt_injected =
1782 events.interrupt.injected ? events.interrupt.nr : -1;
1783 env->soft_interrupt = events.interrupt.soft;
1784
1785 env->nmi_injected = events.nmi.injected;
1786 env->nmi_pending = events.nmi.pending;
1787 if (events.nmi.masked) {
1788 env->hflags2 |= HF2_NMI_MASK;
1789 } else {
1790 env->hflags2 &= ~HF2_NMI_MASK;
1791 }
1792
1793 env->sipi_vector = events.sipi_vector;
1794
1795 return 0;
1796 }
1797
1798 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1799 {
1800 CPUState *cs = CPU(cpu);
1801 CPUX86State *env = &cpu->env;
1802 int ret = 0;
1803 unsigned long reinject_trap = 0;
1804
1805 if (!kvm_has_vcpu_events()) {
1806 if (env->exception_injected == 1) {
1807 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1808 } else if (env->exception_injected == 3) {
1809 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1810 }
1811 env->exception_injected = -1;
1812 }
1813
1814 /*
1815 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1816 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1817 * by updating the debug state once again if single-stepping is on.
1818 * Another reason to call kvm_update_guest_debug here is a pending debug
1819 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1820 * reinject them via SET_GUEST_DEBUG.
1821 */
1822 if (reinject_trap ||
1823 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1824 ret = kvm_update_guest_debug(cs, reinject_trap);
1825 }
1826 return ret;
1827 }
1828
1829 static int kvm_put_debugregs(X86CPU *cpu)
1830 {
1831 CPUX86State *env = &cpu->env;
1832 struct kvm_debugregs dbgregs;
1833 int i;
1834
1835 if (!kvm_has_debugregs()) {
1836 return 0;
1837 }
1838
1839 for (i = 0; i < 4; i++) {
1840 dbgregs.db[i] = env->dr[i];
1841 }
1842 dbgregs.dr6 = env->dr[6];
1843 dbgregs.dr7 = env->dr[7];
1844 dbgregs.flags = 0;
1845
1846 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1847 }
1848
1849 static int kvm_get_debugregs(X86CPU *cpu)
1850 {
1851 CPUX86State *env = &cpu->env;
1852 struct kvm_debugregs dbgregs;
1853 int i, ret;
1854
1855 if (!kvm_has_debugregs()) {
1856 return 0;
1857 }
1858
1859 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1860 if (ret < 0) {
1861 return ret;
1862 }
1863 for (i = 0; i < 4; i++) {
1864 env->dr[i] = dbgregs.db[i];
1865 }
1866 env->dr[4] = env->dr[6] = dbgregs.dr6;
1867 env->dr[5] = env->dr[7] = dbgregs.dr7;
1868
1869 return 0;
1870 }
1871
1872 int kvm_arch_put_registers(CPUState *cpu, int level)
1873 {
1874 X86CPU *x86_cpu = X86_CPU(cpu);
1875 int ret;
1876
1877 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1878
1879 if (level >= KVM_PUT_RESET_STATE && has_msr_feature_control) {
1880 ret = kvm_put_msr_feature_control(x86_cpu);
1881 if (ret < 0) {
1882 return ret;
1883 }
1884 }
1885
1886 ret = kvm_getput_regs(x86_cpu, 1);
1887 if (ret < 0) {
1888 return ret;
1889 }
1890 ret = kvm_put_xsave(x86_cpu);
1891 if (ret < 0) {
1892 return ret;
1893 }
1894 ret = kvm_put_xcrs(x86_cpu);
1895 if (ret < 0) {
1896 return ret;
1897 }
1898 ret = kvm_put_sregs(x86_cpu);
1899 if (ret < 0) {
1900 return ret;
1901 }
1902 /* must be before kvm_put_msrs */
1903 ret = kvm_inject_mce_oldstyle(x86_cpu);
1904 if (ret < 0) {
1905 return ret;
1906 }
1907 ret = kvm_put_msrs(x86_cpu, level);
1908 if (ret < 0) {
1909 return ret;
1910 }
1911 if (level >= KVM_PUT_RESET_STATE) {
1912 ret = kvm_put_mp_state(x86_cpu);
1913 if (ret < 0) {
1914 return ret;
1915 }
1916 ret = kvm_put_apic(x86_cpu);
1917 if (ret < 0) {
1918 return ret;
1919 }
1920 }
1921
1922 ret = kvm_put_tscdeadline_msr(x86_cpu);
1923 if (ret < 0) {
1924 return ret;
1925 }
1926
1927 ret = kvm_put_vcpu_events(x86_cpu, level);
1928 if (ret < 0) {
1929 return ret;
1930 }
1931 ret = kvm_put_debugregs(x86_cpu);
1932 if (ret < 0) {
1933 return ret;
1934 }
1935 /* must be last */
1936 ret = kvm_guest_debug_workarounds(x86_cpu);
1937 if (ret < 0) {
1938 return ret;
1939 }
1940 return 0;
1941 }
1942
1943 int kvm_arch_get_registers(CPUState *cs)
1944 {
1945 X86CPU *cpu = X86_CPU(cs);
1946 int ret;
1947
1948 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1949
1950 ret = kvm_getput_regs(cpu, 0);
1951 if (ret < 0) {
1952 return ret;
1953 }
1954 ret = kvm_get_xsave(cpu);
1955 if (ret < 0) {
1956 return ret;
1957 }
1958 ret = kvm_get_xcrs(cpu);
1959 if (ret < 0) {
1960 return ret;
1961 }
1962 ret = kvm_get_sregs(cpu);
1963 if (ret < 0) {
1964 return ret;
1965 }
1966 ret = kvm_get_msrs(cpu);
1967 if (ret < 0) {
1968 return ret;
1969 }
1970 ret = kvm_get_mp_state(cpu);
1971 if (ret < 0) {
1972 return ret;
1973 }
1974 ret = kvm_get_apic(cpu);
1975 if (ret < 0) {
1976 return ret;
1977 }
1978 ret = kvm_get_vcpu_events(cpu);
1979 if (ret < 0) {
1980 return ret;
1981 }
1982 ret = kvm_get_debugregs(cpu);
1983 if (ret < 0) {
1984 return ret;
1985 }
1986 return 0;
1987 }
1988
1989 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1990 {
1991 X86CPU *x86_cpu = X86_CPU(cpu);
1992 CPUX86State *env = &x86_cpu->env;
1993 int ret;
1994
1995 /* Inject NMI */
1996 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1997 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1998 DPRINTF("injected NMI\n");
1999 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2000 if (ret < 0) {
2001 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2002 strerror(-ret));
2003 }
2004 }
2005
2006 if (!kvm_irqchip_in_kernel()) {
2007 /* Force the VCPU out of its inner loop to process any INIT requests
2008 * or pending TPR access reports. */
2009 if (cpu->interrupt_request &
2010 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2011 cpu->exit_request = 1;
2012 }
2013
2014 /* Try to inject an interrupt if the guest can accept it */
2015 if (run->ready_for_interrupt_injection &&
2016 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2017 (env->eflags & IF_MASK)) {
2018 int irq;
2019
2020 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2021 irq = cpu_get_pic_interrupt(env);
2022 if (irq >= 0) {
2023 struct kvm_interrupt intr;
2024
2025 intr.irq = irq;
2026 DPRINTF("injected interrupt %d\n", irq);
2027 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2028 if (ret < 0) {
2029 fprintf(stderr,
2030 "KVM: injection failed, interrupt lost (%s)\n",
2031 strerror(-ret));
2032 }
2033 }
2034 }
2035
2036 /* If we have an interrupt but the guest is not ready to receive an
2037 * interrupt, request an interrupt window exit. This will
2038 * cause a return to userspace as soon as the guest is ready to
2039 * receive interrupts. */
2040 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2041 run->request_interrupt_window = 1;
2042 } else {
2043 run->request_interrupt_window = 0;
2044 }
2045
2046 DPRINTF("setting tpr\n");
2047 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2048 }
2049 }
2050
2051 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2052 {
2053 X86CPU *x86_cpu = X86_CPU(cpu);
2054 CPUX86State *env = &x86_cpu->env;
2055
2056 if (run->if_flag) {
2057 env->eflags |= IF_MASK;
2058 } else {
2059 env->eflags &= ~IF_MASK;
2060 }
2061 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2062 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2063 }
2064
2065 int kvm_arch_process_async_events(CPUState *cs)
2066 {
2067 X86CPU *cpu = X86_CPU(cs);
2068 CPUX86State *env = &cpu->env;
2069
2070 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2071 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2072 assert(env->mcg_cap);
2073
2074 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2075
2076 kvm_cpu_synchronize_state(cs);
2077
2078 if (env->exception_injected == EXCP08_DBLE) {
2079 /* this means triple fault */
2080 qemu_system_reset_request();
2081 cs->exit_request = 1;
2082 return 0;
2083 }
2084 env->exception_injected = EXCP12_MCHK;
2085 env->has_error_code = 0;
2086
2087 cs->halted = 0;
2088 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2089 env->mp_state = KVM_MP_STATE_RUNNABLE;
2090 }
2091 }
2092
2093 if (kvm_irqchip_in_kernel()) {
2094 return 0;
2095 }
2096
2097 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2098 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2099 apic_poll_irq(cpu->apic_state);
2100 }
2101 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2102 (env->eflags & IF_MASK)) ||
2103 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2104 cs->halted = 0;
2105 }
2106 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2107 kvm_cpu_synchronize_state(cs);
2108 do_cpu_init(cpu);
2109 }
2110 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2111 kvm_cpu_synchronize_state(cs);
2112 do_cpu_sipi(cpu);
2113 }
2114 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2115 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2116 kvm_cpu_synchronize_state(cs);
2117 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2118 env->tpr_access_type);
2119 }
2120
2121 return cs->halted;
2122 }
2123
2124 static int kvm_handle_halt(X86CPU *cpu)
2125 {
2126 CPUState *cs = CPU(cpu);
2127 CPUX86State *env = &cpu->env;
2128
2129 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2130 (env->eflags & IF_MASK)) &&
2131 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2132 cs->halted = 1;
2133 return EXCP_HLT;
2134 }
2135
2136 return 0;
2137 }
2138
2139 static int kvm_handle_tpr_access(X86CPU *cpu)
2140 {
2141 CPUState *cs = CPU(cpu);
2142 struct kvm_run *run = cs->kvm_run;
2143
2144 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2145 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2146 : TPR_ACCESS_READ);
2147 return 1;
2148 }
2149
2150 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2151 {
2152 static const uint8_t int3 = 0xcc;
2153
2154 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2155 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2156 return -EINVAL;
2157 }
2158 return 0;
2159 }
2160
2161 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2162 {
2163 uint8_t int3;
2164
2165 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2166 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2167 return -EINVAL;
2168 }
2169 return 0;
2170 }
2171
2172 static struct {
2173 target_ulong addr;
2174 int len;
2175 int type;
2176 } hw_breakpoint[4];
2177
2178 static int nb_hw_breakpoint;
2179
2180 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2181 {
2182 int n;
2183
2184 for (n = 0; n < nb_hw_breakpoint; n++) {
2185 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2186 (hw_breakpoint[n].len == len || len == -1)) {
2187 return n;
2188 }
2189 }
2190 return -1;
2191 }
2192
2193 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2194 target_ulong len, int type)
2195 {
2196 switch (type) {
2197 case GDB_BREAKPOINT_HW:
2198 len = 1;
2199 break;
2200 case GDB_WATCHPOINT_WRITE:
2201 case GDB_WATCHPOINT_ACCESS:
2202 switch (len) {
2203 case 1:
2204 break;
2205 case 2:
2206 case 4:
2207 case 8:
2208 if (addr & (len - 1)) {
2209 return -EINVAL;
2210 }
2211 break;
2212 default:
2213 return -EINVAL;
2214 }
2215 break;
2216 default:
2217 return -ENOSYS;
2218 }
2219
2220 if (nb_hw_breakpoint == 4) {
2221 return -ENOBUFS;
2222 }
2223 if (find_hw_breakpoint(addr, len, type) >= 0) {
2224 return -EEXIST;
2225 }
2226 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2227 hw_breakpoint[nb_hw_breakpoint].len = len;
2228 hw_breakpoint[nb_hw_breakpoint].type = type;
2229 nb_hw_breakpoint++;
2230
2231 return 0;
2232 }
2233
2234 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2235 target_ulong len, int type)
2236 {
2237 int n;
2238
2239 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2240 if (n < 0) {
2241 return -ENOENT;
2242 }
2243 nb_hw_breakpoint--;
2244 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2245
2246 return 0;
2247 }
2248
2249 void kvm_arch_remove_all_hw_breakpoints(void)
2250 {
2251 nb_hw_breakpoint = 0;
2252 }
2253
2254 static CPUWatchpoint hw_watchpoint;
2255
2256 static int kvm_handle_debug(X86CPU *cpu,
2257 struct kvm_debug_exit_arch *arch_info)
2258 {
2259 CPUState *cs = CPU(cpu);
2260 CPUX86State *env = &cpu->env;
2261 int ret = 0;
2262 int n;
2263
2264 if (arch_info->exception == 1) {
2265 if (arch_info->dr6 & (1 << 14)) {
2266 if (cs->singlestep_enabled) {
2267 ret = EXCP_DEBUG;
2268 }
2269 } else {
2270 for (n = 0; n < 4; n++) {
2271 if (arch_info->dr6 & (1 << n)) {
2272 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2273 case 0x0:
2274 ret = EXCP_DEBUG;
2275 break;
2276 case 0x1:
2277 ret = EXCP_DEBUG;
2278 cs->watchpoint_hit = &hw_watchpoint;
2279 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2280 hw_watchpoint.flags = BP_MEM_WRITE;
2281 break;
2282 case 0x3:
2283 ret = EXCP_DEBUG;
2284 cs->watchpoint_hit = &hw_watchpoint;
2285 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2286 hw_watchpoint.flags = BP_MEM_ACCESS;
2287 break;
2288 }
2289 }
2290 }
2291 }
2292 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
2293 ret = EXCP_DEBUG;
2294 }
2295 if (ret == 0) {
2296 cpu_synchronize_state(cs);
2297 assert(env->exception_injected == -1);
2298
2299 /* pass to guest */
2300 env->exception_injected = arch_info->exception;
2301 env->has_error_code = 0;
2302 }
2303
2304 return ret;
2305 }
2306
2307 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2308 {
2309 const uint8_t type_code[] = {
2310 [GDB_BREAKPOINT_HW] = 0x0,
2311 [GDB_WATCHPOINT_WRITE] = 0x1,
2312 [GDB_WATCHPOINT_ACCESS] = 0x3
2313 };
2314 const uint8_t len_code[] = {
2315 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2316 };
2317 int n;
2318
2319 if (kvm_sw_breakpoints_active(cpu)) {
2320 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2321 }
2322 if (nb_hw_breakpoint > 0) {
2323 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2324 dbg->arch.debugreg[7] = 0x0600;
2325 for (n = 0; n < nb_hw_breakpoint; n++) {
2326 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2327 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2328 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2329 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2330 }
2331 }
2332 }
2333
2334 static bool host_supports_vmx(void)
2335 {
2336 uint32_t ecx, unused;
2337
2338 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2339 return ecx & CPUID_EXT_VMX;
2340 }
2341
2342 #define VMX_INVALID_GUEST_STATE 0x80000021
2343
2344 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2345 {
2346 X86CPU *cpu = X86_CPU(cs);
2347 uint64_t code;
2348 int ret;
2349
2350 switch (run->exit_reason) {
2351 case KVM_EXIT_HLT:
2352 DPRINTF("handle_hlt\n");
2353 ret = kvm_handle_halt(cpu);
2354 break;
2355 case KVM_EXIT_SET_TPR:
2356 ret = 0;
2357 break;
2358 case KVM_EXIT_TPR_ACCESS:
2359 ret = kvm_handle_tpr_access(cpu);
2360 break;
2361 case KVM_EXIT_FAIL_ENTRY:
2362 code = run->fail_entry.hardware_entry_failure_reason;
2363 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2364 code);
2365 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2366 fprintf(stderr,
2367 "\nIf you're running a guest on an Intel machine without "
2368 "unrestricted mode\n"
2369 "support, the failure can be most likely due to the guest "
2370 "entering an invalid\n"
2371 "state for Intel VT. For example, the guest maybe running "
2372 "in big real mode\n"
2373 "which is not supported on less recent Intel processors."
2374 "\n\n");
2375 }
2376 ret = -1;
2377 break;
2378 case KVM_EXIT_EXCEPTION:
2379 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2380 run->ex.exception, run->ex.error_code);
2381 ret = -1;
2382 break;
2383 case KVM_EXIT_DEBUG:
2384 DPRINTF("kvm_exit_debug\n");
2385 ret = kvm_handle_debug(cpu, &run->debug.arch);
2386 break;
2387 default:
2388 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2389 ret = -1;
2390 break;
2391 }
2392
2393 return ret;
2394 }
2395
2396 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2397 {
2398 X86CPU *cpu = X86_CPU(cs);
2399 CPUX86State *env = &cpu->env;
2400
2401 kvm_cpu_synchronize_state(cs);
2402 return !(env->cr[0] & CR0_PE_MASK) ||
2403 ((env->segs[R_CS].selector & 3) != 3);
2404 }
2405
2406 void kvm_arch_init_irq_routing(KVMState *s)
2407 {
2408 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2409 /* If kernel can't do irq routing, interrupt source
2410 * override 0->2 cannot be set up as required by HPET.
2411 * So we have to disable it.
2412 */
2413 no_hpet = 1;
2414 }
2415 /* We know at this point that we're using the in-kernel
2416 * irqchip, so we can use irqfds, and on x86 we know
2417 * we can use msi via irqfd and GSI routing.
2418 */
2419 kvm_irqfds_allowed = true;
2420 kvm_msi_via_irqfd_allowed = true;
2421 kvm_gsi_routing_allowed = true;
2422 }
2423
2424 /* Classic KVM device assignment interface. Will remain x86 only. */
2425 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2426 uint32_t flags, uint32_t *dev_id)
2427 {
2428 struct kvm_assigned_pci_dev dev_data = {
2429 .segnr = dev_addr->domain,
2430 .busnr = dev_addr->bus,
2431 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2432 .flags = flags,
2433 };
2434 int ret;
2435
2436 dev_data.assigned_dev_id =
2437 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2438
2439 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2440 if (ret < 0) {
2441 return ret;
2442 }
2443
2444 *dev_id = dev_data.assigned_dev_id;
2445
2446 return 0;
2447 }
2448
2449 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2450 {
2451 struct kvm_assigned_pci_dev dev_data = {
2452 .assigned_dev_id = dev_id,
2453 };
2454
2455 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2456 }
2457
2458 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2459 uint32_t irq_type, uint32_t guest_irq)
2460 {
2461 struct kvm_assigned_irq assigned_irq = {
2462 .assigned_dev_id = dev_id,
2463 .guest_irq = guest_irq,
2464 .flags = irq_type,
2465 };
2466
2467 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2468 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2469 } else {
2470 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2471 }
2472 }
2473
2474 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2475 uint32_t guest_irq)
2476 {
2477 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2478 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2479
2480 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2481 }
2482
2483 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2484 {
2485 struct kvm_assigned_pci_dev dev_data = {
2486 .assigned_dev_id = dev_id,
2487 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2488 };
2489
2490 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2491 }
2492
2493 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2494 uint32_t type)
2495 {
2496 struct kvm_assigned_irq assigned_irq = {
2497 .assigned_dev_id = dev_id,
2498 .flags = type,
2499 };
2500
2501 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2502 }
2503
2504 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2505 {
2506 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2507 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2508 }
2509
2510 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2511 {
2512 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2513 KVM_DEV_IRQ_GUEST_MSI, virq);
2514 }
2515
2516 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2517 {
2518 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2519 KVM_DEV_IRQ_HOST_MSI);
2520 }
2521
2522 bool kvm_device_msix_supported(KVMState *s)
2523 {
2524 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2525 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2526 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2527 }
2528
2529 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2530 uint32_t nr_vectors)
2531 {
2532 struct kvm_assigned_msix_nr msix_nr = {
2533 .assigned_dev_id = dev_id,
2534 .entry_nr = nr_vectors,
2535 };
2536
2537 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2538 }
2539
2540 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2541 int virq)
2542 {
2543 struct kvm_assigned_msix_entry msix_entry = {
2544 .assigned_dev_id = dev_id,
2545 .gsi = virq,
2546 .entry = vector,
2547 };
2548
2549 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2550 }
2551
2552 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2553 {
2554 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2555 KVM_DEV_IRQ_GUEST_MSIX, 0);
2556 }
2557
2558 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2559 {
2560 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2561 KVM_DEV_IRQ_HOST_MSIX);
2562 }
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