target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34 #include "hw/pci.h"
  35
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 static bool has_msr_tsc_deadline;
  66 static bool has_msr_async_pf_en;
  67 static bool has_msr_pv_eoi_en;
  68 static bool has_msr_misc_enable;
  69 static int lm_capable_kernel;
  70
  71 bool kvm_allows_irq0_override(void)
  72 {
  73     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  74 }
  75
  76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int r, size;
  80
  81     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  82     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  83     cpuid->nent = max;
  84     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  85     if (r == 0 && cpuid->nent >= max) {
  86         r = -E2BIG;
  87     }
  88     if (r < 0) {
  89         if (r == -E2BIG) {
  90             g_free(cpuid);
  91             return NULL;
  92         } else {
  93             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  94                     strerror(-r));
  95             exit(1);
  96         }
  97     }
  98     return cpuid;
  99 }
 100
 101 struct kvm_para_features {
 102     int cap;
 103     int feature;
 104 } para_features[] = {
 105     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 106     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 107     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 108     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 109     { -1, -1 }
 110 };
 111
 112 static int get_para_features(KVMState *s)
 113 {
 114     int i, features = 0;
 115
 116     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 117         if (kvm_check_extension(s, para_features[i].cap)) {
 118             features |= (1 << para_features[i].feature);
 119         }
 120     }
 121
 122     return features;
 123 }
 124
 125
 126 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 127                                       uint32_t index, int reg)
 128 {
 129     struct kvm_cpuid2 *cpuid;
 130     int i, max;
 131     uint32_t ret = 0;
 132     uint32_t cpuid_1_edx;
 133     int has_kvm_features = 0;
 134
 135     max = 1;
 136     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 137         max *= 2;
 138     }
 139
 140     for (i = 0; i < cpuid->nent; ++i) {
 141         if (cpuid->entries[i].function == function &&
 142             cpuid->entries[i].index == index) {
 143             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 144                 has_kvm_features = 1;
 145             }
 146             switch (reg) {
 147             case R_EAX:
 148                 ret = cpuid->entries[i].eax;
 149                 break;
 150             case R_EBX:
 151                 ret = cpuid->entries[i].ebx;
 152                 break;
 153             case R_ECX:
 154                 ret = cpuid->entries[i].ecx;
 155                 break;
 156             case R_EDX:
 157                 ret = cpuid->entries[i].edx;
 158                 break;
 159             }
 160         }
 161     }
 162
 163     /* Fixups for the data returned by KVM, below */
 164
 165     if (reg == R_EDX) {
 166         switch (function) {
 167         case 1:
 168             /* KVM before 2.6.30 misreports the following features */
 169             ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 170             break;
 171         case 0x80000001:
 172             /* On Intel, kvm returns cpuid according to the Intel spec,
 173              * so add missing bits according to the AMD spec:
 174              */
 175             cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 176             ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 177             break;
 178         }
 179     }
 180
 181     g_free(cpuid);
 182
 183     /* fallback for older kernels */
 184     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 185         ret = get_para_features(s);
 186     }
 187
 188     return ret;
 189 }
 190
 191 typedef struct HWPoisonPage {
 192     ram_addr_t ram_addr;
 193     QLIST_ENTRY(HWPoisonPage) list;
 194 } HWPoisonPage;
 195
 196 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 197     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 198
 199 static void kvm_unpoison_all(void *param)
 200 {
 201     HWPoisonPage *page, *next_page;
 202
 203     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 204         QLIST_REMOVE(page, list);
 205         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 206         g_free(page);
 207     }
 208 }
 209
 210 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 211 {
 212     HWPoisonPage *page;
 213
 214     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 215         if (page->ram_addr == ram_addr) {
 216             return;
 217         }
 218     }
 219     page = g_malloc(sizeof(HWPoisonPage));
 220     page->ram_addr = ram_addr;
 221     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 222 }
 223
 224 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 225                                      int *max_banks)
 226 {
 227     int r;
 228
 229     r = kvm_check_extension(s, KVM_CAP_MCE);
 230     if (r > 0) {
 231         *max_banks = r;
 232         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 233     }
 234     return -ENOSYS;
 235 }
 236
 237 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
 238 {
 239     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 240                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 241     uint64_t mcg_status = MCG_STATUS_MCIP;
 242
 243     if (code == BUS_MCEERR_AR) {
 244         status |= MCI_STATUS_AR | 0x134;
 245         mcg_status |= MCG_STATUS_EIPV;
 246     } else {
 247         status |= 0xc0;
 248         mcg_status |= MCG_STATUS_RIPV;
 249     }
 250     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 251                        (MCM_ADDR_PHYS << 6) | 0xc,
 252                        cpu_x86_support_mca_broadcast(env) ?
 253                        MCE_INJECT_BROADCAST : 0);
 254 }
 255
 256 static void hardware_memory_error(void)
 257 {
 258     fprintf(stderr, "Hardware memory error!\n");
 259     exit(1);
 260 }
 261
 262 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 263 {
 264     ram_addr_t ram_addr;
 265     hwaddr paddr;
 266
 267     if ((env->mcg_cap & MCG_SER_P) && addr
 268         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 269         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 270             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 271             fprintf(stderr, "Hardware memory error for memory used by "
 272                     "QEMU itself instead of guest system!\n");
 273             /* Hope we are lucky for AO MCE */
 274             if (code == BUS_MCEERR_AO) {
 275                 return 0;
 276             } else {
 277                 hardware_memory_error();
 278             }
 279         }
 280         kvm_hwpoison_page_add(ram_addr);
 281         kvm_mce_inject(env, paddr, code);
 282     } else {
 283         if (code == BUS_MCEERR_AO) {
 284             return 0;
 285         } else if (code == BUS_MCEERR_AR) {
 286             hardware_memory_error();
 287         } else {
 288             return 1;
 289         }
 290     }
 291     return 0;
 292 }
 293
 294 int kvm_arch_on_sigbus(int code, void *addr)
 295 {
 296     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 297         ram_addr_t ram_addr;
 298         hwaddr paddr;
 299
 300         /* Hope we are lucky for AO MCE */
 301         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 302             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 303                                                 &paddr)) {
 304             fprintf(stderr, "Hardware memory error for memory used by "
 305                     "QEMU itself instead of guest system!: %p\n", addr);
 306             return 0;
 307         }
 308         kvm_hwpoison_page_add(ram_addr);
 309         kvm_mce_inject(first_cpu, paddr, code);
 310     } else {
 311         if (code == BUS_MCEERR_AO) {
 312             return 0;
 313         } else if (code == BUS_MCEERR_AR) {
 314             hardware_memory_error();
 315         } else {
 316             return 1;
 317         }
 318     }
 319     return 0;
 320 }
 321
 322 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 323 {
 324     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 325         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 326         struct kvm_x86_mce mce;
 327
 328         env->exception_injected = -1;
 329
 330         /*
 331          * There must be at least one bank in use if an MCE is pending.
 332          * Find it and use its values for the event injection.
 333          */
 334         for (bank = 0; bank < bank_num; bank++) {
 335             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 336                 break;
 337             }
 338         }
 339         assert(bank < bank_num);
 340
 341         mce.bank = bank;
 342         mce.status = env->mce_banks[bank * 4 + 1];
 343         mce.mcg_status = env->mcg_status;
 344         mce.addr = env->mce_banks[bank * 4 + 2];
 345         mce.misc = env->mce_banks[bank * 4 + 3];
 346
 347         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 348     }
 349     return 0;
 350 }
 351
 352 static void cpu_update_state(void *opaque, int running, RunState state)
 353 {
 354     CPUX86State *env = opaque;
 355
 356     if (running) {
 357         env->tsc_valid = false;
 358     }
 359 }
 360
 361 int kvm_arch_init_vcpu(CPUX86State *env)
 362 {
 363     struct {
 364         struct kvm_cpuid2 cpuid;
 365         struct kvm_cpuid_entry2 entries[100];
 366     } QEMU_PACKED cpuid_data;
 367     KVMState *s = env->kvm_state;
 368     uint32_t limit, i, j, cpuid_i;
 369     uint32_t unused;
 370     struct kvm_cpuid_entry2 *c;
 371     uint32_t signature[3];
 372     int r;
 373
 374     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 375
 376     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 377     j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER;
 378     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 379     env->cpuid_ext_features |= i;
 380     if (j && kvm_irqchip_in_kernel() &&
 381         kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 382         env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER;
 383     }
 384
 385     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 386                                                              0, R_EDX);
 387     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 388                                                              0, R_ECX);
 389     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 390                                                              0, R_EDX);
 391
 392     cpuid_i = 0;
 393
 394     /* Paravirtualization CPUIDs */
 395     c = &cpuid_data.entries[cpuid_i++];
 396     memset(c, 0, sizeof(*c));
 397     c->function = KVM_CPUID_SIGNATURE;
 398     if (!hyperv_enabled()) {
 399         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 400         c->eax = 0;
 401     } else {
 402         memcpy(signature, "Microsoft Hv", 12);
 403         c->eax = HYPERV_CPUID_MIN;
 404     }
 405     c->ebx = signature[0];
 406     c->ecx = signature[1];
 407     c->edx = signature[2];
 408
 409     c = &cpuid_data.entries[cpuid_i++];
 410     memset(c, 0, sizeof(*c));
 411     c->function = KVM_CPUID_FEATURES;
 412     c->eax = env->cpuid_kvm_features &
 413         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 414
 415     if (hyperv_enabled()) {
 416         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 417         c->eax = signature[0];
 418
 419         c = &cpuid_data.entries[cpuid_i++];
 420         memset(c, 0, sizeof(*c));
 421         c->function = HYPERV_CPUID_VERSION;
 422         c->eax = 0x00001bbc;
 423         c->ebx = 0x00060001;
 424
 425         c = &cpuid_data.entries[cpuid_i++];
 426         memset(c, 0, sizeof(*c));
 427         c->function = HYPERV_CPUID_FEATURES;
 428         if (hyperv_relaxed_timing_enabled()) {
 429             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 430         }
 431         if (hyperv_vapic_recommended()) {
 432             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 433             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 434         }
 435
 436         c = &cpuid_data.entries[cpuid_i++];
 437         memset(c, 0, sizeof(*c));
 438         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 439         if (hyperv_relaxed_timing_enabled()) {
 440             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 441         }
 442         if (hyperv_vapic_recommended()) {
 443             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 444         }
 445         c->ebx = hyperv_get_spinlock_retries();
 446
 447         c = &cpuid_data.entries[cpuid_i++];
 448         memset(c, 0, sizeof(*c));
 449         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 450         c->eax = 0x40;
 451         c->ebx = 0x40;
 452
 453         c = &cpuid_data.entries[cpuid_i++];
 454         memset(c, 0, sizeof(*c));
 455         c->function = KVM_CPUID_SIGNATURE_NEXT;
 456         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 457         c->eax = 0;
 458         c->ebx = signature[0];
 459         c->ecx = signature[1];
 460         c->edx = signature[2];
 461     }
 462
 463     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 464
 465     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 466
 467     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 468
 469     for (i = 0; i <= limit; i++) {
 470         c = &cpuid_data.entries[cpuid_i++];
 471
 472         switch (i) {
 473         case 2: {
 474             /* Keep reading function 2 till all the input is received */
 475             int times;
 476
 477             c->function = i;
 478             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 479                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 480             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 481             times = c->eax & 0xff;
 482
 483             for (j = 1; j < times; ++j) {
 484                 c = &cpuid_data.entries[cpuid_i++];
 485                 c->function = i;
 486                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 487                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 488             }
 489             break;
 490         }
 491         case 4:
 492         case 0xb:
 493         case 0xd:
 494             for (j = 0; ; j++) {
 495                 if (i == 0xd && j == 64) {
 496                     break;
 497                 }
 498                 c->function = i;
 499                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 500                 c->index = j;
 501                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 502
 503                 if (i == 4 && c->eax == 0) {
 504                     break;
 505                 }
 506                 if (i == 0xb && !(c->ecx & 0xff00)) {
 507                     break;
 508                 }
 509                 if (i == 0xd && c->eax == 0) {
 510                     continue;
 511                 }
 512                 c = &cpuid_data.entries[cpuid_i++];
 513             }
 514             break;
 515         default:
 516             c->function = i;
 517             c->flags = 0;
 518             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 519             break;
 520         }
 521     }
 522     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 523
 524     for (i = 0x80000000; i <= limit; i++) {
 525         c = &cpuid_data.entries[cpuid_i++];
 526
 527         c->function = i;
 528         c->flags = 0;
 529         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 530     }
 531
 532     /* Call Centaur's CPUID instructions they are supported. */
 533     if (env->cpuid_xlevel2 > 0) {
 534         env->cpuid_ext4_features &=
 535             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 536         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 537
 538         for (i = 0xC0000000; i <= limit; i++) {
 539             c = &cpuid_data.entries[cpuid_i++];
 540
 541             c->function = i;
 542             c->flags = 0;
 543             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 544         }
 545     }
 546
 547     cpuid_data.cpuid.nent = cpuid_i;
 548
 549     if (((env->cpuid_version >> 8)&0xF) >= 6
 550         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 551         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 552         uint64_t mcg_cap;
 553         int banks;
 554         int ret;
 555
 556         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 557         if (ret < 0) {
 558             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 559             return ret;
 560         }
 561
 562         if (banks > MCE_BANKS_DEF) {
 563             banks = MCE_BANKS_DEF;
 564         }
 565         mcg_cap &= MCE_CAP_DEF;
 566         mcg_cap |= banks;
 567         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 568         if (ret < 0) {
 569             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 570             return ret;
 571         }
 572
 573         env->mcg_cap = mcg_cap;
 574     }
 575
 576     qemu_add_vm_change_state_handler(cpu_update_state, env);
 577
 578     cpuid_data.cpuid.padding = 0;
 579     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 580     if (r) {
 581         return r;
 582     }
 583
 584     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 585     if (r && env->tsc_khz) {
 586         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 587         if (r < 0) {
 588             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 589             return r;
 590         }
 591     }
 592
 593     if (kvm_has_xsave()) {
 594         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 595     }
 596
 597     return 0;
 598 }
 599
 600 void kvm_arch_reset_vcpu(CPUX86State *env)
 601 {
 602     X86CPU *cpu = x86_env_get_cpu(env);
 603
 604     env->exception_injected = -1;
 605     env->interrupt_injected = -1;
 606     env->xcr0 = 1;
 607     if (kvm_irqchip_in_kernel()) {
 608         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 609                                           KVM_MP_STATE_UNINITIALIZED;
 610     } else {
 611         env->mp_state = KVM_MP_STATE_RUNNABLE;
 612     }
 613 }
 614
 615 static int kvm_get_supported_msrs(KVMState *s)
 616 {
 617     static int kvm_supported_msrs;
 618     int ret = 0;
 619
 620     /* first time */
 621     if (kvm_supported_msrs == 0) {
 622         struct kvm_msr_list msr_list, *kvm_msr_list;
 623
 624         kvm_supported_msrs = -1;
 625
 626         /* Obtain MSR list from KVM.  These are the MSRs that we must
 627          * save/restore */
 628         msr_list.nmsrs = 0;
 629         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 630         if (ret < 0 && ret != -E2BIG) {
 631             return ret;
 632         }
 633         /* Old kernel modules had a bug and could write beyond the provided
 634            memory. Allocate at least a safe amount of 1K. */
 635         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 636                                               msr_list.nmsrs *
 637                                               sizeof(msr_list.indices[0])));
 638
 639         kvm_msr_list->nmsrs = msr_list.nmsrs;
 640         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 641         if (ret >= 0) {
 642             int i;
 643
 644             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 645                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 646                     has_msr_star = true;
 647                     continue;
 648                 }
 649                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 650                     has_msr_hsave_pa = true;
 651                     continue;
 652                 }
 653                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 654                     has_msr_tsc_deadline = true;
 655                     continue;
 656                 }
 657                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 658                     has_msr_misc_enable = true;
 659                     continue;
 660                 }
 661             }
 662         }
 663
 664         g_free(kvm_msr_list);
 665     }
 666
 667     return ret;
 668 }
 669
 670 int kvm_arch_init(KVMState *s)
 671 {
 672     QemuOptsList *list = qemu_find_opts("machine");
 673     uint64_t identity_base = 0xfffbc000;
 674     uint64_t shadow_mem;
 675     int ret;
 676     struct utsname utsname;
 677
 678     ret = kvm_get_supported_msrs(s);
 679     if (ret < 0) {
 680         return ret;
 681     }
 682
 683     uname(&utsname);
 684     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 685
 686     /*
 687      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 688      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 689      * Since these must be part of guest physical memory, we need to allocate
 690      * them, both by setting their start addresses in the kernel and by
 691      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 692      *
 693      * Older KVM versions may not support setting the identity map base. In
 694      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 695      * size.
 696      */
 697     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 698         /* Allows up to 16M BIOSes. */
 699         identity_base = 0xfeffc000;
 700
 701         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 702         if (ret < 0) {
 703             return ret;
 704         }
 705     }
 706
 707     /* Set TSS base one page after EPT identity map. */
 708     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 709     if (ret < 0) {
 710         return ret;
 711     }
 712
 713     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 714     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 715     if (ret < 0) {
 716         fprintf(stderr, "e820_add_entry() table is full\n");
 717         return ret;
 718     }
 719     qemu_register_reset(kvm_unpoison_all, NULL);
 720
 721     if (!QTAILQ_EMPTY(&list->head)) {
 722         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 723                                        "kvm_shadow_mem", -1);
 724         if (shadow_mem != -1) {
 725             shadow_mem /= 4096;
 726             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 727             if (ret < 0) {
 728                 return ret;
 729             }
 730         }
 731     }
 732     return 0;
 733 }
 734
 735 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 736 {
 737     lhs->selector = rhs->selector;
 738     lhs->base = rhs->base;
 739     lhs->limit = rhs->limit;
 740     lhs->type = 3;
 741     lhs->present = 1;
 742     lhs->dpl = 3;
 743     lhs->db = 0;
 744     lhs->s = 1;
 745     lhs->l = 0;
 746     lhs->g = 0;
 747     lhs->avl = 0;
 748     lhs->unusable = 0;
 749 }
 750
 751 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 752 {
 753     unsigned flags = rhs->flags;
 754     lhs->selector = rhs->selector;
 755     lhs->base = rhs->base;
 756     lhs->limit = rhs->limit;
 757     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 758     lhs->present = (flags & DESC_P_MASK) != 0;
 759     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 760     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 761     lhs->s = (flags & DESC_S_MASK) != 0;
 762     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 763     lhs->g = (flags & DESC_G_MASK) != 0;
 764     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 765     lhs->unusable = 0;
 766     lhs->padding = 0;
 767 }
 768
 769 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 770 {
 771     lhs->selector = rhs->selector;
 772     lhs->base = rhs->base;
 773     lhs->limit = rhs->limit;
 774     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 775                  (rhs->present * DESC_P_MASK) |
 776                  (rhs->dpl << DESC_DPL_SHIFT) |
 777                  (rhs->db << DESC_B_SHIFT) |
 778                  (rhs->s * DESC_S_MASK) |
 779                  (rhs->l << DESC_L_SHIFT) |
 780                  (rhs->g * DESC_G_MASK) |
 781                  (rhs->avl * DESC_AVL_MASK);
 782 }
 783
 784 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 785 {
 786     if (set) {
 787         *kvm_reg = *qemu_reg;
 788     } else {
 789         *qemu_reg = *kvm_reg;
 790     }
 791 }
 792
 793 static int kvm_getput_regs(CPUX86State *env, int set)
 794 {
 795     struct kvm_regs regs;
 796     int ret = 0;
 797
 798     if (!set) {
 799         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 800         if (ret < 0) {
 801             return ret;
 802         }
 803     }
 804
 805     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 806     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 807     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 808     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 809     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 810     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 811     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 812     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 813 #ifdef TARGET_X86_64
 814     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 815     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 816     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 817     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 818     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 819     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 820     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 821     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 822 #endif
 823
 824     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 825     kvm_getput_reg(&regs.rip, &env->eip, set);
 826
 827     if (set) {
 828         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 829     }
 830
 831     return ret;
 832 }
 833
 834 static int kvm_put_fpu(CPUX86State *env)
 835 {
 836     struct kvm_fpu fpu;
 837     int i;
 838
 839     memset(&fpu, 0, sizeof fpu);
 840     fpu.fsw = env->fpus & ~(7 << 11);
 841     fpu.fsw |= (env->fpstt & 7) << 11;
 842     fpu.fcw = env->fpuc;
 843     fpu.last_opcode = env->fpop;
 844     fpu.last_ip = env->fpip;
 845     fpu.last_dp = env->fpdp;
 846     for (i = 0; i < 8; ++i) {
 847         fpu.ftwx |= (!env->fptags[i]) << i;
 848     }
 849     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 850     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 851     fpu.mxcsr = env->mxcsr;
 852
 853     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 854 }
 855
 856 #define XSAVE_FCW_FSW     0
 857 #define XSAVE_FTW_FOP     1
 858 #define XSAVE_CWD_RIP     2
 859 #define XSAVE_CWD_RDP     4
 860 #define XSAVE_MXCSR       6
 861 #define XSAVE_ST_SPACE    8
 862 #define XSAVE_XMM_SPACE   40
 863 #define XSAVE_XSTATE_BV   128
 864 #define XSAVE_YMMH_SPACE  144
 865
 866 static int kvm_put_xsave(CPUX86State *env)
 867 {
 868     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 869     uint16_t cwd, swd, twd;
 870     int i, r;
 871
 872     if (!kvm_has_xsave()) {
 873         return kvm_put_fpu(env);
 874     }
 875
 876     memset(xsave, 0, sizeof(struct kvm_xsave));
 877     twd = 0;
 878     swd = env->fpus & ~(7 << 11);
 879     swd |= (env->fpstt & 7) << 11;
 880     cwd = env->fpuc;
 881     for (i = 0; i < 8; ++i) {
 882         twd |= (!env->fptags[i]) << i;
 883     }
 884     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 885     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 886     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 887     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 888     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 889             sizeof env->fpregs);
 890     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 891             sizeof env->xmm_regs);
 892     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 893     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 894     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 895             sizeof env->ymmh_regs);
 896     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 897     return r;
 898 }
 899
 900 static int kvm_put_xcrs(CPUX86State *env)
 901 {
 902     struct kvm_xcrs xcrs;
 903
 904     if (!kvm_has_xcrs()) {
 905         return 0;
 906     }
 907
 908     xcrs.nr_xcrs = 1;
 909     xcrs.flags = 0;
 910     xcrs.xcrs[0].xcr = 0;
 911     xcrs.xcrs[0].value = env->xcr0;
 912     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 913 }
 914
 915 static int kvm_put_sregs(CPUX86State *env)
 916 {
 917     struct kvm_sregs sregs;
 918
 919     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 920     if (env->interrupt_injected >= 0) {
 921         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 922                 (uint64_t)1 << (env->interrupt_injected % 64);
 923     }
 924
 925     if ((env->eflags & VM_MASK)) {
 926         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 927         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 928         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 929         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 930         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 931         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 932     } else {
 933         set_seg(&sregs.cs, &env->segs[R_CS]);
 934         set_seg(&sregs.ds, &env->segs[R_DS]);
 935         set_seg(&sregs.es, &env->segs[R_ES]);
 936         set_seg(&sregs.fs, &env->segs[R_FS]);
 937         set_seg(&sregs.gs, &env->segs[R_GS]);
 938         set_seg(&sregs.ss, &env->segs[R_SS]);
 939     }
 940
 941     set_seg(&sregs.tr, &env->tr);
 942     set_seg(&sregs.ldt, &env->ldt);
 943
 944     sregs.idt.limit = env->idt.limit;
 945     sregs.idt.base = env->idt.base;
 946     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 947     sregs.gdt.limit = env->gdt.limit;
 948     sregs.gdt.base = env->gdt.base;
 949     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 950
 951     sregs.cr0 = env->cr[0];
 952     sregs.cr2 = env->cr[2];
 953     sregs.cr3 = env->cr[3];
 954     sregs.cr4 = env->cr[4];
 955
 956     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 957     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 958
 959     sregs.efer = env->efer;
 960
 961     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 962 }
 963
 964 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 965                               uint32_t index, uint64_t value)
 966 {
 967     entry->index = index;
 968     entry->data = value;
 969 }
 970
 971 static int kvm_put_msrs(CPUX86State *env, int level)
 972 {
 973     struct {
 974         struct kvm_msrs info;
 975         struct kvm_msr_entry entries[100];
 976     } msr_data;
 977     struct kvm_msr_entry *msrs = msr_data.entries;
 978     int n = 0;
 979
 980     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 981     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 982     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 983     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 984     if (has_msr_star) {
 985         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 986     }
 987     if (has_msr_hsave_pa) {
 988         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 989     }
 990     if (has_msr_tsc_deadline) {
 991         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 992     }
 993     if (has_msr_misc_enable) {
 994         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 995                           env->msr_ia32_misc_enable);
 996     }
 997 #ifdef TARGET_X86_64
 998     if (lm_capable_kernel) {
 999         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1000         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1001         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1002         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1003     }
1004 #endif
1005     if (level == KVM_PUT_FULL_STATE) {
1006         /*
1007          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1008          * writeback. Until this is fixed, we only write the offset to SMP
1009          * guests after migration, desynchronizing the VCPUs, but avoiding
1010          * huge jump-backs that would occur without any writeback at all.
1011          */
1012         if (smp_cpus == 1 || env->tsc != 0) {
1013             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1014         }
1015     }
1016     /*
1017      * The following paravirtual MSRs have side effects on the guest or are
1018      * too heavy for normal writeback. Limit them to reset or full state
1019      * updates.
1020      */
1021     if (level >= KVM_PUT_RESET_STATE) {
1022         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1023                           env->system_time_msr);
1024         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1025         if (has_msr_async_pf_en) {
1026             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1027                               env->async_pf_en_msr);
1028         }
1029         if (has_msr_pv_eoi_en) {
1030             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1031                               env->pv_eoi_en_msr);
1032         }
1033         if (hyperv_hypercall_available()) {
1034             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1035             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1036         }
1037         if (hyperv_vapic_recommended()) {
1038             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1039         }
1040     }
1041     if (env->mcg_cap) {
1042         int i;
1043
1044         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1045         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1046         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1047             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1048         }
1049     }
1050
1051     msr_data.info.nmsrs = n;
1052
1053     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1054
1055 }
1056
1057
1058 static int kvm_get_fpu(CPUX86State *env)
1059 {
1060     struct kvm_fpu fpu;
1061     int i, ret;
1062
1063     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1064     if (ret < 0) {
1065         return ret;
1066     }
1067
1068     env->fpstt = (fpu.fsw >> 11) & 7;
1069     env->fpus = fpu.fsw;
1070     env->fpuc = fpu.fcw;
1071     env->fpop = fpu.last_opcode;
1072     env->fpip = fpu.last_ip;
1073     env->fpdp = fpu.last_dp;
1074     for (i = 0; i < 8; ++i) {
1075         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1076     }
1077     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1078     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1079     env->mxcsr = fpu.mxcsr;
1080
1081     return 0;
1082 }
1083
1084 static int kvm_get_xsave(CPUX86State *env)
1085 {
1086     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1087     int ret, i;
1088     uint16_t cwd, swd, twd;
1089
1090     if (!kvm_has_xsave()) {
1091         return kvm_get_fpu(env);
1092     }
1093
1094     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1095     if (ret < 0) {
1096         return ret;
1097     }
1098
1099     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1100     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1101     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1102     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1103     env->fpstt = (swd >> 11) & 7;
1104     env->fpus = swd;
1105     env->fpuc = cwd;
1106     for (i = 0; i < 8; ++i) {
1107         env->fptags[i] = !((twd >> i) & 1);
1108     }
1109     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1110     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1111     env->mxcsr = xsave->region[XSAVE_MXCSR];
1112     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1113             sizeof env->fpregs);
1114     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1115             sizeof env->xmm_regs);
1116     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1117     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1118             sizeof env->ymmh_regs);
1119     return 0;
1120 }
1121
1122 static int kvm_get_xcrs(CPUX86State *env)
1123 {
1124     int i, ret;
1125     struct kvm_xcrs xcrs;
1126
1127     if (!kvm_has_xcrs()) {
1128         return 0;
1129     }
1130
1131     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1132     if (ret < 0) {
1133         return ret;
1134     }
1135
1136     for (i = 0; i < xcrs.nr_xcrs; i++) {
1137         /* Only support xcr0 now */
1138         if (xcrs.xcrs[0].xcr == 0) {
1139             env->xcr0 = xcrs.xcrs[0].value;
1140             break;
1141         }
1142     }
1143     return 0;
1144 }
1145
1146 static int kvm_get_sregs(CPUX86State *env)
1147 {
1148     struct kvm_sregs sregs;
1149     uint32_t hflags;
1150     int bit, i, ret;
1151
1152     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1153     if (ret < 0) {
1154         return ret;
1155     }
1156
1157     /* There can only be one pending IRQ set in the bitmap at a time, so try
1158        to find it and save its number instead (-1 for none). */
1159     env->interrupt_injected = -1;
1160     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1161         if (sregs.interrupt_bitmap[i]) {
1162             bit = ctz64(sregs.interrupt_bitmap[i]);
1163             env->interrupt_injected = i * 64 + bit;
1164             break;
1165         }
1166     }
1167
1168     get_seg(&env->segs[R_CS], &sregs.cs);
1169     get_seg(&env->segs[R_DS], &sregs.ds);
1170     get_seg(&env->segs[R_ES], &sregs.es);
1171     get_seg(&env->segs[R_FS], &sregs.fs);
1172     get_seg(&env->segs[R_GS], &sregs.gs);
1173     get_seg(&env->segs[R_SS], &sregs.ss);
1174
1175     get_seg(&env->tr, &sregs.tr);
1176     get_seg(&env->ldt, &sregs.ldt);
1177
1178     env->idt.limit = sregs.idt.limit;
1179     env->idt.base = sregs.idt.base;
1180     env->gdt.limit = sregs.gdt.limit;
1181     env->gdt.base = sregs.gdt.base;
1182
1183     env->cr[0] = sregs.cr0;
1184     env->cr[2] = sregs.cr2;
1185     env->cr[3] = sregs.cr3;
1186     env->cr[4] = sregs.cr4;
1187
1188     env->efer = sregs.efer;
1189
1190     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1191
1192 #define HFLAG_COPY_MASK \
1193     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1194        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1195        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1196        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1197
1198     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1199     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1200     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1201                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1202     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1203     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1204                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1205
1206     if (env->efer & MSR_EFER_LMA) {
1207         hflags |= HF_LMA_MASK;
1208     }
1209
1210     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1211         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1212     } else {
1213         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1214                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1215         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1216                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1217         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1218             !(hflags & HF_CS32_MASK)) {
1219             hflags |= HF_ADDSEG_MASK;
1220         } else {
1221             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1222                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1223         }
1224     }
1225     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1226
1227     return 0;
1228 }
1229
1230 static int kvm_get_msrs(CPUX86State *env)
1231 {
1232     struct {
1233         struct kvm_msrs info;
1234         struct kvm_msr_entry entries[100];
1235     } msr_data;
1236     struct kvm_msr_entry *msrs = msr_data.entries;
1237     int ret, i, n;
1238
1239     n = 0;
1240     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1241     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1242     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1243     msrs[n++].index = MSR_PAT;
1244     if (has_msr_star) {
1245         msrs[n++].index = MSR_STAR;
1246     }
1247     if (has_msr_hsave_pa) {
1248         msrs[n++].index = MSR_VM_HSAVE_PA;
1249     }
1250     if (has_msr_tsc_deadline) {
1251         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1252     }
1253     if (has_msr_misc_enable) {
1254         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1255     }
1256
1257     if (!env->tsc_valid) {
1258         msrs[n++].index = MSR_IA32_TSC;
1259         env->tsc_valid = !runstate_is_running();
1260     }
1261
1262 #ifdef TARGET_X86_64
1263     if (lm_capable_kernel) {
1264         msrs[n++].index = MSR_CSTAR;
1265         msrs[n++].index = MSR_KERNELGSBASE;
1266         msrs[n++].index = MSR_FMASK;
1267         msrs[n++].index = MSR_LSTAR;
1268     }
1269 #endif
1270     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1271     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1272     if (has_msr_async_pf_en) {
1273         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1274     }
1275     if (has_msr_pv_eoi_en) {
1276         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1277     }
1278
1279     if (env->mcg_cap) {
1280         msrs[n++].index = MSR_MCG_STATUS;
1281         msrs[n++].index = MSR_MCG_CTL;
1282         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1283             msrs[n++].index = MSR_MC0_CTL + i;
1284         }
1285     }
1286
1287     msr_data.info.nmsrs = n;
1288     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1289     if (ret < 0) {
1290         return ret;
1291     }
1292
1293     for (i = 0; i < ret; i++) {
1294         switch (msrs[i].index) {
1295         case MSR_IA32_SYSENTER_CS:
1296             env->sysenter_cs = msrs[i].data;
1297             break;
1298         case MSR_IA32_SYSENTER_ESP:
1299             env->sysenter_esp = msrs[i].data;
1300             break;
1301         case MSR_IA32_SYSENTER_EIP:
1302             env->sysenter_eip = msrs[i].data;
1303             break;
1304         case MSR_PAT:
1305             env->pat = msrs[i].data;
1306             break;
1307         case MSR_STAR:
1308             env->star = msrs[i].data;
1309             break;
1310 #ifdef TARGET_X86_64
1311         case MSR_CSTAR:
1312             env->cstar = msrs[i].data;
1313             break;
1314         case MSR_KERNELGSBASE:
1315             env->kernelgsbase = msrs[i].data;
1316             break;
1317         case MSR_FMASK:
1318             env->fmask = msrs[i].data;
1319             break;
1320         case MSR_LSTAR:
1321             env->lstar = msrs[i].data;
1322             break;
1323 #endif
1324         case MSR_IA32_TSC:
1325             env->tsc = msrs[i].data;
1326             break;
1327         case MSR_IA32_TSCDEADLINE:
1328             env->tsc_deadline = msrs[i].data;
1329             break;
1330         case MSR_VM_HSAVE_PA:
1331             env->vm_hsave = msrs[i].data;
1332             break;
1333         case MSR_KVM_SYSTEM_TIME:
1334             env->system_time_msr = msrs[i].data;
1335             break;
1336         case MSR_KVM_WALL_CLOCK:
1337             env->wall_clock_msr = msrs[i].data;
1338             break;
1339         case MSR_MCG_STATUS:
1340             env->mcg_status = msrs[i].data;
1341             break;
1342         case MSR_MCG_CTL:
1343             env->mcg_ctl = msrs[i].data;
1344             break;
1345         case MSR_IA32_MISC_ENABLE:
1346             env->msr_ia32_misc_enable = msrs[i].data;
1347             break;
1348         default:
1349             if (msrs[i].index >= MSR_MC0_CTL &&
1350                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1351                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1352             }
1353             break;
1354         case MSR_KVM_ASYNC_PF_EN:
1355             env->async_pf_en_msr = msrs[i].data;
1356             break;
1357         case MSR_KVM_PV_EOI_EN:
1358             env->pv_eoi_en_msr = msrs[i].data;
1359             break;
1360         }
1361     }
1362
1363     return 0;
1364 }
1365
1366 static int kvm_put_mp_state(CPUX86State *env)
1367 {
1368     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1369
1370     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1371 }
1372
1373 static int kvm_get_mp_state(CPUX86State *env)
1374 {
1375     struct kvm_mp_state mp_state;
1376     int ret;
1377
1378     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1379     if (ret < 0) {
1380         return ret;
1381     }
1382     env->mp_state = mp_state.mp_state;
1383     if (kvm_irqchip_in_kernel()) {
1384         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1385     }
1386     return 0;
1387 }
1388
1389 static int kvm_get_apic(CPUX86State *env)
1390 {
1391     DeviceState *apic = env->apic_state;
1392     struct kvm_lapic_state kapic;
1393     int ret;
1394
1395     if (apic && kvm_irqchip_in_kernel()) {
1396         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1397         if (ret < 0) {
1398             return ret;
1399         }
1400
1401         kvm_get_apic_state(apic, &kapic);
1402     }
1403     return 0;
1404 }
1405
1406 static int kvm_put_apic(CPUX86State *env)
1407 {
1408     DeviceState *apic = env->apic_state;
1409     struct kvm_lapic_state kapic;
1410
1411     if (apic && kvm_irqchip_in_kernel()) {
1412         kvm_put_apic_state(apic, &kapic);
1413
1414         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1415     }
1416     return 0;
1417 }
1418
1419 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1420 {
1421     struct kvm_vcpu_events events;
1422
1423     if (!kvm_has_vcpu_events()) {
1424         return 0;
1425     }
1426
1427     events.exception.injected = (env->exception_injected >= 0);
1428     events.exception.nr = env->exception_injected;
1429     events.exception.has_error_code = env->has_error_code;
1430     events.exception.error_code = env->error_code;
1431     events.exception.pad = 0;
1432
1433     events.interrupt.injected = (env->interrupt_injected >= 0);
1434     events.interrupt.nr = env->interrupt_injected;
1435     events.interrupt.soft = env->soft_interrupt;
1436
1437     events.nmi.injected = env->nmi_injected;
1438     events.nmi.pending = env->nmi_pending;
1439     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1440     events.nmi.pad = 0;
1441
1442     events.sipi_vector = env->sipi_vector;
1443
1444     events.flags = 0;
1445     if (level >= KVM_PUT_RESET_STATE) {
1446         events.flags |=
1447             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1448     }
1449
1450     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1451 }
1452
1453 static int kvm_get_vcpu_events(CPUX86State *env)
1454 {
1455     struct kvm_vcpu_events events;
1456     int ret;
1457
1458     if (!kvm_has_vcpu_events()) {
1459         return 0;
1460     }
1461
1462     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1463     if (ret < 0) {
1464        return ret;
1465     }
1466     env->exception_injected =
1467        events.exception.injected ? events.exception.nr : -1;
1468     env->has_error_code = events.exception.has_error_code;
1469     env->error_code = events.exception.error_code;
1470
1471     env->interrupt_injected =
1472         events.interrupt.injected ? events.interrupt.nr : -1;
1473     env->soft_interrupt = events.interrupt.soft;
1474
1475     env->nmi_injected = events.nmi.injected;
1476     env->nmi_pending = events.nmi.pending;
1477     if (events.nmi.masked) {
1478         env->hflags2 |= HF2_NMI_MASK;
1479     } else {
1480         env->hflags2 &= ~HF2_NMI_MASK;
1481     }
1482
1483     env->sipi_vector = events.sipi_vector;
1484
1485     return 0;
1486 }
1487
1488 static int kvm_guest_debug_workarounds(CPUX86State *env)
1489 {
1490     int ret = 0;
1491     unsigned long reinject_trap = 0;
1492
1493     if (!kvm_has_vcpu_events()) {
1494         if (env->exception_injected == 1) {
1495             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1496         } else if (env->exception_injected == 3) {
1497             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1498         }
1499         env->exception_injected = -1;
1500     }
1501
1502     /*
1503      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1504      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1505      * by updating the debug state once again if single-stepping is on.
1506      * Another reason to call kvm_update_guest_debug here is a pending debug
1507      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1508      * reinject them via SET_GUEST_DEBUG.
1509      */
1510     if (reinject_trap ||
1511         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1512         ret = kvm_update_guest_debug(env, reinject_trap);
1513     }
1514     return ret;
1515 }
1516
1517 static int kvm_put_debugregs(CPUX86State *env)
1518 {
1519     struct kvm_debugregs dbgregs;
1520     int i;
1521
1522     if (!kvm_has_debugregs()) {
1523         return 0;
1524     }
1525
1526     for (i = 0; i < 4; i++) {
1527         dbgregs.db[i] = env->dr[i];
1528     }
1529     dbgregs.dr6 = env->dr[6];
1530     dbgregs.dr7 = env->dr[7];
1531     dbgregs.flags = 0;
1532
1533     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1534 }
1535
1536 static int kvm_get_debugregs(CPUX86State *env)
1537 {
1538     struct kvm_debugregs dbgregs;
1539     int i, ret;
1540
1541     if (!kvm_has_debugregs()) {
1542         return 0;
1543     }
1544
1545     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1546     if (ret < 0) {
1547         return ret;
1548     }
1549     for (i = 0; i < 4; i++) {
1550         env->dr[i] = dbgregs.db[i];
1551     }
1552     env->dr[4] = env->dr[6] = dbgregs.dr6;
1553     env->dr[5] = env->dr[7] = dbgregs.dr7;
1554
1555     return 0;
1556 }
1557
1558 int kvm_arch_put_registers(CPUX86State *env, int level)
1559 {
1560     int ret;
1561
1562     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1563
1564     ret = kvm_getput_regs(env, 1);
1565     if (ret < 0) {
1566         return ret;
1567     }
1568     ret = kvm_put_xsave(env);
1569     if (ret < 0) {
1570         return ret;
1571     }
1572     ret = kvm_put_xcrs(env);
1573     if (ret < 0) {
1574         return ret;
1575     }
1576     ret = kvm_put_sregs(env);
1577     if (ret < 0) {
1578         return ret;
1579     }
1580     /* must be before kvm_put_msrs */
1581     ret = kvm_inject_mce_oldstyle(env);
1582     if (ret < 0) {
1583         return ret;
1584     }
1585     ret = kvm_put_msrs(env, level);
1586     if (ret < 0) {
1587         return ret;
1588     }
1589     if (level >= KVM_PUT_RESET_STATE) {
1590         ret = kvm_put_mp_state(env);
1591         if (ret < 0) {
1592             return ret;
1593         }
1594         ret = kvm_put_apic(env);
1595         if (ret < 0) {
1596             return ret;
1597         }
1598     }
1599     ret = kvm_put_vcpu_events(env, level);
1600     if (ret < 0) {
1601         return ret;
1602     }
1603     ret = kvm_put_debugregs(env);
1604     if (ret < 0) {
1605         return ret;
1606     }
1607     /* must be last */
1608     ret = kvm_guest_debug_workarounds(env);
1609     if (ret < 0) {
1610         return ret;
1611     }
1612     return 0;
1613 }
1614
1615 int kvm_arch_get_registers(CPUX86State *env)
1616 {
1617     int ret;
1618
1619     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1620
1621     ret = kvm_getput_regs(env, 0);
1622     if (ret < 0) {
1623         return ret;
1624     }
1625     ret = kvm_get_xsave(env);
1626     if (ret < 0) {
1627         return ret;
1628     }
1629     ret = kvm_get_xcrs(env);
1630     if (ret < 0) {
1631         return ret;
1632     }
1633     ret = kvm_get_sregs(env);
1634     if (ret < 0) {
1635         return ret;
1636     }
1637     ret = kvm_get_msrs(env);
1638     if (ret < 0) {
1639         return ret;
1640     }
1641     ret = kvm_get_mp_state(env);
1642     if (ret < 0) {
1643         return ret;
1644     }
1645     ret = kvm_get_apic(env);
1646     if (ret < 0) {
1647         return ret;
1648     }
1649     ret = kvm_get_vcpu_events(env);
1650     if (ret < 0) {
1651         return ret;
1652     }
1653     ret = kvm_get_debugregs(env);
1654     if (ret < 0) {
1655         return ret;
1656     }
1657     return 0;
1658 }
1659
1660 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1661 {
1662     int ret;
1663
1664     /* Inject NMI */
1665     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1666         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1667         DPRINTF("injected NMI\n");
1668         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1669         if (ret < 0) {
1670             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1671                     strerror(-ret));
1672         }
1673     }
1674
1675     if (!kvm_irqchip_in_kernel()) {
1676         /* Force the VCPU out of its inner loop to process any INIT requests
1677          * or pending TPR access reports. */
1678         if (env->interrupt_request &
1679             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1680             env->exit_request = 1;
1681         }
1682
1683         /* Try to inject an interrupt if the guest can accept it */
1684         if (run->ready_for_interrupt_injection &&
1685             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1686             (env->eflags & IF_MASK)) {
1687             int irq;
1688
1689             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1690             irq = cpu_get_pic_interrupt(env);
1691             if (irq >= 0) {
1692                 struct kvm_interrupt intr;
1693
1694                 intr.irq = irq;
1695                 DPRINTF("injected interrupt %d\n", irq);
1696                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1697                 if (ret < 0) {
1698                     fprintf(stderr,
1699                             "KVM: injection failed, interrupt lost (%s)\n",
1700                             strerror(-ret));
1701                 }
1702             }
1703         }
1704
1705         /* If we have an interrupt but the guest is not ready to receive an
1706          * interrupt, request an interrupt window exit.  This will
1707          * cause a return to userspace as soon as the guest is ready to
1708          * receive interrupts. */
1709         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1710             run->request_interrupt_window = 1;
1711         } else {
1712             run->request_interrupt_window = 0;
1713         }
1714
1715         DPRINTF("setting tpr\n");
1716         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1717     }
1718 }
1719
1720 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1721 {
1722     if (run->if_flag) {
1723         env->eflags |= IF_MASK;
1724     } else {
1725         env->eflags &= ~IF_MASK;
1726     }
1727     cpu_set_apic_tpr(env->apic_state, run->cr8);
1728     cpu_set_apic_base(env->apic_state, run->apic_base);
1729 }
1730
1731 int kvm_arch_process_async_events(CPUX86State *env)
1732 {
1733     X86CPU *cpu = x86_env_get_cpu(env);
1734
1735     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1736         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1737         assert(env->mcg_cap);
1738
1739         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1740
1741         kvm_cpu_synchronize_state(env);
1742
1743         if (env->exception_injected == EXCP08_DBLE) {
1744             /* this means triple fault */
1745             qemu_system_reset_request();
1746             env->exit_request = 1;
1747             return 0;
1748         }
1749         env->exception_injected = EXCP12_MCHK;
1750         env->has_error_code = 0;
1751
1752         env->halted = 0;
1753         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1754             env->mp_state = KVM_MP_STATE_RUNNABLE;
1755         }
1756     }
1757
1758     if (kvm_irqchip_in_kernel()) {
1759         return 0;
1760     }
1761
1762     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1763         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1764         apic_poll_irq(env->apic_state);
1765     }
1766     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1767          (env->eflags & IF_MASK)) ||
1768         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1769         env->halted = 0;
1770     }
1771     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1772         kvm_cpu_synchronize_state(env);
1773         do_cpu_init(cpu);
1774     }
1775     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1776         kvm_cpu_synchronize_state(env);
1777         do_cpu_sipi(cpu);
1778     }
1779     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1780         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1781         kvm_cpu_synchronize_state(env);
1782         apic_handle_tpr_access_report(env->apic_state, env->eip,
1783                                       env->tpr_access_type);
1784     }
1785
1786     return env->halted;
1787 }
1788
1789 static int kvm_handle_halt(CPUX86State *env)
1790 {
1791     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1792           (env->eflags & IF_MASK)) &&
1793         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1794         env->halted = 1;
1795         return EXCP_HLT;
1796     }
1797
1798     return 0;
1799 }
1800
1801 static int kvm_handle_tpr_access(CPUX86State *env)
1802 {
1803     struct kvm_run *run = env->kvm_run;
1804
1805     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1806                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1807                                                            : TPR_ACCESS_READ);
1808     return 1;
1809 }
1810
1811 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1812 {
1813     static const uint8_t int3 = 0xcc;
1814
1815     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1816         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1817         return -EINVAL;
1818     }
1819     return 0;
1820 }
1821
1822 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1823 {
1824     uint8_t int3;
1825
1826     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1827         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1828         return -EINVAL;
1829     }
1830     return 0;
1831 }
1832
1833 static struct {
1834     target_ulong addr;
1835     int len;
1836     int type;
1837 } hw_breakpoint[4];
1838
1839 static int nb_hw_breakpoint;
1840
1841 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1842 {
1843     int n;
1844
1845     for (n = 0; n < nb_hw_breakpoint; n++) {
1846         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1847             (hw_breakpoint[n].len == len || len == -1)) {
1848             return n;
1849         }
1850     }
1851     return -1;
1852 }
1853
1854 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1855                                   target_ulong len, int type)
1856 {
1857     switch (type) {
1858     case GDB_BREAKPOINT_HW:
1859         len = 1;
1860         break;
1861     case GDB_WATCHPOINT_WRITE:
1862     case GDB_WATCHPOINT_ACCESS:
1863         switch (len) {
1864         case 1:
1865             break;
1866         case 2:
1867         case 4:
1868         case 8:
1869             if (addr & (len - 1)) {
1870                 return -EINVAL;
1871             }
1872             break;
1873         default:
1874             return -EINVAL;
1875         }
1876         break;
1877     default:
1878         return -ENOSYS;
1879     }
1880
1881     if (nb_hw_breakpoint == 4) {
1882         return -ENOBUFS;
1883     }
1884     if (find_hw_breakpoint(addr, len, type) >= 0) {
1885         return -EEXIST;
1886     }
1887     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1888     hw_breakpoint[nb_hw_breakpoint].len = len;
1889     hw_breakpoint[nb_hw_breakpoint].type = type;
1890     nb_hw_breakpoint++;
1891
1892     return 0;
1893 }
1894
1895 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1896                                   target_ulong len, int type)
1897 {
1898     int n;
1899
1900     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1901     if (n < 0) {
1902         return -ENOENT;
1903     }
1904     nb_hw_breakpoint--;
1905     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1906
1907     return 0;
1908 }
1909
1910 void kvm_arch_remove_all_hw_breakpoints(void)
1911 {
1912     nb_hw_breakpoint = 0;
1913 }
1914
1915 static CPUWatchpoint hw_watchpoint;
1916
1917 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1918 {
1919     int ret = 0;
1920     int n;
1921
1922     if (arch_info->exception == 1) {
1923         if (arch_info->dr6 & (1 << 14)) {
1924             if (cpu_single_env->singlestep_enabled) {
1925                 ret = EXCP_DEBUG;
1926             }
1927         } else {
1928             for (n = 0; n < 4; n++) {
1929                 if (arch_info->dr6 & (1 << n)) {
1930                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1931                     case 0x0:
1932                         ret = EXCP_DEBUG;
1933                         break;
1934                     case 0x1:
1935                         ret = EXCP_DEBUG;
1936                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1937                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1938                         hw_watchpoint.flags = BP_MEM_WRITE;
1939                         break;
1940                     case 0x3:
1941                         ret = EXCP_DEBUG;
1942                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1943                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1944                         hw_watchpoint.flags = BP_MEM_ACCESS;
1945                         break;
1946                     }
1947                 }
1948             }
1949         }
1950     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1951         ret = EXCP_DEBUG;
1952     }
1953     if (ret == 0) {
1954         cpu_synchronize_state(cpu_single_env);
1955         assert(cpu_single_env->exception_injected == -1);
1956
1957         /* pass to guest */
1958         cpu_single_env->exception_injected = arch_info->exception;
1959         cpu_single_env->has_error_code = 0;
1960     }
1961
1962     return ret;
1963 }
1964
1965 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1966 {
1967     const uint8_t type_code[] = {
1968         [GDB_BREAKPOINT_HW] = 0x0,
1969         [GDB_WATCHPOINT_WRITE] = 0x1,
1970         [GDB_WATCHPOINT_ACCESS] = 0x3
1971     };
1972     const uint8_t len_code[] = {
1973         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1974     };
1975     int n;
1976
1977     if (kvm_sw_breakpoints_active(env)) {
1978         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1979     }
1980     if (nb_hw_breakpoint > 0) {
1981         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1982         dbg->arch.debugreg[7] = 0x0600;
1983         for (n = 0; n < nb_hw_breakpoint; n++) {
1984             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1985             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1986                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1987                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1988         }
1989     }
1990 }
1991
1992 static bool host_supports_vmx(void)
1993 {
1994     uint32_t ecx, unused;
1995
1996     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1997     return ecx & CPUID_EXT_VMX;
1998 }
1999
2000 #define VMX_INVALID_GUEST_STATE 0x80000021
2001
2002 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2003 {
2004     uint64_t code;
2005     int ret;
2006
2007     switch (run->exit_reason) {
2008     case KVM_EXIT_HLT:
2009         DPRINTF("handle_hlt\n");
2010         ret = kvm_handle_halt(env);
2011         break;
2012     case KVM_EXIT_SET_TPR:
2013         ret = 0;
2014         break;
2015     case KVM_EXIT_TPR_ACCESS:
2016         ret = kvm_handle_tpr_access(env);
2017         break;
2018     case KVM_EXIT_FAIL_ENTRY:
2019         code = run->fail_entry.hardware_entry_failure_reason;
2020         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2021                 code);
2022         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2023             fprintf(stderr,
2024                     "\nIf you're running a guest on an Intel machine without "
2025                         "unrestricted mode\n"
2026                     "support, the failure can be most likely due to the guest "
2027                         "entering an invalid\n"
2028                     "state for Intel VT. For example, the guest maybe running "
2029                         "in big real mode\n"
2030                     "which is not supported on less recent Intel processors."
2031                         "\n\n");
2032         }
2033         ret = -1;
2034         break;
2035     case KVM_EXIT_EXCEPTION:
2036         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2037                 run->ex.exception, run->ex.error_code);
2038         ret = -1;
2039         break;
2040     case KVM_EXIT_DEBUG:
2041         DPRINTF("kvm_exit_debug\n");
2042         ret = kvm_handle_debug(&run->debug.arch);
2043         break;
2044     default:
2045         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2046         ret = -1;
2047         break;
2048     }
2049
2050     return ret;
2051 }
2052
2053 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2054 {
2055     kvm_cpu_synchronize_state(env);
2056     return !(env->cr[0] & CR0_PE_MASK) ||
2057            ((env->segs[R_CS].selector  & 3) != 3);
2058 }
2059
2060 void kvm_arch_init_irq_routing(KVMState *s)
2061 {
2062     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2063         /* If kernel can't do irq routing, interrupt source
2064          * override 0->2 cannot be set up as required by HPET.
2065          * So we have to disable it.
2066          */
2067         no_hpet = 1;
2068     }
2069     /* We know at this point that we're using the in-kernel
2070      * irqchip, so we can use irqfds, and on x86 we know
2071      * we can use msi via irqfd and GSI routing.
2072      */
2073     kvm_irqfds_allowed = true;
2074     kvm_msi_via_irqfd_allowed = true;
2075     kvm_gsi_routing_allowed = true;
2076 }
2077
2078 /* Classic KVM device assignment interface. Will remain x86 only. */
2079 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2080                           uint32_t flags, uint32_t *dev_id)
2081 {
2082     struct kvm_assigned_pci_dev dev_data = {
2083         .segnr = dev_addr->domain,
2084         .busnr = dev_addr->bus,
2085         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2086         .flags = flags,
2087     };
2088     int ret;
2089
2090     dev_data.assigned_dev_id =
2091         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2092
2093     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2094     if (ret < 0) {
2095         return ret;
2096     }
2097
2098     *dev_id = dev_data.assigned_dev_id;
2099
2100     return 0;
2101 }
2102
2103 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2104 {
2105     struct kvm_assigned_pci_dev dev_data = {
2106         .assigned_dev_id = dev_id,
2107     };
2108
2109     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2110 }
2111
2112 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2113                                    uint32_t irq_type, uint32_t guest_irq)
2114 {
2115     struct kvm_assigned_irq assigned_irq = {
2116         .assigned_dev_id = dev_id,
2117         .guest_irq = guest_irq,
2118         .flags = irq_type,
2119     };
2120
2121     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2122         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2123     } else {
2124         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2125     }
2126 }
2127
2128 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2129                            uint32_t guest_irq)
2130 {
2131     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2132         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2133
2134     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2135 }
2136
2137 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2138 {
2139     struct kvm_assigned_pci_dev dev_data = {
2140         .assigned_dev_id = dev_id,
2141         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2142     };
2143
2144     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2145 }
2146
2147 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2148                                      uint32_t type)
2149 {
2150     struct kvm_assigned_irq assigned_irq = {
2151         .assigned_dev_id = dev_id,
2152         .flags = type,
2153     };
2154
2155     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2156 }
2157
2158 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2159 {
2160     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2161         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2162 }
2163
2164 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2165 {
2166     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2167                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2168 }
2169
2170 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2171 {
2172     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2173                                                 KVM_DEV_IRQ_HOST_MSI);
2174 }
2175
2176 bool kvm_device_msix_supported(KVMState *s)
2177 {
2178     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2179      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2180     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2181 }
2182
2183 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2184                                  uint32_t nr_vectors)
2185 {
2186     struct kvm_assigned_msix_nr msix_nr = {
2187         .assigned_dev_id = dev_id,
2188         .entry_nr = nr_vectors,
2189     };
2190
2191     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2192 }
2193
2194 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2195                                int virq)
2196 {
2197     struct kvm_assigned_msix_entry msix_entry = {
2198         .assigned_dev_id = dev_id,
2199         .gsi = virq,
2200         .entry = vector,
2201     };
2202
2203     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2204 }
2205
2206 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2207 {
2208     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2209                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2210 }
2211
2212 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2213 {
2214     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2215                                                 KVM_DEV_IRQ_HOST_MSIX);
2216 }