target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34
  35 //#define DEBUG_KVM
  36
  37 #ifdef DEBUG_KVM
  38 #define DPRINTF(fmt, ...) \
  39     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  40 #else
  41 #define DPRINTF(fmt, ...) \
  42     do { } while (0)
  43 #endif
  44
  45 #define MSR_KVM_WALL_CLOCK  0x11
  46 #define MSR_KVM_SYSTEM_TIME 0x12
  47
  48 #ifndef BUS_MCEERR_AR
  49 #define BUS_MCEERR_AR 4
  50 #endif
  51 #ifndef BUS_MCEERR_AO
  52 #define BUS_MCEERR_AO 5
  53 #endif
  54
  55 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  56     KVM_CAP_INFO(SET_TSS_ADDR),
  57     KVM_CAP_INFO(EXT_CPUID),
  58     KVM_CAP_INFO(MP_STATE),
  59     KVM_CAP_LAST_INFO
  60 };
  61
  62 static bool has_msr_star;
  63 static bool has_msr_hsave_pa;
  64 static bool has_msr_tsc_deadline;
  65 static bool has_msr_async_pf_en;
  66 static bool has_msr_misc_enable;
  67 static int lm_capable_kernel;
  68
  69 bool kvm_allows_irq0_override(void)
  70 {
  71     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  72 }
  73
  74 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  75 {
  76     struct kvm_cpuid2 *cpuid;
  77     int r, size;
  78
  79     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  80     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  81     cpuid->nent = max;
  82     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  83     if (r == 0 && cpuid->nent >= max) {
  84         r = -E2BIG;
  85     }
  86     if (r < 0) {
  87         if (r == -E2BIG) {
  88             g_free(cpuid);
  89             return NULL;
  90         } else {
  91             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  92                     strerror(-r));
  93             exit(1);
  94         }
  95     }
  96     return cpuid;
  97 }
  98
  99 struct kvm_para_features {
 100     int cap;
 101     int feature;
 102 } para_features[] = {
 103     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 104     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 105     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 106     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 107     { -1, -1 }
 108 };
 109
 110 static int get_para_features(KVMState *s)
 111 {
 112     int i, features = 0;
 113
 114     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 115         if (kvm_check_extension(s, para_features[i].cap)) {
 116             features |= (1 << para_features[i].feature);
 117         }
 118     }
 119
 120     return features;
 121 }
 122
 123
 124 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 125                                       uint32_t index, int reg)
 126 {
 127     struct kvm_cpuid2 *cpuid;
 128     int i, max;
 129     uint32_t ret = 0;
 130     uint32_t cpuid_1_edx;
 131     int has_kvm_features = 0;
 132
 133     max = 1;
 134     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 135         max *= 2;
 136     }
 137
 138     for (i = 0; i < cpuid->nent; ++i) {
 139         if (cpuid->entries[i].function == function &&
 140             cpuid->entries[i].index == index) {
 141             if (cpuid->entries[i].function == KVM_CPUID_FEATURES) {
 142                 has_kvm_features = 1;
 143             }
 144             switch (reg) {
 145             case R_EAX:
 146                 ret = cpuid->entries[i].eax;
 147                 break;
 148             case R_EBX:
 149                 ret = cpuid->entries[i].ebx;
 150                 break;
 151             case R_ECX:
 152                 ret = cpuid->entries[i].ecx;
 153                 break;
 154             case R_EDX:
 155                 ret = cpuid->entries[i].edx;
 156                 switch (function) {
 157                 case 1:
 158                     /* KVM before 2.6.30 misreports the following features */
 159                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 160                     break;
 161                 case 0x80000001:
 162                     /* On Intel, kvm returns cpuid according to the Intel spec,
 163                      * so add missing bits according to the AMD spec:
 164                      */
 165                     cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 166                     ret |= cpuid_1_edx & 0x183f7ff;
 167                     break;
 168                 }
 169                 break;
 170             }
 171         }
 172     }
 173
 174     g_free(cpuid);
 175
 176     /* fallback for older kernels */
 177     if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) {
 178         ret = get_para_features(s);
 179     }
 180
 181     return ret;
 182 }
 183
 184 typedef struct HWPoisonPage {
 185     ram_addr_t ram_addr;
 186     QLIST_ENTRY(HWPoisonPage) list;
 187 } HWPoisonPage;
 188
 189 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 190     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 191
 192 static void kvm_unpoison_all(void *param)
 193 {
 194     HWPoisonPage *page, *next_page;
 195
 196     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 197         QLIST_REMOVE(page, list);
 198         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 199         g_free(page);
 200     }
 201 }
 202
 203 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 204 {
 205     HWPoisonPage *page;
 206
 207     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 208         if (page->ram_addr == ram_addr) {
 209             return;
 210         }
 211     }
 212     page = g_malloc(sizeof(HWPoisonPage));
 213     page->ram_addr = ram_addr;
 214     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 215 }
 216
 217 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 218                                      int *max_banks)
 219 {
 220     int r;
 221
 222     r = kvm_check_extension(s, KVM_CAP_MCE);
 223     if (r > 0) {
 224         *max_banks = r;
 225         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 226     }
 227     return -ENOSYS;
 228 }
 229
 230 static void kvm_mce_inject(CPUX86State *env, target_phys_addr_t paddr, int code)
 231 {
 232     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 233                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 234     uint64_t mcg_status = MCG_STATUS_MCIP;
 235
 236     if (code == BUS_MCEERR_AR) {
 237         status |= MCI_STATUS_AR | 0x134;
 238         mcg_status |= MCG_STATUS_EIPV;
 239     } else {
 240         status |= 0xc0;
 241         mcg_status |= MCG_STATUS_RIPV;
 242     }
 243     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 244                        (MCM_ADDR_PHYS << 6) | 0xc,
 245                        cpu_x86_support_mca_broadcast(env) ?
 246                        MCE_INJECT_BROADCAST : 0);
 247 }
 248
 249 static void hardware_memory_error(void)
 250 {
 251     fprintf(stderr, "Hardware memory error!\n");
 252     exit(1);
 253 }
 254
 255 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 256 {
 257     ram_addr_t ram_addr;
 258     target_phys_addr_t paddr;
 259
 260     if ((env->mcg_cap & MCG_SER_P) && addr
 261         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 262         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 263             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 264             fprintf(stderr, "Hardware memory error for memory used by "
 265                     "QEMU itself instead of guest system!\n");
 266             /* Hope we are lucky for AO MCE */
 267             if (code == BUS_MCEERR_AO) {
 268                 return 0;
 269             } else {
 270                 hardware_memory_error();
 271             }
 272         }
 273         kvm_hwpoison_page_add(ram_addr);
 274         kvm_mce_inject(env, paddr, code);
 275     } else {
 276         if (code == BUS_MCEERR_AO) {
 277             return 0;
 278         } else if (code == BUS_MCEERR_AR) {
 279             hardware_memory_error();
 280         } else {
 281             return 1;
 282         }
 283     }
 284     return 0;
 285 }
 286
 287 int kvm_arch_on_sigbus(int code, void *addr)
 288 {
 289     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 290         ram_addr_t ram_addr;
 291         target_phys_addr_t paddr;
 292
 293         /* Hope we are lucky for AO MCE */
 294         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 295             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 296                                                 &paddr)) {
 297             fprintf(stderr, "Hardware memory error for memory used by "
 298                     "QEMU itself instead of guest system!: %p\n", addr);
 299             return 0;
 300         }
 301         kvm_hwpoison_page_add(ram_addr);
 302         kvm_mce_inject(first_cpu, paddr, code);
 303     } else {
 304         if (code == BUS_MCEERR_AO) {
 305             return 0;
 306         } else if (code == BUS_MCEERR_AR) {
 307             hardware_memory_error();
 308         } else {
 309             return 1;
 310         }
 311     }
 312     return 0;
 313 }
 314
 315 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 316 {
 317     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 318         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 319         struct kvm_x86_mce mce;
 320
 321         env->exception_injected = -1;
 322
 323         /*
 324          * There must be at least one bank in use if an MCE is pending.
 325          * Find it and use its values for the event injection.
 326          */
 327         for (bank = 0; bank < bank_num; bank++) {
 328             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 329                 break;
 330             }
 331         }
 332         assert(bank < bank_num);
 333
 334         mce.bank = bank;
 335         mce.status = env->mce_banks[bank * 4 + 1];
 336         mce.mcg_status = env->mcg_status;
 337         mce.addr = env->mce_banks[bank * 4 + 2];
 338         mce.misc = env->mce_banks[bank * 4 + 3];
 339
 340         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 341     }
 342     return 0;
 343 }
 344
 345 static void cpu_update_state(void *opaque, int running, RunState state)
 346 {
 347     CPUX86State *env = opaque;
 348
 349     if (running) {
 350         env->tsc_valid = false;
 351     }
 352 }
 353
 354 int kvm_arch_init_vcpu(CPUX86State *env)
 355 {
 356     struct {
 357         struct kvm_cpuid2 cpuid;
 358         struct kvm_cpuid_entry2 entries[100];
 359     } QEMU_PACKED cpuid_data;
 360     KVMState *s = env->kvm_state;
 361     uint32_t limit, i, j, cpuid_i;
 362     uint32_t unused;
 363     struct kvm_cpuid_entry2 *c;
 364     uint32_t signature[3];
 365     int r;
 366
 367     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 368
 369     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 370     j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER;
 371     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 372     env->cpuid_ext_features |= i;
 373     if (j && kvm_irqchip_in_kernel() &&
 374         kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 375         env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER;
 376     }
 377
 378     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 379                                                              0, R_EDX);
 380     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 381                                                              0, R_ECX);
 382     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 383                                                              0, R_EDX);
 384
 385     cpuid_i = 0;
 386
 387     /* Paravirtualization CPUIDs */
 388     c = &cpuid_data.entries[cpuid_i++];
 389     memset(c, 0, sizeof(*c));
 390     c->function = KVM_CPUID_SIGNATURE;
 391     if (!hyperv_enabled()) {
 392         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 393         c->eax = 0;
 394     } else {
 395         memcpy(signature, "Microsoft Hv", 12);
 396         c->eax = HYPERV_CPUID_MIN;
 397     }
 398     c->ebx = signature[0];
 399     c->ecx = signature[1];
 400     c->edx = signature[2];
 401
 402     c = &cpuid_data.entries[cpuid_i++];
 403     memset(c, 0, sizeof(*c));
 404     c->function = KVM_CPUID_FEATURES;
 405     c->eax = env->cpuid_kvm_features &
 406         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 407
 408     if (hyperv_enabled()) {
 409         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 410         c->eax = signature[0];
 411
 412         c = &cpuid_data.entries[cpuid_i++];
 413         memset(c, 0, sizeof(*c));
 414         c->function = HYPERV_CPUID_VERSION;
 415         c->eax = 0x00001bbc;
 416         c->ebx = 0x00060001;
 417
 418         c = &cpuid_data.entries[cpuid_i++];
 419         memset(c, 0, sizeof(*c));
 420         c->function = HYPERV_CPUID_FEATURES;
 421         if (hyperv_relaxed_timing_enabled()) {
 422             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 423         }
 424         if (hyperv_vapic_recommended()) {
 425             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 426             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 427         }
 428
 429         c = &cpuid_data.entries[cpuid_i++];
 430         memset(c, 0, sizeof(*c));
 431         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 432         if (hyperv_relaxed_timing_enabled()) {
 433             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 434         }
 435         if (hyperv_vapic_recommended()) {
 436             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 437         }
 438         c->ebx = hyperv_get_spinlock_retries();
 439
 440         c = &cpuid_data.entries[cpuid_i++];
 441         memset(c, 0, sizeof(*c));
 442         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 443         c->eax = 0x40;
 444         c->ebx = 0x40;
 445
 446         c = &cpuid_data.entries[cpuid_i++];
 447         memset(c, 0, sizeof(*c));
 448         c->function = KVM_CPUID_SIGNATURE_NEXT;
 449         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 450         c->eax = 0;
 451         c->ebx = signature[0];
 452         c->ecx = signature[1];
 453         c->edx = signature[2];
 454     }
 455
 456     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 457
 458     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 459
 460     for (i = 0; i <= limit; i++) {
 461         c = &cpuid_data.entries[cpuid_i++];
 462
 463         switch (i) {
 464         case 2: {
 465             /* Keep reading function 2 till all the input is received */
 466             int times;
 467
 468             c->function = i;
 469             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 470                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 471             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 472             times = c->eax & 0xff;
 473
 474             for (j = 1; j < times; ++j) {
 475                 c = &cpuid_data.entries[cpuid_i++];
 476                 c->function = i;
 477                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 478                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 479             }
 480             break;
 481         }
 482         case 4:
 483         case 0xb:
 484         case 0xd:
 485             for (j = 0; ; j++) {
 486                 if (i == 0xd && j == 64) {
 487                     break;
 488                 }
 489                 c->function = i;
 490                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 491                 c->index = j;
 492                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 493
 494                 if (i == 4 && c->eax == 0) {
 495                     break;
 496                 }
 497                 if (i == 0xb && !(c->ecx & 0xff00)) {
 498                     break;
 499                 }
 500                 if (i == 0xd && c->eax == 0) {
 501                     continue;
 502                 }
 503                 c = &cpuid_data.entries[cpuid_i++];
 504             }
 505             break;
 506         default:
 507             c->function = i;
 508             c->flags = 0;
 509             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 510             break;
 511         }
 512     }
 513     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 514
 515     for (i = 0x80000000; i <= limit; i++) {
 516         c = &cpuid_data.entries[cpuid_i++];
 517
 518         c->function = i;
 519         c->flags = 0;
 520         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 521     }
 522
 523     /* Call Centaur's CPUID instructions they are supported. */
 524     if (env->cpuid_xlevel2 > 0) {
 525         env->cpuid_ext4_features &=
 526             kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 527         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 528
 529         for (i = 0xC0000000; i <= limit; i++) {
 530             c = &cpuid_data.entries[cpuid_i++];
 531
 532             c->function = i;
 533             c->flags = 0;
 534             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 535         }
 536     }
 537
 538     cpuid_data.cpuid.nent = cpuid_i;
 539
 540     if (((env->cpuid_version >> 8)&0xF) >= 6
 541         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 542         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 543         uint64_t mcg_cap;
 544         int banks;
 545         int ret;
 546
 547         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 548         if (ret < 0) {
 549             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 550             return ret;
 551         }
 552
 553         if (banks > MCE_BANKS_DEF) {
 554             banks = MCE_BANKS_DEF;
 555         }
 556         mcg_cap &= MCE_CAP_DEF;
 557         mcg_cap |= banks;
 558         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 559         if (ret < 0) {
 560             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 561             return ret;
 562         }
 563
 564         env->mcg_cap = mcg_cap;
 565     }
 566
 567     qemu_add_vm_change_state_handler(cpu_update_state, env);
 568
 569     cpuid_data.cpuid.padding = 0;
 570     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 571     if (r) {
 572         return r;
 573     }
 574
 575     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 576     if (r && env->tsc_khz) {
 577         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 578         if (r < 0) {
 579             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 580             return r;
 581         }
 582     }
 583
 584     if (kvm_has_xsave()) {
 585         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 586     }
 587
 588     return 0;
 589 }
 590
 591 void kvm_arch_reset_vcpu(CPUX86State *env)
 592 {
 593     X86CPU *cpu = x86_env_get_cpu(env);
 594
 595     env->exception_injected = -1;
 596     env->interrupt_injected = -1;
 597     env->xcr0 = 1;
 598     if (kvm_irqchip_in_kernel()) {
 599         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 600                                           KVM_MP_STATE_UNINITIALIZED;
 601     } else {
 602         env->mp_state = KVM_MP_STATE_RUNNABLE;
 603     }
 604 }
 605
 606 static int kvm_get_supported_msrs(KVMState *s)
 607 {
 608     static int kvm_supported_msrs;
 609     int ret = 0;
 610
 611     /* first time */
 612     if (kvm_supported_msrs == 0) {
 613         struct kvm_msr_list msr_list, *kvm_msr_list;
 614
 615         kvm_supported_msrs = -1;
 616
 617         /* Obtain MSR list from KVM.  These are the MSRs that we must
 618          * save/restore */
 619         msr_list.nmsrs = 0;
 620         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 621         if (ret < 0 && ret != -E2BIG) {
 622             return ret;
 623         }
 624         /* Old kernel modules had a bug and could write beyond the provided
 625            memory. Allocate at least a safe amount of 1K. */
 626         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 627                                               msr_list.nmsrs *
 628                                               sizeof(msr_list.indices[0])));
 629
 630         kvm_msr_list->nmsrs = msr_list.nmsrs;
 631         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 632         if (ret >= 0) {
 633             int i;
 634
 635             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 636                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 637                     has_msr_star = true;
 638                     continue;
 639                 }
 640                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 641                     has_msr_hsave_pa = true;
 642                     continue;
 643                 }
 644                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 645                     has_msr_tsc_deadline = true;
 646                     continue;
 647                 }
 648                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 649                     has_msr_misc_enable = true;
 650                     continue;
 651                 }
 652             }
 653         }
 654
 655         g_free(kvm_msr_list);
 656     }
 657
 658     return ret;
 659 }
 660
 661 int kvm_arch_init(KVMState *s)
 662 {
 663     QemuOptsList *list = qemu_find_opts("machine");
 664     uint64_t identity_base = 0xfffbc000;
 665     uint64_t shadow_mem;
 666     int ret;
 667     struct utsname utsname;
 668
 669     ret = kvm_get_supported_msrs(s);
 670     if (ret < 0) {
 671         return ret;
 672     }
 673
 674     uname(&utsname);
 675     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 676
 677     /*
 678      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 679      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 680      * Since these must be part of guest physical memory, we need to allocate
 681      * them, both by setting their start addresses in the kernel and by
 682      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 683      *
 684      * Older KVM versions may not support setting the identity map base. In
 685      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 686      * size.
 687      */
 688     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 689         /* Allows up to 16M BIOSes. */
 690         identity_base = 0xfeffc000;
 691
 692         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 693         if (ret < 0) {
 694             return ret;
 695         }
 696     }
 697
 698     /* Set TSS base one page after EPT identity map. */
 699     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 700     if (ret < 0) {
 701         return ret;
 702     }
 703
 704     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 705     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 706     if (ret < 0) {
 707         fprintf(stderr, "e820_add_entry() table is full\n");
 708         return ret;
 709     }
 710     qemu_register_reset(kvm_unpoison_all, NULL);
 711
 712     if (!QTAILQ_EMPTY(&list->head)) {
 713         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 714                                        "kvm_shadow_mem", -1);
 715         if (shadow_mem != -1) {
 716             shadow_mem /= 4096;
 717             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 718             if (ret < 0) {
 719                 return ret;
 720             }
 721         }
 722     }
 723     return 0;
 724 }
 725
 726 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 727 {
 728     lhs->selector = rhs->selector;
 729     lhs->base = rhs->base;
 730     lhs->limit = rhs->limit;
 731     lhs->type = 3;
 732     lhs->present = 1;
 733     lhs->dpl = 3;
 734     lhs->db = 0;
 735     lhs->s = 1;
 736     lhs->l = 0;
 737     lhs->g = 0;
 738     lhs->avl = 0;
 739     lhs->unusable = 0;
 740 }
 741
 742 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 743 {
 744     unsigned flags = rhs->flags;
 745     lhs->selector = rhs->selector;
 746     lhs->base = rhs->base;
 747     lhs->limit = rhs->limit;
 748     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 749     lhs->present = (flags & DESC_P_MASK) != 0;
 750     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 751     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 752     lhs->s = (flags & DESC_S_MASK) != 0;
 753     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 754     lhs->g = (flags & DESC_G_MASK) != 0;
 755     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 756     lhs->unusable = 0;
 757     lhs->padding = 0;
 758 }
 759
 760 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 761 {
 762     lhs->selector = rhs->selector;
 763     lhs->base = rhs->base;
 764     lhs->limit = rhs->limit;
 765     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 766                  (rhs->present * DESC_P_MASK) |
 767                  (rhs->dpl << DESC_DPL_SHIFT) |
 768                  (rhs->db << DESC_B_SHIFT) |
 769                  (rhs->s * DESC_S_MASK) |
 770                  (rhs->l << DESC_L_SHIFT) |
 771                  (rhs->g * DESC_G_MASK) |
 772                  (rhs->avl * DESC_AVL_MASK);
 773 }
 774
 775 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 776 {
 777     if (set) {
 778         *kvm_reg = *qemu_reg;
 779     } else {
 780         *qemu_reg = *kvm_reg;
 781     }
 782 }
 783
 784 static int kvm_getput_regs(CPUX86State *env, int set)
 785 {
 786     struct kvm_regs regs;
 787     int ret = 0;
 788
 789     if (!set) {
 790         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 791         if (ret < 0) {
 792             return ret;
 793         }
 794     }
 795
 796     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 797     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 798     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 799     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 800     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 801     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 802     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 803     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 804 #ifdef TARGET_X86_64
 805     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 806     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 807     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 808     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 809     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 810     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 811     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 812     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 813 #endif
 814
 815     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 816     kvm_getput_reg(&regs.rip, &env->eip, set);
 817
 818     if (set) {
 819         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 820     }
 821
 822     return ret;
 823 }
 824
 825 static int kvm_put_fpu(CPUX86State *env)
 826 {
 827     struct kvm_fpu fpu;
 828     int i;
 829
 830     memset(&fpu, 0, sizeof fpu);
 831     fpu.fsw = env->fpus & ~(7 << 11);
 832     fpu.fsw |= (env->fpstt & 7) << 11;
 833     fpu.fcw = env->fpuc;
 834     fpu.last_opcode = env->fpop;
 835     fpu.last_ip = env->fpip;
 836     fpu.last_dp = env->fpdp;
 837     for (i = 0; i < 8; ++i) {
 838         fpu.ftwx |= (!env->fptags[i]) << i;
 839     }
 840     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 841     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 842     fpu.mxcsr = env->mxcsr;
 843
 844     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 845 }
 846
 847 #define XSAVE_FCW_FSW     0
 848 #define XSAVE_FTW_FOP     1
 849 #define XSAVE_CWD_RIP     2
 850 #define XSAVE_CWD_RDP     4
 851 #define XSAVE_MXCSR       6
 852 #define XSAVE_ST_SPACE    8
 853 #define XSAVE_XMM_SPACE   40
 854 #define XSAVE_XSTATE_BV   128
 855 #define XSAVE_YMMH_SPACE  144
 856
 857 static int kvm_put_xsave(CPUX86State *env)
 858 {
 859     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 860     uint16_t cwd, swd, twd;
 861     int i, r;
 862
 863     if (!kvm_has_xsave()) {
 864         return kvm_put_fpu(env);
 865     }
 866
 867     memset(xsave, 0, sizeof(struct kvm_xsave));
 868     twd = 0;
 869     swd = env->fpus & ~(7 << 11);
 870     swd |= (env->fpstt & 7) << 11;
 871     cwd = env->fpuc;
 872     for (i = 0; i < 8; ++i) {
 873         twd |= (!env->fptags[i]) << i;
 874     }
 875     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 876     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 877     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 878     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 879     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 880             sizeof env->fpregs);
 881     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 882             sizeof env->xmm_regs);
 883     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 884     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 885     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 886             sizeof env->ymmh_regs);
 887     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 888     return r;
 889 }
 890
 891 static int kvm_put_xcrs(CPUX86State *env)
 892 {
 893     struct kvm_xcrs xcrs;
 894
 895     if (!kvm_has_xcrs()) {
 896         return 0;
 897     }
 898
 899     xcrs.nr_xcrs = 1;
 900     xcrs.flags = 0;
 901     xcrs.xcrs[0].xcr = 0;
 902     xcrs.xcrs[0].value = env->xcr0;
 903     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 904 }
 905
 906 static int kvm_put_sregs(CPUX86State *env)
 907 {
 908     struct kvm_sregs sregs;
 909
 910     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 911     if (env->interrupt_injected >= 0) {
 912         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 913                 (uint64_t)1 << (env->interrupt_injected % 64);
 914     }
 915
 916     if ((env->eflags & VM_MASK)) {
 917         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 918         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 919         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 920         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 921         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 922         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 923     } else {
 924         set_seg(&sregs.cs, &env->segs[R_CS]);
 925         set_seg(&sregs.ds, &env->segs[R_DS]);
 926         set_seg(&sregs.es, &env->segs[R_ES]);
 927         set_seg(&sregs.fs, &env->segs[R_FS]);
 928         set_seg(&sregs.gs, &env->segs[R_GS]);
 929         set_seg(&sregs.ss, &env->segs[R_SS]);
 930     }
 931
 932     set_seg(&sregs.tr, &env->tr);
 933     set_seg(&sregs.ldt, &env->ldt);
 934
 935     sregs.idt.limit = env->idt.limit;
 936     sregs.idt.base = env->idt.base;
 937     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 938     sregs.gdt.limit = env->gdt.limit;
 939     sregs.gdt.base = env->gdt.base;
 940     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 941
 942     sregs.cr0 = env->cr[0];
 943     sregs.cr2 = env->cr[2];
 944     sregs.cr3 = env->cr[3];
 945     sregs.cr4 = env->cr[4];
 946
 947     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 948     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 949
 950     sregs.efer = env->efer;
 951
 952     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 953 }
 954
 955 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 956                               uint32_t index, uint64_t value)
 957 {
 958     entry->index = index;
 959     entry->data = value;
 960 }
 961
 962 static int kvm_put_msrs(CPUX86State *env, int level)
 963 {
 964     struct {
 965         struct kvm_msrs info;
 966         struct kvm_msr_entry entries[100];
 967     } msr_data;
 968     struct kvm_msr_entry *msrs = msr_data.entries;
 969     int n = 0;
 970
 971     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 972     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 973     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 974     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
 975     if (has_msr_star) {
 976         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 977     }
 978     if (has_msr_hsave_pa) {
 979         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 980     }
 981     if (has_msr_tsc_deadline) {
 982         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
 983     }
 984     if (has_msr_misc_enable) {
 985         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
 986                           env->msr_ia32_misc_enable);
 987     }
 988 #ifdef TARGET_X86_64
 989     if (lm_capable_kernel) {
 990         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 991         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 992         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 993         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 994     }
 995 #endif
 996     if (level == KVM_PUT_FULL_STATE) {
 997         /*
 998          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 999          * writeback. Until this is fixed, we only write the offset to SMP
1000          * guests after migration, desynchronizing the VCPUs, but avoiding
1001          * huge jump-backs that would occur without any writeback at all.
1002          */
1003         if (smp_cpus == 1 || env->tsc != 0) {
1004             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1005         }
1006     }
1007     /*
1008      * The following paravirtual MSRs have side effects on the guest or are
1009      * too heavy for normal writeback. Limit them to reset or full state
1010      * updates.
1011      */
1012     if (level >= KVM_PUT_RESET_STATE) {
1013         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1014                           env->system_time_msr);
1015         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1016         if (has_msr_async_pf_en) {
1017             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1018                               env->async_pf_en_msr);
1019         }
1020         if (hyperv_hypercall_available()) {
1021             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1022             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1023         }
1024         if (hyperv_vapic_recommended()) {
1025             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1026         }
1027     }
1028     if (env->mcg_cap) {
1029         int i;
1030
1031         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1032         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1033         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1034             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1035         }
1036     }
1037
1038     msr_data.info.nmsrs = n;
1039
1040     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1041
1042 }
1043
1044
1045 static int kvm_get_fpu(CPUX86State *env)
1046 {
1047     struct kvm_fpu fpu;
1048     int i, ret;
1049
1050     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1051     if (ret < 0) {
1052         return ret;
1053     }
1054
1055     env->fpstt = (fpu.fsw >> 11) & 7;
1056     env->fpus = fpu.fsw;
1057     env->fpuc = fpu.fcw;
1058     env->fpop = fpu.last_opcode;
1059     env->fpip = fpu.last_ip;
1060     env->fpdp = fpu.last_dp;
1061     for (i = 0; i < 8; ++i) {
1062         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1063     }
1064     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1065     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1066     env->mxcsr = fpu.mxcsr;
1067
1068     return 0;
1069 }
1070
1071 static int kvm_get_xsave(CPUX86State *env)
1072 {
1073     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1074     int ret, i;
1075     uint16_t cwd, swd, twd;
1076
1077     if (!kvm_has_xsave()) {
1078         return kvm_get_fpu(env);
1079     }
1080
1081     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1082     if (ret < 0) {
1083         return ret;
1084     }
1085
1086     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1087     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1088     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1089     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1090     env->fpstt = (swd >> 11) & 7;
1091     env->fpus = swd;
1092     env->fpuc = cwd;
1093     for (i = 0; i < 8; ++i) {
1094         env->fptags[i] = !((twd >> i) & 1);
1095     }
1096     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1097     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1098     env->mxcsr = xsave->region[XSAVE_MXCSR];
1099     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1100             sizeof env->fpregs);
1101     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1102             sizeof env->xmm_regs);
1103     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1104     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1105             sizeof env->ymmh_regs);
1106     return 0;
1107 }
1108
1109 static int kvm_get_xcrs(CPUX86State *env)
1110 {
1111     int i, ret;
1112     struct kvm_xcrs xcrs;
1113
1114     if (!kvm_has_xcrs()) {
1115         return 0;
1116     }
1117
1118     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1119     if (ret < 0) {
1120         return ret;
1121     }
1122
1123     for (i = 0; i < xcrs.nr_xcrs; i++) {
1124         /* Only support xcr0 now */
1125         if (xcrs.xcrs[0].xcr == 0) {
1126             env->xcr0 = xcrs.xcrs[0].value;
1127             break;
1128         }
1129     }
1130     return 0;
1131 }
1132
1133 static int kvm_get_sregs(CPUX86State *env)
1134 {
1135     struct kvm_sregs sregs;
1136     uint32_t hflags;
1137     int bit, i, ret;
1138
1139     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1140     if (ret < 0) {
1141         return ret;
1142     }
1143
1144     /* There can only be one pending IRQ set in the bitmap at a time, so try
1145        to find it and save its number instead (-1 for none). */
1146     env->interrupt_injected = -1;
1147     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1148         if (sregs.interrupt_bitmap[i]) {
1149             bit = ctz64(sregs.interrupt_bitmap[i]);
1150             env->interrupt_injected = i * 64 + bit;
1151             break;
1152         }
1153     }
1154
1155     get_seg(&env->segs[R_CS], &sregs.cs);
1156     get_seg(&env->segs[R_DS], &sregs.ds);
1157     get_seg(&env->segs[R_ES], &sregs.es);
1158     get_seg(&env->segs[R_FS], &sregs.fs);
1159     get_seg(&env->segs[R_GS], &sregs.gs);
1160     get_seg(&env->segs[R_SS], &sregs.ss);
1161
1162     get_seg(&env->tr, &sregs.tr);
1163     get_seg(&env->ldt, &sregs.ldt);
1164
1165     env->idt.limit = sregs.idt.limit;
1166     env->idt.base = sregs.idt.base;
1167     env->gdt.limit = sregs.gdt.limit;
1168     env->gdt.base = sregs.gdt.base;
1169
1170     env->cr[0] = sregs.cr0;
1171     env->cr[2] = sregs.cr2;
1172     env->cr[3] = sregs.cr3;
1173     env->cr[4] = sregs.cr4;
1174
1175     env->efer = sregs.efer;
1176
1177     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1178
1179 #define HFLAG_COPY_MASK \
1180     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1181        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1182        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1183        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1184
1185     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1186     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1187     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1188                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1189     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1190     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1191                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1192
1193     if (env->efer & MSR_EFER_LMA) {
1194         hflags |= HF_LMA_MASK;
1195     }
1196
1197     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1198         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1199     } else {
1200         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1201                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1202         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1203                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1204         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1205             !(hflags & HF_CS32_MASK)) {
1206             hflags |= HF_ADDSEG_MASK;
1207         } else {
1208             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1209                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1210         }
1211     }
1212     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1213
1214     return 0;
1215 }
1216
1217 static int kvm_get_msrs(CPUX86State *env)
1218 {
1219     struct {
1220         struct kvm_msrs info;
1221         struct kvm_msr_entry entries[100];
1222     } msr_data;
1223     struct kvm_msr_entry *msrs = msr_data.entries;
1224     int ret, i, n;
1225
1226     n = 0;
1227     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1228     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1229     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1230     msrs[n++].index = MSR_PAT;
1231     if (has_msr_star) {
1232         msrs[n++].index = MSR_STAR;
1233     }
1234     if (has_msr_hsave_pa) {
1235         msrs[n++].index = MSR_VM_HSAVE_PA;
1236     }
1237     if (has_msr_tsc_deadline) {
1238         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1239     }
1240     if (has_msr_misc_enable) {
1241         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1242     }
1243
1244     if (!env->tsc_valid) {
1245         msrs[n++].index = MSR_IA32_TSC;
1246         env->tsc_valid = !runstate_is_running();
1247     }
1248
1249 #ifdef TARGET_X86_64
1250     if (lm_capable_kernel) {
1251         msrs[n++].index = MSR_CSTAR;
1252         msrs[n++].index = MSR_KERNELGSBASE;
1253         msrs[n++].index = MSR_FMASK;
1254         msrs[n++].index = MSR_LSTAR;
1255     }
1256 #endif
1257     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1258     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1259     if (has_msr_async_pf_en) {
1260         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1261     }
1262
1263     if (env->mcg_cap) {
1264         msrs[n++].index = MSR_MCG_STATUS;
1265         msrs[n++].index = MSR_MCG_CTL;
1266         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1267             msrs[n++].index = MSR_MC0_CTL + i;
1268         }
1269     }
1270
1271     msr_data.info.nmsrs = n;
1272     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1273     if (ret < 0) {
1274         return ret;
1275     }
1276
1277     for (i = 0; i < ret; i++) {
1278         switch (msrs[i].index) {
1279         case MSR_IA32_SYSENTER_CS:
1280             env->sysenter_cs = msrs[i].data;
1281             break;
1282         case MSR_IA32_SYSENTER_ESP:
1283             env->sysenter_esp = msrs[i].data;
1284             break;
1285         case MSR_IA32_SYSENTER_EIP:
1286             env->sysenter_eip = msrs[i].data;
1287             break;
1288         case MSR_PAT:
1289             env->pat = msrs[i].data;
1290             break;
1291         case MSR_STAR:
1292             env->star = msrs[i].data;
1293             break;
1294 #ifdef TARGET_X86_64
1295         case MSR_CSTAR:
1296             env->cstar = msrs[i].data;
1297             break;
1298         case MSR_KERNELGSBASE:
1299             env->kernelgsbase = msrs[i].data;
1300             break;
1301         case MSR_FMASK:
1302             env->fmask = msrs[i].data;
1303             break;
1304         case MSR_LSTAR:
1305             env->lstar = msrs[i].data;
1306             break;
1307 #endif
1308         case MSR_IA32_TSC:
1309             env->tsc = msrs[i].data;
1310             break;
1311         case MSR_IA32_TSCDEADLINE:
1312             env->tsc_deadline = msrs[i].data;
1313             break;
1314         case MSR_VM_HSAVE_PA:
1315             env->vm_hsave = msrs[i].data;
1316             break;
1317         case MSR_KVM_SYSTEM_TIME:
1318             env->system_time_msr = msrs[i].data;
1319             break;
1320         case MSR_KVM_WALL_CLOCK:
1321             env->wall_clock_msr = msrs[i].data;
1322             break;
1323         case MSR_MCG_STATUS:
1324             env->mcg_status = msrs[i].data;
1325             break;
1326         case MSR_MCG_CTL:
1327             env->mcg_ctl = msrs[i].data;
1328             break;
1329         case MSR_IA32_MISC_ENABLE:
1330             env->msr_ia32_misc_enable = msrs[i].data;
1331             break;
1332         default:
1333             if (msrs[i].index >= MSR_MC0_CTL &&
1334                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1335                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1336             }
1337             break;
1338         case MSR_KVM_ASYNC_PF_EN:
1339             env->async_pf_en_msr = msrs[i].data;
1340             break;
1341         }
1342     }
1343
1344     return 0;
1345 }
1346
1347 static int kvm_put_mp_state(CPUX86State *env)
1348 {
1349     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1350
1351     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1352 }
1353
1354 static int kvm_get_mp_state(CPUX86State *env)
1355 {
1356     struct kvm_mp_state mp_state;
1357     int ret;
1358
1359     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1360     if (ret < 0) {
1361         return ret;
1362     }
1363     env->mp_state = mp_state.mp_state;
1364     if (kvm_irqchip_in_kernel()) {
1365         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1366     }
1367     return 0;
1368 }
1369
1370 static int kvm_get_apic(CPUX86State *env)
1371 {
1372     DeviceState *apic = env->apic_state;
1373     struct kvm_lapic_state kapic;
1374     int ret;
1375
1376     if (apic && kvm_irqchip_in_kernel()) {
1377         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1378         if (ret < 0) {
1379             return ret;
1380         }
1381
1382         kvm_get_apic_state(apic, &kapic);
1383     }
1384     return 0;
1385 }
1386
1387 static int kvm_put_apic(CPUX86State *env)
1388 {
1389     DeviceState *apic = env->apic_state;
1390     struct kvm_lapic_state kapic;
1391
1392     if (apic && kvm_irqchip_in_kernel()) {
1393         kvm_put_apic_state(apic, &kapic);
1394
1395         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1396     }
1397     return 0;
1398 }
1399
1400 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1401 {
1402     struct kvm_vcpu_events events;
1403
1404     if (!kvm_has_vcpu_events()) {
1405         return 0;
1406     }
1407
1408     events.exception.injected = (env->exception_injected >= 0);
1409     events.exception.nr = env->exception_injected;
1410     events.exception.has_error_code = env->has_error_code;
1411     events.exception.error_code = env->error_code;
1412     events.exception.pad = 0;
1413
1414     events.interrupt.injected = (env->interrupt_injected >= 0);
1415     events.interrupt.nr = env->interrupt_injected;
1416     events.interrupt.soft = env->soft_interrupt;
1417
1418     events.nmi.injected = env->nmi_injected;
1419     events.nmi.pending = env->nmi_pending;
1420     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1421     events.nmi.pad = 0;
1422
1423     events.sipi_vector = env->sipi_vector;
1424
1425     events.flags = 0;
1426     if (level >= KVM_PUT_RESET_STATE) {
1427         events.flags |=
1428             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1429     }
1430
1431     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1432 }
1433
1434 static int kvm_get_vcpu_events(CPUX86State *env)
1435 {
1436     struct kvm_vcpu_events events;
1437     int ret;
1438
1439     if (!kvm_has_vcpu_events()) {
1440         return 0;
1441     }
1442
1443     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1444     if (ret < 0) {
1445        return ret;
1446     }
1447     env->exception_injected =
1448        events.exception.injected ? events.exception.nr : -1;
1449     env->has_error_code = events.exception.has_error_code;
1450     env->error_code = events.exception.error_code;
1451
1452     env->interrupt_injected =
1453         events.interrupt.injected ? events.interrupt.nr : -1;
1454     env->soft_interrupt = events.interrupt.soft;
1455
1456     env->nmi_injected = events.nmi.injected;
1457     env->nmi_pending = events.nmi.pending;
1458     if (events.nmi.masked) {
1459         env->hflags2 |= HF2_NMI_MASK;
1460     } else {
1461         env->hflags2 &= ~HF2_NMI_MASK;
1462     }
1463
1464     env->sipi_vector = events.sipi_vector;
1465
1466     return 0;
1467 }
1468
1469 static int kvm_guest_debug_workarounds(CPUX86State *env)
1470 {
1471     int ret = 0;
1472     unsigned long reinject_trap = 0;
1473
1474     if (!kvm_has_vcpu_events()) {
1475         if (env->exception_injected == 1) {
1476             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1477         } else if (env->exception_injected == 3) {
1478             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1479         }
1480         env->exception_injected = -1;
1481     }
1482
1483     /*
1484      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1485      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1486      * by updating the debug state once again if single-stepping is on.
1487      * Another reason to call kvm_update_guest_debug here is a pending debug
1488      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1489      * reinject them via SET_GUEST_DEBUG.
1490      */
1491     if (reinject_trap ||
1492         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1493         ret = kvm_update_guest_debug(env, reinject_trap);
1494     }
1495     return ret;
1496 }
1497
1498 static int kvm_put_debugregs(CPUX86State *env)
1499 {
1500     struct kvm_debugregs dbgregs;
1501     int i;
1502
1503     if (!kvm_has_debugregs()) {
1504         return 0;
1505     }
1506
1507     for (i = 0; i < 4; i++) {
1508         dbgregs.db[i] = env->dr[i];
1509     }
1510     dbgregs.dr6 = env->dr[6];
1511     dbgregs.dr7 = env->dr[7];
1512     dbgregs.flags = 0;
1513
1514     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1515 }
1516
1517 static int kvm_get_debugregs(CPUX86State *env)
1518 {
1519     struct kvm_debugregs dbgregs;
1520     int i, ret;
1521
1522     if (!kvm_has_debugregs()) {
1523         return 0;
1524     }
1525
1526     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1527     if (ret < 0) {
1528         return ret;
1529     }
1530     for (i = 0; i < 4; i++) {
1531         env->dr[i] = dbgregs.db[i];
1532     }
1533     env->dr[4] = env->dr[6] = dbgregs.dr6;
1534     env->dr[5] = env->dr[7] = dbgregs.dr7;
1535
1536     return 0;
1537 }
1538
1539 int kvm_arch_put_registers(CPUX86State *env, int level)
1540 {
1541     int ret;
1542
1543     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1544
1545     ret = kvm_getput_regs(env, 1);
1546     if (ret < 0) {
1547         return ret;
1548     }
1549     ret = kvm_put_xsave(env);
1550     if (ret < 0) {
1551         return ret;
1552     }
1553     ret = kvm_put_xcrs(env);
1554     if (ret < 0) {
1555         return ret;
1556     }
1557     ret = kvm_put_sregs(env);
1558     if (ret < 0) {
1559         return ret;
1560     }
1561     /* must be before kvm_put_msrs */
1562     ret = kvm_inject_mce_oldstyle(env);
1563     if (ret < 0) {
1564         return ret;
1565     }
1566     ret = kvm_put_msrs(env, level);
1567     if (ret < 0) {
1568         return ret;
1569     }
1570     if (level >= KVM_PUT_RESET_STATE) {
1571         ret = kvm_put_mp_state(env);
1572         if (ret < 0) {
1573             return ret;
1574         }
1575         ret = kvm_put_apic(env);
1576         if (ret < 0) {
1577             return ret;
1578         }
1579     }
1580     ret = kvm_put_vcpu_events(env, level);
1581     if (ret < 0) {
1582         return ret;
1583     }
1584     ret = kvm_put_debugregs(env);
1585     if (ret < 0) {
1586         return ret;
1587     }
1588     /* must be last */
1589     ret = kvm_guest_debug_workarounds(env);
1590     if (ret < 0) {
1591         return ret;
1592     }
1593     return 0;
1594 }
1595
1596 int kvm_arch_get_registers(CPUX86State *env)
1597 {
1598     int ret;
1599
1600     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1601
1602     ret = kvm_getput_regs(env, 0);
1603     if (ret < 0) {
1604         return ret;
1605     }
1606     ret = kvm_get_xsave(env);
1607     if (ret < 0) {
1608         return ret;
1609     }
1610     ret = kvm_get_xcrs(env);
1611     if (ret < 0) {
1612         return ret;
1613     }
1614     ret = kvm_get_sregs(env);
1615     if (ret < 0) {
1616         return ret;
1617     }
1618     ret = kvm_get_msrs(env);
1619     if (ret < 0) {
1620         return ret;
1621     }
1622     ret = kvm_get_mp_state(env);
1623     if (ret < 0) {
1624         return ret;
1625     }
1626     ret = kvm_get_apic(env);
1627     if (ret < 0) {
1628         return ret;
1629     }
1630     ret = kvm_get_vcpu_events(env);
1631     if (ret < 0) {
1632         return ret;
1633     }
1634     ret = kvm_get_debugregs(env);
1635     if (ret < 0) {
1636         return ret;
1637     }
1638     return 0;
1639 }
1640
1641 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1642 {
1643     int ret;
1644
1645     /* Inject NMI */
1646     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1647         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1648         DPRINTF("injected NMI\n");
1649         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1650         if (ret < 0) {
1651             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1652                     strerror(-ret));
1653         }
1654     }
1655
1656     if (!kvm_irqchip_in_kernel()) {
1657         /* Force the VCPU out of its inner loop to process any INIT requests
1658          * or pending TPR access reports. */
1659         if (env->interrupt_request &
1660             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1661             env->exit_request = 1;
1662         }
1663
1664         /* Try to inject an interrupt if the guest can accept it */
1665         if (run->ready_for_interrupt_injection &&
1666             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1667             (env->eflags & IF_MASK)) {
1668             int irq;
1669
1670             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1671             irq = cpu_get_pic_interrupt(env);
1672             if (irq >= 0) {
1673                 struct kvm_interrupt intr;
1674
1675                 intr.irq = irq;
1676                 DPRINTF("injected interrupt %d\n", irq);
1677                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1678                 if (ret < 0) {
1679                     fprintf(stderr,
1680                             "KVM: injection failed, interrupt lost (%s)\n",
1681                             strerror(-ret));
1682                 }
1683             }
1684         }
1685
1686         /* If we have an interrupt but the guest is not ready to receive an
1687          * interrupt, request an interrupt window exit.  This will
1688          * cause a return to userspace as soon as the guest is ready to
1689          * receive interrupts. */
1690         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1691             run->request_interrupt_window = 1;
1692         } else {
1693             run->request_interrupt_window = 0;
1694         }
1695
1696         DPRINTF("setting tpr\n");
1697         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1698     }
1699 }
1700
1701 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1702 {
1703     if (run->if_flag) {
1704         env->eflags |= IF_MASK;
1705     } else {
1706         env->eflags &= ~IF_MASK;
1707     }
1708     cpu_set_apic_tpr(env->apic_state, run->cr8);
1709     cpu_set_apic_base(env->apic_state, run->apic_base);
1710 }
1711
1712 int kvm_arch_process_async_events(CPUX86State *env)
1713 {
1714     X86CPU *cpu = x86_env_get_cpu(env);
1715
1716     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1717         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1718         assert(env->mcg_cap);
1719
1720         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1721
1722         kvm_cpu_synchronize_state(env);
1723
1724         if (env->exception_injected == EXCP08_DBLE) {
1725             /* this means triple fault */
1726             qemu_system_reset_request();
1727             env->exit_request = 1;
1728             return 0;
1729         }
1730         env->exception_injected = EXCP12_MCHK;
1731         env->has_error_code = 0;
1732
1733         env->halted = 0;
1734         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1735             env->mp_state = KVM_MP_STATE_RUNNABLE;
1736         }
1737     }
1738
1739     if (kvm_irqchip_in_kernel()) {
1740         return 0;
1741     }
1742
1743     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1744         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1745         apic_poll_irq(env->apic_state);
1746     }
1747     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1748          (env->eflags & IF_MASK)) ||
1749         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1750         env->halted = 0;
1751     }
1752     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1753         kvm_cpu_synchronize_state(env);
1754         do_cpu_init(cpu);
1755     }
1756     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1757         kvm_cpu_synchronize_state(env);
1758         do_cpu_sipi(cpu);
1759     }
1760     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1761         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1762         kvm_cpu_synchronize_state(env);
1763         apic_handle_tpr_access_report(env->apic_state, env->eip,
1764                                       env->tpr_access_type);
1765     }
1766
1767     return env->halted;
1768 }
1769
1770 static int kvm_handle_halt(CPUX86State *env)
1771 {
1772     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1773           (env->eflags & IF_MASK)) &&
1774         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1775         env->halted = 1;
1776         return EXCP_HLT;
1777     }
1778
1779     return 0;
1780 }
1781
1782 static int kvm_handle_tpr_access(CPUX86State *env)
1783 {
1784     struct kvm_run *run = env->kvm_run;
1785
1786     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1787                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1788                                                            : TPR_ACCESS_READ);
1789     return 1;
1790 }
1791
1792 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1793 {
1794     static const uint8_t int3 = 0xcc;
1795
1796     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1797         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1798         return -EINVAL;
1799     }
1800     return 0;
1801 }
1802
1803 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1804 {
1805     uint8_t int3;
1806
1807     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1808         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1809         return -EINVAL;
1810     }
1811     return 0;
1812 }
1813
1814 static struct {
1815     target_ulong addr;
1816     int len;
1817     int type;
1818 } hw_breakpoint[4];
1819
1820 static int nb_hw_breakpoint;
1821
1822 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1823 {
1824     int n;
1825
1826     for (n = 0; n < nb_hw_breakpoint; n++) {
1827         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1828             (hw_breakpoint[n].len == len || len == -1)) {
1829             return n;
1830         }
1831     }
1832     return -1;
1833 }
1834
1835 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1836                                   target_ulong len, int type)
1837 {
1838     switch (type) {
1839     case GDB_BREAKPOINT_HW:
1840         len = 1;
1841         break;
1842     case GDB_WATCHPOINT_WRITE:
1843     case GDB_WATCHPOINT_ACCESS:
1844         switch (len) {
1845         case 1:
1846             break;
1847         case 2:
1848         case 4:
1849         case 8:
1850             if (addr & (len - 1)) {
1851                 return -EINVAL;
1852             }
1853             break;
1854         default:
1855             return -EINVAL;
1856         }
1857         break;
1858     default:
1859         return -ENOSYS;
1860     }
1861
1862     if (nb_hw_breakpoint == 4) {
1863         return -ENOBUFS;
1864     }
1865     if (find_hw_breakpoint(addr, len, type) >= 0) {
1866         return -EEXIST;
1867     }
1868     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1869     hw_breakpoint[nb_hw_breakpoint].len = len;
1870     hw_breakpoint[nb_hw_breakpoint].type = type;
1871     nb_hw_breakpoint++;
1872
1873     return 0;
1874 }
1875
1876 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1877                                   target_ulong len, int type)
1878 {
1879     int n;
1880
1881     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1882     if (n < 0) {
1883         return -ENOENT;
1884     }
1885     nb_hw_breakpoint--;
1886     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1887
1888     return 0;
1889 }
1890
1891 void kvm_arch_remove_all_hw_breakpoints(void)
1892 {
1893     nb_hw_breakpoint = 0;
1894 }
1895
1896 static CPUWatchpoint hw_watchpoint;
1897
1898 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1899 {
1900     int ret = 0;
1901     int n;
1902
1903     if (arch_info->exception == 1) {
1904         if (arch_info->dr6 & (1 << 14)) {
1905             if (cpu_single_env->singlestep_enabled) {
1906                 ret = EXCP_DEBUG;
1907             }
1908         } else {
1909             for (n = 0; n < 4; n++) {
1910                 if (arch_info->dr6 & (1 << n)) {
1911                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1912                     case 0x0:
1913                         ret = EXCP_DEBUG;
1914                         break;
1915                     case 0x1:
1916                         ret = EXCP_DEBUG;
1917                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1918                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1919                         hw_watchpoint.flags = BP_MEM_WRITE;
1920                         break;
1921                     case 0x3:
1922                         ret = EXCP_DEBUG;
1923                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1924                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1925                         hw_watchpoint.flags = BP_MEM_ACCESS;
1926                         break;
1927                     }
1928                 }
1929             }
1930         }
1931     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1932         ret = EXCP_DEBUG;
1933     }
1934     if (ret == 0) {
1935         cpu_synchronize_state(cpu_single_env);
1936         assert(cpu_single_env->exception_injected == -1);
1937
1938         /* pass to guest */
1939         cpu_single_env->exception_injected = arch_info->exception;
1940         cpu_single_env->has_error_code = 0;
1941     }
1942
1943     return ret;
1944 }
1945
1946 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
1947 {
1948     const uint8_t type_code[] = {
1949         [GDB_BREAKPOINT_HW] = 0x0,
1950         [GDB_WATCHPOINT_WRITE] = 0x1,
1951         [GDB_WATCHPOINT_ACCESS] = 0x3
1952     };
1953     const uint8_t len_code[] = {
1954         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1955     };
1956     int n;
1957
1958     if (kvm_sw_breakpoints_active(env)) {
1959         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1960     }
1961     if (nb_hw_breakpoint > 0) {
1962         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1963         dbg->arch.debugreg[7] = 0x0600;
1964         for (n = 0; n < nb_hw_breakpoint; n++) {
1965             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1966             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1967                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1968                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1969         }
1970     }
1971 }
1972
1973 static bool host_supports_vmx(void)
1974 {
1975     uint32_t ecx, unused;
1976
1977     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1978     return ecx & CPUID_EXT_VMX;
1979 }
1980
1981 #define VMX_INVALID_GUEST_STATE 0x80000021
1982
1983 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
1984 {
1985     uint64_t code;
1986     int ret;
1987
1988     switch (run->exit_reason) {
1989     case KVM_EXIT_HLT:
1990         DPRINTF("handle_hlt\n");
1991         ret = kvm_handle_halt(env);
1992         break;
1993     case KVM_EXIT_SET_TPR:
1994         ret = 0;
1995         break;
1996     case KVM_EXIT_TPR_ACCESS:
1997         ret = kvm_handle_tpr_access(env);
1998         break;
1999     case KVM_EXIT_FAIL_ENTRY:
2000         code = run->fail_entry.hardware_entry_failure_reason;
2001         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2002                 code);
2003         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2004             fprintf(stderr,
2005                     "\nIf you're running a guest on an Intel machine without "
2006                         "unrestricted mode\n"
2007                     "support, the failure can be most likely due to the guest "
2008                         "entering an invalid\n"
2009                     "state for Intel VT. For example, the guest maybe running "
2010                         "in big real mode\n"
2011                     "which is not supported on less recent Intel processors."
2012                         "\n\n");
2013         }
2014         ret = -1;
2015         break;
2016     case KVM_EXIT_EXCEPTION:
2017         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2018                 run->ex.exception, run->ex.error_code);
2019         ret = -1;
2020         break;
2021     case KVM_EXIT_DEBUG:
2022         DPRINTF("kvm_exit_debug\n");
2023         ret = kvm_handle_debug(&run->debug.arch);
2024         break;
2025     default:
2026         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2027         ret = -1;
2028         break;
2029     }
2030
2031     return ret;
2032 }
2033
2034 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2035 {
2036     kvm_cpu_synchronize_state(env);
2037     return !(env->cr[0] & CR0_PE_MASK) ||
2038            ((env->segs[R_CS].selector  & 3) != 3);
2039 }
2040
2041 void kvm_arch_init_irq_routing(KVMState *s)
2042 {
2043     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2044         /* If kernel can't do irq routing, interrupt source
2045          * override 0->2 cannot be set up as required by HPET.
2046          * So we have to disable it.
2047          */
2048         no_hpet = 1;
2049     }
2050     /* We know at this point that we're using the in-kernel
2051      * irqchip, so we can use irqfds, and on x86 we know
2052      * we can use msi via irqfd and GSI routing.
2053      */
2054     kvm_irqfds_allowed = true;
2055     kvm_msi_via_irqfd_allowed = true;
2056     kvm_gsi_routing_allowed = true;
2057 }