target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu/sysemu.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "exec/gdbstub.h"
  29 #include "qemu/host-utils.h"
  30 #include "qemu/config-file.h"
  31 #include "hw/i386/pc.h"
  32 #include "hw/i386/apic.h"
  33 #include "exec/ioport.h"
  34 #include "hyperv.h"
  35 #include "hw/pci/pci.h"
  36
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static bool has_msr_tsc_adjust;
  67 static bool has_msr_tsc_deadline;
  68 static bool has_msr_async_pf_en;
  69 static bool has_msr_pv_eoi_en;
  70 static bool has_msr_misc_enable;
  71 static bool has_msr_kvm_steal_time;
  72 static int lm_capable_kernel;
  73
  74 bool kvm_allows_irq0_override(void)
  75 {
  76     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  77 }
  78
  79 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  80 {
  81     struct kvm_cpuid2 *cpuid;
  82     int r, size;
  83
  84     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  85     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  86     cpuid->nent = max;
  87     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  88     if (r == 0 && cpuid->nent >= max) {
  89         r = -E2BIG;
  90     }
  91     if (r < 0) {
  92         if (r == -E2BIG) {
  93             g_free(cpuid);
  94             return NULL;
  95         } else {
  96             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  97                     strerror(-r));
  98             exit(1);
  99         }
 100     }
 101     return cpuid;
 102 }
 103
 104 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 105  * for all entries.
 106  */
 107 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 108 {
 109     struct kvm_cpuid2 *cpuid;
 110     int max = 1;
 111     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 112         max *= 2;
 113     }
 114     return cpuid;
 115 }
 116
 117 struct kvm_para_features {
 118     int cap;
 119     int feature;
 120 } para_features[] = {
 121     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 122     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 123     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 124     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 125     { -1, -1 }
 126 };
 127
 128 static int get_para_features(KVMState *s)
 129 {
 130     int i, features = 0;
 131
 132     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 133         if (kvm_check_extension(s, para_features[i].cap)) {
 134             features |= (1 << para_features[i].feature);
 135         }
 136     }
 137
 138     return features;
 139 }
 140
 141
 142 /* Returns the value for a specific register on the cpuid entry
 143  */
 144 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 145 {
 146     uint32_t ret = 0;
 147     switch (reg) {
 148     case R_EAX:
 149         ret = entry->eax;
 150         break;
 151     case R_EBX:
 152         ret = entry->ebx;
 153         break;
 154     case R_ECX:
 155         ret = entry->ecx;
 156         break;
 157     case R_EDX:
 158         ret = entry->edx;
 159         break;
 160     }
 161     return ret;
 162 }
 163
 164 /* Find matching entry for function/index on kvm_cpuid2 struct
 165  */
 166 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 167                                                  uint32_t function,
 168                                                  uint32_t index)
 169 {
 170     int i;
 171     for (i = 0; i < cpuid->nent; ++i) {
 172         if (cpuid->entries[i].function == function &&
 173             cpuid->entries[i].index == index) {
 174             return &cpuid->entries[i];
 175         }
 176     }
 177     /* not found: */
 178     return NULL;
 179 }
 180
 181 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 182                                       uint32_t index, int reg)
 183 {
 184     struct kvm_cpuid2 *cpuid;
 185     uint32_t ret = 0;
 186     uint32_t cpuid_1_edx;
 187     bool found = false;
 188
 189     cpuid = get_supported_cpuid(s);
 190
 191     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 192     if (entry) {
 193         found = true;
 194         ret = cpuid_entry_get_reg(entry, reg);
 195     }
 196
 197     /* Fixups for the data returned by KVM, below */
 198
 199     if (function == 1 && reg == R_EDX) {
 200         /* KVM before 2.6.30 misreports the following features */
 201         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 202     } else if (function == 1 && reg == R_ECX) {
 203         /* We can set the hypervisor flag, even if KVM does not return it on
 204          * GET_SUPPORTED_CPUID
 205          */
 206         ret |= CPUID_EXT_HYPERVISOR;
 207         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 208          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 209          * and the irqchip is in the kernel.
 210          */
 211         if (kvm_irqchip_in_kernel() &&
 212                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 213             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 214         }
 215
 216         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 217          * without the in-kernel irqchip
 218          */
 219         if (!kvm_irqchip_in_kernel()) {
 220             ret &= ~CPUID_EXT_X2APIC;
 221         }
 222     } else if (function == 0x80000001 && reg == R_EDX) {
 223         /* On Intel, kvm returns cpuid according to the Intel spec,
 224          * so add missing bits according to the AMD spec:
 225          */
 226         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 227         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 228     }
 229
 230     g_free(cpuid);
 231
 232     /* fallback for older kernels */
 233     if ((function == KVM_CPUID_FEATURES) && !found) {
 234         ret = get_para_features(s);
 235     }
 236
 237     return ret;
 238 }
 239
 240 typedef struct HWPoisonPage {
 241     ram_addr_t ram_addr;
 242     QLIST_ENTRY(HWPoisonPage) list;
 243 } HWPoisonPage;
 244
 245 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 246     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 247
 248 static void kvm_unpoison_all(void *param)
 249 {
 250     HWPoisonPage *page, *next_page;
 251
 252     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 253         QLIST_REMOVE(page, list);
 254         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 255         g_free(page);
 256     }
 257 }
 258
 259 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 260 {
 261     HWPoisonPage *page;
 262
 263     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 264         if (page->ram_addr == ram_addr) {
 265             return;
 266         }
 267     }
 268     page = g_malloc(sizeof(HWPoisonPage));
 269     page->ram_addr = ram_addr;
 270     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 271 }
 272
 273 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 274                                      int *max_banks)
 275 {
 276     int r;
 277
 278     r = kvm_check_extension(s, KVM_CAP_MCE);
 279     if (r > 0) {
 280         *max_banks = r;
 281         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 282     }
 283     return -ENOSYS;
 284 }
 285
 286 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 287 {
 288     CPUX86State *env = &cpu->env;
 289     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 290                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 291     uint64_t mcg_status = MCG_STATUS_MCIP;
 292
 293     if (code == BUS_MCEERR_AR) {
 294         status |= MCI_STATUS_AR | 0x134;
 295         mcg_status |= MCG_STATUS_EIPV;
 296     } else {
 297         status |= 0xc0;
 298         mcg_status |= MCG_STATUS_RIPV;
 299     }
 300     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 301                        (MCM_ADDR_PHYS << 6) | 0xc,
 302                        cpu_x86_support_mca_broadcast(env) ?
 303                        MCE_INJECT_BROADCAST : 0);
 304 }
 305
 306 static void hardware_memory_error(void)
 307 {
 308     fprintf(stderr, "Hardware memory error!\n");
 309     exit(1);
 310 }
 311
 312 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 313 {
 314     X86CPU *cpu = X86_CPU(c);
 315     CPUX86State *env = &cpu->env;
 316     ram_addr_t ram_addr;
 317     hwaddr paddr;
 318
 319     if ((env->mcg_cap & MCG_SER_P) && addr
 320         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 321         if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
 322             !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 323             fprintf(stderr, "Hardware memory error for memory used by "
 324                     "QEMU itself instead of guest system!\n");
 325             /* Hope we are lucky for AO MCE */
 326             if (code == BUS_MCEERR_AO) {
 327                 return 0;
 328             } else {
 329                 hardware_memory_error();
 330             }
 331         }
 332         kvm_hwpoison_page_add(ram_addr);
 333         kvm_mce_inject(cpu, paddr, code);
 334     } else {
 335         if (code == BUS_MCEERR_AO) {
 336             return 0;
 337         } else if (code == BUS_MCEERR_AR) {
 338             hardware_memory_error();
 339         } else {
 340             return 1;
 341         }
 342     }
 343     return 0;
 344 }
 345
 346 int kvm_arch_on_sigbus(int code, void *addr)
 347 {
 348     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 349         ram_addr_t ram_addr;
 350         hwaddr paddr;
 351
 352         /* Hope we are lucky for AO MCE */
 353         if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
 354             !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_state,
 355                                                 addr, &paddr)) {
 356             fprintf(stderr, "Hardware memory error for memory used by "
 357                     "QEMU itself instead of guest system!: %p\n", addr);
 358             return 0;
 359         }
 360         kvm_hwpoison_page_add(ram_addr);
 361         kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code);
 362     } else {
 363         if (code == BUS_MCEERR_AO) {
 364             return 0;
 365         } else if (code == BUS_MCEERR_AR) {
 366             hardware_memory_error();
 367         } else {
 368             return 1;
 369         }
 370     }
 371     return 0;
 372 }
 373
 374 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 375 {
 376     CPUX86State *env = &cpu->env;
 377
 378     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 379         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 380         struct kvm_x86_mce mce;
 381
 382         env->exception_injected = -1;
 383
 384         /*
 385          * There must be at least one bank in use if an MCE is pending.
 386          * Find it and use its values for the event injection.
 387          */
 388         for (bank = 0; bank < bank_num; bank++) {
 389             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 390                 break;
 391             }
 392         }
 393         assert(bank < bank_num);
 394
 395         mce.bank = bank;
 396         mce.status = env->mce_banks[bank * 4 + 1];
 397         mce.mcg_status = env->mcg_status;
 398         mce.addr = env->mce_banks[bank * 4 + 2];
 399         mce.misc = env->mce_banks[bank * 4 + 3];
 400
 401         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 402     }
 403     return 0;
 404 }
 405
 406 static void cpu_update_state(void *opaque, int running, RunState state)
 407 {
 408     CPUX86State *env = opaque;
 409
 410     if (running) {
 411         env->tsc_valid = false;
 412     }
 413 }
 414
 415 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 416 {
 417     X86CPU *cpu = X86_CPU(cs);
 418     return cpu->env.cpuid_apic_id;
 419 }
 420
 421 #define KVM_MAX_CPUID_ENTRIES  100
 422
 423 int kvm_arch_init_vcpu(CPUState *cs)
 424 {
 425     struct {
 426         struct kvm_cpuid2 cpuid;
 427         struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
 428     } QEMU_PACKED cpuid_data;
 429     X86CPU *cpu = X86_CPU(cs);
 430     CPUX86State *env = &cpu->env;
 431     uint32_t limit, i, j, cpuid_i;
 432     uint32_t unused;
 433     struct kvm_cpuid_entry2 *c;
 434     uint32_t signature[3];
 435     int r;
 436
 437     cpuid_i = 0;
 438
 439     /* Paravirtualization CPUIDs */
 440     c = &cpuid_data.entries[cpuid_i++];
 441     memset(c, 0, sizeof(*c));
 442     c->function = KVM_CPUID_SIGNATURE;
 443     if (!hyperv_enabled()) {
 444         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 445         c->eax = 0;
 446     } else {
 447         memcpy(signature, "Microsoft Hv", 12);
 448         c->eax = HYPERV_CPUID_MIN;
 449     }
 450     c->ebx = signature[0];
 451     c->ecx = signature[1];
 452     c->edx = signature[2];
 453
 454     c = &cpuid_data.entries[cpuid_i++];
 455     memset(c, 0, sizeof(*c));
 456     c->function = KVM_CPUID_FEATURES;
 457     c->eax = env->features[FEAT_KVM];
 458
 459     if (hyperv_enabled()) {
 460         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 461         c->eax = signature[0];
 462
 463         c = &cpuid_data.entries[cpuid_i++];
 464         memset(c, 0, sizeof(*c));
 465         c->function = HYPERV_CPUID_VERSION;
 466         c->eax = 0x00001bbc;
 467         c->ebx = 0x00060001;
 468
 469         c = &cpuid_data.entries[cpuid_i++];
 470         memset(c, 0, sizeof(*c));
 471         c->function = HYPERV_CPUID_FEATURES;
 472         if (hyperv_relaxed_timing_enabled()) {
 473             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 474         }
 475         if (hyperv_vapic_recommended()) {
 476             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 477             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 478         }
 479
 480         c = &cpuid_data.entries[cpuid_i++];
 481         memset(c, 0, sizeof(*c));
 482         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 483         if (hyperv_relaxed_timing_enabled()) {
 484             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 485         }
 486         if (hyperv_vapic_recommended()) {
 487             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 488         }
 489         c->ebx = hyperv_get_spinlock_retries();
 490
 491         c = &cpuid_data.entries[cpuid_i++];
 492         memset(c, 0, sizeof(*c));
 493         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 494         c->eax = 0x40;
 495         c->ebx = 0x40;
 496
 497         c = &cpuid_data.entries[cpuid_i++];
 498         memset(c, 0, sizeof(*c));
 499         c->function = KVM_CPUID_SIGNATURE_NEXT;
 500         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 501         c->eax = 0;
 502         c->ebx = signature[0];
 503         c->ecx = signature[1];
 504         c->edx = signature[2];
 505     }
 506
 507     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 508
 509     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 510
 511     has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
 512
 513     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 514
 515     for (i = 0; i <= limit; i++) {
 516         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 517             fprintf(stderr, "unsupported level value: 0x%x\n", limit);
 518             abort();
 519         }
 520         c = &cpuid_data.entries[cpuid_i++];
 521
 522         switch (i) {
 523         case 2: {
 524             /* Keep reading function 2 till all the input is received */
 525             int times;
 526
 527             c->function = i;
 528             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 529                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 530             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 531             times = c->eax & 0xff;
 532
 533             for (j = 1; j < times; ++j) {
 534                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 535                     fprintf(stderr, "cpuid_data is full, no space for "
 536                             "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
 537                     abort();
 538                 }
 539                 c = &cpuid_data.entries[cpuid_i++];
 540                 c->function = i;
 541                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 542                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 543             }
 544             break;
 545         }
 546         case 4:
 547         case 0xb:
 548         case 0xd:
 549             for (j = 0; ; j++) {
 550                 if (i == 0xd && j == 64) {
 551                     break;
 552                 }
 553                 c->function = i;
 554                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 555                 c->index = j;
 556                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 557
 558                 if (i == 4 && c->eax == 0) {
 559                     break;
 560                 }
 561                 if (i == 0xb && !(c->ecx & 0xff00)) {
 562                     break;
 563                 }
 564                 if (i == 0xd && c->eax == 0) {
 565                     continue;
 566                 }
 567                 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 568                     fprintf(stderr, "cpuid_data is full, no space for "
 569                             "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
 570                     abort();
 571                 }
 572                 c = &cpuid_data.entries[cpuid_i++];
 573             }
 574             break;
 575         default:
 576             c->function = i;
 577             c->flags = 0;
 578             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 579             break;
 580         }
 581     }
 582     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 583
 584     for (i = 0x80000000; i <= limit; i++) {
 585         if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 586             fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
 587             abort();
 588         }
 589         c = &cpuid_data.entries[cpuid_i++];
 590
 591         c->function = i;
 592         c->flags = 0;
 593         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 594     }
 595
 596     /* Call Centaur's CPUID instructions they are supported. */
 597     if (env->cpuid_xlevel2 > 0) {
 598         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 599
 600         for (i = 0xC0000000; i <= limit; i++) {
 601             if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
 602                 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
 603                 abort();
 604             }
 605             c = &cpuid_data.entries[cpuid_i++];
 606
 607             c->function = i;
 608             c->flags = 0;
 609             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 610         }
 611     }
 612
 613     cpuid_data.cpuid.nent = cpuid_i;
 614
 615     if (((env->cpuid_version >> 8)&0xF) >= 6
 616         && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
 617            (CPUID_MCE | CPUID_MCA)
 618         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
 619         uint64_t mcg_cap;
 620         int banks;
 621         int ret;
 622
 623         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
 624         if (ret < 0) {
 625             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 626             return ret;
 627         }
 628
 629         if (banks > MCE_BANKS_DEF) {
 630             banks = MCE_BANKS_DEF;
 631         }
 632         mcg_cap &= MCE_CAP_DEF;
 633         mcg_cap |= banks;
 634         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
 635         if (ret < 0) {
 636             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 637             return ret;
 638         }
 639
 640         env->mcg_cap = mcg_cap;
 641     }
 642
 643     qemu_add_vm_change_state_handler(cpu_update_state, env);
 644
 645     cpuid_data.cpuid.padding = 0;
 646     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
 647     if (r) {
 648         return r;
 649     }
 650
 651     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
 652     if (r && env->tsc_khz) {
 653         r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
 654         if (r < 0) {
 655             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 656             return r;
 657         }
 658     }
 659
 660     if (kvm_has_xsave()) {
 661         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 662     }
 663
 664     return 0;
 665 }
 666
 667 void kvm_arch_reset_vcpu(CPUState *cs)
 668 {
 669     X86CPU *cpu = X86_CPU(cs);
 670     CPUX86State *env = &cpu->env;
 671
 672     env->exception_injected = -1;
 673     env->interrupt_injected = -1;
 674     env->xcr0 = 1;
 675     if (kvm_irqchip_in_kernel()) {
 676         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 677                                           KVM_MP_STATE_UNINITIALIZED;
 678     } else {
 679         env->mp_state = KVM_MP_STATE_RUNNABLE;
 680     }
 681 }
 682
 683 static int kvm_get_supported_msrs(KVMState *s)
 684 {
 685     static int kvm_supported_msrs;
 686     int ret = 0;
 687
 688     /* first time */
 689     if (kvm_supported_msrs == 0) {
 690         struct kvm_msr_list msr_list, *kvm_msr_list;
 691
 692         kvm_supported_msrs = -1;
 693
 694         /* Obtain MSR list from KVM.  These are the MSRs that we must
 695          * save/restore */
 696         msr_list.nmsrs = 0;
 697         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 698         if (ret < 0 && ret != -E2BIG) {
 699             return ret;
 700         }
 701         /* Old kernel modules had a bug and could write beyond the provided
 702            memory. Allocate at least a safe amount of 1K. */
 703         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 704                                               msr_list.nmsrs *
 705                                               sizeof(msr_list.indices[0])));
 706
 707         kvm_msr_list->nmsrs = msr_list.nmsrs;
 708         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 709         if (ret >= 0) {
 710             int i;
 711
 712             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 713                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 714                     has_msr_star = true;
 715                     continue;
 716                 }
 717                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 718                     has_msr_hsave_pa = true;
 719                     continue;
 720                 }
 721                 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
 722                     has_msr_tsc_adjust = true;
 723                     continue;
 724                 }
 725                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 726                     has_msr_tsc_deadline = true;
 727                     continue;
 728                 }
 729                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 730                     has_msr_misc_enable = true;
 731                     continue;
 732                 }
 733             }
 734         }
 735
 736         g_free(kvm_msr_list);
 737     }
 738
 739     return ret;
 740 }
 741
 742 int kvm_arch_init(KVMState *s)
 743 {
 744     uint64_t identity_base = 0xfffbc000;
 745     uint64_t shadow_mem;
 746     int ret;
 747     struct utsname utsname;
 748
 749     ret = kvm_get_supported_msrs(s);
 750     if (ret < 0) {
 751         return ret;
 752     }
 753
 754     uname(&utsname);
 755     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 756
 757     /*
 758      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 759      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 760      * Since these must be part of guest physical memory, we need to allocate
 761      * them, both by setting their start addresses in the kernel and by
 762      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 763      *
 764      * Older KVM versions may not support setting the identity map base. In
 765      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 766      * size.
 767      */
 768     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 769         /* Allows up to 16M BIOSes. */
 770         identity_base = 0xfeffc000;
 771
 772         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 773         if (ret < 0) {
 774             return ret;
 775         }
 776     }
 777
 778     /* Set TSS base one page after EPT identity map. */
 779     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 780     if (ret < 0) {
 781         return ret;
 782     }
 783
 784     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 785     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 786     if (ret < 0) {
 787         fprintf(stderr, "e820_add_entry() table is full\n");
 788         return ret;
 789     }
 790     qemu_register_reset(kvm_unpoison_all, NULL);
 791
 792     shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
 793                                    "kvm_shadow_mem", -1);
 794     if (shadow_mem != -1) {
 795         shadow_mem /= 4096;
 796         ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 797         if (ret < 0) {
 798             return ret;
 799         }
 800     }
 801     return 0;
 802 }
 803
 804 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 805 {
 806     lhs->selector = rhs->selector;
 807     lhs->base = rhs->base;
 808     lhs->limit = rhs->limit;
 809     lhs->type = 3;
 810     lhs->present = 1;
 811     lhs->dpl = 3;
 812     lhs->db = 0;
 813     lhs->s = 1;
 814     lhs->l = 0;
 815     lhs->g = 0;
 816     lhs->avl = 0;
 817     lhs->unusable = 0;
 818 }
 819
 820 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 821 {
 822     unsigned flags = rhs->flags;
 823     lhs->selector = rhs->selector;
 824     lhs->base = rhs->base;
 825     lhs->limit = rhs->limit;
 826     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 827     lhs->present = (flags & DESC_P_MASK) != 0;
 828     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 829     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 830     lhs->s = (flags & DESC_S_MASK) != 0;
 831     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 832     lhs->g = (flags & DESC_G_MASK) != 0;
 833     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 834     lhs->unusable = 0;
 835     lhs->padding = 0;
 836 }
 837
 838 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 839 {
 840     lhs->selector = rhs->selector;
 841     lhs->base = rhs->base;
 842     lhs->limit = rhs->limit;
 843     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 844                  (rhs->present * DESC_P_MASK) |
 845                  (rhs->dpl << DESC_DPL_SHIFT) |
 846                  (rhs->db << DESC_B_SHIFT) |
 847                  (rhs->s * DESC_S_MASK) |
 848                  (rhs->l << DESC_L_SHIFT) |
 849                  (rhs->g * DESC_G_MASK) |
 850                  (rhs->avl * DESC_AVL_MASK);
 851 }
 852
 853 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 854 {
 855     if (set) {
 856         *kvm_reg = *qemu_reg;
 857     } else {
 858         *qemu_reg = *kvm_reg;
 859     }
 860 }
 861
 862 static int kvm_getput_regs(X86CPU *cpu, int set)
 863 {
 864     CPUX86State *env = &cpu->env;
 865     struct kvm_regs regs;
 866     int ret = 0;
 867
 868     if (!set) {
 869         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
 870         if (ret < 0) {
 871             return ret;
 872         }
 873     }
 874
 875     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 876     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 877     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 878     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 879     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 880     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 881     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 882     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 883 #ifdef TARGET_X86_64
 884     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 885     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 886     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 887     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 888     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 889     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 890     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 891     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 892 #endif
 893
 894     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 895     kvm_getput_reg(&regs.rip, &env->eip, set);
 896
 897     if (set) {
 898         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
 899     }
 900
 901     return ret;
 902 }
 903
 904 static int kvm_put_fpu(X86CPU *cpu)
 905 {
 906     CPUX86State *env = &cpu->env;
 907     struct kvm_fpu fpu;
 908     int i;
 909
 910     memset(&fpu, 0, sizeof fpu);
 911     fpu.fsw = env->fpus & ~(7 << 11);
 912     fpu.fsw |= (env->fpstt & 7) << 11;
 913     fpu.fcw = env->fpuc;
 914     fpu.last_opcode = env->fpop;
 915     fpu.last_ip = env->fpip;
 916     fpu.last_dp = env->fpdp;
 917     for (i = 0; i < 8; ++i) {
 918         fpu.ftwx |= (!env->fptags[i]) << i;
 919     }
 920     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 921     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 922     fpu.mxcsr = env->mxcsr;
 923
 924     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
 925 }
 926
 927 #define XSAVE_FCW_FSW     0
 928 #define XSAVE_FTW_FOP     1
 929 #define XSAVE_CWD_RIP     2
 930 #define XSAVE_CWD_RDP     4
 931 #define XSAVE_MXCSR       6
 932 #define XSAVE_ST_SPACE    8
 933 #define XSAVE_XMM_SPACE   40
 934 #define XSAVE_XSTATE_BV   128
 935 #define XSAVE_YMMH_SPACE  144
 936
 937 static int kvm_put_xsave(X86CPU *cpu)
 938 {
 939     CPUX86State *env = &cpu->env;
 940     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 941     uint16_t cwd, swd, twd;
 942     int i, r;
 943
 944     if (!kvm_has_xsave()) {
 945         return kvm_put_fpu(cpu);
 946     }
 947
 948     memset(xsave, 0, sizeof(struct kvm_xsave));
 949     twd = 0;
 950     swd = env->fpus & ~(7 << 11);
 951     swd |= (env->fpstt & 7) << 11;
 952     cwd = env->fpuc;
 953     for (i = 0; i < 8; ++i) {
 954         twd |= (!env->fptags[i]) << i;
 955     }
 956     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 957     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 958     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 959     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 960     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 961             sizeof env->fpregs);
 962     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 963             sizeof env->xmm_regs);
 964     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 965     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 966     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 967             sizeof env->ymmh_regs);
 968     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
 969     return r;
 970 }
 971
 972 static int kvm_put_xcrs(X86CPU *cpu)
 973 {
 974     CPUX86State *env = &cpu->env;
 975     struct kvm_xcrs xcrs;
 976
 977     if (!kvm_has_xcrs()) {
 978         return 0;
 979     }
 980
 981     xcrs.nr_xcrs = 1;
 982     xcrs.flags = 0;
 983     xcrs.xcrs[0].xcr = 0;
 984     xcrs.xcrs[0].value = env->xcr0;
 985     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
 986 }
 987
 988 static int kvm_put_sregs(X86CPU *cpu)
 989 {
 990     CPUX86State *env = &cpu->env;
 991     struct kvm_sregs sregs;
 992
 993     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 994     if (env->interrupt_injected >= 0) {
 995         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 996                 (uint64_t)1 << (env->interrupt_injected % 64);
 997     }
 998
 999     if ((env->eflags & VM_MASK)) {
1000         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1001         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1002         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1003         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1004         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1005         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1006     } else {
1007         set_seg(&sregs.cs, &env->segs[R_CS]);
1008         set_seg(&sregs.ds, &env->segs[R_DS]);
1009         set_seg(&sregs.es, &env->segs[R_ES]);
1010         set_seg(&sregs.fs, &env->segs[R_FS]);
1011         set_seg(&sregs.gs, &env->segs[R_GS]);
1012         set_seg(&sregs.ss, &env->segs[R_SS]);
1013     }
1014
1015     set_seg(&sregs.tr, &env->tr);
1016     set_seg(&sregs.ldt, &env->ldt);
1017
1018     sregs.idt.limit = env->idt.limit;
1019     sregs.idt.base = env->idt.base;
1020     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1021     sregs.gdt.limit = env->gdt.limit;
1022     sregs.gdt.base = env->gdt.base;
1023     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1024
1025     sregs.cr0 = env->cr[0];
1026     sregs.cr2 = env->cr[2];
1027     sregs.cr3 = env->cr[3];
1028     sregs.cr4 = env->cr[4];
1029
1030     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1031     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1032
1033     sregs.efer = env->efer;
1034
1035     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1036 }
1037
1038 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1039                               uint32_t index, uint64_t value)
1040 {
1041     entry->index = index;
1042     entry->data = value;
1043 }
1044
1045 static int kvm_put_msrs(X86CPU *cpu, int level)
1046 {
1047     CPUX86State *env = &cpu->env;
1048     struct {
1049         struct kvm_msrs info;
1050         struct kvm_msr_entry entries[100];
1051     } msr_data;
1052     struct kvm_msr_entry *msrs = msr_data.entries;
1053     int n = 0;
1054
1055     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1056     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1057     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1058     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1059     if (has_msr_star) {
1060         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1061     }
1062     if (has_msr_hsave_pa) {
1063         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1064     }
1065     if (has_msr_tsc_adjust) {
1066         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1067     }
1068     if (has_msr_tsc_deadline) {
1069         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1070     }
1071     if (has_msr_misc_enable) {
1072         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1073                           env->msr_ia32_misc_enable);
1074     }
1075 #ifdef TARGET_X86_64
1076     if (lm_capable_kernel) {
1077         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1078         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1079         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1080         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1081     }
1082 #endif
1083     if (level == KVM_PUT_FULL_STATE) {
1084         /*
1085          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1086          * writeback. Until this is fixed, we only write the offset to SMP
1087          * guests after migration, desynchronizing the VCPUs, but avoiding
1088          * huge jump-backs that would occur without any writeback at all.
1089          */
1090         if (smp_cpus == 1 || env->tsc != 0) {
1091             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1092         }
1093     }
1094     /*
1095      * The following paravirtual MSRs have side effects on the guest or are
1096      * too heavy for normal writeback. Limit them to reset or full state
1097      * updates.
1098      */
1099     if (level >= KVM_PUT_RESET_STATE) {
1100         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1101                           env->system_time_msr);
1102         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1103         if (has_msr_async_pf_en) {
1104             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1105                               env->async_pf_en_msr);
1106         }
1107         if (has_msr_pv_eoi_en) {
1108             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1109                               env->pv_eoi_en_msr);
1110         }
1111         if (has_msr_kvm_steal_time) {
1112             kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1113                               env->steal_time_msr);
1114         }
1115         if (hyperv_hypercall_available()) {
1116             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1117             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1118         }
1119         if (hyperv_vapic_recommended()) {
1120             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1121         }
1122     }
1123     if (env->mcg_cap) {
1124         int i;
1125
1126         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1127         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1128         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1129             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1130         }
1131     }
1132
1133     msr_data.info.nmsrs = n;
1134
1135     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1136
1137 }
1138
1139
1140 static int kvm_get_fpu(X86CPU *cpu)
1141 {
1142     CPUX86State *env = &cpu->env;
1143     struct kvm_fpu fpu;
1144     int i, ret;
1145
1146     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1147     if (ret < 0) {
1148         return ret;
1149     }
1150
1151     env->fpstt = (fpu.fsw >> 11) & 7;
1152     env->fpus = fpu.fsw;
1153     env->fpuc = fpu.fcw;
1154     env->fpop = fpu.last_opcode;
1155     env->fpip = fpu.last_ip;
1156     env->fpdp = fpu.last_dp;
1157     for (i = 0; i < 8; ++i) {
1158         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1159     }
1160     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1161     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1162     env->mxcsr = fpu.mxcsr;
1163
1164     return 0;
1165 }
1166
1167 static int kvm_get_xsave(X86CPU *cpu)
1168 {
1169     CPUX86State *env = &cpu->env;
1170     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1171     int ret, i;
1172     uint16_t cwd, swd, twd;
1173
1174     if (!kvm_has_xsave()) {
1175         return kvm_get_fpu(cpu);
1176     }
1177
1178     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1179     if (ret < 0) {
1180         return ret;
1181     }
1182
1183     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1184     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1185     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1186     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1187     env->fpstt = (swd >> 11) & 7;
1188     env->fpus = swd;
1189     env->fpuc = cwd;
1190     for (i = 0; i < 8; ++i) {
1191         env->fptags[i] = !((twd >> i) & 1);
1192     }
1193     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1194     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1195     env->mxcsr = xsave->region[XSAVE_MXCSR];
1196     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1197             sizeof env->fpregs);
1198     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1199             sizeof env->xmm_regs);
1200     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1201     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1202             sizeof env->ymmh_regs);
1203     return 0;
1204 }
1205
1206 static int kvm_get_xcrs(X86CPU *cpu)
1207 {
1208     CPUX86State *env = &cpu->env;
1209     int i, ret;
1210     struct kvm_xcrs xcrs;
1211
1212     if (!kvm_has_xcrs()) {
1213         return 0;
1214     }
1215
1216     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1217     if (ret < 0) {
1218         return ret;
1219     }
1220
1221     for (i = 0; i < xcrs.nr_xcrs; i++) {
1222         /* Only support xcr0 now */
1223         if (xcrs.xcrs[0].xcr == 0) {
1224             env->xcr0 = xcrs.xcrs[0].value;
1225             break;
1226         }
1227     }
1228     return 0;
1229 }
1230
1231 static int kvm_get_sregs(X86CPU *cpu)
1232 {
1233     CPUX86State *env = &cpu->env;
1234     struct kvm_sregs sregs;
1235     uint32_t hflags;
1236     int bit, i, ret;
1237
1238     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1239     if (ret < 0) {
1240         return ret;
1241     }
1242
1243     /* There can only be one pending IRQ set in the bitmap at a time, so try
1244        to find it and save its number instead (-1 for none). */
1245     env->interrupt_injected = -1;
1246     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1247         if (sregs.interrupt_bitmap[i]) {
1248             bit = ctz64(sregs.interrupt_bitmap[i]);
1249             env->interrupt_injected = i * 64 + bit;
1250             break;
1251         }
1252     }
1253
1254     get_seg(&env->segs[R_CS], &sregs.cs);
1255     get_seg(&env->segs[R_DS], &sregs.ds);
1256     get_seg(&env->segs[R_ES], &sregs.es);
1257     get_seg(&env->segs[R_FS], &sregs.fs);
1258     get_seg(&env->segs[R_GS], &sregs.gs);
1259     get_seg(&env->segs[R_SS], &sregs.ss);
1260
1261     get_seg(&env->tr, &sregs.tr);
1262     get_seg(&env->ldt, &sregs.ldt);
1263
1264     env->idt.limit = sregs.idt.limit;
1265     env->idt.base = sregs.idt.base;
1266     env->gdt.limit = sregs.gdt.limit;
1267     env->gdt.base = sregs.gdt.base;
1268
1269     env->cr[0] = sregs.cr0;
1270     env->cr[2] = sregs.cr2;
1271     env->cr[3] = sregs.cr3;
1272     env->cr[4] = sregs.cr4;
1273
1274     env->efer = sregs.efer;
1275
1276     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1277
1278 #define HFLAG_COPY_MASK \
1279     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1280        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1281        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1282        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1283
1284     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1285     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1286     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1287                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1288     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1289     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1290                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1291
1292     if (env->efer & MSR_EFER_LMA) {
1293         hflags |= HF_LMA_MASK;
1294     }
1295
1296     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1297         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1298     } else {
1299         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1300                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1301         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1302                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1303         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1304             !(hflags & HF_CS32_MASK)) {
1305             hflags |= HF_ADDSEG_MASK;
1306         } else {
1307             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1308                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1309         }
1310     }
1311     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1312
1313     return 0;
1314 }
1315
1316 static int kvm_get_msrs(X86CPU *cpu)
1317 {
1318     CPUX86State *env = &cpu->env;
1319     struct {
1320         struct kvm_msrs info;
1321         struct kvm_msr_entry entries[100];
1322     } msr_data;
1323     struct kvm_msr_entry *msrs = msr_data.entries;
1324     int ret, i, n;
1325
1326     n = 0;
1327     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1328     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1329     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1330     msrs[n++].index = MSR_PAT;
1331     if (has_msr_star) {
1332         msrs[n++].index = MSR_STAR;
1333     }
1334     if (has_msr_hsave_pa) {
1335         msrs[n++].index = MSR_VM_HSAVE_PA;
1336     }
1337     if (has_msr_tsc_adjust) {
1338         msrs[n++].index = MSR_TSC_ADJUST;
1339     }
1340     if (has_msr_tsc_deadline) {
1341         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1342     }
1343     if (has_msr_misc_enable) {
1344         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1345     }
1346
1347     if (!env->tsc_valid) {
1348         msrs[n++].index = MSR_IA32_TSC;
1349         env->tsc_valid = !runstate_is_running();
1350     }
1351
1352 #ifdef TARGET_X86_64
1353     if (lm_capable_kernel) {
1354         msrs[n++].index = MSR_CSTAR;
1355         msrs[n++].index = MSR_KERNELGSBASE;
1356         msrs[n++].index = MSR_FMASK;
1357         msrs[n++].index = MSR_LSTAR;
1358     }
1359 #endif
1360     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1361     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1362     if (has_msr_async_pf_en) {
1363         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1364     }
1365     if (has_msr_pv_eoi_en) {
1366         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1367     }
1368     if (has_msr_kvm_steal_time) {
1369         msrs[n++].index = MSR_KVM_STEAL_TIME;
1370     }
1371
1372     if (env->mcg_cap) {
1373         msrs[n++].index = MSR_MCG_STATUS;
1374         msrs[n++].index = MSR_MCG_CTL;
1375         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1376             msrs[n++].index = MSR_MC0_CTL + i;
1377         }
1378     }
1379
1380     msr_data.info.nmsrs = n;
1381     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1382     if (ret < 0) {
1383         return ret;
1384     }
1385
1386     for (i = 0; i < ret; i++) {
1387         switch (msrs[i].index) {
1388         case MSR_IA32_SYSENTER_CS:
1389             env->sysenter_cs = msrs[i].data;
1390             break;
1391         case MSR_IA32_SYSENTER_ESP:
1392             env->sysenter_esp = msrs[i].data;
1393             break;
1394         case MSR_IA32_SYSENTER_EIP:
1395             env->sysenter_eip = msrs[i].data;
1396             break;
1397         case MSR_PAT:
1398             env->pat = msrs[i].data;
1399             break;
1400         case MSR_STAR:
1401             env->star = msrs[i].data;
1402             break;
1403 #ifdef TARGET_X86_64
1404         case MSR_CSTAR:
1405             env->cstar = msrs[i].data;
1406             break;
1407         case MSR_KERNELGSBASE:
1408             env->kernelgsbase = msrs[i].data;
1409             break;
1410         case MSR_FMASK:
1411             env->fmask = msrs[i].data;
1412             break;
1413         case MSR_LSTAR:
1414             env->lstar = msrs[i].data;
1415             break;
1416 #endif
1417         case MSR_IA32_TSC:
1418             env->tsc = msrs[i].data;
1419             break;
1420         case MSR_TSC_ADJUST:
1421             env->tsc_adjust = msrs[i].data;
1422             break;
1423         case MSR_IA32_TSCDEADLINE:
1424             env->tsc_deadline = msrs[i].data;
1425             break;
1426         case MSR_VM_HSAVE_PA:
1427             env->vm_hsave = msrs[i].data;
1428             break;
1429         case MSR_KVM_SYSTEM_TIME:
1430             env->system_time_msr = msrs[i].data;
1431             break;
1432         case MSR_KVM_WALL_CLOCK:
1433             env->wall_clock_msr = msrs[i].data;
1434             break;
1435         case MSR_MCG_STATUS:
1436             env->mcg_status = msrs[i].data;
1437             break;
1438         case MSR_MCG_CTL:
1439             env->mcg_ctl = msrs[i].data;
1440             break;
1441         case MSR_IA32_MISC_ENABLE:
1442             env->msr_ia32_misc_enable = msrs[i].data;
1443             break;
1444         default:
1445             if (msrs[i].index >= MSR_MC0_CTL &&
1446                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1447                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1448             }
1449             break;
1450         case MSR_KVM_ASYNC_PF_EN:
1451             env->async_pf_en_msr = msrs[i].data;
1452             break;
1453         case MSR_KVM_PV_EOI_EN:
1454             env->pv_eoi_en_msr = msrs[i].data;
1455             break;
1456         case MSR_KVM_STEAL_TIME:
1457             env->steal_time_msr = msrs[i].data;
1458             break;
1459         }
1460     }
1461
1462     return 0;
1463 }
1464
1465 static int kvm_put_mp_state(X86CPU *cpu)
1466 {
1467     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1468
1469     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1470 }
1471
1472 static int kvm_get_mp_state(X86CPU *cpu)
1473 {
1474     CPUState *cs = CPU(cpu);
1475     CPUX86State *env = &cpu->env;
1476     struct kvm_mp_state mp_state;
1477     int ret;
1478
1479     ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1480     if (ret < 0) {
1481         return ret;
1482     }
1483     env->mp_state = mp_state.mp_state;
1484     if (kvm_irqchip_in_kernel()) {
1485         cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1486     }
1487     return 0;
1488 }
1489
1490 static int kvm_get_apic(X86CPU *cpu)
1491 {
1492     CPUX86State *env = &cpu->env;
1493     DeviceState *apic = env->apic_state;
1494     struct kvm_lapic_state kapic;
1495     int ret;
1496
1497     if (apic && kvm_irqchip_in_kernel()) {
1498         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1499         if (ret < 0) {
1500             return ret;
1501         }
1502
1503         kvm_get_apic_state(apic, &kapic);
1504     }
1505     return 0;
1506 }
1507
1508 static int kvm_put_apic(X86CPU *cpu)
1509 {
1510     CPUX86State *env = &cpu->env;
1511     DeviceState *apic = env->apic_state;
1512     struct kvm_lapic_state kapic;
1513
1514     if (apic && kvm_irqchip_in_kernel()) {
1515         kvm_put_apic_state(apic, &kapic);
1516
1517         return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1518     }
1519     return 0;
1520 }
1521
1522 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1523 {
1524     CPUX86State *env = &cpu->env;
1525     struct kvm_vcpu_events events;
1526
1527     if (!kvm_has_vcpu_events()) {
1528         return 0;
1529     }
1530
1531     events.exception.injected = (env->exception_injected >= 0);
1532     events.exception.nr = env->exception_injected;
1533     events.exception.has_error_code = env->has_error_code;
1534     events.exception.error_code = env->error_code;
1535     events.exception.pad = 0;
1536
1537     events.interrupt.injected = (env->interrupt_injected >= 0);
1538     events.interrupt.nr = env->interrupt_injected;
1539     events.interrupt.soft = env->soft_interrupt;
1540
1541     events.nmi.injected = env->nmi_injected;
1542     events.nmi.pending = env->nmi_pending;
1543     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1544     events.nmi.pad = 0;
1545
1546     events.sipi_vector = env->sipi_vector;
1547
1548     events.flags = 0;
1549     if (level >= KVM_PUT_RESET_STATE) {
1550         events.flags |=
1551             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1552     }
1553
1554     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1555 }
1556
1557 static int kvm_get_vcpu_events(X86CPU *cpu)
1558 {
1559     CPUX86State *env = &cpu->env;
1560     struct kvm_vcpu_events events;
1561     int ret;
1562
1563     if (!kvm_has_vcpu_events()) {
1564         return 0;
1565     }
1566
1567     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1568     if (ret < 0) {
1569        return ret;
1570     }
1571     env->exception_injected =
1572        events.exception.injected ? events.exception.nr : -1;
1573     env->has_error_code = events.exception.has_error_code;
1574     env->error_code = events.exception.error_code;
1575
1576     env->interrupt_injected =
1577         events.interrupt.injected ? events.interrupt.nr : -1;
1578     env->soft_interrupt = events.interrupt.soft;
1579
1580     env->nmi_injected = events.nmi.injected;
1581     env->nmi_pending = events.nmi.pending;
1582     if (events.nmi.masked) {
1583         env->hflags2 |= HF2_NMI_MASK;
1584     } else {
1585         env->hflags2 &= ~HF2_NMI_MASK;
1586     }
1587
1588     env->sipi_vector = events.sipi_vector;
1589
1590     return 0;
1591 }
1592
1593 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1594 {
1595     CPUX86State *env = &cpu->env;
1596     int ret = 0;
1597     unsigned long reinject_trap = 0;
1598
1599     if (!kvm_has_vcpu_events()) {
1600         if (env->exception_injected == 1) {
1601             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1602         } else if (env->exception_injected == 3) {
1603             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1604         }
1605         env->exception_injected = -1;
1606     }
1607
1608     /*
1609      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1610      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1611      * by updating the debug state once again if single-stepping is on.
1612      * Another reason to call kvm_update_guest_debug here is a pending debug
1613      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1614      * reinject them via SET_GUEST_DEBUG.
1615      */
1616     if (reinject_trap ||
1617         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1618         ret = kvm_update_guest_debug(env, reinject_trap);
1619     }
1620     return ret;
1621 }
1622
1623 static int kvm_put_debugregs(X86CPU *cpu)
1624 {
1625     CPUX86State *env = &cpu->env;
1626     struct kvm_debugregs dbgregs;
1627     int i;
1628
1629     if (!kvm_has_debugregs()) {
1630         return 0;
1631     }
1632
1633     for (i = 0; i < 4; i++) {
1634         dbgregs.db[i] = env->dr[i];
1635     }
1636     dbgregs.dr6 = env->dr[6];
1637     dbgregs.dr7 = env->dr[7];
1638     dbgregs.flags = 0;
1639
1640     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1641 }
1642
1643 static int kvm_get_debugregs(X86CPU *cpu)
1644 {
1645     CPUX86State *env = &cpu->env;
1646     struct kvm_debugregs dbgregs;
1647     int i, ret;
1648
1649     if (!kvm_has_debugregs()) {
1650         return 0;
1651     }
1652
1653     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1654     if (ret < 0) {
1655         return ret;
1656     }
1657     for (i = 0; i < 4; i++) {
1658         env->dr[i] = dbgregs.db[i];
1659     }
1660     env->dr[4] = env->dr[6] = dbgregs.dr6;
1661     env->dr[5] = env->dr[7] = dbgregs.dr7;
1662
1663     return 0;
1664 }
1665
1666 int kvm_arch_put_registers(CPUState *cpu, int level)
1667 {
1668     X86CPU *x86_cpu = X86_CPU(cpu);
1669     int ret;
1670
1671     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1672
1673     ret = kvm_getput_regs(x86_cpu, 1);
1674     if (ret < 0) {
1675         return ret;
1676     }
1677     ret = kvm_put_xsave(x86_cpu);
1678     if (ret < 0) {
1679         return ret;
1680     }
1681     ret = kvm_put_xcrs(x86_cpu);
1682     if (ret < 0) {
1683         return ret;
1684     }
1685     ret = kvm_put_sregs(x86_cpu);
1686     if (ret < 0) {
1687         return ret;
1688     }
1689     /* must be before kvm_put_msrs */
1690     ret = kvm_inject_mce_oldstyle(x86_cpu);
1691     if (ret < 0) {
1692         return ret;
1693     }
1694     ret = kvm_put_msrs(x86_cpu, level);
1695     if (ret < 0) {
1696         return ret;
1697     }
1698     if (level >= KVM_PUT_RESET_STATE) {
1699         ret = kvm_put_mp_state(x86_cpu);
1700         if (ret < 0) {
1701             return ret;
1702         }
1703         ret = kvm_put_apic(x86_cpu);
1704         if (ret < 0) {
1705             return ret;
1706         }
1707     }
1708     ret = kvm_put_vcpu_events(x86_cpu, level);
1709     if (ret < 0) {
1710         return ret;
1711     }
1712     ret = kvm_put_debugregs(x86_cpu);
1713     if (ret < 0) {
1714         return ret;
1715     }
1716     /* must be last */
1717     ret = kvm_guest_debug_workarounds(x86_cpu);
1718     if (ret < 0) {
1719         return ret;
1720     }
1721     return 0;
1722 }
1723
1724 int kvm_arch_get_registers(CPUState *cs)
1725 {
1726     X86CPU *cpu = X86_CPU(cs);
1727     int ret;
1728
1729     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1730
1731     ret = kvm_getput_regs(cpu, 0);
1732     if (ret < 0) {
1733         return ret;
1734     }
1735     ret = kvm_get_xsave(cpu);
1736     if (ret < 0) {
1737         return ret;
1738     }
1739     ret = kvm_get_xcrs(cpu);
1740     if (ret < 0) {
1741         return ret;
1742     }
1743     ret = kvm_get_sregs(cpu);
1744     if (ret < 0) {
1745         return ret;
1746     }
1747     ret = kvm_get_msrs(cpu);
1748     if (ret < 0) {
1749         return ret;
1750     }
1751     ret = kvm_get_mp_state(cpu);
1752     if (ret < 0) {
1753         return ret;
1754     }
1755     ret = kvm_get_apic(cpu);
1756     if (ret < 0) {
1757         return ret;
1758     }
1759     ret = kvm_get_vcpu_events(cpu);
1760     if (ret < 0) {
1761         return ret;
1762     }
1763     ret = kvm_get_debugregs(cpu);
1764     if (ret < 0) {
1765         return ret;
1766     }
1767     return 0;
1768 }
1769
1770 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1771 {
1772     X86CPU *x86_cpu = X86_CPU(cpu);
1773     CPUX86State *env = &x86_cpu->env;
1774     int ret;
1775
1776     /* Inject NMI */
1777     if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1778         cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1779         DPRINTF("injected NMI\n");
1780         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1781         if (ret < 0) {
1782             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1783                     strerror(-ret));
1784         }
1785     }
1786
1787     if (!kvm_irqchip_in_kernel()) {
1788         /* Force the VCPU out of its inner loop to process any INIT requests
1789          * or pending TPR access reports. */
1790         if (cpu->interrupt_request &
1791             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1792             cpu->exit_request = 1;
1793         }
1794
1795         /* Try to inject an interrupt if the guest can accept it */
1796         if (run->ready_for_interrupt_injection &&
1797             (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1798             (env->eflags & IF_MASK)) {
1799             int irq;
1800
1801             cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
1802             irq = cpu_get_pic_interrupt(env);
1803             if (irq >= 0) {
1804                 struct kvm_interrupt intr;
1805
1806                 intr.irq = irq;
1807                 DPRINTF("injected interrupt %d\n", irq);
1808                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1809                 if (ret < 0) {
1810                     fprintf(stderr,
1811                             "KVM: injection failed, interrupt lost (%s)\n",
1812                             strerror(-ret));
1813                 }
1814             }
1815         }
1816
1817         /* If we have an interrupt but the guest is not ready to receive an
1818          * interrupt, request an interrupt window exit.  This will
1819          * cause a return to userspace as soon as the guest is ready to
1820          * receive interrupts. */
1821         if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
1822             run->request_interrupt_window = 1;
1823         } else {
1824             run->request_interrupt_window = 0;
1825         }
1826
1827         DPRINTF("setting tpr\n");
1828         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1829     }
1830 }
1831
1832 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1833 {
1834     X86CPU *x86_cpu = X86_CPU(cpu);
1835     CPUX86State *env = &x86_cpu->env;
1836
1837     if (run->if_flag) {
1838         env->eflags |= IF_MASK;
1839     } else {
1840         env->eflags &= ~IF_MASK;
1841     }
1842     cpu_set_apic_tpr(env->apic_state, run->cr8);
1843     cpu_set_apic_base(env->apic_state, run->apic_base);
1844 }
1845
1846 int kvm_arch_process_async_events(CPUState *cs)
1847 {
1848     X86CPU *cpu = X86_CPU(cs);
1849     CPUX86State *env = &cpu->env;
1850
1851     if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
1852         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1853         assert(env->mcg_cap);
1854
1855         cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1856
1857         kvm_cpu_synchronize_state(cs);
1858
1859         if (env->exception_injected == EXCP08_DBLE) {
1860             /* this means triple fault */
1861             qemu_system_reset_request();
1862             cs->exit_request = 1;
1863             return 0;
1864         }
1865         env->exception_injected = EXCP12_MCHK;
1866         env->has_error_code = 0;
1867
1868         cs->halted = 0;
1869         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1870             env->mp_state = KVM_MP_STATE_RUNNABLE;
1871         }
1872     }
1873
1874     if (kvm_irqchip_in_kernel()) {
1875         return 0;
1876     }
1877
1878     if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
1879         cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
1880         apic_poll_irq(env->apic_state);
1881     }
1882     if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1883          (env->eflags & IF_MASK)) ||
1884         (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
1885         cs->halted = 0;
1886     }
1887     if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
1888         kvm_cpu_synchronize_state(cs);
1889         do_cpu_init(cpu);
1890     }
1891     if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
1892         kvm_cpu_synchronize_state(cs);
1893         do_cpu_sipi(cpu);
1894     }
1895     if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
1896         cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
1897         kvm_cpu_synchronize_state(cs);
1898         apic_handle_tpr_access_report(env->apic_state, env->eip,
1899                                       env->tpr_access_type);
1900     }
1901
1902     return cs->halted;
1903 }
1904
1905 static int kvm_handle_halt(X86CPU *cpu)
1906 {
1907     CPUState *cs = CPU(cpu);
1908     CPUX86State *env = &cpu->env;
1909
1910     if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1911           (env->eflags & IF_MASK)) &&
1912         !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
1913         cs->halted = 1;
1914         return EXCP_HLT;
1915     }
1916
1917     return 0;
1918 }
1919
1920 static int kvm_handle_tpr_access(X86CPU *cpu)
1921 {
1922     CPUX86State *env = &cpu->env;
1923     CPUState *cs = CPU(cpu);
1924     struct kvm_run *run = cs->kvm_run;
1925
1926     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1927                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1928                                                            : TPR_ACCESS_READ);
1929     return 1;
1930 }
1931
1932 int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1933 {
1934     CPUX86State *env = &X86_CPU(cpu)->env;
1935     static const uint8_t int3 = 0xcc;
1936
1937     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1938         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1939         return -EINVAL;
1940     }
1941     return 0;
1942 }
1943
1944 int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1945 {
1946     CPUX86State *env = &X86_CPU(cpu)->env;
1947     uint8_t int3;
1948
1949     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1950         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1951         return -EINVAL;
1952     }
1953     return 0;
1954 }
1955
1956 static struct {
1957     target_ulong addr;
1958     int len;
1959     int type;
1960 } hw_breakpoint[4];
1961
1962 static int nb_hw_breakpoint;
1963
1964 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1965 {
1966     int n;
1967
1968     for (n = 0; n < nb_hw_breakpoint; n++) {
1969         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1970             (hw_breakpoint[n].len == len || len == -1)) {
1971             return n;
1972         }
1973     }
1974     return -1;
1975 }
1976
1977 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1978                                   target_ulong len, int type)
1979 {
1980     switch (type) {
1981     case GDB_BREAKPOINT_HW:
1982         len = 1;
1983         break;
1984     case GDB_WATCHPOINT_WRITE:
1985     case GDB_WATCHPOINT_ACCESS:
1986         switch (len) {
1987         case 1:
1988             break;
1989         case 2:
1990         case 4:
1991         case 8:
1992             if (addr & (len - 1)) {
1993                 return -EINVAL;
1994             }
1995             break;
1996         default:
1997             return -EINVAL;
1998         }
1999         break;
2000     default:
2001         return -ENOSYS;
2002     }
2003
2004     if (nb_hw_breakpoint == 4) {
2005         return -ENOBUFS;
2006     }
2007     if (find_hw_breakpoint(addr, len, type) >= 0) {
2008         return -EEXIST;
2009     }
2010     hw_breakpoint[nb_hw_breakpoint].addr = addr;
2011     hw_breakpoint[nb_hw_breakpoint].len = len;
2012     hw_breakpoint[nb_hw_breakpoint].type = type;
2013     nb_hw_breakpoint++;
2014
2015     return 0;
2016 }
2017
2018 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2019                                   target_ulong len, int type)
2020 {
2021     int n;
2022
2023     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2024     if (n < 0) {
2025         return -ENOENT;
2026     }
2027     nb_hw_breakpoint--;
2028     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2029
2030     return 0;
2031 }
2032
2033 void kvm_arch_remove_all_hw_breakpoints(void)
2034 {
2035     nb_hw_breakpoint = 0;
2036 }
2037
2038 static CPUWatchpoint hw_watchpoint;
2039
2040 static int kvm_handle_debug(X86CPU *cpu,
2041                             struct kvm_debug_exit_arch *arch_info)
2042 {
2043     CPUX86State *env = &cpu->env;
2044     int ret = 0;
2045     int n;
2046
2047     if (arch_info->exception == 1) {
2048         if (arch_info->dr6 & (1 << 14)) {
2049             if (env->singlestep_enabled) {
2050                 ret = EXCP_DEBUG;
2051             }
2052         } else {
2053             for (n = 0; n < 4; n++) {
2054                 if (arch_info->dr6 & (1 << n)) {
2055                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2056                     case 0x0:
2057                         ret = EXCP_DEBUG;
2058                         break;
2059                     case 0x1:
2060                         ret = EXCP_DEBUG;
2061                         env->watchpoint_hit = &hw_watchpoint;
2062                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2063                         hw_watchpoint.flags = BP_MEM_WRITE;
2064                         break;
2065                     case 0x3:
2066                         ret = EXCP_DEBUG;
2067                         env->watchpoint_hit = &hw_watchpoint;
2068                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2069                         hw_watchpoint.flags = BP_MEM_ACCESS;
2070                         break;
2071                     }
2072                 }
2073             }
2074         }
2075     } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2076         ret = EXCP_DEBUG;
2077     }
2078     if (ret == 0) {
2079         cpu_synchronize_state(CPU(cpu));
2080         assert(env->exception_injected == -1);
2081
2082         /* pass to guest */
2083         env->exception_injected = arch_info->exception;
2084         env->has_error_code = 0;
2085     }
2086
2087     return ret;
2088 }
2089
2090 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2091 {
2092     const uint8_t type_code[] = {
2093         [GDB_BREAKPOINT_HW] = 0x0,
2094         [GDB_WATCHPOINT_WRITE] = 0x1,
2095         [GDB_WATCHPOINT_ACCESS] = 0x3
2096     };
2097     const uint8_t len_code[] = {
2098         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2099     };
2100     int n;
2101
2102     if (kvm_sw_breakpoints_active(cpu)) {
2103         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2104     }
2105     if (nb_hw_breakpoint > 0) {
2106         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2107         dbg->arch.debugreg[7] = 0x0600;
2108         for (n = 0; n < nb_hw_breakpoint; n++) {
2109             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2110             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2111                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2112                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2113         }
2114     }
2115 }
2116
2117 static bool host_supports_vmx(void)
2118 {
2119     uint32_t ecx, unused;
2120
2121     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2122     return ecx & CPUID_EXT_VMX;
2123 }
2124
2125 #define VMX_INVALID_GUEST_STATE 0x80000021
2126
2127 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2128 {
2129     X86CPU *cpu = X86_CPU(cs);
2130     uint64_t code;
2131     int ret;
2132
2133     switch (run->exit_reason) {
2134     case KVM_EXIT_HLT:
2135         DPRINTF("handle_hlt\n");
2136         ret = kvm_handle_halt(cpu);
2137         break;
2138     case KVM_EXIT_SET_TPR:
2139         ret = 0;
2140         break;
2141     case KVM_EXIT_TPR_ACCESS:
2142         ret = kvm_handle_tpr_access(cpu);
2143         break;
2144     case KVM_EXIT_FAIL_ENTRY:
2145         code = run->fail_entry.hardware_entry_failure_reason;
2146         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2147                 code);
2148         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2149             fprintf(stderr,
2150                     "\nIf you're running a guest on an Intel machine without "
2151                         "unrestricted mode\n"
2152                     "support, the failure can be most likely due to the guest "
2153                         "entering an invalid\n"
2154                     "state for Intel VT. For example, the guest maybe running "
2155                         "in big real mode\n"
2156                     "which is not supported on less recent Intel processors."
2157                         "\n\n");
2158         }
2159         ret = -1;
2160         break;
2161     case KVM_EXIT_EXCEPTION:
2162         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2163                 run->ex.exception, run->ex.error_code);
2164         ret = -1;
2165         break;
2166     case KVM_EXIT_DEBUG:
2167         DPRINTF("kvm_exit_debug\n");
2168         ret = kvm_handle_debug(cpu, &run->debug.arch);
2169         break;
2170     default:
2171         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2172         ret = -1;
2173         break;
2174     }
2175
2176     return ret;
2177 }
2178
2179 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2180 {
2181     X86CPU *cpu = X86_CPU(cs);
2182     CPUX86State *env = &cpu->env;
2183
2184     kvm_cpu_synchronize_state(cs);
2185     return !(env->cr[0] & CR0_PE_MASK) ||
2186            ((env->segs[R_CS].selector  & 3) != 3);
2187 }
2188
2189 void kvm_arch_init_irq_routing(KVMState *s)
2190 {
2191     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2192         /* If kernel can't do irq routing, interrupt source
2193          * override 0->2 cannot be set up as required by HPET.
2194          * So we have to disable it.
2195          */
2196         no_hpet = 1;
2197     }
2198     /* We know at this point that we're using the in-kernel
2199      * irqchip, so we can use irqfds, and on x86 we know
2200      * we can use msi via irqfd and GSI routing.
2201      */
2202     kvm_irqfds_allowed = true;
2203     kvm_msi_via_irqfd_allowed = true;
2204     kvm_gsi_routing_allowed = true;
2205 }
2206
2207 /* Classic KVM device assignment interface. Will remain x86 only. */
2208 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2209                           uint32_t flags, uint32_t *dev_id)
2210 {
2211     struct kvm_assigned_pci_dev dev_data = {
2212         .segnr = dev_addr->domain,
2213         .busnr = dev_addr->bus,
2214         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2215         .flags = flags,
2216     };
2217     int ret;
2218
2219     dev_data.assigned_dev_id =
2220         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2221
2222     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2223     if (ret < 0) {
2224         return ret;
2225     }
2226
2227     *dev_id = dev_data.assigned_dev_id;
2228
2229     return 0;
2230 }
2231
2232 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2233 {
2234     struct kvm_assigned_pci_dev dev_data = {
2235         .assigned_dev_id = dev_id,
2236     };
2237
2238     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2239 }
2240
2241 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2242                                    uint32_t irq_type, uint32_t guest_irq)
2243 {
2244     struct kvm_assigned_irq assigned_irq = {
2245         .assigned_dev_id = dev_id,
2246         .guest_irq = guest_irq,
2247         .flags = irq_type,
2248     };
2249
2250     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2251         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2252     } else {
2253         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2254     }
2255 }
2256
2257 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2258                            uint32_t guest_irq)
2259 {
2260     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2261         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2262
2263     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2264 }
2265
2266 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2267 {
2268     struct kvm_assigned_pci_dev dev_data = {
2269         .assigned_dev_id = dev_id,
2270         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2271     };
2272
2273     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2274 }
2275
2276 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2277                                      uint32_t type)
2278 {
2279     struct kvm_assigned_irq assigned_irq = {
2280         .assigned_dev_id = dev_id,
2281         .flags = type,
2282     };
2283
2284     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2285 }
2286
2287 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2288 {
2289     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2290         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2291 }
2292
2293 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2294 {
2295     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2296                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2297 }
2298
2299 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2300 {
2301     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2302                                                 KVM_DEV_IRQ_HOST_MSI);
2303 }
2304
2305 bool kvm_device_msix_supported(KVMState *s)
2306 {
2307     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2308      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2309     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2310 }
2311
2312 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2313                                  uint32_t nr_vectors)
2314 {
2315     struct kvm_assigned_msix_nr msix_nr = {
2316         .assigned_dev_id = dev_id,
2317         .entry_nr = nr_vectors,
2318     };
2319
2320     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2321 }
2322
2323 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2324                                int virq)
2325 {
2326     struct kvm_assigned_msix_entry msix_entry = {
2327         .assigned_dev_id = dev_id,
2328         .gsi = virq,
2329         .entry = vector,
2330     };
2331
2332     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2333 }
2334
2335 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2336 {
2337     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2338                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2339 }
2340
2341 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2342 {
2343     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2344                                                 KVM_DEV_IRQ_HOST_MSIX);
2345 }