4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
33 #include "exec/ioport.h"
35 #include "hw/pci/pci.h"
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
43 #define DPRINTF(fmt, ...) \
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
51 #define BUS_MCEERR_AR 4
54 #define BUS_MCEERR_AO 5
57 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR
),
59 KVM_CAP_INFO(EXT_CPUID
),
60 KVM_CAP_INFO(MP_STATE
),
64 static bool has_msr_star
;
65 static bool has_msr_hsave_pa
;
66 static bool has_msr_tsc_adjust
;
67 static bool has_msr_tsc_deadline
;
68 static bool has_msr_async_pf_en
;
69 static bool has_msr_pv_eoi_en
;
70 static bool has_msr_misc_enable
;
71 static int lm_capable_kernel
;
73 bool kvm_allows_irq0_override(void)
75 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
78 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
80 struct kvm_cpuid2
*cpuid
;
83 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
84 cpuid
= (struct kvm_cpuid2
*)g_malloc0(size
);
86 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
87 if (r
== 0 && cpuid
->nent
>= max
) {
95 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
103 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
106 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
108 struct kvm_cpuid2
*cpuid
;
110 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
116 struct kvm_para_features
{
119 } para_features
[] = {
120 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
121 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
122 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
123 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
127 static int get_para_features(KVMState
*s
)
131 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
132 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
133 features
|= (1 << para_features
[i
].feature
);
141 /* Returns the value for a specific register on the cpuid entry
143 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
163 /* Find matching entry for function/index on kvm_cpuid2 struct
165 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
170 for (i
= 0; i
< cpuid
->nent
; ++i
) {
171 if (cpuid
->entries
[i
].function
== function
&&
172 cpuid
->entries
[i
].index
== index
) {
173 return &cpuid
->entries
[i
];
180 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
181 uint32_t index
, int reg
)
183 struct kvm_cpuid2
*cpuid
;
185 uint32_t cpuid_1_edx
;
188 cpuid
= get_supported_cpuid(s
);
190 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
193 ret
= cpuid_entry_get_reg(entry
, reg
);
196 /* Fixups for the data returned by KVM, below */
198 if (function
== 1 && reg
== R_EDX
) {
199 /* KVM before 2.6.30 misreports the following features */
200 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
201 } else if (function
== 1 && reg
== R_ECX
) {
202 /* We can set the hypervisor flag, even if KVM does not return it on
203 * GET_SUPPORTED_CPUID
205 ret
|= CPUID_EXT_HYPERVISOR
;
206 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
207 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
208 * and the irqchip is in the kernel.
210 if (kvm_irqchip_in_kernel() &&
211 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
212 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
215 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
216 * without the in-kernel irqchip
218 if (!kvm_irqchip_in_kernel()) {
219 ret
&= ~CPUID_EXT_X2APIC
;
221 } else if (function
== 0x80000001 && reg
== R_EDX
) {
222 /* On Intel, kvm returns cpuid according to the Intel spec,
223 * so add missing bits according to the AMD spec:
225 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
226 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
231 /* fallback for older kernels */
232 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
233 ret
= get_para_features(s
);
239 typedef struct HWPoisonPage
{
241 QLIST_ENTRY(HWPoisonPage
) list
;
244 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
245 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
247 static void kvm_unpoison_all(void *param
)
249 HWPoisonPage
*page
, *next_page
;
251 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
252 QLIST_REMOVE(page
, list
);
253 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
258 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
262 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
263 if (page
->ram_addr
== ram_addr
) {
267 page
= g_malloc(sizeof(HWPoisonPage
));
268 page
->ram_addr
= ram_addr
;
269 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
272 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
277 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
280 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
285 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
287 CPUX86State
*env
= &cpu
->env
;
288 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
289 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
290 uint64_t mcg_status
= MCG_STATUS_MCIP
;
292 if (code
== BUS_MCEERR_AR
) {
293 status
|= MCI_STATUS_AR
| 0x134;
294 mcg_status
|= MCG_STATUS_EIPV
;
297 mcg_status
|= MCG_STATUS_RIPV
;
299 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
300 (MCM_ADDR_PHYS
<< 6) | 0xc,
301 cpu_x86_support_mca_broadcast(env
) ?
302 MCE_INJECT_BROADCAST
: 0);
305 static void hardware_memory_error(void)
307 fprintf(stderr
, "Hardware memory error!\n");
311 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
313 X86CPU
*cpu
= X86_CPU(c
);
314 CPUX86State
*env
= &cpu
->env
;
318 if ((env
->mcg_cap
& MCG_SER_P
) && addr
319 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
320 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
321 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
322 fprintf(stderr
, "Hardware memory error for memory used by "
323 "QEMU itself instead of guest system!\n");
324 /* Hope we are lucky for AO MCE */
325 if (code
== BUS_MCEERR_AO
) {
328 hardware_memory_error();
331 kvm_hwpoison_page_add(ram_addr
);
332 kvm_mce_inject(cpu
, paddr
, code
);
334 if (code
== BUS_MCEERR_AO
) {
336 } else if (code
== BUS_MCEERR_AR
) {
337 hardware_memory_error();
345 int kvm_arch_on_sigbus(int code
, void *addr
)
347 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
351 /* Hope we are lucky for AO MCE */
352 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
353 !kvm_physical_memory_addr_from_host(CPU(first_cpu
)->kvm_state
,
355 fprintf(stderr
, "Hardware memory error for memory used by "
356 "QEMU itself instead of guest system!: %p\n", addr
);
359 kvm_hwpoison_page_add(ram_addr
);
360 kvm_mce_inject(x86_env_get_cpu(first_cpu
), paddr
, code
);
362 if (code
== BUS_MCEERR_AO
) {
364 } else if (code
== BUS_MCEERR_AR
) {
365 hardware_memory_error();
373 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
375 CPUX86State
*env
= &cpu
->env
;
377 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
378 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
379 struct kvm_x86_mce mce
;
381 env
->exception_injected
= -1;
384 * There must be at least one bank in use if an MCE is pending.
385 * Find it and use its values for the event injection.
387 for (bank
= 0; bank
< bank_num
; bank
++) {
388 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
392 assert(bank
< bank_num
);
395 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
396 mce
.mcg_status
= env
->mcg_status
;
397 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
398 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
400 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
405 static void cpu_update_state(void *opaque
, int running
, RunState state
)
407 CPUX86State
*env
= opaque
;
410 env
->tsc_valid
= false;
414 unsigned long kvm_arch_vcpu_id(CPUState
*cpu
)
416 return cpu
->cpu_index
;
419 int kvm_arch_init_vcpu(CPUState
*cs
)
422 struct kvm_cpuid2 cpuid
;
423 struct kvm_cpuid_entry2 entries
[100];
424 } QEMU_PACKED cpuid_data
;
425 X86CPU
*cpu
= X86_CPU(cs
);
426 CPUX86State
*env
= &cpu
->env
;
427 uint32_t limit
, i
, j
, cpuid_i
;
429 struct kvm_cpuid_entry2
*c
;
430 uint32_t signature
[3];
435 /* Paravirtualization CPUIDs */
436 c
= &cpuid_data
.entries
[cpuid_i
++];
437 memset(c
, 0, sizeof(*c
));
438 c
->function
= KVM_CPUID_SIGNATURE
;
439 if (!hyperv_enabled()) {
440 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
443 memcpy(signature
, "Microsoft Hv", 12);
444 c
->eax
= HYPERV_CPUID_MIN
;
446 c
->ebx
= signature
[0];
447 c
->ecx
= signature
[1];
448 c
->edx
= signature
[2];
450 c
= &cpuid_data
.entries
[cpuid_i
++];
451 memset(c
, 0, sizeof(*c
));
452 c
->function
= KVM_CPUID_FEATURES
;
453 c
->eax
= env
->cpuid_kvm_features
;
455 if (hyperv_enabled()) {
456 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
457 c
->eax
= signature
[0];
459 c
= &cpuid_data
.entries
[cpuid_i
++];
460 memset(c
, 0, sizeof(*c
));
461 c
->function
= HYPERV_CPUID_VERSION
;
465 c
= &cpuid_data
.entries
[cpuid_i
++];
466 memset(c
, 0, sizeof(*c
));
467 c
->function
= HYPERV_CPUID_FEATURES
;
468 if (hyperv_relaxed_timing_enabled()) {
469 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
471 if (hyperv_vapic_recommended()) {
472 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
473 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
476 c
= &cpuid_data
.entries
[cpuid_i
++];
477 memset(c
, 0, sizeof(*c
));
478 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
479 if (hyperv_relaxed_timing_enabled()) {
480 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
482 if (hyperv_vapic_recommended()) {
483 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
485 c
->ebx
= hyperv_get_spinlock_retries();
487 c
= &cpuid_data
.entries
[cpuid_i
++];
488 memset(c
, 0, sizeof(*c
));
489 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
493 c
= &cpuid_data
.entries
[cpuid_i
++];
494 memset(c
, 0, sizeof(*c
));
495 c
->function
= KVM_CPUID_SIGNATURE_NEXT
;
496 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
498 c
->ebx
= signature
[0];
499 c
->ecx
= signature
[1];
500 c
->edx
= signature
[2];
503 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
505 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
507 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
509 for (i
= 0; i
<= limit
; i
++) {
510 c
= &cpuid_data
.entries
[cpuid_i
++];
514 /* Keep reading function 2 till all the input is received */
518 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
519 KVM_CPUID_FLAG_STATE_READ_NEXT
;
520 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
521 times
= c
->eax
& 0xff;
523 for (j
= 1; j
< times
; ++j
) {
524 c
= &cpuid_data
.entries
[cpuid_i
++];
526 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
527 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
535 if (i
== 0xd && j
== 64) {
539 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
541 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
543 if (i
== 4 && c
->eax
== 0) {
546 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
549 if (i
== 0xd && c
->eax
== 0) {
552 c
= &cpuid_data
.entries
[cpuid_i
++];
558 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
562 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
564 for (i
= 0x80000000; i
<= limit
; i
++) {
565 c
= &cpuid_data
.entries
[cpuid_i
++];
569 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
572 /* Call Centaur's CPUID instructions they are supported. */
573 if (env
->cpuid_xlevel2
> 0) {
574 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
576 for (i
= 0xC0000000; i
<= limit
; i
++) {
577 c
= &cpuid_data
.entries
[cpuid_i
++];
581 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
585 cpuid_data
.cpuid
.nent
= cpuid_i
;
587 if (((env
->cpuid_version
>> 8)&0xF) >= 6
588 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
589 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
594 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
596 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
600 if (banks
> MCE_BANKS_DEF
) {
601 banks
= MCE_BANKS_DEF
;
603 mcg_cap
&= MCE_CAP_DEF
;
605 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &mcg_cap
);
607 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
611 env
->mcg_cap
= mcg_cap
;
614 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
616 cpuid_data
.cpuid
.padding
= 0;
617 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
622 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
);
623 if (r
&& env
->tsc_khz
) {
624 r
= kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
);
626 fprintf(stderr
, "KVM_SET_TSC_KHZ failed\n");
631 if (kvm_has_xsave()) {
632 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
638 void kvm_arch_reset_vcpu(CPUState
*cs
)
640 X86CPU
*cpu
= X86_CPU(cs
);
641 CPUX86State
*env
= &cpu
->env
;
643 env
->exception_injected
= -1;
644 env
->interrupt_injected
= -1;
646 if (kvm_irqchip_in_kernel()) {
647 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
648 KVM_MP_STATE_UNINITIALIZED
;
650 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
654 static int kvm_get_supported_msrs(KVMState
*s
)
656 static int kvm_supported_msrs
;
660 if (kvm_supported_msrs
== 0) {
661 struct kvm_msr_list msr_list
, *kvm_msr_list
;
663 kvm_supported_msrs
= -1;
665 /* Obtain MSR list from KVM. These are the MSRs that we must
668 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
669 if (ret
< 0 && ret
!= -E2BIG
) {
672 /* Old kernel modules had a bug and could write beyond the provided
673 memory. Allocate at least a safe amount of 1K. */
674 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
676 sizeof(msr_list
.indices
[0])));
678 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
679 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
683 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
684 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
688 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
689 has_msr_hsave_pa
= true;
692 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
693 has_msr_tsc_adjust
= true;
696 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
697 has_msr_tsc_deadline
= true;
700 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
701 has_msr_misc_enable
= true;
707 g_free(kvm_msr_list
);
713 int kvm_arch_init(KVMState
*s
)
715 QemuOptsList
*list
= qemu_find_opts("machine");
716 uint64_t identity_base
= 0xfffbc000;
719 struct utsname utsname
;
721 ret
= kvm_get_supported_msrs(s
);
727 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
730 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
731 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
732 * Since these must be part of guest physical memory, we need to allocate
733 * them, both by setting their start addresses in the kernel and by
734 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
736 * Older KVM versions may not support setting the identity map base. In
737 * that case we need to stick with the default, i.e. a 256K maximum BIOS
740 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
741 /* Allows up to 16M BIOSes. */
742 identity_base
= 0xfeffc000;
744 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
750 /* Set TSS base one page after EPT identity map. */
751 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
756 /* Tell fw_cfg to notify the BIOS to reserve the range. */
757 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
759 fprintf(stderr
, "e820_add_entry() table is full\n");
762 qemu_register_reset(kvm_unpoison_all
, NULL
);
764 if (!QTAILQ_EMPTY(&list
->head
)) {
765 shadow_mem
= qemu_opt_get_size(QTAILQ_FIRST(&list
->head
),
766 "kvm_shadow_mem", -1);
767 if (shadow_mem
!= -1) {
769 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
778 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
780 lhs
->selector
= rhs
->selector
;
781 lhs
->base
= rhs
->base
;
782 lhs
->limit
= rhs
->limit
;
794 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
796 unsigned flags
= rhs
->flags
;
797 lhs
->selector
= rhs
->selector
;
798 lhs
->base
= rhs
->base
;
799 lhs
->limit
= rhs
->limit
;
800 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
801 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
802 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
803 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
804 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
805 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
806 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
807 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
812 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
814 lhs
->selector
= rhs
->selector
;
815 lhs
->base
= rhs
->base
;
816 lhs
->limit
= rhs
->limit
;
817 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
818 (rhs
->present
* DESC_P_MASK
) |
819 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
820 (rhs
->db
<< DESC_B_SHIFT
) |
821 (rhs
->s
* DESC_S_MASK
) |
822 (rhs
->l
<< DESC_L_SHIFT
) |
823 (rhs
->g
* DESC_G_MASK
) |
824 (rhs
->avl
* DESC_AVL_MASK
);
827 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
830 *kvm_reg
= *qemu_reg
;
832 *qemu_reg
= *kvm_reg
;
836 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
838 CPUX86State
*env
= &cpu
->env
;
839 struct kvm_regs regs
;
843 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
849 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
850 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
851 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
852 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
853 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
854 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
855 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
856 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
858 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
859 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
860 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
861 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
862 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
863 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
864 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
865 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
868 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
869 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
872 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
878 static int kvm_put_fpu(X86CPU
*cpu
)
880 CPUX86State
*env
= &cpu
->env
;
884 memset(&fpu
, 0, sizeof fpu
);
885 fpu
.fsw
= env
->fpus
& ~(7 << 11);
886 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
888 fpu
.last_opcode
= env
->fpop
;
889 fpu
.last_ip
= env
->fpip
;
890 fpu
.last_dp
= env
->fpdp
;
891 for (i
= 0; i
< 8; ++i
) {
892 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
894 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
895 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
896 fpu
.mxcsr
= env
->mxcsr
;
898 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
901 #define XSAVE_FCW_FSW 0
902 #define XSAVE_FTW_FOP 1
903 #define XSAVE_CWD_RIP 2
904 #define XSAVE_CWD_RDP 4
905 #define XSAVE_MXCSR 6
906 #define XSAVE_ST_SPACE 8
907 #define XSAVE_XMM_SPACE 40
908 #define XSAVE_XSTATE_BV 128
909 #define XSAVE_YMMH_SPACE 144
911 static int kvm_put_xsave(X86CPU
*cpu
)
913 CPUX86State
*env
= &cpu
->env
;
914 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
915 uint16_t cwd
, swd
, twd
;
918 if (!kvm_has_xsave()) {
919 return kvm_put_fpu(cpu
);
922 memset(xsave
, 0, sizeof(struct kvm_xsave
));
924 swd
= env
->fpus
& ~(7 << 11);
925 swd
|= (env
->fpstt
& 7) << 11;
927 for (i
= 0; i
< 8; ++i
) {
928 twd
|= (!env
->fptags
[i
]) << i
;
930 xsave
->region
[XSAVE_FCW_FSW
] = (uint32_t)(swd
<< 16) + cwd
;
931 xsave
->region
[XSAVE_FTW_FOP
] = (uint32_t)(env
->fpop
<< 16) + twd
;
932 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
933 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
934 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
936 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
937 sizeof env
->xmm_regs
);
938 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
939 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
940 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
941 sizeof env
->ymmh_regs
);
942 r
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
946 static int kvm_put_xcrs(X86CPU
*cpu
)
948 CPUX86State
*env
= &cpu
->env
;
949 struct kvm_xcrs xcrs
;
951 if (!kvm_has_xcrs()) {
957 xcrs
.xcrs
[0].xcr
= 0;
958 xcrs
.xcrs
[0].value
= env
->xcr0
;
959 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
962 static int kvm_put_sregs(X86CPU
*cpu
)
964 CPUX86State
*env
= &cpu
->env
;
965 struct kvm_sregs sregs
;
967 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
968 if (env
->interrupt_injected
>= 0) {
969 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
970 (uint64_t)1 << (env
->interrupt_injected
% 64);
973 if ((env
->eflags
& VM_MASK
)) {
974 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
975 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
976 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
977 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
978 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
979 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
981 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
982 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
983 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
984 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
985 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
986 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
989 set_seg(&sregs
.tr
, &env
->tr
);
990 set_seg(&sregs
.ldt
, &env
->ldt
);
992 sregs
.idt
.limit
= env
->idt
.limit
;
993 sregs
.idt
.base
= env
->idt
.base
;
994 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
995 sregs
.gdt
.limit
= env
->gdt
.limit
;
996 sregs
.gdt
.base
= env
->gdt
.base
;
997 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
999 sregs
.cr0
= env
->cr
[0];
1000 sregs
.cr2
= env
->cr
[2];
1001 sregs
.cr3
= env
->cr
[3];
1002 sregs
.cr4
= env
->cr
[4];
1004 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
1005 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
1007 sregs
.efer
= env
->efer
;
1009 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1012 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
1013 uint32_t index
, uint64_t value
)
1015 entry
->index
= index
;
1016 entry
->data
= value
;
1019 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1021 CPUX86State
*env
= &cpu
->env
;
1023 struct kvm_msrs info
;
1024 struct kvm_msr_entry entries
[100];
1026 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1029 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1030 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1031 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1032 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
1034 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
1036 if (has_msr_hsave_pa
) {
1037 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1039 if (has_msr_tsc_adjust
) {
1040 kvm_msr_entry_set(&msrs
[n
++], MSR_TSC_ADJUST
, env
->tsc_adjust
);
1042 if (has_msr_tsc_deadline
) {
1043 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1045 if (has_msr_misc_enable
) {
1046 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_MISC_ENABLE
,
1047 env
->msr_ia32_misc_enable
);
1049 #ifdef TARGET_X86_64
1050 if (lm_capable_kernel
) {
1051 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1052 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1053 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1054 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1057 if (level
== KVM_PUT_FULL_STATE
) {
1059 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1060 * writeback. Until this is fixed, we only write the offset to SMP
1061 * guests after migration, desynchronizing the VCPUs, but avoiding
1062 * huge jump-backs that would occur without any writeback at all.
1064 if (smp_cpus
== 1 || env
->tsc
!= 0) {
1065 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
1069 * The following paravirtual MSRs have side effects on the guest or are
1070 * too heavy for normal writeback. Limit them to reset or full state
1073 if (level
>= KVM_PUT_RESET_STATE
) {
1074 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
1075 env
->system_time_msr
);
1076 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1077 if (has_msr_async_pf_en
) {
1078 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
1079 env
->async_pf_en_msr
);
1081 if (has_msr_pv_eoi_en
) {
1082 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_PV_EOI_EN
,
1083 env
->pv_eoi_en_msr
);
1085 if (hyperv_hypercall_available()) {
1086 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_GUEST_OS_ID
, 0);
1087 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_HYPERCALL
, 0);
1089 if (hyperv_vapic_recommended()) {
1090 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
1096 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
1097 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
1098 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1099 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1103 msr_data
.info
.nmsrs
= n
;
1105 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1110 static int kvm_get_fpu(X86CPU
*cpu
)
1112 CPUX86State
*env
= &cpu
->env
;
1116 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1121 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1122 env
->fpus
= fpu
.fsw
;
1123 env
->fpuc
= fpu
.fcw
;
1124 env
->fpop
= fpu
.last_opcode
;
1125 env
->fpip
= fpu
.last_ip
;
1126 env
->fpdp
= fpu
.last_dp
;
1127 for (i
= 0; i
< 8; ++i
) {
1128 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1130 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1131 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1132 env
->mxcsr
= fpu
.mxcsr
;
1137 static int kvm_get_xsave(X86CPU
*cpu
)
1139 CPUX86State
*env
= &cpu
->env
;
1140 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1142 uint16_t cwd
, swd
, twd
;
1144 if (!kvm_has_xsave()) {
1145 return kvm_get_fpu(cpu
);
1148 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1153 cwd
= (uint16_t)xsave
->region
[XSAVE_FCW_FSW
];
1154 swd
= (uint16_t)(xsave
->region
[XSAVE_FCW_FSW
] >> 16);
1155 twd
= (uint16_t)xsave
->region
[XSAVE_FTW_FOP
];
1156 env
->fpop
= (uint16_t)(xsave
->region
[XSAVE_FTW_FOP
] >> 16);
1157 env
->fpstt
= (swd
>> 11) & 7;
1160 for (i
= 0; i
< 8; ++i
) {
1161 env
->fptags
[i
] = !((twd
>> i
) & 1);
1163 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1164 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1165 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1166 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1167 sizeof env
->fpregs
);
1168 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1169 sizeof env
->xmm_regs
);
1170 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1171 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1172 sizeof env
->ymmh_regs
);
1176 static int kvm_get_xcrs(X86CPU
*cpu
)
1178 CPUX86State
*env
= &cpu
->env
;
1180 struct kvm_xcrs xcrs
;
1182 if (!kvm_has_xcrs()) {
1186 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1191 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1192 /* Only support xcr0 now */
1193 if (xcrs
.xcrs
[0].xcr
== 0) {
1194 env
->xcr0
= xcrs
.xcrs
[0].value
;
1201 static int kvm_get_sregs(X86CPU
*cpu
)
1203 CPUX86State
*env
= &cpu
->env
;
1204 struct kvm_sregs sregs
;
1208 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1213 /* There can only be one pending IRQ set in the bitmap at a time, so try
1214 to find it and save its number instead (-1 for none). */
1215 env
->interrupt_injected
= -1;
1216 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1217 if (sregs
.interrupt_bitmap
[i
]) {
1218 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1219 env
->interrupt_injected
= i
* 64 + bit
;
1224 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1225 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1226 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1227 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1228 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1229 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1231 get_seg(&env
->tr
, &sregs
.tr
);
1232 get_seg(&env
->ldt
, &sregs
.ldt
);
1234 env
->idt
.limit
= sregs
.idt
.limit
;
1235 env
->idt
.base
= sregs
.idt
.base
;
1236 env
->gdt
.limit
= sregs
.gdt
.limit
;
1237 env
->gdt
.base
= sregs
.gdt
.base
;
1239 env
->cr
[0] = sregs
.cr0
;
1240 env
->cr
[2] = sregs
.cr2
;
1241 env
->cr
[3] = sregs
.cr3
;
1242 env
->cr
[4] = sregs
.cr4
;
1244 env
->efer
= sregs
.efer
;
1246 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1248 #define HFLAG_COPY_MASK \
1249 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1250 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1251 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1252 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1254 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1255 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1256 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1257 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1258 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1259 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1260 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1262 if (env
->efer
& MSR_EFER_LMA
) {
1263 hflags
|= HF_LMA_MASK
;
1266 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1267 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1269 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1270 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1271 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1272 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1273 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1274 !(hflags
& HF_CS32_MASK
)) {
1275 hflags
|= HF_ADDSEG_MASK
;
1277 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1278 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1281 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1286 static int kvm_get_msrs(X86CPU
*cpu
)
1288 CPUX86State
*env
= &cpu
->env
;
1290 struct kvm_msrs info
;
1291 struct kvm_msr_entry entries
[100];
1293 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1297 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1298 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1299 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1300 msrs
[n
++].index
= MSR_PAT
;
1302 msrs
[n
++].index
= MSR_STAR
;
1304 if (has_msr_hsave_pa
) {
1305 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1307 if (has_msr_tsc_adjust
) {
1308 msrs
[n
++].index
= MSR_TSC_ADJUST
;
1310 if (has_msr_tsc_deadline
) {
1311 msrs
[n
++].index
= MSR_IA32_TSCDEADLINE
;
1313 if (has_msr_misc_enable
) {
1314 msrs
[n
++].index
= MSR_IA32_MISC_ENABLE
;
1317 if (!env
->tsc_valid
) {
1318 msrs
[n
++].index
= MSR_IA32_TSC
;
1319 env
->tsc_valid
= !runstate_is_running();
1322 #ifdef TARGET_X86_64
1323 if (lm_capable_kernel
) {
1324 msrs
[n
++].index
= MSR_CSTAR
;
1325 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1326 msrs
[n
++].index
= MSR_FMASK
;
1327 msrs
[n
++].index
= MSR_LSTAR
;
1330 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1331 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1332 if (has_msr_async_pf_en
) {
1333 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1335 if (has_msr_pv_eoi_en
) {
1336 msrs
[n
++].index
= MSR_KVM_PV_EOI_EN
;
1340 msrs
[n
++].index
= MSR_MCG_STATUS
;
1341 msrs
[n
++].index
= MSR_MCG_CTL
;
1342 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1343 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1347 msr_data
.info
.nmsrs
= n
;
1348 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
1353 for (i
= 0; i
< ret
; i
++) {
1354 switch (msrs
[i
].index
) {
1355 case MSR_IA32_SYSENTER_CS
:
1356 env
->sysenter_cs
= msrs
[i
].data
;
1358 case MSR_IA32_SYSENTER_ESP
:
1359 env
->sysenter_esp
= msrs
[i
].data
;
1361 case MSR_IA32_SYSENTER_EIP
:
1362 env
->sysenter_eip
= msrs
[i
].data
;
1365 env
->pat
= msrs
[i
].data
;
1368 env
->star
= msrs
[i
].data
;
1370 #ifdef TARGET_X86_64
1372 env
->cstar
= msrs
[i
].data
;
1374 case MSR_KERNELGSBASE
:
1375 env
->kernelgsbase
= msrs
[i
].data
;
1378 env
->fmask
= msrs
[i
].data
;
1381 env
->lstar
= msrs
[i
].data
;
1385 env
->tsc
= msrs
[i
].data
;
1387 case MSR_TSC_ADJUST
:
1388 env
->tsc_adjust
= msrs
[i
].data
;
1390 case MSR_IA32_TSCDEADLINE
:
1391 env
->tsc_deadline
= msrs
[i
].data
;
1393 case MSR_VM_HSAVE_PA
:
1394 env
->vm_hsave
= msrs
[i
].data
;
1396 case MSR_KVM_SYSTEM_TIME
:
1397 env
->system_time_msr
= msrs
[i
].data
;
1399 case MSR_KVM_WALL_CLOCK
:
1400 env
->wall_clock_msr
= msrs
[i
].data
;
1402 case MSR_MCG_STATUS
:
1403 env
->mcg_status
= msrs
[i
].data
;
1406 env
->mcg_ctl
= msrs
[i
].data
;
1408 case MSR_IA32_MISC_ENABLE
:
1409 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
1412 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1413 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1414 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1417 case MSR_KVM_ASYNC_PF_EN
:
1418 env
->async_pf_en_msr
= msrs
[i
].data
;
1420 case MSR_KVM_PV_EOI_EN
:
1421 env
->pv_eoi_en_msr
= msrs
[i
].data
;
1429 static int kvm_put_mp_state(X86CPU
*cpu
)
1431 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
1433 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
1436 static int kvm_get_mp_state(X86CPU
*cpu
)
1438 CPUX86State
*env
= &cpu
->env
;
1439 struct kvm_mp_state mp_state
;
1442 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MP_STATE
, &mp_state
);
1446 env
->mp_state
= mp_state
.mp_state
;
1447 if (kvm_irqchip_in_kernel()) {
1448 env
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1453 static int kvm_get_apic(X86CPU
*cpu
)
1455 CPUX86State
*env
= &cpu
->env
;
1456 DeviceState
*apic
= env
->apic_state
;
1457 struct kvm_lapic_state kapic
;
1460 if (apic
&& kvm_irqchip_in_kernel()) {
1461 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
1466 kvm_get_apic_state(apic
, &kapic
);
1471 static int kvm_put_apic(X86CPU
*cpu
)
1473 CPUX86State
*env
= &cpu
->env
;
1474 DeviceState
*apic
= env
->apic_state
;
1475 struct kvm_lapic_state kapic
;
1477 if (apic
&& kvm_irqchip_in_kernel()) {
1478 kvm_put_apic_state(apic
, &kapic
);
1480 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_LAPIC
, &kapic
);
1485 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
1487 CPUX86State
*env
= &cpu
->env
;
1488 struct kvm_vcpu_events events
;
1490 if (!kvm_has_vcpu_events()) {
1494 events
.exception
.injected
= (env
->exception_injected
>= 0);
1495 events
.exception
.nr
= env
->exception_injected
;
1496 events
.exception
.has_error_code
= env
->has_error_code
;
1497 events
.exception
.error_code
= env
->error_code
;
1498 events
.exception
.pad
= 0;
1500 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1501 events
.interrupt
.nr
= env
->interrupt_injected
;
1502 events
.interrupt
.soft
= env
->soft_interrupt
;
1504 events
.nmi
.injected
= env
->nmi_injected
;
1505 events
.nmi
.pending
= env
->nmi_pending
;
1506 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1509 events
.sipi_vector
= env
->sipi_vector
;
1512 if (level
>= KVM_PUT_RESET_STATE
) {
1514 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1517 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
1520 static int kvm_get_vcpu_events(X86CPU
*cpu
)
1522 CPUX86State
*env
= &cpu
->env
;
1523 struct kvm_vcpu_events events
;
1526 if (!kvm_has_vcpu_events()) {
1530 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
1534 env
->exception_injected
=
1535 events
.exception
.injected
? events
.exception
.nr
: -1;
1536 env
->has_error_code
= events
.exception
.has_error_code
;
1537 env
->error_code
= events
.exception
.error_code
;
1539 env
->interrupt_injected
=
1540 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1541 env
->soft_interrupt
= events
.interrupt
.soft
;
1543 env
->nmi_injected
= events
.nmi
.injected
;
1544 env
->nmi_pending
= events
.nmi
.pending
;
1545 if (events
.nmi
.masked
) {
1546 env
->hflags2
|= HF2_NMI_MASK
;
1548 env
->hflags2
&= ~HF2_NMI_MASK
;
1551 env
->sipi_vector
= events
.sipi_vector
;
1556 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
1558 CPUX86State
*env
= &cpu
->env
;
1560 unsigned long reinject_trap
= 0;
1562 if (!kvm_has_vcpu_events()) {
1563 if (env
->exception_injected
== 1) {
1564 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1565 } else if (env
->exception_injected
== 3) {
1566 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1568 env
->exception_injected
= -1;
1572 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1573 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1574 * by updating the debug state once again if single-stepping is on.
1575 * Another reason to call kvm_update_guest_debug here is a pending debug
1576 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1577 * reinject them via SET_GUEST_DEBUG.
1579 if (reinject_trap
||
1580 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1581 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1586 static int kvm_put_debugregs(X86CPU
*cpu
)
1588 CPUX86State
*env
= &cpu
->env
;
1589 struct kvm_debugregs dbgregs
;
1592 if (!kvm_has_debugregs()) {
1596 for (i
= 0; i
< 4; i
++) {
1597 dbgregs
.db
[i
] = env
->dr
[i
];
1599 dbgregs
.dr6
= env
->dr
[6];
1600 dbgregs
.dr7
= env
->dr
[7];
1603 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
1606 static int kvm_get_debugregs(X86CPU
*cpu
)
1608 CPUX86State
*env
= &cpu
->env
;
1609 struct kvm_debugregs dbgregs
;
1612 if (!kvm_has_debugregs()) {
1616 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
1620 for (i
= 0; i
< 4; i
++) {
1621 env
->dr
[i
] = dbgregs
.db
[i
];
1623 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1624 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1629 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
1631 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1634 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
1636 ret
= kvm_getput_regs(x86_cpu
, 1);
1640 ret
= kvm_put_xsave(x86_cpu
);
1644 ret
= kvm_put_xcrs(x86_cpu
);
1648 ret
= kvm_put_sregs(x86_cpu
);
1652 /* must be before kvm_put_msrs */
1653 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
1657 ret
= kvm_put_msrs(x86_cpu
, level
);
1661 if (level
>= KVM_PUT_RESET_STATE
) {
1662 ret
= kvm_put_mp_state(x86_cpu
);
1666 ret
= kvm_put_apic(x86_cpu
);
1671 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
1675 ret
= kvm_put_debugregs(x86_cpu
);
1680 ret
= kvm_guest_debug_workarounds(x86_cpu
);
1687 int kvm_arch_get_registers(CPUState
*cs
)
1689 X86CPU
*cpu
= X86_CPU(cs
);
1692 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
1694 ret
= kvm_getput_regs(cpu
, 0);
1698 ret
= kvm_get_xsave(cpu
);
1702 ret
= kvm_get_xcrs(cpu
);
1706 ret
= kvm_get_sregs(cpu
);
1710 ret
= kvm_get_msrs(cpu
);
1714 ret
= kvm_get_mp_state(cpu
);
1718 ret
= kvm_get_apic(cpu
);
1722 ret
= kvm_get_vcpu_events(cpu
);
1726 ret
= kvm_get_debugregs(cpu
);
1733 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
1735 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1736 CPUX86State
*env
= &x86_cpu
->env
;
1740 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1741 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1742 DPRINTF("injected NMI\n");
1743 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
1745 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
1750 if (!kvm_irqchip_in_kernel()) {
1751 /* Force the VCPU out of its inner loop to process any INIT requests
1752 * or pending TPR access reports. */
1753 if (env
->interrupt_request
&
1754 (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
1755 env
->exit_request
= 1;
1758 /* Try to inject an interrupt if the guest can accept it */
1759 if (run
->ready_for_interrupt_injection
&&
1760 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1761 (env
->eflags
& IF_MASK
)) {
1764 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1765 irq
= cpu_get_pic_interrupt(env
);
1767 struct kvm_interrupt intr
;
1770 DPRINTF("injected interrupt %d\n", irq
);
1771 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
1774 "KVM: injection failed, interrupt lost (%s)\n",
1780 /* If we have an interrupt but the guest is not ready to receive an
1781 * interrupt, request an interrupt window exit. This will
1782 * cause a return to userspace as soon as the guest is ready to
1783 * receive interrupts. */
1784 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1785 run
->request_interrupt_window
= 1;
1787 run
->request_interrupt_window
= 0;
1790 DPRINTF("setting tpr\n");
1791 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1795 void kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
1797 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1798 CPUX86State
*env
= &x86_cpu
->env
;
1801 env
->eflags
|= IF_MASK
;
1803 env
->eflags
&= ~IF_MASK
;
1805 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1806 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1809 int kvm_arch_process_async_events(CPUState
*cs
)
1811 X86CPU
*cpu
= X86_CPU(cs
);
1812 CPUX86State
*env
= &cpu
->env
;
1814 if (env
->interrupt_request
& CPU_INTERRUPT_MCE
) {
1815 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1816 assert(env
->mcg_cap
);
1818 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
1820 kvm_cpu_synchronize_state(env
);
1822 if (env
->exception_injected
== EXCP08_DBLE
) {
1823 /* this means triple fault */
1824 qemu_system_reset_request();
1825 env
->exit_request
= 1;
1828 env
->exception_injected
= EXCP12_MCHK
;
1829 env
->has_error_code
= 0;
1832 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
1833 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1837 if (kvm_irqchip_in_kernel()) {
1841 if (env
->interrupt_request
& CPU_INTERRUPT_POLL
) {
1842 env
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
1843 apic_poll_irq(env
->apic_state
);
1845 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1846 (env
->eflags
& IF_MASK
)) ||
1847 (env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1850 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1851 kvm_cpu_synchronize_state(env
);
1854 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1855 kvm_cpu_synchronize_state(env
);
1858 if (env
->interrupt_request
& CPU_INTERRUPT_TPR
) {
1859 env
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
1860 kvm_cpu_synchronize_state(env
);
1861 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
,
1862 env
->tpr_access_type
);
1868 static int kvm_handle_halt(X86CPU
*cpu
)
1870 CPUX86State
*env
= &cpu
->env
;
1872 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1873 (env
->eflags
& IF_MASK
)) &&
1874 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1882 static int kvm_handle_tpr_access(X86CPU
*cpu
)
1884 CPUX86State
*env
= &cpu
->env
;
1885 CPUState
*cs
= CPU(cpu
);
1886 struct kvm_run
*run
= cs
->kvm_run
;
1888 apic_handle_tpr_access_report(env
->apic_state
, run
->tpr_access
.rip
,
1889 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
1894 int kvm_arch_insert_sw_breakpoint(CPUState
*cpu
, struct kvm_sw_breakpoint
*bp
)
1896 CPUX86State
*env
= &X86_CPU(cpu
)->env
;
1897 static const uint8_t int3
= 0xcc;
1899 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1900 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
1906 int kvm_arch_remove_sw_breakpoint(CPUState
*cpu
, struct kvm_sw_breakpoint
*bp
)
1908 CPUX86State
*env
= &X86_CPU(cpu
)->env
;
1911 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1912 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
1924 static int nb_hw_breakpoint
;
1926 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1930 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1931 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1932 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
1939 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1940 target_ulong len
, int type
)
1943 case GDB_BREAKPOINT_HW
:
1946 case GDB_WATCHPOINT_WRITE
:
1947 case GDB_WATCHPOINT_ACCESS
:
1954 if (addr
& (len
- 1)) {
1966 if (nb_hw_breakpoint
== 4) {
1969 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
1972 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1973 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1974 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1980 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1981 target_ulong len
, int type
)
1985 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1990 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1995 void kvm_arch_remove_all_hw_breakpoints(void)
1997 nb_hw_breakpoint
= 0;
2000 static CPUWatchpoint hw_watchpoint
;
2002 static int kvm_handle_debug(X86CPU
*cpu
,
2003 struct kvm_debug_exit_arch
*arch_info
)
2005 CPUX86State
*env
= &cpu
->env
;
2009 if (arch_info
->exception
== 1) {
2010 if (arch_info
->dr6
& (1 << 14)) {
2011 if (env
->singlestep_enabled
) {
2015 for (n
= 0; n
< 4; n
++) {
2016 if (arch_info
->dr6
& (1 << n
)) {
2017 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
2023 env
->watchpoint_hit
= &hw_watchpoint
;
2024 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2025 hw_watchpoint
.flags
= BP_MEM_WRITE
;
2029 env
->watchpoint_hit
= &hw_watchpoint
;
2030 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2031 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
2037 } else if (kvm_find_sw_breakpoint(CPU(cpu
), arch_info
->pc
)) {
2041 cpu_synchronize_state(env
);
2042 assert(env
->exception_injected
== -1);
2045 env
->exception_injected
= arch_info
->exception
;
2046 env
->has_error_code
= 0;
2052 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
2054 const uint8_t type_code
[] = {
2055 [GDB_BREAKPOINT_HW
] = 0x0,
2056 [GDB_WATCHPOINT_WRITE
] = 0x1,
2057 [GDB_WATCHPOINT_ACCESS
] = 0x3
2059 const uint8_t len_code
[] = {
2060 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2064 if (kvm_sw_breakpoints_active(cpu
)) {
2065 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
2067 if (nb_hw_breakpoint
> 0) {
2068 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
2069 dbg
->arch
.debugreg
[7] = 0x0600;
2070 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2071 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
2072 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
2073 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
2074 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
2079 static bool host_supports_vmx(void)
2081 uint32_t ecx
, unused
;
2083 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
2084 return ecx
& CPUID_EXT_VMX
;
2087 #define VMX_INVALID_GUEST_STATE 0x80000021
2089 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
2091 X86CPU
*cpu
= X86_CPU(cs
);
2095 switch (run
->exit_reason
) {
2097 DPRINTF("handle_hlt\n");
2098 ret
= kvm_handle_halt(cpu
);
2100 case KVM_EXIT_SET_TPR
:
2103 case KVM_EXIT_TPR_ACCESS
:
2104 ret
= kvm_handle_tpr_access(cpu
);
2106 case KVM_EXIT_FAIL_ENTRY
:
2107 code
= run
->fail_entry
.hardware_entry_failure_reason
;
2108 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
2110 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
2112 "\nIf you're running a guest on an Intel machine without "
2113 "unrestricted mode\n"
2114 "support, the failure can be most likely due to the guest "
2115 "entering an invalid\n"
2116 "state for Intel VT. For example, the guest maybe running "
2117 "in big real mode\n"
2118 "which is not supported on less recent Intel processors."
2123 case KVM_EXIT_EXCEPTION
:
2124 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
2125 run
->ex
.exception
, run
->ex
.error_code
);
2128 case KVM_EXIT_DEBUG
:
2129 DPRINTF("kvm_exit_debug\n");
2130 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
2133 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
2141 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
2143 X86CPU
*cpu
= X86_CPU(cs
);
2144 CPUX86State
*env
= &cpu
->env
;
2146 kvm_cpu_synchronize_state(env
);
2147 return !(env
->cr
[0] & CR0_PE_MASK
) ||
2148 ((env
->segs
[R_CS
].selector
& 3) != 3);
2151 void kvm_arch_init_irq_routing(KVMState
*s
)
2153 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
2154 /* If kernel can't do irq routing, interrupt source
2155 * override 0->2 cannot be set up as required by HPET.
2156 * So we have to disable it.
2160 /* We know at this point that we're using the in-kernel
2161 * irqchip, so we can use irqfds, and on x86 we know
2162 * we can use msi via irqfd and GSI routing.
2164 kvm_irqfds_allowed
= true;
2165 kvm_msi_via_irqfd_allowed
= true;
2166 kvm_gsi_routing_allowed
= true;
2169 /* Classic KVM device assignment interface. Will remain x86 only. */
2170 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
2171 uint32_t flags
, uint32_t *dev_id
)
2173 struct kvm_assigned_pci_dev dev_data
= {
2174 .segnr
= dev_addr
->domain
,
2175 .busnr
= dev_addr
->bus
,
2176 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
2181 dev_data
.assigned_dev_id
=
2182 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
2184 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
2189 *dev_id
= dev_data
.assigned_dev_id
;
2194 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
2196 struct kvm_assigned_pci_dev dev_data
= {
2197 .assigned_dev_id
= dev_id
,
2200 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
2203 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2204 uint32_t irq_type
, uint32_t guest_irq
)
2206 struct kvm_assigned_irq assigned_irq
= {
2207 .assigned_dev_id
= dev_id
,
2208 .guest_irq
= guest_irq
,
2212 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
2213 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
2215 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
2219 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
2222 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
2223 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
2225 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
2228 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
2230 struct kvm_assigned_pci_dev dev_data
= {
2231 .assigned_dev_id
= dev_id
,
2232 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
2235 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
2238 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2241 struct kvm_assigned_irq assigned_irq
= {
2242 .assigned_dev_id
= dev_id
,
2246 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
2249 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
2251 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
2252 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
2255 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
2257 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
2258 KVM_DEV_IRQ_GUEST_MSI
, virq
);
2261 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
2263 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
2264 KVM_DEV_IRQ_HOST_MSI
);
2267 bool kvm_device_msix_supported(KVMState
*s
)
2269 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2270 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2271 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
2274 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
2275 uint32_t nr_vectors
)
2277 struct kvm_assigned_msix_nr msix_nr
= {
2278 .assigned_dev_id
= dev_id
,
2279 .entry_nr
= nr_vectors
,
2282 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
2285 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
2288 struct kvm_assigned_msix_entry msix_entry
= {
2289 .assigned_dev_id
= dev_id
,
2294 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
2297 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
2299 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
2300 KVM_DEV_IRQ_GUEST_MSIX
, 0);
2303 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
2305 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
2306 KVM_DEV_IRQ_HOST_MSIX
);