target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "gdbstub.h"
  29 #include "host-utils.h"
  30 #include "hw/pc.h"
  31 #include "hw/apic.h"
  32 #include "ioport.h"
  33 #include "hyperv.h"
  34 #include "hw/pci.h"
  35
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  57     KVM_CAP_INFO(SET_TSS_ADDR),
  58     KVM_CAP_INFO(EXT_CPUID),
  59     KVM_CAP_INFO(MP_STATE),
  60     KVM_CAP_LAST_INFO
  61 };
  62
  63 static bool has_msr_star;
  64 static bool has_msr_hsave_pa;
  65 static bool has_msr_tsc_deadline;
  66 static bool has_msr_async_pf_en;
  67 static bool has_msr_pv_eoi_en;
  68 static bool has_msr_misc_enable;
  69 static int lm_capable_kernel;
  70
  71 bool kvm_allows_irq0_override(void)
  72 {
  73     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  74 }
  75
  76 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  77 {
  78     struct kvm_cpuid2 *cpuid;
  79     int r, size;
  80
  81     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  82     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  83     cpuid->nent = max;
  84     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  85     if (r == 0 && cpuid->nent >= max) {
  86         r = -E2BIG;
  87     }
  88     if (r < 0) {
  89         if (r == -E2BIG) {
  90             g_free(cpuid);
  91             return NULL;
  92         } else {
  93             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  94                     strerror(-r));
  95             exit(1);
  96         }
  97     }
  98     return cpuid;
  99 }
 100
 101 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 102  * for all entries.
 103  */
 104 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 105 {
 106     struct kvm_cpuid2 *cpuid;
 107     int max = 1;
 108     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 109         max *= 2;
 110     }
 111     return cpuid;
 112 }
 113
 114 struct kvm_para_features {
 115     int cap;
 116     int feature;
 117 } para_features[] = {
 118     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 119     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 120     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 121     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 122     { -1, -1 }
 123 };
 124
 125 static int get_para_features(KVMState *s)
 126 {
 127     int i, features = 0;
 128
 129     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 130         if (kvm_check_extension(s, para_features[i].cap)) {
 131             features |= (1 << para_features[i].feature);
 132         }
 133     }
 134
 135     return features;
 136 }
 137
 138
 139 /* Returns the value for a specific register on the cpuid entry
 140  */
 141 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 142 {
 143     uint32_t ret = 0;
 144     switch (reg) {
 145     case R_EAX:
 146         ret = entry->eax;
 147         break;
 148     case R_EBX:
 149         ret = entry->ebx;
 150         break;
 151     case R_ECX:
 152         ret = entry->ecx;
 153         break;
 154     case R_EDX:
 155         ret = entry->edx;
 156         break;
 157     }
 158     return ret;
 159 }
 160
 161 /* Find matching entry for function/index on kvm_cpuid2 struct
 162  */
 163 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 164                                                  uint32_t function,
 165                                                  uint32_t index)
 166 {
 167     int i;
 168     for (i = 0; i < cpuid->nent; ++i) {
 169         if (cpuid->entries[i].function == function &&
 170             cpuid->entries[i].index == index) {
 171             return &cpuid->entries[i];
 172         }
 173     }
 174     /* not found: */
 175     return NULL;
 176 }
 177
 178 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 179                                       uint32_t index, int reg)
 180 {
 181     struct kvm_cpuid2 *cpuid;
 182     uint32_t ret = 0;
 183     uint32_t cpuid_1_edx;
 184     bool found = false;
 185
 186     cpuid = get_supported_cpuid(s);
 187
 188     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 189     if (entry) {
 190         found = true;
 191         ret = cpuid_entry_get_reg(entry, reg);
 192     }
 193
 194     /* Fixups for the data returned by KVM, below */
 195
 196     if (function == 1 && reg == R_EDX) {
 197         /* KVM before 2.6.30 misreports the following features */
 198         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 199     } else if (function == 1 && reg == R_ECX) {
 200         /* We can set the hypervisor flag, even if KVM does not return it on
 201          * GET_SUPPORTED_CPUID
 202          */
 203         ret |= CPUID_EXT_HYPERVISOR;
 204         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 205          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 206          * and the irqchip is in the kernel.
 207          */
 208         if (kvm_irqchip_in_kernel() &&
 209                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 210             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 211         }
 212
 213         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 214          * without the in-kernel irqchip
 215          */
 216         if (!kvm_irqchip_in_kernel()) {
 217             ret &= ~CPUID_EXT_X2APIC;
 218         }
 219     } else if (function == 0x80000001 && reg == R_EDX) {
 220         /* On Intel, kvm returns cpuid according to the Intel spec,
 221          * so add missing bits according to the AMD spec:
 222          */
 223         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 224         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 225     }
 226
 227     g_free(cpuid);
 228
 229     /* fallback for older kernels */
 230     if ((function == KVM_CPUID_FEATURES) && !found) {
 231         ret = get_para_features(s);
 232     }
 233
 234     return ret;
 235 }
 236
 237 typedef struct HWPoisonPage {
 238     ram_addr_t ram_addr;
 239     QLIST_ENTRY(HWPoisonPage) list;
 240 } HWPoisonPage;
 241
 242 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 243     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 244
 245 static void kvm_unpoison_all(void *param)
 246 {
 247     HWPoisonPage *page, *next_page;
 248
 249     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 250         QLIST_REMOVE(page, list);
 251         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 252         g_free(page);
 253     }
 254 }
 255
 256 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 257 {
 258     HWPoisonPage *page;
 259
 260     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 261         if (page->ram_addr == ram_addr) {
 262             return;
 263         }
 264     }
 265     page = g_malloc(sizeof(HWPoisonPage));
 266     page->ram_addr = ram_addr;
 267     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 268 }
 269
 270 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 271                                      int *max_banks)
 272 {
 273     int r;
 274
 275     r = kvm_check_extension(s, KVM_CAP_MCE);
 276     if (r > 0) {
 277         *max_banks = r;
 278         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 279     }
 280     return -ENOSYS;
 281 }
 282
 283 static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code)
 284 {
 285     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 286                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 287     uint64_t mcg_status = MCG_STATUS_MCIP;
 288
 289     if (code == BUS_MCEERR_AR) {
 290         status |= MCI_STATUS_AR | 0x134;
 291         mcg_status |= MCG_STATUS_EIPV;
 292     } else {
 293         status |= 0xc0;
 294         mcg_status |= MCG_STATUS_RIPV;
 295     }
 296     cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr,
 297                        (MCM_ADDR_PHYS << 6) | 0xc,
 298                        cpu_x86_support_mca_broadcast(env) ?
 299                        MCE_INJECT_BROADCAST : 0);
 300 }
 301
 302 static void hardware_memory_error(void)
 303 {
 304     fprintf(stderr, "Hardware memory error!\n");
 305     exit(1);
 306 }
 307
 308 int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
 309 {
 310     ram_addr_t ram_addr;
 311     hwaddr paddr;
 312
 313     if ((env->mcg_cap & MCG_SER_P) && addr
 314         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 315         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 316             !kvm_physical_memory_addr_from_host(env->kvm_state, addr, &paddr)) {
 317             fprintf(stderr, "Hardware memory error for memory used by "
 318                     "QEMU itself instead of guest system!\n");
 319             /* Hope we are lucky for AO MCE */
 320             if (code == BUS_MCEERR_AO) {
 321                 return 0;
 322             } else {
 323                 hardware_memory_error();
 324             }
 325         }
 326         kvm_hwpoison_page_add(ram_addr);
 327         kvm_mce_inject(env, paddr, code);
 328     } else {
 329         if (code == BUS_MCEERR_AO) {
 330             return 0;
 331         } else if (code == BUS_MCEERR_AR) {
 332             hardware_memory_error();
 333         } else {
 334             return 1;
 335         }
 336     }
 337     return 0;
 338 }
 339
 340 int kvm_arch_on_sigbus(int code, void *addr)
 341 {
 342     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 343         ram_addr_t ram_addr;
 344         hwaddr paddr;
 345
 346         /* Hope we are lucky for AO MCE */
 347         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 348             !kvm_physical_memory_addr_from_host(first_cpu->kvm_state, addr,
 349                                                 &paddr)) {
 350             fprintf(stderr, "Hardware memory error for memory used by "
 351                     "QEMU itself instead of guest system!: %p\n", addr);
 352             return 0;
 353         }
 354         kvm_hwpoison_page_add(ram_addr);
 355         kvm_mce_inject(first_cpu, paddr, code);
 356     } else {
 357         if (code == BUS_MCEERR_AO) {
 358             return 0;
 359         } else if (code == BUS_MCEERR_AR) {
 360             hardware_memory_error();
 361         } else {
 362             return 1;
 363         }
 364     }
 365     return 0;
 366 }
 367
 368 static int kvm_inject_mce_oldstyle(CPUX86State *env)
 369 {
 370     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 371         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 372         struct kvm_x86_mce mce;
 373
 374         env->exception_injected = -1;
 375
 376         /*
 377          * There must be at least one bank in use if an MCE is pending.
 378          * Find it and use its values for the event injection.
 379          */
 380         for (bank = 0; bank < bank_num; bank++) {
 381             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 382                 break;
 383             }
 384         }
 385         assert(bank < bank_num);
 386
 387         mce.bank = bank;
 388         mce.status = env->mce_banks[bank * 4 + 1];
 389         mce.mcg_status = env->mcg_status;
 390         mce.addr = env->mce_banks[bank * 4 + 2];
 391         mce.misc = env->mce_banks[bank * 4 + 3];
 392
 393         return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, &mce);
 394     }
 395     return 0;
 396 }
 397
 398 static void cpu_update_state(void *opaque, int running, RunState state)
 399 {
 400     CPUX86State *env = opaque;
 401
 402     if (running) {
 403         env->tsc_valid = false;
 404     }
 405 }
 406
 407 int kvm_arch_init_vcpu(CPUX86State *env)
 408 {
 409     struct {
 410         struct kvm_cpuid2 cpuid;
 411         struct kvm_cpuid_entry2 entries[100];
 412     } QEMU_PACKED cpuid_data;
 413     KVMState *s = env->kvm_state;
 414     uint32_t limit, i, j, cpuid_i;
 415     uint32_t unused;
 416     struct kvm_cpuid_entry2 *c;
 417     uint32_t signature[3];
 418     int r;
 419
 420     env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 421
 422     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
 423
 424     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 425                                                              0, R_EDX);
 426     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001,
 427                                                              0, R_ECX);
 428     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(s, 0x8000000A,
 429                                                              0, R_EDX);
 430
 431     env->cpuid_kvm_features &=
 432             kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 433
 434     env->cpuid_ext4_features &= kvm_arch_get_supported_cpuid(s, 0xC0000001,
 435                                                              0, R_EDX);
 436
 437     cpuid_i = 0;
 438
 439     /* Paravirtualization CPUIDs */
 440     c = &cpuid_data.entries[cpuid_i++];
 441     memset(c, 0, sizeof(*c));
 442     c->function = KVM_CPUID_SIGNATURE;
 443     if (!hyperv_enabled()) {
 444         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 445         c->eax = 0;
 446     } else {
 447         memcpy(signature, "Microsoft Hv", 12);
 448         c->eax = HYPERV_CPUID_MIN;
 449     }
 450     c->ebx = signature[0];
 451     c->ecx = signature[1];
 452     c->edx = signature[2];
 453
 454     c = &cpuid_data.entries[cpuid_i++];
 455     memset(c, 0, sizeof(*c));
 456     c->function = KVM_CPUID_FEATURES;
 457     c->eax = env->cpuid_kvm_features;
 458
 459     if (hyperv_enabled()) {
 460         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 461         c->eax = signature[0];
 462
 463         c = &cpuid_data.entries[cpuid_i++];
 464         memset(c, 0, sizeof(*c));
 465         c->function = HYPERV_CPUID_VERSION;
 466         c->eax = 0x00001bbc;
 467         c->ebx = 0x00060001;
 468
 469         c = &cpuid_data.entries[cpuid_i++];
 470         memset(c, 0, sizeof(*c));
 471         c->function = HYPERV_CPUID_FEATURES;
 472         if (hyperv_relaxed_timing_enabled()) {
 473             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 474         }
 475         if (hyperv_vapic_recommended()) {
 476             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 477             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 478         }
 479
 480         c = &cpuid_data.entries[cpuid_i++];
 481         memset(c, 0, sizeof(*c));
 482         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 483         if (hyperv_relaxed_timing_enabled()) {
 484             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 485         }
 486         if (hyperv_vapic_recommended()) {
 487             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 488         }
 489         c->ebx = hyperv_get_spinlock_retries();
 490
 491         c = &cpuid_data.entries[cpuid_i++];
 492         memset(c, 0, sizeof(*c));
 493         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 494         c->eax = 0x40;
 495         c->ebx = 0x40;
 496
 497         c = &cpuid_data.entries[cpuid_i++];
 498         memset(c, 0, sizeof(*c));
 499         c->function = KVM_CPUID_SIGNATURE_NEXT;
 500         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 501         c->eax = 0;
 502         c->ebx = signature[0];
 503         c->ecx = signature[1];
 504         c->edx = signature[2];
 505     }
 506
 507     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 508
 509     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 510
 511     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 512
 513     for (i = 0; i <= limit; i++) {
 514         c = &cpuid_data.entries[cpuid_i++];
 515
 516         switch (i) {
 517         case 2: {
 518             /* Keep reading function 2 till all the input is received */
 519             int times;
 520
 521             c->function = i;
 522             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 523                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 524             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 525             times = c->eax & 0xff;
 526
 527             for (j = 1; j < times; ++j) {
 528                 c = &cpuid_data.entries[cpuid_i++];
 529                 c->function = i;
 530                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 531                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 532             }
 533             break;
 534         }
 535         case 4:
 536         case 0xb:
 537         case 0xd:
 538             for (j = 0; ; j++) {
 539                 if (i == 0xd && j == 64) {
 540                     break;
 541                 }
 542                 c->function = i;
 543                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 544                 c->index = j;
 545                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 546
 547                 if (i == 4 && c->eax == 0) {
 548                     break;
 549                 }
 550                 if (i == 0xb && !(c->ecx & 0xff00)) {
 551                     break;
 552                 }
 553                 if (i == 0xd && c->eax == 0) {
 554                     continue;
 555                 }
 556                 c = &cpuid_data.entries[cpuid_i++];
 557             }
 558             break;
 559         default:
 560             c->function = i;
 561             c->flags = 0;
 562             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 563             break;
 564         }
 565     }
 566     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 567
 568     for (i = 0x80000000; i <= limit; i++) {
 569         c = &cpuid_data.entries[cpuid_i++];
 570
 571         c->function = i;
 572         c->flags = 0;
 573         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 574     }
 575
 576     /* Call Centaur's CPUID instructions they are supported. */
 577     if (env->cpuid_xlevel2 > 0) {
 578         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 579
 580         for (i = 0xC0000000; i <= limit; i++) {
 581             c = &cpuid_data.entries[cpuid_i++];
 582
 583             c->function = i;
 584             c->flags = 0;
 585             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 586         }
 587     }
 588
 589     cpuid_data.cpuid.nent = cpuid_i;
 590
 591     if (((env->cpuid_version >> 8)&0xF) >= 6
 592         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 593         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 594         uint64_t mcg_cap;
 595         int banks;
 596         int ret;
 597
 598         ret = kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks);
 599         if (ret < 0) {
 600             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 601             return ret;
 602         }
 603
 604         if (banks > MCE_BANKS_DEF) {
 605             banks = MCE_BANKS_DEF;
 606         }
 607         mcg_cap &= MCE_CAP_DEF;
 608         mcg_cap |= banks;
 609         ret = kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, &mcg_cap);
 610         if (ret < 0) {
 611             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 612             return ret;
 613         }
 614
 615         env->mcg_cap = mcg_cap;
 616     }
 617
 618     qemu_add_vm_change_state_handler(cpu_update_state, env);
 619
 620     cpuid_data.cpuid.padding = 0;
 621     r = kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 622     if (r) {
 623         return r;
 624     }
 625
 626     r = kvm_check_extension(env->kvm_state, KVM_CAP_TSC_CONTROL);
 627     if (r && env->tsc_khz) {
 628         r = kvm_vcpu_ioctl(env, KVM_SET_TSC_KHZ, env->tsc_khz);
 629         if (r < 0) {
 630             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 631             return r;
 632         }
 633     }
 634
 635     if (kvm_has_xsave()) {
 636         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 637     }
 638
 639     return 0;
 640 }
 641
 642 void kvm_arch_reset_vcpu(CPUX86State *env)
 643 {
 644     X86CPU *cpu = x86_env_get_cpu(env);
 645
 646     env->exception_injected = -1;
 647     env->interrupt_injected = -1;
 648     env->xcr0 = 1;
 649     if (kvm_irqchip_in_kernel()) {
 650         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 651                                           KVM_MP_STATE_UNINITIALIZED;
 652     } else {
 653         env->mp_state = KVM_MP_STATE_RUNNABLE;
 654     }
 655 }
 656
 657 static int kvm_get_supported_msrs(KVMState *s)
 658 {
 659     static int kvm_supported_msrs;
 660     int ret = 0;
 661
 662     /* first time */
 663     if (kvm_supported_msrs == 0) {
 664         struct kvm_msr_list msr_list, *kvm_msr_list;
 665
 666         kvm_supported_msrs = -1;
 667
 668         /* Obtain MSR list from KVM.  These are the MSRs that we must
 669          * save/restore */
 670         msr_list.nmsrs = 0;
 671         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 672         if (ret < 0 && ret != -E2BIG) {
 673             return ret;
 674         }
 675         /* Old kernel modules had a bug and could write beyond the provided
 676            memory. Allocate at least a safe amount of 1K. */
 677         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 678                                               msr_list.nmsrs *
 679                                               sizeof(msr_list.indices[0])));
 680
 681         kvm_msr_list->nmsrs = msr_list.nmsrs;
 682         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 683         if (ret >= 0) {
 684             int i;
 685
 686             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 687                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 688                     has_msr_star = true;
 689                     continue;
 690                 }
 691                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 692                     has_msr_hsave_pa = true;
 693                     continue;
 694                 }
 695                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 696                     has_msr_tsc_deadline = true;
 697                     continue;
 698                 }
 699                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 700                     has_msr_misc_enable = true;
 701                     continue;
 702                 }
 703             }
 704         }
 705
 706         g_free(kvm_msr_list);
 707     }
 708
 709     return ret;
 710 }
 711
 712 int kvm_arch_init(KVMState *s)
 713 {
 714     QemuOptsList *list = qemu_find_opts("machine");
 715     uint64_t identity_base = 0xfffbc000;
 716     uint64_t shadow_mem;
 717     int ret;
 718     struct utsname utsname;
 719
 720     ret = kvm_get_supported_msrs(s);
 721     if (ret < 0) {
 722         return ret;
 723     }
 724
 725     uname(&utsname);
 726     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 727
 728     /*
 729      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 730      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 731      * Since these must be part of guest physical memory, we need to allocate
 732      * them, both by setting their start addresses in the kernel and by
 733      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 734      *
 735      * Older KVM versions may not support setting the identity map base. In
 736      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 737      * size.
 738      */
 739     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 740         /* Allows up to 16M BIOSes. */
 741         identity_base = 0xfeffc000;
 742
 743         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 744         if (ret < 0) {
 745             return ret;
 746         }
 747     }
 748
 749     /* Set TSS base one page after EPT identity map. */
 750     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 751     if (ret < 0) {
 752         return ret;
 753     }
 754
 755     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 756     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 757     if (ret < 0) {
 758         fprintf(stderr, "e820_add_entry() table is full\n");
 759         return ret;
 760     }
 761     qemu_register_reset(kvm_unpoison_all, NULL);
 762
 763     if (!QTAILQ_EMPTY(&list->head)) {
 764         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 765                                        "kvm_shadow_mem", -1);
 766         if (shadow_mem != -1) {
 767             shadow_mem /= 4096;
 768             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 769             if (ret < 0) {
 770                 return ret;
 771             }
 772         }
 773     }
 774     return 0;
 775 }
 776
 777 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 778 {
 779     lhs->selector = rhs->selector;
 780     lhs->base = rhs->base;
 781     lhs->limit = rhs->limit;
 782     lhs->type = 3;
 783     lhs->present = 1;
 784     lhs->dpl = 3;
 785     lhs->db = 0;
 786     lhs->s = 1;
 787     lhs->l = 0;
 788     lhs->g = 0;
 789     lhs->avl = 0;
 790     lhs->unusable = 0;
 791 }
 792
 793 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 794 {
 795     unsigned flags = rhs->flags;
 796     lhs->selector = rhs->selector;
 797     lhs->base = rhs->base;
 798     lhs->limit = rhs->limit;
 799     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 800     lhs->present = (flags & DESC_P_MASK) != 0;
 801     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 802     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 803     lhs->s = (flags & DESC_S_MASK) != 0;
 804     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 805     lhs->g = (flags & DESC_G_MASK) != 0;
 806     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 807     lhs->unusable = 0;
 808     lhs->padding = 0;
 809 }
 810
 811 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 812 {
 813     lhs->selector = rhs->selector;
 814     lhs->base = rhs->base;
 815     lhs->limit = rhs->limit;
 816     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 817                  (rhs->present * DESC_P_MASK) |
 818                  (rhs->dpl << DESC_DPL_SHIFT) |
 819                  (rhs->db << DESC_B_SHIFT) |
 820                  (rhs->s * DESC_S_MASK) |
 821                  (rhs->l << DESC_L_SHIFT) |
 822                  (rhs->g * DESC_G_MASK) |
 823                  (rhs->avl * DESC_AVL_MASK);
 824 }
 825
 826 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 827 {
 828     if (set) {
 829         *kvm_reg = *qemu_reg;
 830     } else {
 831         *qemu_reg = *kvm_reg;
 832     }
 833 }
 834
 835 static int kvm_getput_regs(CPUX86State *env, int set)
 836 {
 837     struct kvm_regs regs;
 838     int ret = 0;
 839
 840     if (!set) {
 841         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 842         if (ret < 0) {
 843             return ret;
 844         }
 845     }
 846
 847     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 848     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 849     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 850     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 851     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 852     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 853     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 854     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 855 #ifdef TARGET_X86_64
 856     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 857     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 858     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 859     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 860     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 861     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 862     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 863     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 864 #endif
 865
 866     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 867     kvm_getput_reg(&regs.rip, &env->eip, set);
 868
 869     if (set) {
 870         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 871     }
 872
 873     return ret;
 874 }
 875
 876 static int kvm_put_fpu(CPUX86State *env)
 877 {
 878     struct kvm_fpu fpu;
 879     int i;
 880
 881     memset(&fpu, 0, sizeof fpu);
 882     fpu.fsw = env->fpus & ~(7 << 11);
 883     fpu.fsw |= (env->fpstt & 7) << 11;
 884     fpu.fcw = env->fpuc;
 885     fpu.last_opcode = env->fpop;
 886     fpu.last_ip = env->fpip;
 887     fpu.last_dp = env->fpdp;
 888     for (i = 0; i < 8; ++i) {
 889         fpu.ftwx |= (!env->fptags[i]) << i;
 890     }
 891     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 892     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 893     fpu.mxcsr = env->mxcsr;
 894
 895     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 896 }
 897
 898 #define XSAVE_FCW_FSW     0
 899 #define XSAVE_FTW_FOP     1
 900 #define XSAVE_CWD_RIP     2
 901 #define XSAVE_CWD_RDP     4
 902 #define XSAVE_MXCSR       6
 903 #define XSAVE_ST_SPACE    8
 904 #define XSAVE_XMM_SPACE   40
 905 #define XSAVE_XSTATE_BV   128
 906 #define XSAVE_YMMH_SPACE  144
 907
 908 static int kvm_put_xsave(CPUX86State *env)
 909 {
 910     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 911     uint16_t cwd, swd, twd;
 912     int i, r;
 913
 914     if (!kvm_has_xsave()) {
 915         return kvm_put_fpu(env);
 916     }
 917
 918     memset(xsave, 0, sizeof(struct kvm_xsave));
 919     twd = 0;
 920     swd = env->fpus & ~(7 << 11);
 921     swd |= (env->fpstt & 7) << 11;
 922     cwd = env->fpuc;
 923     for (i = 0; i < 8; ++i) {
 924         twd |= (!env->fptags[i]) << i;
 925     }
 926     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 927     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 928     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 929     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 930     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 931             sizeof env->fpregs);
 932     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 933             sizeof env->xmm_regs);
 934     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 935     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 936     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 937             sizeof env->ymmh_regs);
 938     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 939     return r;
 940 }
 941
 942 static int kvm_put_xcrs(CPUX86State *env)
 943 {
 944     struct kvm_xcrs xcrs;
 945
 946     if (!kvm_has_xcrs()) {
 947         return 0;
 948     }
 949
 950     xcrs.nr_xcrs = 1;
 951     xcrs.flags = 0;
 952     xcrs.xcrs[0].xcr = 0;
 953     xcrs.xcrs[0].value = env->xcr0;
 954     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 955 }
 956
 957 static int kvm_put_sregs(CPUX86State *env)
 958 {
 959     struct kvm_sregs sregs;
 960
 961     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 962     if (env->interrupt_injected >= 0) {
 963         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 964                 (uint64_t)1 << (env->interrupt_injected % 64);
 965     }
 966
 967     if ((env->eflags & VM_MASK)) {
 968         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 969         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 970         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 971         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 972         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 973         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 974     } else {
 975         set_seg(&sregs.cs, &env->segs[R_CS]);
 976         set_seg(&sregs.ds, &env->segs[R_DS]);
 977         set_seg(&sregs.es, &env->segs[R_ES]);
 978         set_seg(&sregs.fs, &env->segs[R_FS]);
 979         set_seg(&sregs.gs, &env->segs[R_GS]);
 980         set_seg(&sregs.ss, &env->segs[R_SS]);
 981     }
 982
 983     set_seg(&sregs.tr, &env->tr);
 984     set_seg(&sregs.ldt, &env->ldt);
 985
 986     sregs.idt.limit = env->idt.limit;
 987     sregs.idt.base = env->idt.base;
 988     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 989     sregs.gdt.limit = env->gdt.limit;
 990     sregs.gdt.base = env->gdt.base;
 991     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 992
 993     sregs.cr0 = env->cr[0];
 994     sregs.cr2 = env->cr[2];
 995     sregs.cr3 = env->cr[3];
 996     sregs.cr4 = env->cr[4];
 997
 998     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 999     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1000
1001     sregs.efer = env->efer;
1002
1003     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
1004 }
1005
1006 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1007                               uint32_t index, uint64_t value)
1008 {
1009     entry->index = index;
1010     entry->data = value;
1011 }
1012
1013 static int kvm_put_msrs(CPUX86State *env, int level)
1014 {
1015     struct {
1016         struct kvm_msrs info;
1017         struct kvm_msr_entry entries[100];
1018     } msr_data;
1019     struct kvm_msr_entry *msrs = msr_data.entries;
1020     int n = 0;
1021
1022     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1023     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1024     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1025     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1026     if (has_msr_star) {
1027         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1028     }
1029     if (has_msr_hsave_pa) {
1030         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1031     }
1032     if (has_msr_tsc_deadline) {
1033         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1034     }
1035     if (has_msr_misc_enable) {
1036         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1037                           env->msr_ia32_misc_enable);
1038     }
1039 #ifdef TARGET_X86_64
1040     if (lm_capable_kernel) {
1041         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1042         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1043         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1044         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1045     }
1046 #endif
1047     if (level == KVM_PUT_FULL_STATE) {
1048         /*
1049          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1050          * writeback. Until this is fixed, we only write the offset to SMP
1051          * guests after migration, desynchronizing the VCPUs, but avoiding
1052          * huge jump-backs that would occur without any writeback at all.
1053          */
1054         if (smp_cpus == 1 || env->tsc != 0) {
1055             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1056         }
1057     }
1058     /*
1059      * The following paravirtual MSRs have side effects on the guest or are
1060      * too heavy for normal writeback. Limit them to reset or full state
1061      * updates.
1062      */
1063     if (level >= KVM_PUT_RESET_STATE) {
1064         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1065                           env->system_time_msr);
1066         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1067         if (has_msr_async_pf_en) {
1068             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1069                               env->async_pf_en_msr);
1070         }
1071         if (has_msr_pv_eoi_en) {
1072             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1073                               env->pv_eoi_en_msr);
1074         }
1075         if (hyperv_hypercall_available()) {
1076             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1077             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1078         }
1079         if (hyperv_vapic_recommended()) {
1080             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1081         }
1082     }
1083     if (env->mcg_cap) {
1084         int i;
1085
1086         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1087         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1088         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1089             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1090         }
1091     }
1092
1093     msr_data.info.nmsrs = n;
1094
1095     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
1096
1097 }
1098
1099
1100 static int kvm_get_fpu(CPUX86State *env)
1101 {
1102     struct kvm_fpu fpu;
1103     int i, ret;
1104
1105     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
1106     if (ret < 0) {
1107         return ret;
1108     }
1109
1110     env->fpstt = (fpu.fsw >> 11) & 7;
1111     env->fpus = fpu.fsw;
1112     env->fpuc = fpu.fcw;
1113     env->fpop = fpu.last_opcode;
1114     env->fpip = fpu.last_ip;
1115     env->fpdp = fpu.last_dp;
1116     for (i = 0; i < 8; ++i) {
1117         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1118     }
1119     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1120     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1121     env->mxcsr = fpu.mxcsr;
1122
1123     return 0;
1124 }
1125
1126 static int kvm_get_xsave(CPUX86State *env)
1127 {
1128     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1129     int ret, i;
1130     uint16_t cwd, swd, twd;
1131
1132     if (!kvm_has_xsave()) {
1133         return kvm_get_fpu(env);
1134     }
1135
1136     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
1137     if (ret < 0) {
1138         return ret;
1139     }
1140
1141     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1142     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1143     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1144     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1145     env->fpstt = (swd >> 11) & 7;
1146     env->fpus = swd;
1147     env->fpuc = cwd;
1148     for (i = 0; i < 8; ++i) {
1149         env->fptags[i] = !((twd >> i) & 1);
1150     }
1151     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1152     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1153     env->mxcsr = xsave->region[XSAVE_MXCSR];
1154     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1155             sizeof env->fpregs);
1156     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1157             sizeof env->xmm_regs);
1158     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1159     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1160             sizeof env->ymmh_regs);
1161     return 0;
1162 }
1163
1164 static int kvm_get_xcrs(CPUX86State *env)
1165 {
1166     int i, ret;
1167     struct kvm_xcrs xcrs;
1168
1169     if (!kvm_has_xcrs()) {
1170         return 0;
1171     }
1172
1173     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
1174     if (ret < 0) {
1175         return ret;
1176     }
1177
1178     for (i = 0; i < xcrs.nr_xcrs; i++) {
1179         /* Only support xcr0 now */
1180         if (xcrs.xcrs[0].xcr == 0) {
1181             env->xcr0 = xcrs.xcrs[0].value;
1182             break;
1183         }
1184     }
1185     return 0;
1186 }
1187
1188 static int kvm_get_sregs(CPUX86State *env)
1189 {
1190     struct kvm_sregs sregs;
1191     uint32_t hflags;
1192     int bit, i, ret;
1193
1194     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
1195     if (ret < 0) {
1196         return ret;
1197     }
1198
1199     /* There can only be one pending IRQ set in the bitmap at a time, so try
1200        to find it and save its number instead (-1 for none). */
1201     env->interrupt_injected = -1;
1202     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1203         if (sregs.interrupt_bitmap[i]) {
1204             bit = ctz64(sregs.interrupt_bitmap[i]);
1205             env->interrupt_injected = i * 64 + bit;
1206             break;
1207         }
1208     }
1209
1210     get_seg(&env->segs[R_CS], &sregs.cs);
1211     get_seg(&env->segs[R_DS], &sregs.ds);
1212     get_seg(&env->segs[R_ES], &sregs.es);
1213     get_seg(&env->segs[R_FS], &sregs.fs);
1214     get_seg(&env->segs[R_GS], &sregs.gs);
1215     get_seg(&env->segs[R_SS], &sregs.ss);
1216
1217     get_seg(&env->tr, &sregs.tr);
1218     get_seg(&env->ldt, &sregs.ldt);
1219
1220     env->idt.limit = sregs.idt.limit;
1221     env->idt.base = sregs.idt.base;
1222     env->gdt.limit = sregs.gdt.limit;
1223     env->gdt.base = sregs.gdt.base;
1224
1225     env->cr[0] = sregs.cr0;
1226     env->cr[2] = sregs.cr2;
1227     env->cr[3] = sregs.cr3;
1228     env->cr[4] = sregs.cr4;
1229
1230     env->efer = sregs.efer;
1231
1232     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1233
1234 #define HFLAG_COPY_MASK \
1235     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1236        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1237        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1238        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1239
1240     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1241     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1242     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1243                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1244     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1245     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1246                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1247
1248     if (env->efer & MSR_EFER_LMA) {
1249         hflags |= HF_LMA_MASK;
1250     }
1251
1252     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1253         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1254     } else {
1255         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1256                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1257         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1258                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1259         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1260             !(hflags & HF_CS32_MASK)) {
1261             hflags |= HF_ADDSEG_MASK;
1262         } else {
1263             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1264                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1265         }
1266     }
1267     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1268
1269     return 0;
1270 }
1271
1272 static int kvm_get_msrs(CPUX86State *env)
1273 {
1274     struct {
1275         struct kvm_msrs info;
1276         struct kvm_msr_entry entries[100];
1277     } msr_data;
1278     struct kvm_msr_entry *msrs = msr_data.entries;
1279     int ret, i, n;
1280
1281     n = 0;
1282     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1283     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1284     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1285     msrs[n++].index = MSR_PAT;
1286     if (has_msr_star) {
1287         msrs[n++].index = MSR_STAR;
1288     }
1289     if (has_msr_hsave_pa) {
1290         msrs[n++].index = MSR_VM_HSAVE_PA;
1291     }
1292     if (has_msr_tsc_deadline) {
1293         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1294     }
1295     if (has_msr_misc_enable) {
1296         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1297     }
1298
1299     if (!env->tsc_valid) {
1300         msrs[n++].index = MSR_IA32_TSC;
1301         env->tsc_valid = !runstate_is_running();
1302     }
1303
1304 #ifdef TARGET_X86_64
1305     if (lm_capable_kernel) {
1306         msrs[n++].index = MSR_CSTAR;
1307         msrs[n++].index = MSR_KERNELGSBASE;
1308         msrs[n++].index = MSR_FMASK;
1309         msrs[n++].index = MSR_LSTAR;
1310     }
1311 #endif
1312     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1313     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1314     if (has_msr_async_pf_en) {
1315         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1316     }
1317     if (has_msr_pv_eoi_en) {
1318         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1319     }
1320
1321     if (env->mcg_cap) {
1322         msrs[n++].index = MSR_MCG_STATUS;
1323         msrs[n++].index = MSR_MCG_CTL;
1324         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1325             msrs[n++].index = MSR_MC0_CTL + i;
1326         }
1327     }
1328
1329     msr_data.info.nmsrs = n;
1330     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1331     if (ret < 0) {
1332         return ret;
1333     }
1334
1335     for (i = 0; i < ret; i++) {
1336         switch (msrs[i].index) {
1337         case MSR_IA32_SYSENTER_CS:
1338             env->sysenter_cs = msrs[i].data;
1339             break;
1340         case MSR_IA32_SYSENTER_ESP:
1341             env->sysenter_esp = msrs[i].data;
1342             break;
1343         case MSR_IA32_SYSENTER_EIP:
1344             env->sysenter_eip = msrs[i].data;
1345             break;
1346         case MSR_PAT:
1347             env->pat = msrs[i].data;
1348             break;
1349         case MSR_STAR:
1350             env->star = msrs[i].data;
1351             break;
1352 #ifdef TARGET_X86_64
1353         case MSR_CSTAR:
1354             env->cstar = msrs[i].data;
1355             break;
1356         case MSR_KERNELGSBASE:
1357             env->kernelgsbase = msrs[i].data;
1358             break;
1359         case MSR_FMASK:
1360             env->fmask = msrs[i].data;
1361             break;
1362         case MSR_LSTAR:
1363             env->lstar = msrs[i].data;
1364             break;
1365 #endif
1366         case MSR_IA32_TSC:
1367             env->tsc = msrs[i].data;
1368             break;
1369         case MSR_IA32_TSCDEADLINE:
1370             env->tsc_deadline = msrs[i].data;
1371             break;
1372         case MSR_VM_HSAVE_PA:
1373             env->vm_hsave = msrs[i].data;
1374             break;
1375         case MSR_KVM_SYSTEM_TIME:
1376             env->system_time_msr = msrs[i].data;
1377             break;
1378         case MSR_KVM_WALL_CLOCK:
1379             env->wall_clock_msr = msrs[i].data;
1380             break;
1381         case MSR_MCG_STATUS:
1382             env->mcg_status = msrs[i].data;
1383             break;
1384         case MSR_MCG_CTL:
1385             env->mcg_ctl = msrs[i].data;
1386             break;
1387         case MSR_IA32_MISC_ENABLE:
1388             env->msr_ia32_misc_enable = msrs[i].data;
1389             break;
1390         default:
1391             if (msrs[i].index >= MSR_MC0_CTL &&
1392                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1393                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1394             }
1395             break;
1396         case MSR_KVM_ASYNC_PF_EN:
1397             env->async_pf_en_msr = msrs[i].data;
1398             break;
1399         case MSR_KVM_PV_EOI_EN:
1400             env->pv_eoi_en_msr = msrs[i].data;
1401             break;
1402         }
1403     }
1404
1405     return 0;
1406 }
1407
1408 static int kvm_put_mp_state(CPUX86State *env)
1409 {
1410     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1411
1412     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1413 }
1414
1415 static int kvm_get_mp_state(CPUX86State *env)
1416 {
1417     struct kvm_mp_state mp_state;
1418     int ret;
1419
1420     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1421     if (ret < 0) {
1422         return ret;
1423     }
1424     env->mp_state = mp_state.mp_state;
1425     if (kvm_irqchip_in_kernel()) {
1426         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1427     }
1428     return 0;
1429 }
1430
1431 static int kvm_get_apic(CPUX86State *env)
1432 {
1433     DeviceState *apic = env->apic_state;
1434     struct kvm_lapic_state kapic;
1435     int ret;
1436
1437     if (apic && kvm_irqchip_in_kernel()) {
1438         ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
1439         if (ret < 0) {
1440             return ret;
1441         }
1442
1443         kvm_get_apic_state(apic, &kapic);
1444     }
1445     return 0;
1446 }
1447
1448 static int kvm_put_apic(CPUX86State *env)
1449 {
1450     DeviceState *apic = env->apic_state;
1451     struct kvm_lapic_state kapic;
1452
1453     if (apic && kvm_irqchip_in_kernel()) {
1454         kvm_put_apic_state(apic, &kapic);
1455
1456         return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
1457     }
1458     return 0;
1459 }
1460
1461 static int kvm_put_vcpu_events(CPUX86State *env, int level)
1462 {
1463     struct kvm_vcpu_events events;
1464
1465     if (!kvm_has_vcpu_events()) {
1466         return 0;
1467     }
1468
1469     events.exception.injected = (env->exception_injected >= 0);
1470     events.exception.nr = env->exception_injected;
1471     events.exception.has_error_code = env->has_error_code;
1472     events.exception.error_code = env->error_code;
1473     events.exception.pad = 0;
1474
1475     events.interrupt.injected = (env->interrupt_injected >= 0);
1476     events.interrupt.nr = env->interrupt_injected;
1477     events.interrupt.soft = env->soft_interrupt;
1478
1479     events.nmi.injected = env->nmi_injected;
1480     events.nmi.pending = env->nmi_pending;
1481     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1482     events.nmi.pad = 0;
1483
1484     events.sipi_vector = env->sipi_vector;
1485
1486     events.flags = 0;
1487     if (level >= KVM_PUT_RESET_STATE) {
1488         events.flags |=
1489             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1490     }
1491
1492     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1493 }
1494
1495 static int kvm_get_vcpu_events(CPUX86State *env)
1496 {
1497     struct kvm_vcpu_events events;
1498     int ret;
1499
1500     if (!kvm_has_vcpu_events()) {
1501         return 0;
1502     }
1503
1504     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1505     if (ret < 0) {
1506        return ret;
1507     }
1508     env->exception_injected =
1509        events.exception.injected ? events.exception.nr : -1;
1510     env->has_error_code = events.exception.has_error_code;
1511     env->error_code = events.exception.error_code;
1512
1513     env->interrupt_injected =
1514         events.interrupt.injected ? events.interrupt.nr : -1;
1515     env->soft_interrupt = events.interrupt.soft;
1516
1517     env->nmi_injected = events.nmi.injected;
1518     env->nmi_pending = events.nmi.pending;
1519     if (events.nmi.masked) {
1520         env->hflags2 |= HF2_NMI_MASK;
1521     } else {
1522         env->hflags2 &= ~HF2_NMI_MASK;
1523     }
1524
1525     env->sipi_vector = events.sipi_vector;
1526
1527     return 0;
1528 }
1529
1530 static int kvm_guest_debug_workarounds(CPUX86State *env)
1531 {
1532     int ret = 0;
1533     unsigned long reinject_trap = 0;
1534
1535     if (!kvm_has_vcpu_events()) {
1536         if (env->exception_injected == 1) {
1537             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1538         } else if (env->exception_injected == 3) {
1539             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1540         }
1541         env->exception_injected = -1;
1542     }
1543
1544     /*
1545      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1546      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1547      * by updating the debug state once again if single-stepping is on.
1548      * Another reason to call kvm_update_guest_debug here is a pending debug
1549      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1550      * reinject them via SET_GUEST_DEBUG.
1551      */
1552     if (reinject_trap ||
1553         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1554         ret = kvm_update_guest_debug(env, reinject_trap);
1555     }
1556     return ret;
1557 }
1558
1559 static int kvm_put_debugregs(CPUX86State *env)
1560 {
1561     struct kvm_debugregs dbgregs;
1562     int i;
1563
1564     if (!kvm_has_debugregs()) {
1565         return 0;
1566     }
1567
1568     for (i = 0; i < 4; i++) {
1569         dbgregs.db[i] = env->dr[i];
1570     }
1571     dbgregs.dr6 = env->dr[6];
1572     dbgregs.dr7 = env->dr[7];
1573     dbgregs.flags = 0;
1574
1575     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1576 }
1577
1578 static int kvm_get_debugregs(CPUX86State *env)
1579 {
1580     struct kvm_debugregs dbgregs;
1581     int i, ret;
1582
1583     if (!kvm_has_debugregs()) {
1584         return 0;
1585     }
1586
1587     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1588     if (ret < 0) {
1589         return ret;
1590     }
1591     for (i = 0; i < 4; i++) {
1592         env->dr[i] = dbgregs.db[i];
1593     }
1594     env->dr[4] = env->dr[6] = dbgregs.dr6;
1595     env->dr[5] = env->dr[7] = dbgregs.dr7;
1596
1597     return 0;
1598 }
1599
1600 int kvm_arch_put_registers(CPUX86State *env, int level)
1601 {
1602     int ret;
1603
1604     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1605
1606     ret = kvm_getput_regs(env, 1);
1607     if (ret < 0) {
1608         return ret;
1609     }
1610     ret = kvm_put_xsave(env);
1611     if (ret < 0) {
1612         return ret;
1613     }
1614     ret = kvm_put_xcrs(env);
1615     if (ret < 0) {
1616         return ret;
1617     }
1618     ret = kvm_put_sregs(env);
1619     if (ret < 0) {
1620         return ret;
1621     }
1622     /* must be before kvm_put_msrs */
1623     ret = kvm_inject_mce_oldstyle(env);
1624     if (ret < 0) {
1625         return ret;
1626     }
1627     ret = kvm_put_msrs(env, level);
1628     if (ret < 0) {
1629         return ret;
1630     }
1631     if (level >= KVM_PUT_RESET_STATE) {
1632         ret = kvm_put_mp_state(env);
1633         if (ret < 0) {
1634             return ret;
1635         }
1636         ret = kvm_put_apic(env);
1637         if (ret < 0) {
1638             return ret;
1639         }
1640     }
1641     ret = kvm_put_vcpu_events(env, level);
1642     if (ret < 0) {
1643         return ret;
1644     }
1645     ret = kvm_put_debugregs(env);
1646     if (ret < 0) {
1647         return ret;
1648     }
1649     /* must be last */
1650     ret = kvm_guest_debug_workarounds(env);
1651     if (ret < 0) {
1652         return ret;
1653     }
1654     return 0;
1655 }
1656
1657 int kvm_arch_get_registers(CPUX86State *env)
1658 {
1659     int ret;
1660
1661     assert(cpu_is_stopped(env) || qemu_cpu_is_self(env));
1662
1663     ret = kvm_getput_regs(env, 0);
1664     if (ret < 0) {
1665         return ret;
1666     }
1667     ret = kvm_get_xsave(env);
1668     if (ret < 0) {
1669         return ret;
1670     }
1671     ret = kvm_get_xcrs(env);
1672     if (ret < 0) {
1673         return ret;
1674     }
1675     ret = kvm_get_sregs(env);
1676     if (ret < 0) {
1677         return ret;
1678     }
1679     ret = kvm_get_msrs(env);
1680     if (ret < 0) {
1681         return ret;
1682     }
1683     ret = kvm_get_mp_state(env);
1684     if (ret < 0) {
1685         return ret;
1686     }
1687     ret = kvm_get_apic(env);
1688     if (ret < 0) {
1689         return ret;
1690     }
1691     ret = kvm_get_vcpu_events(env);
1692     if (ret < 0) {
1693         return ret;
1694     }
1695     ret = kvm_get_debugregs(env);
1696     if (ret < 0) {
1697         return ret;
1698     }
1699     return 0;
1700 }
1701
1702 void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
1703 {
1704     int ret;
1705
1706     /* Inject NMI */
1707     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1708         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1709         DPRINTF("injected NMI\n");
1710         ret = kvm_vcpu_ioctl(env, KVM_NMI);
1711         if (ret < 0) {
1712             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1713                     strerror(-ret));
1714         }
1715     }
1716
1717     if (!kvm_irqchip_in_kernel()) {
1718         /* Force the VCPU out of its inner loop to process any INIT requests
1719          * or pending TPR access reports. */
1720         if (env->interrupt_request &
1721             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1722             env->exit_request = 1;
1723         }
1724
1725         /* Try to inject an interrupt if the guest can accept it */
1726         if (run->ready_for_interrupt_injection &&
1727             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1728             (env->eflags & IF_MASK)) {
1729             int irq;
1730
1731             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1732             irq = cpu_get_pic_interrupt(env);
1733             if (irq >= 0) {
1734                 struct kvm_interrupt intr;
1735
1736                 intr.irq = irq;
1737                 DPRINTF("injected interrupt %d\n", irq);
1738                 ret = kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1739                 if (ret < 0) {
1740                     fprintf(stderr,
1741                             "KVM: injection failed, interrupt lost (%s)\n",
1742                             strerror(-ret));
1743                 }
1744             }
1745         }
1746
1747         /* If we have an interrupt but the guest is not ready to receive an
1748          * interrupt, request an interrupt window exit.  This will
1749          * cause a return to userspace as soon as the guest is ready to
1750          * receive interrupts. */
1751         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1752             run->request_interrupt_window = 1;
1753         } else {
1754             run->request_interrupt_window = 0;
1755         }
1756
1757         DPRINTF("setting tpr\n");
1758         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1759     }
1760 }
1761
1762 void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
1763 {
1764     if (run->if_flag) {
1765         env->eflags |= IF_MASK;
1766     } else {
1767         env->eflags &= ~IF_MASK;
1768     }
1769     cpu_set_apic_tpr(env->apic_state, run->cr8);
1770     cpu_set_apic_base(env->apic_state, run->apic_base);
1771 }
1772
1773 int kvm_arch_process_async_events(CPUX86State *env)
1774 {
1775     X86CPU *cpu = x86_env_get_cpu(env);
1776
1777     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1778         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1779         assert(env->mcg_cap);
1780
1781         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1782
1783         kvm_cpu_synchronize_state(env);
1784
1785         if (env->exception_injected == EXCP08_DBLE) {
1786             /* this means triple fault */
1787             qemu_system_reset_request();
1788             env->exit_request = 1;
1789             return 0;
1790         }
1791         env->exception_injected = EXCP12_MCHK;
1792         env->has_error_code = 0;
1793
1794         env->halted = 0;
1795         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1796             env->mp_state = KVM_MP_STATE_RUNNABLE;
1797         }
1798     }
1799
1800     if (kvm_irqchip_in_kernel()) {
1801         return 0;
1802     }
1803
1804     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1805         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1806         apic_poll_irq(env->apic_state);
1807     }
1808     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1809          (env->eflags & IF_MASK)) ||
1810         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1811         env->halted = 0;
1812     }
1813     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1814         kvm_cpu_synchronize_state(env);
1815         do_cpu_init(cpu);
1816     }
1817     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1818         kvm_cpu_synchronize_state(env);
1819         do_cpu_sipi(cpu);
1820     }
1821     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1822         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1823         kvm_cpu_synchronize_state(env);
1824         apic_handle_tpr_access_report(env->apic_state, env->eip,
1825                                       env->tpr_access_type);
1826     }
1827
1828     return env->halted;
1829 }
1830
1831 static int kvm_handle_halt(CPUX86State *env)
1832 {
1833     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1834           (env->eflags & IF_MASK)) &&
1835         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1836         env->halted = 1;
1837         return EXCP_HLT;
1838     }
1839
1840     return 0;
1841 }
1842
1843 static int kvm_handle_tpr_access(CPUX86State *env)
1844 {
1845     struct kvm_run *run = env->kvm_run;
1846
1847     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1848                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1849                                                            : TPR_ACCESS_READ);
1850     return 1;
1851 }
1852
1853 int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1854 {
1855     static const uint8_t int3 = 0xcc;
1856
1857     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1858         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1859         return -EINVAL;
1860     }
1861     return 0;
1862 }
1863
1864 int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
1865 {
1866     uint8_t int3;
1867
1868     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1869         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1870         return -EINVAL;
1871     }
1872     return 0;
1873 }
1874
1875 static struct {
1876     target_ulong addr;
1877     int len;
1878     int type;
1879 } hw_breakpoint[4];
1880
1881 static int nb_hw_breakpoint;
1882
1883 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1884 {
1885     int n;
1886
1887     for (n = 0; n < nb_hw_breakpoint; n++) {
1888         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1889             (hw_breakpoint[n].len == len || len == -1)) {
1890             return n;
1891         }
1892     }
1893     return -1;
1894 }
1895
1896 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1897                                   target_ulong len, int type)
1898 {
1899     switch (type) {
1900     case GDB_BREAKPOINT_HW:
1901         len = 1;
1902         break;
1903     case GDB_WATCHPOINT_WRITE:
1904     case GDB_WATCHPOINT_ACCESS:
1905         switch (len) {
1906         case 1:
1907             break;
1908         case 2:
1909         case 4:
1910         case 8:
1911             if (addr & (len - 1)) {
1912                 return -EINVAL;
1913             }
1914             break;
1915         default:
1916             return -EINVAL;
1917         }
1918         break;
1919     default:
1920         return -ENOSYS;
1921     }
1922
1923     if (nb_hw_breakpoint == 4) {
1924         return -ENOBUFS;
1925     }
1926     if (find_hw_breakpoint(addr, len, type) >= 0) {
1927         return -EEXIST;
1928     }
1929     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1930     hw_breakpoint[nb_hw_breakpoint].len = len;
1931     hw_breakpoint[nb_hw_breakpoint].type = type;
1932     nb_hw_breakpoint++;
1933
1934     return 0;
1935 }
1936
1937 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1938                                   target_ulong len, int type)
1939 {
1940     int n;
1941
1942     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1943     if (n < 0) {
1944         return -ENOENT;
1945     }
1946     nb_hw_breakpoint--;
1947     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1948
1949     return 0;
1950 }
1951
1952 void kvm_arch_remove_all_hw_breakpoints(void)
1953 {
1954     nb_hw_breakpoint = 0;
1955 }
1956
1957 static CPUWatchpoint hw_watchpoint;
1958
1959 static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
1960 {
1961     int ret = 0;
1962     int n;
1963
1964     if (arch_info->exception == 1) {
1965         if (arch_info->dr6 & (1 << 14)) {
1966             if (cpu_single_env->singlestep_enabled) {
1967                 ret = EXCP_DEBUG;
1968             }
1969         } else {
1970             for (n = 0; n < 4; n++) {
1971                 if (arch_info->dr6 & (1 << n)) {
1972                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1973                     case 0x0:
1974                         ret = EXCP_DEBUG;
1975                         break;
1976                     case 0x1:
1977                         ret = EXCP_DEBUG;
1978                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1979                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1980                         hw_watchpoint.flags = BP_MEM_WRITE;
1981                         break;
1982                     case 0x3:
1983                         ret = EXCP_DEBUG;
1984                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1985                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1986                         hw_watchpoint.flags = BP_MEM_ACCESS;
1987                         break;
1988                     }
1989                 }
1990             }
1991         }
1992     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1993         ret = EXCP_DEBUG;
1994     }
1995     if (ret == 0) {
1996         cpu_synchronize_state(cpu_single_env);
1997         assert(cpu_single_env->exception_injected == -1);
1998
1999         /* pass to guest */
2000         cpu_single_env->exception_injected = arch_info->exception;
2001         cpu_single_env->has_error_code = 0;
2002     }
2003
2004     return ret;
2005 }
2006
2007 void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
2008 {
2009     const uint8_t type_code[] = {
2010         [GDB_BREAKPOINT_HW] = 0x0,
2011         [GDB_WATCHPOINT_WRITE] = 0x1,
2012         [GDB_WATCHPOINT_ACCESS] = 0x3
2013     };
2014     const uint8_t len_code[] = {
2015         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2016     };
2017     int n;
2018
2019     if (kvm_sw_breakpoints_active(env)) {
2020         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2021     }
2022     if (nb_hw_breakpoint > 0) {
2023         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2024         dbg->arch.debugreg[7] = 0x0600;
2025         for (n = 0; n < nb_hw_breakpoint; n++) {
2026             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2027             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2028                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2029                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2030         }
2031     }
2032 }
2033
2034 static bool host_supports_vmx(void)
2035 {
2036     uint32_t ecx, unused;
2037
2038     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2039     return ecx & CPUID_EXT_VMX;
2040 }
2041
2042 #define VMX_INVALID_GUEST_STATE 0x80000021
2043
2044 int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
2045 {
2046     uint64_t code;
2047     int ret;
2048
2049     switch (run->exit_reason) {
2050     case KVM_EXIT_HLT:
2051         DPRINTF("handle_hlt\n");
2052         ret = kvm_handle_halt(env);
2053         break;
2054     case KVM_EXIT_SET_TPR:
2055         ret = 0;
2056         break;
2057     case KVM_EXIT_TPR_ACCESS:
2058         ret = kvm_handle_tpr_access(env);
2059         break;
2060     case KVM_EXIT_FAIL_ENTRY:
2061         code = run->fail_entry.hardware_entry_failure_reason;
2062         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2063                 code);
2064         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2065             fprintf(stderr,
2066                     "\nIf you're running a guest on an Intel machine without "
2067                         "unrestricted mode\n"
2068                     "support, the failure can be most likely due to the guest "
2069                         "entering an invalid\n"
2070                     "state for Intel VT. For example, the guest maybe running "
2071                         "in big real mode\n"
2072                     "which is not supported on less recent Intel processors."
2073                         "\n\n");
2074         }
2075         ret = -1;
2076         break;
2077     case KVM_EXIT_EXCEPTION:
2078         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2079                 run->ex.exception, run->ex.error_code);
2080         ret = -1;
2081         break;
2082     case KVM_EXIT_DEBUG:
2083         DPRINTF("kvm_exit_debug\n");
2084         ret = kvm_handle_debug(&run->debug.arch);
2085         break;
2086     default:
2087         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2088         ret = -1;
2089         break;
2090     }
2091
2092     return ret;
2093 }
2094
2095 bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
2096 {
2097     kvm_cpu_synchronize_state(env);
2098     return !(env->cr[0] & CR0_PE_MASK) ||
2099            ((env->segs[R_CS].selector  & 3) != 3);
2100 }
2101
2102 void kvm_arch_init_irq_routing(KVMState *s)
2103 {
2104     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2105         /* If kernel can't do irq routing, interrupt source
2106          * override 0->2 cannot be set up as required by HPET.
2107          * So we have to disable it.
2108          */
2109         no_hpet = 1;
2110     }
2111     /* We know at this point that we're using the in-kernel
2112      * irqchip, so we can use irqfds, and on x86 we know
2113      * we can use msi via irqfd and GSI routing.
2114      */
2115     kvm_irqfds_allowed = true;
2116     kvm_msi_via_irqfd_allowed = true;
2117     kvm_gsi_routing_allowed = true;
2118 }
2119
2120 /* Classic KVM device assignment interface. Will remain x86 only. */
2121 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2122                           uint32_t flags, uint32_t *dev_id)
2123 {
2124     struct kvm_assigned_pci_dev dev_data = {
2125         .segnr = dev_addr->domain,
2126         .busnr = dev_addr->bus,
2127         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2128         .flags = flags,
2129     };
2130     int ret;
2131
2132     dev_data.assigned_dev_id =
2133         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2134
2135     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2136     if (ret < 0) {
2137         return ret;
2138     }
2139
2140     *dev_id = dev_data.assigned_dev_id;
2141
2142     return 0;
2143 }
2144
2145 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2146 {
2147     struct kvm_assigned_pci_dev dev_data = {
2148         .assigned_dev_id = dev_id,
2149     };
2150
2151     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2152 }
2153
2154 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2155                                    uint32_t irq_type, uint32_t guest_irq)
2156 {
2157     struct kvm_assigned_irq assigned_irq = {
2158         .assigned_dev_id = dev_id,
2159         .guest_irq = guest_irq,
2160         .flags = irq_type,
2161     };
2162
2163     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2164         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2165     } else {
2166         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2167     }
2168 }
2169
2170 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2171                            uint32_t guest_irq)
2172 {
2173     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2174         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2175
2176     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2177 }
2178
2179 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2180 {
2181     struct kvm_assigned_pci_dev dev_data = {
2182         .assigned_dev_id = dev_id,
2183         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2184     };
2185
2186     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2187 }
2188
2189 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2190                                      uint32_t type)
2191 {
2192     struct kvm_assigned_irq assigned_irq = {
2193         .assigned_dev_id = dev_id,
2194         .flags = type,
2195     };
2196
2197     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2198 }
2199
2200 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2201 {
2202     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2203         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2204 }
2205
2206 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2207 {
2208     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2209                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2210 }
2211
2212 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2213 {
2214     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2215                                                 KVM_DEV_IRQ_HOST_MSI);
2216 }
2217
2218 bool kvm_device_msix_supported(KVMState *s)
2219 {
2220     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2221      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2222     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2223 }
2224
2225 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2226                                  uint32_t nr_vectors)
2227 {
2228     struct kvm_assigned_msix_nr msix_nr = {
2229         .assigned_dev_id = dev_id,
2230         .entry_nr = nr_vectors,
2231     };
2232
2233     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2234 }
2235
2236 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2237                                int virq)
2238 {
2239     struct kvm_assigned_msix_entry msix_entry = {
2240         .assigned_dev_id = dev_id,
2241         .gsi = virq,
2242         .entry = vector,
2243     };
2244
2245     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2246 }
2247
2248 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2249 {
2250     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2251                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2252 }
2253
2254 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2255 {
2256     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2257                                                 KVM_DEV_IRQ_HOST_MSIX);
2258 }