target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 static bool has_msr_star;
  58 static bool has_msr_hsave_pa;
  59 static int lm_capable_kernel;
  60
  61 #ifdef KVM_CAP_EXT_CPUID
  62
  63 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  64 {
  65     struct kvm_cpuid2 *cpuid;
  66     int r, size;
  67
  68     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  69     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  70     cpuid->nent = max;
  71     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  72     if (r == 0 && cpuid->nent >= max) {
  73         r = -E2BIG;
  74     }
  75     if (r < 0) {
  76         if (r == -E2BIG) {
  77             qemu_free(cpuid);
  78             return NULL;
  79         } else {
  80             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  81                     strerror(-r));
  82             exit(1);
  83         }
  84     }
  85     return cpuid;
  86 }
  87
  88 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  89                                       uint32_t index, int reg)
  90 {
  91     struct kvm_cpuid2 *cpuid;
  92     int i, max;
  93     uint32_t ret = 0;
  94     uint32_t cpuid_1_edx;
  95
  96     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  97         return -1U;
  98     }
  99
 100     max = 1;
 101     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 102         max *= 2;
 103     }
 104
 105     for (i = 0; i < cpuid->nent; ++i) {
 106         if (cpuid->entries[i].function == function &&
 107             cpuid->entries[i].index == index) {
 108             switch (reg) {
 109             case R_EAX:
 110                 ret = cpuid->entries[i].eax;
 111                 break;
 112             case R_EBX:
 113                 ret = cpuid->entries[i].ebx;
 114                 break;
 115             case R_ECX:
 116                 ret = cpuid->entries[i].ecx;
 117                 break;
 118             case R_EDX:
 119                 ret = cpuid->entries[i].edx;
 120                 switch (function) {
 121                 case 1:
 122                     /* KVM before 2.6.30 misreports the following features */
 123                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 124                     break;
 125                 case 0x80000001:
 126                     /* On Intel, kvm returns cpuid according to the Intel spec,
 127                      * so add missing bits according to the AMD spec:
 128                      */
 129                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 130                     ret |= cpuid_1_edx & 0x183f7ff;
 131                     break;
 132                 }
 133                 break;
 134             }
 135         }
 136     }
 137
 138     qemu_free(cpuid);
 139
 140     return ret;
 141 }
 142
 143 #else
 144
 145 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 146                                       uint32_t index, int reg)
 147 {
 148     return -1U;
 149 }
 150
 151 #endif
 152
 153 #ifdef CONFIG_KVM_PARA
 154 struct kvm_para_features {
 155     int cap;
 156     int feature;
 157 } para_features[] = {
 158 #ifdef KVM_CAP_CLOCKSOURCE
 159     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 160 #endif
 161 #ifdef KVM_CAP_NOP_IO_DELAY
 162     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 163 #endif
 164 #ifdef KVM_CAP_PV_MMU
 165     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 166 #endif
 167 #ifdef KVM_CAP_ASYNC_PF
 168     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 169 #endif
 170     { -1, -1 }
 171 };
 172
 173 static int get_para_features(CPUState *env)
 174 {
 175     int i, features = 0;
 176
 177     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 178         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 179             features |= (1 << para_features[i].feature);
 180         }
 181     }
 182     return features;
 183 }
 184 #endif
 185
 186 #ifdef KVM_CAP_MCE
 187 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 188                                      int *max_banks)
 189 {
 190     int r;
 191
 192     r = kvm_check_extension(s, KVM_CAP_MCE);
 193     if (r > 0) {
 194         *max_banks = r;
 195         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 196     }
 197     return -ENOSYS;
 198 }
 199
 200 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 201 {
 202     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 203 }
 204
 205 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 206 {
 207     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 208 }
 209
 210 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 211 {
 212     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 213     int r;
 214
 215     kmsrs->nmsrs = n;
 216     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 217     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 218     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 219     free(kmsrs);
 220     return r;
 221 }
 222
 223 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 224 static int kvm_mce_in_progress(CPUState *env)
 225 {
 226     struct kvm_msr_entry msr_mcg_status = {
 227         .index = MSR_MCG_STATUS,
 228     };
 229     int r;
 230
 231     r = kvm_get_msr(env, &msr_mcg_status, 1);
 232     if (r == -1 || r == 0) {
 233         fprintf(stderr, "Failed to get MCE status\n");
 234         return 0;
 235     }
 236     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 237 }
 238
 239 struct kvm_x86_mce_data
 240 {
 241     CPUState *env;
 242     struct kvm_x86_mce *mce;
 243     int abort_on_error;
 244 };
 245
 246 static void kvm_do_inject_x86_mce(void *_data)
 247 {
 248     struct kvm_x86_mce_data *data = _data;
 249     int r;
 250
 251     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 252     if ((data->env->mcg_cap & MCG_SER_P) &&
 253         !(data->mce->status & MCI_STATUS_AR)) {
 254         if (kvm_mce_in_progress(data->env)) {
 255             return;
 256         }
 257     }
 258
 259     r = kvm_set_mce(data->env, data->mce);
 260     if (r < 0) {
 261         perror("kvm_set_mce FAILED");
 262         if (data->abort_on_error) {
 263             abort();
 264         }
 265     }
 266 }
 267
 268 static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
 269                                   int flag)
 270 {
 271     struct kvm_x86_mce_data data = {
 272         .env = env,
 273         .mce = mce,
 274         .abort_on_error = (flag & ABORT_ON_ERROR),
 275     };
 276
 277     if (!env->mcg_cap) {
 278         fprintf(stderr, "MCE support is not enabled!\n");
 279         return;
 280     }
 281
 282     run_on_cpu(env, kvm_do_inject_x86_mce, &data);
 283 }
 284
 285 static void kvm_mce_broadcast_rest(CPUState *env);
 286 #endif
 287
 288 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 289                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 290                         int flag)
 291 {
 292 #ifdef KVM_CAP_MCE
 293     struct kvm_x86_mce mce = {
 294         .bank = bank,
 295         .status = status,
 296         .mcg_status = mcg_status,
 297         .addr = addr,
 298         .misc = misc,
 299     };
 300
 301     if (flag & MCE_BROADCAST) {
 302         kvm_mce_broadcast_rest(cenv);
 303     }
 304
 305     kvm_inject_x86_mce_on(cenv, &mce, flag);
 306 #else
 307     if (flag & ABORT_ON_ERROR) {
 308         abort();
 309     }
 310 #endif
 311 }
 312
 313 int kvm_arch_init_vcpu(CPUState *env)
 314 {
 315     struct {
 316         struct kvm_cpuid2 cpuid;
 317         struct kvm_cpuid_entry2 entries[100];
 318     } __attribute__((packed)) cpuid_data;
 319     uint32_t limit, i, j, cpuid_i;
 320     uint32_t unused;
 321     struct kvm_cpuid_entry2 *c;
 322 #ifdef CONFIG_KVM_PARA
 323     uint32_t signature[3];
 324 #endif
 325
 326     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 327
 328     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 329     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 330     env->cpuid_ext_features |= i;
 331
 332     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 333                                                              0, R_EDX);
 334     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 335                                                              0, R_ECX);
 336     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 337                                                              0, R_EDX);
 338
 339
 340     cpuid_i = 0;
 341
 342 #ifdef CONFIG_KVM_PARA
 343     /* Paravirtualization CPUIDs */
 344     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 345     c = &cpuid_data.entries[cpuid_i++];
 346     memset(c, 0, sizeof(*c));
 347     c->function = KVM_CPUID_SIGNATURE;
 348     c->eax = 0;
 349     c->ebx = signature[0];
 350     c->ecx = signature[1];
 351     c->edx = signature[2];
 352
 353     c = &cpuid_data.entries[cpuid_i++];
 354     memset(c, 0, sizeof(*c));
 355     c->function = KVM_CPUID_FEATURES;
 356     c->eax = env->cpuid_kvm_features & get_para_features(env);
 357 #endif
 358
 359     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 360
 361     for (i = 0; i <= limit; i++) {
 362         c = &cpuid_data.entries[cpuid_i++];
 363
 364         switch (i) {
 365         case 2: {
 366             /* Keep reading function 2 till all the input is received */
 367             int times;
 368
 369             c->function = i;
 370             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 371                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 372             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 373             times = c->eax & 0xff;
 374
 375             for (j = 1; j < times; ++j) {
 376                 c = &cpuid_data.entries[cpuid_i++];
 377                 c->function = i;
 378                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 379                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 380             }
 381             break;
 382         }
 383         case 4:
 384         case 0xb:
 385         case 0xd:
 386             for (j = 0; ; j++) {
 387                 c->function = i;
 388                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 389                 c->index = j;
 390                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 391
 392                 if (i == 4 && c->eax == 0) {
 393                     break;
 394                 }
 395                 if (i == 0xb && !(c->ecx & 0xff00)) {
 396                     break;
 397                 }
 398                 if (i == 0xd && c->eax == 0) {
 399                     break;
 400                 }
 401                 c = &cpuid_data.entries[cpuid_i++];
 402             }
 403             break;
 404         default:
 405             c->function = i;
 406             c->flags = 0;
 407             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 408             break;
 409         }
 410     }
 411     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 412
 413     for (i = 0x80000000; i <= limit; i++) {
 414         c = &cpuid_data.entries[cpuid_i++];
 415
 416         c->function = i;
 417         c->flags = 0;
 418         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 419     }
 420
 421     cpuid_data.cpuid.nent = cpuid_i;
 422
 423 #ifdef KVM_CAP_MCE
 424     if (((env->cpuid_version >> 8)&0xF) >= 6
 425         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 426         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 427         uint64_t mcg_cap;
 428         int banks;
 429
 430         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
 431             perror("kvm_get_mce_cap_supported FAILED");
 432         } else {
 433             if (banks > MCE_BANKS_DEF)
 434                 banks = MCE_BANKS_DEF;
 435             mcg_cap &= MCE_CAP_DEF;
 436             mcg_cap |= banks;
 437             if (kvm_setup_mce(env, &mcg_cap)) {
 438                 perror("kvm_setup_mce FAILED");
 439             } else {
 440                 env->mcg_cap = mcg_cap;
 441             }
 442         }
 443     }
 444 #endif
 445
 446     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 447 }
 448
 449 void kvm_arch_reset_vcpu(CPUState *env)
 450 {
 451     env->exception_injected = -1;
 452     env->interrupt_injected = -1;
 453     env->nmi_injected = 0;
 454     env->nmi_pending = 0;
 455     env->xcr0 = 1;
 456     if (kvm_irqchip_in_kernel()) {
 457         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 458                                           KVM_MP_STATE_UNINITIALIZED;
 459     } else {
 460         env->mp_state = KVM_MP_STATE_RUNNABLE;
 461     }
 462 }
 463
 464 static int kvm_get_supported_msrs(KVMState *s)
 465 {
 466     static int kvm_supported_msrs;
 467     int ret = 0;
 468
 469     /* first time */
 470     if (kvm_supported_msrs == 0) {
 471         struct kvm_msr_list msr_list, *kvm_msr_list;
 472
 473         kvm_supported_msrs = -1;
 474
 475         /* Obtain MSR list from KVM.  These are the MSRs that we must
 476          * save/restore */
 477         msr_list.nmsrs = 0;
 478         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 479         if (ret < 0 && ret != -E2BIG) {
 480             return ret;
 481         }
 482         /* Old kernel modules had a bug and could write beyond the provided
 483            memory. Allocate at least a safe amount of 1K. */
 484         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 485                                               msr_list.nmsrs *
 486                                               sizeof(msr_list.indices[0])));
 487
 488         kvm_msr_list->nmsrs = msr_list.nmsrs;
 489         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 490         if (ret >= 0) {
 491             int i;
 492
 493             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 494                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 495                     has_msr_star = true;
 496                     continue;
 497                 }
 498                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 499                     has_msr_hsave_pa = true;
 500                     continue;
 501                 }
 502             }
 503         }
 504
 505         free(kvm_msr_list);
 506     }
 507
 508     return ret;
 509 }
 510
 511 static int kvm_init_identity_map_page(KVMState *s)
 512 {
 513 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 514     int ret;
 515     uint64_t addr = 0xfffbc000;
 516
 517     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 518         return 0;
 519     }
 520
 521     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 522     if (ret < 0) {
 523         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 524         return ret;
 525     }
 526 #endif
 527     return 0;
 528 }
 529
 530 int kvm_arch_init(KVMState *s)
 531 {
 532     int ret;
 533     struct utsname utsname;
 534
 535     ret = kvm_get_supported_msrs(s);
 536     if (ret < 0) {
 537         return ret;
 538     }
 539
 540     uname(&utsname);
 541     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 542
 543     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 544      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 545      * must be part of guest physical memory, we need to allocate it.  Older
 546      * versions of KVM just assumed that it would be at the end of physical
 547      * memory but that doesn't work with more than 4GB of memory.  We simply
 548      * refuse to work with those older versions of KVM. */
 549     ret = kvm_check_extension(s, KVM_CAP_SET_TSS_ADDR);
 550     if (ret <= 0) {
 551         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 552         return ret;
 553     }
 554
 555     /* this address is 3 pages before the bios, and the bios should present
 556      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 557      * this?
 558      */
 559     /*
 560      * Tell fw_cfg to notify the BIOS to reserve the range.
 561      */
 562     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 563         perror("e820_add_entry() table is full");
 564         exit(1);
 565     }
 566     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 567     if (ret < 0) {
 568         return ret;
 569     }
 570
 571     return kvm_init_identity_map_page(s);
 572 }
 573
 574 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 575 {
 576     lhs->selector = rhs->selector;
 577     lhs->base = rhs->base;
 578     lhs->limit = rhs->limit;
 579     lhs->type = 3;
 580     lhs->present = 1;
 581     lhs->dpl = 3;
 582     lhs->db = 0;
 583     lhs->s = 1;
 584     lhs->l = 0;
 585     lhs->g = 0;
 586     lhs->avl = 0;
 587     lhs->unusable = 0;
 588 }
 589
 590 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 591 {
 592     unsigned flags = rhs->flags;
 593     lhs->selector = rhs->selector;
 594     lhs->base = rhs->base;
 595     lhs->limit = rhs->limit;
 596     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 597     lhs->present = (flags & DESC_P_MASK) != 0;
 598     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 599     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 600     lhs->s = (flags & DESC_S_MASK) != 0;
 601     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 602     lhs->g = (flags & DESC_G_MASK) != 0;
 603     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 604     lhs->unusable = 0;
 605 }
 606
 607 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 608 {
 609     lhs->selector = rhs->selector;
 610     lhs->base = rhs->base;
 611     lhs->limit = rhs->limit;
 612     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 613                  (rhs->present * DESC_P_MASK) |
 614                  (rhs->dpl << DESC_DPL_SHIFT) |
 615                  (rhs->db << DESC_B_SHIFT) |
 616                  (rhs->s * DESC_S_MASK) |
 617                  (rhs->l << DESC_L_SHIFT) |
 618                  (rhs->g * DESC_G_MASK) |
 619                  (rhs->avl * DESC_AVL_MASK);
 620 }
 621
 622 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 623 {
 624     if (set) {
 625         *kvm_reg = *qemu_reg;
 626     } else {
 627         *qemu_reg = *kvm_reg;
 628     }
 629 }
 630
 631 static int kvm_getput_regs(CPUState *env, int set)
 632 {
 633     struct kvm_regs regs;
 634     int ret = 0;
 635
 636     if (!set) {
 637         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 638         if (ret < 0) {
 639             return ret;
 640         }
 641     }
 642
 643     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 644     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 645     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 646     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 647     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 648     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 649     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 650     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 651 #ifdef TARGET_X86_64
 652     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 653     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 654     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 655     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 656     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 657     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 658     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 659     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 660 #endif
 661
 662     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 663     kvm_getput_reg(&regs.rip, &env->eip, set);
 664
 665     if (set) {
 666         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 667     }
 668
 669     return ret;
 670 }
 671
 672 static int kvm_put_fpu(CPUState *env)
 673 {
 674     struct kvm_fpu fpu;
 675     int i;
 676
 677     memset(&fpu, 0, sizeof fpu);
 678     fpu.fsw = env->fpus & ~(7 << 11);
 679     fpu.fsw |= (env->fpstt & 7) << 11;
 680     fpu.fcw = env->fpuc;
 681     for (i = 0; i < 8; ++i) {
 682         fpu.ftwx |= (!env->fptags[i]) << i;
 683     }
 684     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 685     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 686     fpu.mxcsr = env->mxcsr;
 687
 688     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 689 }
 690
 691 #ifdef KVM_CAP_XSAVE
 692 #define XSAVE_CWD_RIP     2
 693 #define XSAVE_CWD_RDP     4
 694 #define XSAVE_MXCSR       6
 695 #define XSAVE_ST_SPACE    8
 696 #define XSAVE_XMM_SPACE   40
 697 #define XSAVE_XSTATE_BV   128
 698 #define XSAVE_YMMH_SPACE  144
 699 #endif
 700
 701 static int kvm_put_xsave(CPUState *env)
 702 {
 703 #ifdef KVM_CAP_XSAVE
 704     int i, r;
 705     struct kvm_xsave* xsave;
 706     uint16_t cwd, swd, twd, fop;
 707
 708     if (!kvm_has_xsave()) {
 709         return kvm_put_fpu(env);
 710     }
 711
 712     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 713     memset(xsave, 0, sizeof(struct kvm_xsave));
 714     cwd = swd = twd = fop = 0;
 715     swd = env->fpus & ~(7 << 11);
 716     swd |= (env->fpstt & 7) << 11;
 717     cwd = env->fpuc;
 718     for (i = 0; i < 8; ++i) {
 719         twd |= (!env->fptags[i]) << i;
 720     }
 721     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 722     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 723     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 724             sizeof env->fpregs);
 725     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 726             sizeof env->xmm_regs);
 727     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 728     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 729     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 730             sizeof env->ymmh_regs);
 731     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 732     qemu_free(xsave);
 733     return r;
 734 #else
 735     return kvm_put_fpu(env);
 736 #endif
 737 }
 738
 739 static int kvm_put_xcrs(CPUState *env)
 740 {
 741 #ifdef KVM_CAP_XCRS
 742     struct kvm_xcrs xcrs;
 743
 744     if (!kvm_has_xcrs()) {
 745         return 0;
 746     }
 747
 748     xcrs.nr_xcrs = 1;
 749     xcrs.flags = 0;
 750     xcrs.xcrs[0].xcr = 0;
 751     xcrs.xcrs[0].value = env->xcr0;
 752     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 753 #else
 754     return 0;
 755 #endif
 756 }
 757
 758 static int kvm_put_sregs(CPUState *env)
 759 {
 760     struct kvm_sregs sregs;
 761
 762     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 763     if (env->interrupt_injected >= 0) {
 764         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 765                 (uint64_t)1 << (env->interrupt_injected % 64);
 766     }
 767
 768     if ((env->eflags & VM_MASK)) {
 769         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 770         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 771         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 772         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 773         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 774         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 775     } else {
 776         set_seg(&sregs.cs, &env->segs[R_CS]);
 777         set_seg(&sregs.ds, &env->segs[R_DS]);
 778         set_seg(&sregs.es, &env->segs[R_ES]);
 779         set_seg(&sregs.fs, &env->segs[R_FS]);
 780         set_seg(&sregs.gs, &env->segs[R_GS]);
 781         set_seg(&sregs.ss, &env->segs[R_SS]);
 782     }
 783
 784     set_seg(&sregs.tr, &env->tr);
 785     set_seg(&sregs.ldt, &env->ldt);
 786
 787     sregs.idt.limit = env->idt.limit;
 788     sregs.idt.base = env->idt.base;
 789     sregs.gdt.limit = env->gdt.limit;
 790     sregs.gdt.base = env->gdt.base;
 791
 792     sregs.cr0 = env->cr[0];
 793     sregs.cr2 = env->cr[2];
 794     sregs.cr3 = env->cr[3];
 795     sregs.cr4 = env->cr[4];
 796
 797     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 798     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 799
 800     sregs.efer = env->efer;
 801
 802     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 803 }
 804
 805 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 806                               uint32_t index, uint64_t value)
 807 {
 808     entry->index = index;
 809     entry->data = value;
 810 }
 811
 812 static int kvm_put_msrs(CPUState *env, int level)
 813 {
 814     struct {
 815         struct kvm_msrs info;
 816         struct kvm_msr_entry entries[100];
 817     } msr_data;
 818     struct kvm_msr_entry *msrs = msr_data.entries;
 819     int n = 0;
 820
 821     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 822     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 823     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 824     if (has_msr_star) {
 825         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 826     }
 827     if (has_msr_hsave_pa) {
 828         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 829     }
 830 #ifdef TARGET_X86_64
 831     if (lm_capable_kernel) {
 832         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 833         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 834         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 835         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 836     }
 837 #endif
 838     if (level == KVM_PUT_FULL_STATE) {
 839         /*
 840          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 841          * writeback. Until this is fixed, we only write the offset to SMP
 842          * guests after migration, desynchronizing the VCPUs, but avoiding
 843          * huge jump-backs that would occur without any writeback at all.
 844          */
 845         if (smp_cpus == 1 || env->tsc != 0) {
 846             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 847         }
 848     }
 849     /*
 850      * The following paravirtual MSRs have side effects on the guest or are
 851      * too heavy for normal writeback. Limit them to reset or full state
 852      * updates.
 853      */
 854     if (level >= KVM_PUT_RESET_STATE) {
 855         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 856                           env->system_time_msr);
 857         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 858 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 859         kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
 860 #endif
 861     }
 862 #ifdef KVM_CAP_MCE
 863     if (env->mcg_cap) {
 864         int i;
 865
 866         if (level == KVM_PUT_RESET_STATE) {
 867             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 868         } else if (level == KVM_PUT_FULL_STATE) {
 869             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 870             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 871             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 872                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 873             }
 874         }
 875     }
 876 #endif
 877
 878     msr_data.info.nmsrs = n;
 879
 880     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 881
 882 }
 883
 884
 885 static int kvm_get_fpu(CPUState *env)
 886 {
 887     struct kvm_fpu fpu;
 888     int i, ret;
 889
 890     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 891     if (ret < 0) {
 892         return ret;
 893     }
 894
 895     env->fpstt = (fpu.fsw >> 11) & 7;
 896     env->fpus = fpu.fsw;
 897     env->fpuc = fpu.fcw;
 898     for (i = 0; i < 8; ++i) {
 899         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 900     }
 901     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 902     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 903     env->mxcsr = fpu.mxcsr;
 904
 905     return 0;
 906 }
 907
 908 static int kvm_get_xsave(CPUState *env)
 909 {
 910 #ifdef KVM_CAP_XSAVE
 911     struct kvm_xsave* xsave;
 912     int ret, i;
 913     uint16_t cwd, swd, twd, fop;
 914
 915     if (!kvm_has_xsave()) {
 916         return kvm_get_fpu(env);
 917     }
 918
 919     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 920     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 921     if (ret < 0) {
 922         qemu_free(xsave);
 923         return ret;
 924     }
 925
 926     cwd = (uint16_t)xsave->region[0];
 927     swd = (uint16_t)(xsave->region[0] >> 16);
 928     twd = (uint16_t)xsave->region[1];
 929     fop = (uint16_t)(xsave->region[1] >> 16);
 930     env->fpstt = (swd >> 11) & 7;
 931     env->fpus = swd;
 932     env->fpuc = cwd;
 933     for (i = 0; i < 8; ++i) {
 934         env->fptags[i] = !((twd >> i) & 1);
 935     }
 936     env->mxcsr = xsave->region[XSAVE_MXCSR];
 937     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 938             sizeof env->fpregs);
 939     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 940             sizeof env->xmm_regs);
 941     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 942     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 943             sizeof env->ymmh_regs);
 944     qemu_free(xsave);
 945     return 0;
 946 #else
 947     return kvm_get_fpu(env);
 948 #endif
 949 }
 950
 951 static int kvm_get_xcrs(CPUState *env)
 952 {
 953 #ifdef KVM_CAP_XCRS
 954     int i, ret;
 955     struct kvm_xcrs xcrs;
 956
 957     if (!kvm_has_xcrs()) {
 958         return 0;
 959     }
 960
 961     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 962     if (ret < 0) {
 963         return ret;
 964     }
 965
 966     for (i = 0; i < xcrs.nr_xcrs; i++) {
 967         /* Only support xcr0 now */
 968         if (xcrs.xcrs[0].xcr == 0) {
 969             env->xcr0 = xcrs.xcrs[0].value;
 970             break;
 971         }
 972     }
 973     return 0;
 974 #else
 975     return 0;
 976 #endif
 977 }
 978
 979 static int kvm_get_sregs(CPUState *env)
 980 {
 981     struct kvm_sregs sregs;
 982     uint32_t hflags;
 983     int bit, i, ret;
 984
 985     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 986     if (ret < 0) {
 987         return ret;
 988     }
 989
 990     /* There can only be one pending IRQ set in the bitmap at a time, so try
 991        to find it and save its number instead (-1 for none). */
 992     env->interrupt_injected = -1;
 993     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 994         if (sregs.interrupt_bitmap[i]) {
 995             bit = ctz64(sregs.interrupt_bitmap[i]);
 996             env->interrupt_injected = i * 64 + bit;
 997             break;
 998         }
 999     }
1000
1001     get_seg(&env->segs[R_CS], &sregs.cs);
1002     get_seg(&env->segs[R_DS], &sregs.ds);
1003     get_seg(&env->segs[R_ES], &sregs.es);
1004     get_seg(&env->segs[R_FS], &sregs.fs);
1005     get_seg(&env->segs[R_GS], &sregs.gs);
1006     get_seg(&env->segs[R_SS], &sregs.ss);
1007
1008     get_seg(&env->tr, &sregs.tr);
1009     get_seg(&env->ldt, &sregs.ldt);
1010
1011     env->idt.limit = sregs.idt.limit;
1012     env->idt.base = sregs.idt.base;
1013     env->gdt.limit = sregs.gdt.limit;
1014     env->gdt.base = sregs.gdt.base;
1015
1016     env->cr[0] = sregs.cr0;
1017     env->cr[2] = sregs.cr2;
1018     env->cr[3] = sregs.cr3;
1019     env->cr[4] = sregs.cr4;
1020
1021     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1022
1023     env->efer = sregs.efer;
1024     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1025
1026 #define HFLAG_COPY_MASK \
1027     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1028        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1029        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1030        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1031
1032     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1033     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1034     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1035                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1036     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1037     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1038                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1039
1040     if (env->efer & MSR_EFER_LMA) {
1041         hflags |= HF_LMA_MASK;
1042     }
1043
1044     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1045         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1046     } else {
1047         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1048                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1049         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1050                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1051         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1052             !(hflags & HF_CS32_MASK)) {
1053             hflags |= HF_ADDSEG_MASK;
1054         } else {
1055             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1056                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1057         }
1058     }
1059     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1060
1061     return 0;
1062 }
1063
1064 static int kvm_get_msrs(CPUState *env)
1065 {
1066     struct {
1067         struct kvm_msrs info;
1068         struct kvm_msr_entry entries[100];
1069     } msr_data;
1070     struct kvm_msr_entry *msrs = msr_data.entries;
1071     int ret, i, n;
1072
1073     n = 0;
1074     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1075     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1076     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1077     if (has_msr_star) {
1078         msrs[n++].index = MSR_STAR;
1079     }
1080     if (has_msr_hsave_pa) {
1081         msrs[n++].index = MSR_VM_HSAVE_PA;
1082     }
1083     msrs[n++].index = MSR_IA32_TSC;
1084 #ifdef TARGET_X86_64
1085     if (lm_capable_kernel) {
1086         msrs[n++].index = MSR_CSTAR;
1087         msrs[n++].index = MSR_KERNELGSBASE;
1088         msrs[n++].index = MSR_FMASK;
1089         msrs[n++].index = MSR_LSTAR;
1090     }
1091 #endif
1092     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1093     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1094 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1095     msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1096 #endif
1097
1098 #ifdef KVM_CAP_MCE
1099     if (env->mcg_cap) {
1100         msrs[n++].index = MSR_MCG_STATUS;
1101         msrs[n++].index = MSR_MCG_CTL;
1102         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1103             msrs[n++].index = MSR_MC0_CTL + i;
1104         }
1105     }
1106 #endif
1107
1108     msr_data.info.nmsrs = n;
1109     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1110     if (ret < 0) {
1111         return ret;
1112     }
1113
1114     for (i = 0; i < ret; i++) {
1115         switch (msrs[i].index) {
1116         case MSR_IA32_SYSENTER_CS:
1117             env->sysenter_cs = msrs[i].data;
1118             break;
1119         case MSR_IA32_SYSENTER_ESP:
1120             env->sysenter_esp = msrs[i].data;
1121             break;
1122         case MSR_IA32_SYSENTER_EIP:
1123             env->sysenter_eip = msrs[i].data;
1124             break;
1125         case MSR_STAR:
1126             env->star = msrs[i].data;
1127             break;
1128 #ifdef TARGET_X86_64
1129         case MSR_CSTAR:
1130             env->cstar = msrs[i].data;
1131             break;
1132         case MSR_KERNELGSBASE:
1133             env->kernelgsbase = msrs[i].data;
1134             break;
1135         case MSR_FMASK:
1136             env->fmask = msrs[i].data;
1137             break;
1138         case MSR_LSTAR:
1139             env->lstar = msrs[i].data;
1140             break;
1141 #endif
1142         case MSR_IA32_TSC:
1143             env->tsc = msrs[i].data;
1144             break;
1145         case MSR_VM_HSAVE_PA:
1146             env->vm_hsave = msrs[i].data;
1147             break;
1148         case MSR_KVM_SYSTEM_TIME:
1149             env->system_time_msr = msrs[i].data;
1150             break;
1151         case MSR_KVM_WALL_CLOCK:
1152             env->wall_clock_msr = msrs[i].data;
1153             break;
1154 #ifdef KVM_CAP_MCE
1155         case MSR_MCG_STATUS:
1156             env->mcg_status = msrs[i].data;
1157             break;
1158         case MSR_MCG_CTL:
1159             env->mcg_ctl = msrs[i].data;
1160             break;
1161 #endif
1162         default:
1163 #ifdef KVM_CAP_MCE
1164             if (msrs[i].index >= MSR_MC0_CTL &&
1165                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1166                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1167             }
1168 #endif
1169             break;
1170 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1171         case MSR_KVM_ASYNC_PF_EN:
1172             env->async_pf_en_msr = msrs[i].data;
1173             break;
1174 #endif
1175         }
1176     }
1177
1178     return 0;
1179 }
1180
1181 static int kvm_put_mp_state(CPUState *env)
1182 {
1183     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1184
1185     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1186 }
1187
1188 static int kvm_get_mp_state(CPUState *env)
1189 {
1190     struct kvm_mp_state mp_state;
1191     int ret;
1192
1193     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1194     if (ret < 0) {
1195         return ret;
1196     }
1197     env->mp_state = mp_state.mp_state;
1198     if (kvm_irqchip_in_kernel()) {
1199         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1200     }
1201     return 0;
1202 }
1203
1204 static int kvm_put_vcpu_events(CPUState *env, int level)
1205 {
1206 #ifdef KVM_CAP_VCPU_EVENTS
1207     struct kvm_vcpu_events events;
1208
1209     if (!kvm_has_vcpu_events()) {
1210         return 0;
1211     }
1212
1213     events.exception.injected = (env->exception_injected >= 0);
1214     events.exception.nr = env->exception_injected;
1215     events.exception.has_error_code = env->has_error_code;
1216     events.exception.error_code = env->error_code;
1217
1218     events.interrupt.injected = (env->interrupt_injected >= 0);
1219     events.interrupt.nr = env->interrupt_injected;
1220     events.interrupt.soft = env->soft_interrupt;
1221
1222     events.nmi.injected = env->nmi_injected;
1223     events.nmi.pending = env->nmi_pending;
1224     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1225
1226     events.sipi_vector = env->sipi_vector;
1227
1228     events.flags = 0;
1229     if (level >= KVM_PUT_RESET_STATE) {
1230         events.flags |=
1231             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1232     }
1233
1234     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1235 #else
1236     return 0;
1237 #endif
1238 }
1239
1240 static int kvm_get_vcpu_events(CPUState *env)
1241 {
1242 #ifdef KVM_CAP_VCPU_EVENTS
1243     struct kvm_vcpu_events events;
1244     int ret;
1245
1246     if (!kvm_has_vcpu_events()) {
1247         return 0;
1248     }
1249
1250     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1251     if (ret < 0) {
1252        return ret;
1253     }
1254     env->exception_injected =
1255        events.exception.injected ? events.exception.nr : -1;
1256     env->has_error_code = events.exception.has_error_code;
1257     env->error_code = events.exception.error_code;
1258
1259     env->interrupt_injected =
1260         events.interrupt.injected ? events.interrupt.nr : -1;
1261     env->soft_interrupt = events.interrupt.soft;
1262
1263     env->nmi_injected = events.nmi.injected;
1264     env->nmi_pending = events.nmi.pending;
1265     if (events.nmi.masked) {
1266         env->hflags2 |= HF2_NMI_MASK;
1267     } else {
1268         env->hflags2 &= ~HF2_NMI_MASK;
1269     }
1270
1271     env->sipi_vector = events.sipi_vector;
1272 #endif
1273
1274     return 0;
1275 }
1276
1277 static int kvm_guest_debug_workarounds(CPUState *env)
1278 {
1279     int ret = 0;
1280 #ifdef KVM_CAP_SET_GUEST_DEBUG
1281     unsigned long reinject_trap = 0;
1282
1283     if (!kvm_has_vcpu_events()) {
1284         if (env->exception_injected == 1) {
1285             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1286         } else if (env->exception_injected == 3) {
1287             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1288         }
1289         env->exception_injected = -1;
1290     }
1291
1292     /*
1293      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1294      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1295      * by updating the debug state once again if single-stepping is on.
1296      * Another reason to call kvm_update_guest_debug here is a pending debug
1297      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1298      * reinject them via SET_GUEST_DEBUG.
1299      */
1300     if (reinject_trap ||
1301         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1302         ret = kvm_update_guest_debug(env, reinject_trap);
1303     }
1304 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1305     return ret;
1306 }
1307
1308 static int kvm_put_debugregs(CPUState *env)
1309 {
1310 #ifdef KVM_CAP_DEBUGREGS
1311     struct kvm_debugregs dbgregs;
1312     int i;
1313
1314     if (!kvm_has_debugregs()) {
1315         return 0;
1316     }
1317
1318     for (i = 0; i < 4; i++) {
1319         dbgregs.db[i] = env->dr[i];
1320     }
1321     dbgregs.dr6 = env->dr[6];
1322     dbgregs.dr7 = env->dr[7];
1323     dbgregs.flags = 0;
1324
1325     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1326 #else
1327     return 0;
1328 #endif
1329 }
1330
1331 static int kvm_get_debugregs(CPUState *env)
1332 {
1333 #ifdef KVM_CAP_DEBUGREGS
1334     struct kvm_debugregs dbgregs;
1335     int i, ret;
1336
1337     if (!kvm_has_debugregs()) {
1338         return 0;
1339     }
1340
1341     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1342     if (ret < 0) {
1343         return ret;
1344     }
1345     for (i = 0; i < 4; i++) {
1346         env->dr[i] = dbgregs.db[i];
1347     }
1348     env->dr[4] = env->dr[6] = dbgregs.dr6;
1349     env->dr[5] = env->dr[7] = dbgregs.dr7;
1350 #endif
1351
1352     return 0;
1353 }
1354
1355 int kvm_arch_put_registers(CPUState *env, int level)
1356 {
1357     int ret;
1358
1359     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1360
1361     ret = kvm_getput_regs(env, 1);
1362     if (ret < 0) {
1363         return ret;
1364     }
1365     ret = kvm_put_xsave(env);
1366     if (ret < 0) {
1367         return ret;
1368     }
1369     ret = kvm_put_xcrs(env);
1370     if (ret < 0) {
1371         return ret;
1372     }
1373     ret = kvm_put_sregs(env);
1374     if (ret < 0) {
1375         return ret;
1376     }
1377     ret = kvm_put_msrs(env, level);
1378     if (ret < 0) {
1379         return ret;
1380     }
1381     if (level >= KVM_PUT_RESET_STATE) {
1382         ret = kvm_put_mp_state(env);
1383         if (ret < 0) {
1384             return ret;
1385         }
1386     }
1387     ret = kvm_put_vcpu_events(env, level);
1388     if (ret < 0) {
1389         return ret;
1390     }
1391     ret = kvm_put_debugregs(env);
1392     if (ret < 0) {
1393         return ret;
1394     }
1395     /* must be last */
1396     ret = kvm_guest_debug_workarounds(env);
1397     if (ret < 0) {
1398         return ret;
1399     }
1400     return 0;
1401 }
1402
1403 int kvm_arch_get_registers(CPUState *env)
1404 {
1405     int ret;
1406
1407     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1408
1409     ret = kvm_getput_regs(env, 0);
1410     if (ret < 0) {
1411         return ret;
1412     }
1413     ret = kvm_get_xsave(env);
1414     if (ret < 0) {
1415         return ret;
1416     }
1417     ret = kvm_get_xcrs(env);
1418     if (ret < 0) {
1419         return ret;
1420     }
1421     ret = kvm_get_sregs(env);
1422     if (ret < 0) {
1423         return ret;
1424     }
1425     ret = kvm_get_msrs(env);
1426     if (ret < 0) {
1427         return ret;
1428     }
1429     ret = kvm_get_mp_state(env);
1430     if (ret < 0) {
1431         return ret;
1432     }
1433     ret = kvm_get_vcpu_events(env);
1434     if (ret < 0) {
1435         return ret;
1436     }
1437     ret = kvm_get_debugregs(env);
1438     if (ret < 0) {
1439         return ret;
1440     }
1441     return 0;
1442 }
1443
1444 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1445 {
1446     /* Inject NMI */
1447     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1448         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1449         DPRINTF("injected NMI\n");
1450         kvm_vcpu_ioctl(env, KVM_NMI);
1451     }
1452
1453     /* Try to inject an interrupt if the guest can accept it */
1454     if (run->ready_for_interrupt_injection &&
1455         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1456         (env->eflags & IF_MASK)) {
1457         int irq;
1458
1459         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1460         irq = cpu_get_pic_interrupt(env);
1461         if (irq >= 0) {
1462             struct kvm_interrupt intr;
1463             intr.irq = irq;
1464             /* FIXME: errors */
1465             DPRINTF("injected interrupt %d\n", irq);
1466             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1467         }
1468     }
1469
1470     /* If we have an interrupt but the guest is not ready to receive an
1471      * interrupt, request an interrupt window exit.  This will
1472      * cause a return to userspace as soon as the guest is ready to
1473      * receive interrupts. */
1474     if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1475         run->request_interrupt_window = 1;
1476     } else {
1477         run->request_interrupt_window = 0;
1478     }
1479
1480     DPRINTF("setting tpr\n");
1481     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1482
1483     return 0;
1484 }
1485
1486 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1487 {
1488     if (run->if_flag) {
1489         env->eflags |= IF_MASK;
1490     } else {
1491         env->eflags &= ~IF_MASK;
1492     }
1493     cpu_set_apic_tpr(env->apic_state, run->cr8);
1494     cpu_set_apic_base(env->apic_state, run->apic_base);
1495
1496     return 0;
1497 }
1498
1499 int kvm_arch_process_irqchip_events(CPUState *env)
1500 {
1501     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1502         kvm_cpu_synchronize_state(env);
1503         do_cpu_init(env);
1504         env->exception_index = EXCP_HALTED;
1505     }
1506
1507     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1508         kvm_cpu_synchronize_state(env);
1509         do_cpu_sipi(env);
1510     }
1511
1512     return env->halted;
1513 }
1514
1515 static int kvm_handle_halt(CPUState *env)
1516 {
1517     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1518           (env->eflags & IF_MASK)) &&
1519         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1520         env->halted = 1;
1521         env->exception_index = EXCP_HLT;
1522         return 0;
1523     }
1524
1525     return 1;
1526 }
1527
1528 static bool host_supports_vmx(void)
1529 {
1530     uint32_t ecx, unused;
1531
1532     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1533     return ecx & CPUID_EXT_VMX;
1534 }
1535
1536 #define VMX_INVALID_GUEST_STATE 0x80000021
1537
1538 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1539 {
1540     uint64_t code;
1541     int ret = 0;
1542
1543     switch (run->exit_reason) {
1544     case KVM_EXIT_HLT:
1545         DPRINTF("handle_hlt\n");
1546         ret = kvm_handle_halt(env);
1547         break;
1548     case KVM_EXIT_SET_TPR:
1549         ret = 1;
1550         break;
1551     case KVM_EXIT_FAIL_ENTRY:
1552         code = run->fail_entry.hardware_entry_failure_reason;
1553         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1554                 code);
1555         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1556             fprintf(stderr,
1557                     "\nIf you're runnning a guest on an Intel machine without "
1558                         "unrestricted mode\n"
1559                     "support, the failure can be most likely due to the guest "
1560                         "entering an invalid\n"
1561                     "state for Intel VT. For example, the guest maybe running "
1562                         "in big real mode\n"
1563                     "which is not supported on less recent Intel processors."
1564                         "\n\n");
1565         }
1566         ret = -1;
1567         break;
1568     case KVM_EXIT_EXCEPTION:
1569         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1570                 run->ex.exception, run->ex.error_code);
1571         ret = -1;
1572         break;
1573     default:
1574         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1575         ret = -1;
1576         break;
1577     }
1578
1579     return ret;
1580 }
1581
1582 #ifdef KVM_CAP_SET_GUEST_DEBUG
1583 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1584 {
1585     static const uint8_t int3 = 0xcc;
1586
1587     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1588         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1589         return -EINVAL;
1590     }
1591     return 0;
1592 }
1593
1594 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1595 {
1596     uint8_t int3;
1597
1598     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1599         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1600         return -EINVAL;
1601     }
1602     return 0;
1603 }
1604
1605 static struct {
1606     target_ulong addr;
1607     int len;
1608     int type;
1609 } hw_breakpoint[4];
1610
1611 static int nb_hw_breakpoint;
1612
1613 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1614 {
1615     int n;
1616
1617     for (n = 0; n < nb_hw_breakpoint; n++) {
1618         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1619             (hw_breakpoint[n].len == len || len == -1)) {
1620             return n;
1621         }
1622     }
1623     return -1;
1624 }
1625
1626 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1627                                   target_ulong len, int type)
1628 {
1629     switch (type) {
1630     case GDB_BREAKPOINT_HW:
1631         len = 1;
1632         break;
1633     case GDB_WATCHPOINT_WRITE:
1634     case GDB_WATCHPOINT_ACCESS:
1635         switch (len) {
1636         case 1:
1637             break;
1638         case 2:
1639         case 4:
1640         case 8:
1641             if (addr & (len - 1)) {
1642                 return -EINVAL;
1643             }
1644             break;
1645         default:
1646             return -EINVAL;
1647         }
1648         break;
1649     default:
1650         return -ENOSYS;
1651     }
1652
1653     if (nb_hw_breakpoint == 4) {
1654         return -ENOBUFS;
1655     }
1656     if (find_hw_breakpoint(addr, len, type) >= 0) {
1657         return -EEXIST;
1658     }
1659     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1660     hw_breakpoint[nb_hw_breakpoint].len = len;
1661     hw_breakpoint[nb_hw_breakpoint].type = type;
1662     nb_hw_breakpoint++;
1663
1664     return 0;
1665 }
1666
1667 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1668                                   target_ulong len, int type)
1669 {
1670     int n;
1671
1672     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1673     if (n < 0) {
1674         return -ENOENT;
1675     }
1676     nb_hw_breakpoint--;
1677     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1678
1679     return 0;
1680 }
1681
1682 void kvm_arch_remove_all_hw_breakpoints(void)
1683 {
1684     nb_hw_breakpoint = 0;
1685 }
1686
1687 static CPUWatchpoint hw_watchpoint;
1688
1689 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1690 {
1691     int handle = 0;
1692     int n;
1693
1694     if (arch_info->exception == 1) {
1695         if (arch_info->dr6 & (1 << 14)) {
1696             if (cpu_single_env->singlestep_enabled) {
1697                 handle = 1;
1698             }
1699         } else {
1700             for (n = 0; n < 4; n++) {
1701                 if (arch_info->dr6 & (1 << n)) {
1702                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1703                     case 0x0:
1704                         handle = 1;
1705                         break;
1706                     case 0x1:
1707                         handle = 1;
1708                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1709                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1710                         hw_watchpoint.flags = BP_MEM_WRITE;
1711                         break;
1712                     case 0x3:
1713                         handle = 1;
1714                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1715                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1716                         hw_watchpoint.flags = BP_MEM_ACCESS;
1717                         break;
1718                     }
1719                 }
1720             }
1721         }
1722     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1723         handle = 1;
1724     }
1725     if (!handle) {
1726         cpu_synchronize_state(cpu_single_env);
1727         assert(cpu_single_env->exception_injected == -1);
1728
1729         cpu_single_env->exception_injected = arch_info->exception;
1730         cpu_single_env->has_error_code = 0;
1731     }
1732
1733     return handle;
1734 }
1735
1736 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1737 {
1738     const uint8_t type_code[] = {
1739         [GDB_BREAKPOINT_HW] = 0x0,
1740         [GDB_WATCHPOINT_WRITE] = 0x1,
1741         [GDB_WATCHPOINT_ACCESS] = 0x3
1742     };
1743     const uint8_t len_code[] = {
1744         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1745     };
1746     int n;
1747
1748     if (kvm_sw_breakpoints_active(env)) {
1749         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1750     }
1751     if (nb_hw_breakpoint > 0) {
1752         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1753         dbg->arch.debugreg[7] = 0x0600;
1754         for (n = 0; n < nb_hw_breakpoint; n++) {
1755             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1756             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1757                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1758                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1759         }
1760     }
1761 }
1762 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1763
1764 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1765 {
1766     return !(env->cr[0] & CR0_PE_MASK) ||
1767            ((env->segs[R_CS].selector  & 3) != 3);
1768 }
1769
1770 static void hardware_memory_error(void)
1771 {
1772     fprintf(stderr, "Hardware memory error!\n");
1773     exit(1);
1774 }
1775
1776 #ifdef KVM_CAP_MCE
1777 static void kvm_mce_broadcast_rest(CPUState *env)
1778 {
1779     struct kvm_x86_mce mce = {
1780         .bank = 1,
1781         .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1782         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1783         .addr = 0,
1784         .misc = 0,
1785     };
1786     CPUState *cenv;
1787
1788     /* Broadcast MCA signal for processor version 06H_EH and above */
1789     if (cpu_x86_support_mca_broadcast(env)) {
1790         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1791             if (cenv == env) {
1792                 continue;
1793             }
1794             kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
1795         }
1796     }
1797 }
1798
1799 static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1800 {
1801     struct kvm_x86_mce mce = {
1802         .bank = 9,
1803         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1804                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1805                   | MCI_STATUS_AR | 0x134,
1806         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1807         .addr = paddr,
1808         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1809     };
1810     int r;
1811
1812     r = kvm_set_mce(env, &mce);
1813     if (r < 0) {
1814         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1815         abort();
1816     }
1817     kvm_mce_broadcast_rest(env);
1818 }
1819
1820 static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1821 {
1822     struct kvm_x86_mce mce = {
1823         .bank = 9,
1824         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1825                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1826                   | 0xc0,
1827         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1828         .addr = paddr,
1829         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1830     };
1831     int r;
1832
1833     r = kvm_set_mce(env, &mce);
1834     if (r < 0) {
1835         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1836         abort();
1837     }
1838     kvm_mce_broadcast_rest(env);
1839 }
1840
1841 static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1842 {
1843     struct kvm_x86_mce mce = {
1844         .bank = 9,
1845         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1846                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1847                   | 0xc0,
1848         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1849         .addr = paddr,
1850         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1851     };
1852
1853     kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
1854     kvm_mce_broadcast_rest(env);
1855 }
1856
1857 #endif
1858
1859 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1860 {
1861 #if defined(KVM_CAP_MCE)
1862     void *vaddr;
1863     ram_addr_t ram_addr;
1864     target_phys_addr_t paddr;
1865
1866     if ((env->mcg_cap & MCG_SER_P) && addr
1867         && (code == BUS_MCEERR_AR
1868             || code == BUS_MCEERR_AO)) {
1869         vaddr = (void *)addr;
1870         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1871             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1872             fprintf(stderr, "Hardware memory error for memory used by "
1873                     "QEMU itself instead of guest system!\n");
1874             /* Hope we are lucky for AO MCE */
1875             if (code == BUS_MCEERR_AO) {
1876                 return 0;
1877             } else {
1878                 hardware_memory_error();
1879             }
1880         }
1881
1882         if (code == BUS_MCEERR_AR) {
1883             /* Fake an Intel architectural Data Load SRAR UCR */
1884             kvm_mce_inj_srar_dataload(env, paddr);
1885         } else {
1886             /*
1887              * If there is an MCE excpetion being processed, ignore
1888              * this SRAO MCE
1889              */
1890             if (!kvm_mce_in_progress(env)) {
1891                 /* Fake an Intel architectural Memory scrubbing UCR */
1892                 kvm_mce_inj_srao_memscrub(env, paddr);
1893             }
1894         }
1895     } else
1896 #endif
1897     {
1898         if (code == BUS_MCEERR_AO) {
1899             return 0;
1900         } else if (code == BUS_MCEERR_AR) {
1901             hardware_memory_error();
1902         } else {
1903             return 1;
1904         }
1905     }
1906     return 0;
1907 }
1908
1909 int kvm_on_sigbus(int code, void *addr)
1910 {
1911 #if defined(KVM_CAP_MCE)
1912     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1913         void *vaddr;
1914         ram_addr_t ram_addr;
1915         target_phys_addr_t paddr;
1916
1917         /* Hope we are lucky for AO MCE */
1918         vaddr = addr;
1919         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1920             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1921             fprintf(stderr, "Hardware memory error for memory used by "
1922                     "QEMU itself instead of guest system!: %p\n", addr);
1923             return 0;
1924         }
1925         kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
1926     } else
1927 #endif
1928     {
1929         if (code == BUS_MCEERR_AO) {
1930             return 0;
1931         } else if (code == BUS_MCEERR_AR) {
1932             hardware_memory_error();
1933         } else {
1934             return 1;
1935         }
1936     }
1937     return 0;
1938 }