target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21 #include <linux/kvm_para.h>
  22
  23 #include "qemu-common.h"
  24 #include "sysemu/sysemu.h"
  25 #include "sysemu/kvm.h"
  26 #include "kvm_i386.h"
  27 #include "cpu.h"
  28 #include "exec/gdbstub.h"
  29 #include "qemu/host-utils.h"
  30 #include "qemu/config-file.h"
  31 #include "hw/pc.h"
  32 #include "hw/apic.h"
  33 #include "exec/ioport.h"
  34 #include "hyperv.h"
  35 #include "hw/pci/pci.h"
  36
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 static bool has_msr_tsc_adjust;
  67 static bool has_msr_tsc_deadline;
  68 static bool has_msr_async_pf_en;
  69 static bool has_msr_pv_eoi_en;
  70 static bool has_msr_misc_enable;
  71 static int lm_capable_kernel;
  72
  73 bool kvm_allows_irq0_override(void)
  74 {
  75     return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
  76 }
  77
  78 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  79 {
  80     struct kvm_cpuid2 *cpuid;
  81     int r, size;
  82
  83     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  84     cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
  85     cpuid->nent = max;
  86     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  87     if (r == 0 && cpuid->nent >= max) {
  88         r = -E2BIG;
  89     }
  90     if (r < 0) {
  91         if (r == -E2BIG) {
  92             g_free(cpuid);
  93             return NULL;
  94         } else {
  95             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  96                     strerror(-r));
  97             exit(1);
  98         }
  99     }
 100     return cpuid;
 101 }
 102
 103 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
 104  * for all entries.
 105  */
 106 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
 107 {
 108     struct kvm_cpuid2 *cpuid;
 109     int max = 1;
 110     while ((cpuid = try_get_cpuid(s, max)) == NULL) {
 111         max *= 2;
 112     }
 113     return cpuid;
 114 }
 115
 116 struct kvm_para_features {
 117     int cap;
 118     int feature;
 119 } para_features[] = {
 120     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 121     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 122     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 123     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 124     { -1, -1 }
 125 };
 126
 127 static int get_para_features(KVMState *s)
 128 {
 129     int i, features = 0;
 130
 131     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 132         if (kvm_check_extension(s, para_features[i].cap)) {
 133             features |= (1 << para_features[i].feature);
 134         }
 135     }
 136
 137     return features;
 138 }
 139
 140
 141 /* Returns the value for a specific register on the cpuid entry
 142  */
 143 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
 144 {
 145     uint32_t ret = 0;
 146     switch (reg) {
 147     case R_EAX:
 148         ret = entry->eax;
 149         break;
 150     case R_EBX:
 151         ret = entry->ebx;
 152         break;
 153     case R_ECX:
 154         ret = entry->ecx;
 155         break;
 156     case R_EDX:
 157         ret = entry->edx;
 158         break;
 159     }
 160     return ret;
 161 }
 162
 163 /* Find matching entry for function/index on kvm_cpuid2 struct
 164  */
 165 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
 166                                                  uint32_t function,
 167                                                  uint32_t index)
 168 {
 169     int i;
 170     for (i = 0; i < cpuid->nent; ++i) {
 171         if (cpuid->entries[i].function == function &&
 172             cpuid->entries[i].index == index) {
 173             return &cpuid->entries[i];
 174         }
 175     }
 176     /* not found: */
 177     return NULL;
 178 }
 179
 180 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
 181                                       uint32_t index, int reg)
 182 {
 183     struct kvm_cpuid2 *cpuid;
 184     uint32_t ret = 0;
 185     uint32_t cpuid_1_edx;
 186     bool found = false;
 187
 188     cpuid = get_supported_cpuid(s);
 189
 190     struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
 191     if (entry) {
 192         found = true;
 193         ret = cpuid_entry_get_reg(entry, reg);
 194     }
 195
 196     /* Fixups for the data returned by KVM, below */
 197
 198     if (function == 1 && reg == R_EDX) {
 199         /* KVM before 2.6.30 misreports the following features */
 200         ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 201     } else if (function == 1 && reg == R_ECX) {
 202         /* We can set the hypervisor flag, even if KVM does not return it on
 203          * GET_SUPPORTED_CPUID
 204          */
 205         ret |= CPUID_EXT_HYPERVISOR;
 206         /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
 207          * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
 208          * and the irqchip is in the kernel.
 209          */
 210         if (kvm_irqchip_in_kernel() &&
 211                 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
 212             ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
 213         }
 214
 215         /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
 216          * without the in-kernel irqchip
 217          */
 218         if (!kvm_irqchip_in_kernel()) {
 219             ret &= ~CPUID_EXT_X2APIC;
 220         }
 221     } else if (function == 0x80000001 && reg == R_EDX) {
 222         /* On Intel, kvm returns cpuid according to the Intel spec,
 223          * so add missing bits according to the AMD spec:
 224          */
 225         cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
 226         ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
 227     }
 228
 229     g_free(cpuid);
 230
 231     /* fallback for older kernels */
 232     if ((function == KVM_CPUID_FEATURES) && !found) {
 233         ret = get_para_features(s);
 234     }
 235
 236     return ret;
 237 }
 238
 239 typedef struct HWPoisonPage {
 240     ram_addr_t ram_addr;
 241     QLIST_ENTRY(HWPoisonPage) list;
 242 } HWPoisonPage;
 243
 244 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
 245     QLIST_HEAD_INITIALIZER(hwpoison_page_list);
 246
 247 static void kvm_unpoison_all(void *param)
 248 {
 249     HWPoisonPage *page, *next_page;
 250
 251     QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
 252         QLIST_REMOVE(page, list);
 253         qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
 254         g_free(page);
 255     }
 256 }
 257
 258 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
 259 {
 260     HWPoisonPage *page;
 261
 262     QLIST_FOREACH(page, &hwpoison_page_list, list) {
 263         if (page->ram_addr == ram_addr) {
 264             return;
 265         }
 266     }
 267     page = g_malloc(sizeof(HWPoisonPage));
 268     page->ram_addr = ram_addr;
 269     QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
 270 }
 271
 272 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 273                                      int *max_banks)
 274 {
 275     int r;
 276
 277     r = kvm_check_extension(s, KVM_CAP_MCE);
 278     if (r > 0) {
 279         *max_banks = r;
 280         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 281     }
 282     return -ENOSYS;
 283 }
 284
 285 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
 286 {
 287     CPUX86State *env = &cpu->env;
 288     uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 289                       MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
 290     uint64_t mcg_status = MCG_STATUS_MCIP;
 291
 292     if (code == BUS_MCEERR_AR) {
 293         status |= MCI_STATUS_AR | 0x134;
 294         mcg_status |= MCG_STATUS_EIPV;
 295     } else {
 296         status |= 0xc0;
 297         mcg_status |= MCG_STATUS_RIPV;
 298     }
 299     cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
 300                        (MCM_ADDR_PHYS << 6) | 0xc,
 301                        cpu_x86_support_mca_broadcast(env) ?
 302                        MCE_INJECT_BROADCAST : 0);
 303 }
 304
 305 static void hardware_memory_error(void)
 306 {
 307     fprintf(stderr, "Hardware memory error!\n");
 308     exit(1);
 309 }
 310
 311 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
 312 {
 313     X86CPU *cpu = X86_CPU(c);
 314     CPUX86State *env = &cpu->env;
 315     ram_addr_t ram_addr;
 316     hwaddr paddr;
 317
 318     if ((env->mcg_cap & MCG_SER_P) && addr
 319         && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
 320         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 321             !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
 322             fprintf(stderr, "Hardware memory error for memory used by "
 323                     "QEMU itself instead of guest system!\n");
 324             /* Hope we are lucky for AO MCE */
 325             if (code == BUS_MCEERR_AO) {
 326                 return 0;
 327             } else {
 328                 hardware_memory_error();
 329             }
 330         }
 331         kvm_hwpoison_page_add(ram_addr);
 332         kvm_mce_inject(cpu, paddr, code);
 333     } else {
 334         if (code == BUS_MCEERR_AO) {
 335             return 0;
 336         } else if (code == BUS_MCEERR_AR) {
 337             hardware_memory_error();
 338         } else {
 339             return 1;
 340         }
 341     }
 342     return 0;
 343 }
 344
 345 int kvm_arch_on_sigbus(int code, void *addr)
 346 {
 347     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
 348         ram_addr_t ram_addr;
 349         hwaddr paddr;
 350
 351         /* Hope we are lucky for AO MCE */
 352         if (qemu_ram_addr_from_host(addr, &ram_addr) ||
 353             !kvm_physical_memory_addr_from_host(CPU(first_cpu)->kvm_state,
 354                                                 addr, &paddr)) {
 355             fprintf(stderr, "Hardware memory error for memory used by "
 356                     "QEMU itself instead of guest system!: %p\n", addr);
 357             return 0;
 358         }
 359         kvm_hwpoison_page_add(ram_addr);
 360         kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code);
 361     } else {
 362         if (code == BUS_MCEERR_AO) {
 363             return 0;
 364         } else if (code == BUS_MCEERR_AR) {
 365             hardware_memory_error();
 366         } else {
 367             return 1;
 368         }
 369     }
 370     return 0;
 371 }
 372
 373 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
 374 {
 375     CPUX86State *env = &cpu->env;
 376
 377     if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
 378         unsigned int bank, bank_num = env->mcg_cap & 0xff;
 379         struct kvm_x86_mce mce;
 380
 381         env->exception_injected = -1;
 382
 383         /*
 384          * There must be at least one bank in use if an MCE is pending.
 385          * Find it and use its values for the event injection.
 386          */
 387         for (bank = 0; bank < bank_num; bank++) {
 388             if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
 389                 break;
 390             }
 391         }
 392         assert(bank < bank_num);
 393
 394         mce.bank = bank;
 395         mce.status = env->mce_banks[bank * 4 + 1];
 396         mce.mcg_status = env->mcg_status;
 397         mce.addr = env->mce_banks[bank * 4 + 2];
 398         mce.misc = env->mce_banks[bank * 4 + 3];
 399
 400         return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
 401     }
 402     return 0;
 403 }
 404
 405 static void cpu_update_state(void *opaque, int running, RunState state)
 406 {
 407     CPUX86State *env = opaque;
 408
 409     if (running) {
 410         env->tsc_valid = false;
 411     }
 412 }
 413
 414 unsigned long kvm_arch_vcpu_id(CPUState *cs)
 415 {
 416     X86CPU *cpu = X86_CPU(cs);
 417     return cpu->env.cpuid_apic_id;
 418 }
 419
 420 int kvm_arch_init_vcpu(CPUState *cs)
 421 {
 422     struct {
 423         struct kvm_cpuid2 cpuid;
 424         struct kvm_cpuid_entry2 entries[100];
 425     } QEMU_PACKED cpuid_data;
 426     X86CPU *cpu = X86_CPU(cs);
 427     CPUX86State *env = &cpu->env;
 428     uint32_t limit, i, j, cpuid_i;
 429     uint32_t unused;
 430     struct kvm_cpuid_entry2 *c;
 431     uint32_t signature[3];
 432     int r;
 433
 434     cpuid_i = 0;
 435
 436     /* Paravirtualization CPUIDs */
 437     c = &cpuid_data.entries[cpuid_i++];
 438     memset(c, 0, sizeof(*c));
 439     c->function = KVM_CPUID_SIGNATURE;
 440     if (!hyperv_enabled()) {
 441         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 442         c->eax = 0;
 443     } else {
 444         memcpy(signature, "Microsoft Hv", 12);
 445         c->eax = HYPERV_CPUID_MIN;
 446     }
 447     c->ebx = signature[0];
 448     c->ecx = signature[1];
 449     c->edx = signature[2];
 450
 451     c = &cpuid_data.entries[cpuid_i++];
 452     memset(c, 0, sizeof(*c));
 453     c->function = KVM_CPUID_FEATURES;
 454     c->eax = env->cpuid_kvm_features;
 455
 456     if (hyperv_enabled()) {
 457         memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
 458         c->eax = signature[0];
 459
 460         c = &cpuid_data.entries[cpuid_i++];
 461         memset(c, 0, sizeof(*c));
 462         c->function = HYPERV_CPUID_VERSION;
 463         c->eax = 0x00001bbc;
 464         c->ebx = 0x00060001;
 465
 466         c = &cpuid_data.entries[cpuid_i++];
 467         memset(c, 0, sizeof(*c));
 468         c->function = HYPERV_CPUID_FEATURES;
 469         if (hyperv_relaxed_timing_enabled()) {
 470             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 471         }
 472         if (hyperv_vapic_recommended()) {
 473             c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
 474             c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
 475         }
 476
 477         c = &cpuid_data.entries[cpuid_i++];
 478         memset(c, 0, sizeof(*c));
 479         c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
 480         if (hyperv_relaxed_timing_enabled()) {
 481             c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
 482         }
 483         if (hyperv_vapic_recommended()) {
 484             c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
 485         }
 486         c->ebx = hyperv_get_spinlock_retries();
 487
 488         c = &cpuid_data.entries[cpuid_i++];
 489         memset(c, 0, sizeof(*c));
 490         c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
 491         c->eax = 0x40;
 492         c->ebx = 0x40;
 493
 494         c = &cpuid_data.entries[cpuid_i++];
 495         memset(c, 0, sizeof(*c));
 496         c->function = KVM_CPUID_SIGNATURE_NEXT;
 497         memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 498         c->eax = 0;
 499         c->ebx = signature[0];
 500         c->ecx = signature[1];
 501         c->edx = signature[2];
 502     }
 503
 504     has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
 505
 506     has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
 507
 508     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 509
 510     for (i = 0; i <= limit; i++) {
 511         c = &cpuid_data.entries[cpuid_i++];
 512
 513         switch (i) {
 514         case 2: {
 515             /* Keep reading function 2 till all the input is received */
 516             int times;
 517
 518             c->function = i;
 519             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 520                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 521             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 522             times = c->eax & 0xff;
 523
 524             for (j = 1; j < times; ++j) {
 525                 c = &cpuid_data.entries[cpuid_i++];
 526                 c->function = i;
 527                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 528                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 529             }
 530             break;
 531         }
 532         case 4:
 533         case 0xb:
 534         case 0xd:
 535             for (j = 0; ; j++) {
 536                 if (i == 0xd && j == 64) {
 537                     break;
 538                 }
 539                 c->function = i;
 540                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 541                 c->index = j;
 542                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 543
 544                 if (i == 4 && c->eax == 0) {
 545                     break;
 546                 }
 547                 if (i == 0xb && !(c->ecx & 0xff00)) {
 548                     break;
 549                 }
 550                 if (i == 0xd && c->eax == 0) {
 551                     continue;
 552                 }
 553                 c = &cpuid_data.entries[cpuid_i++];
 554             }
 555             break;
 556         default:
 557             c->function = i;
 558             c->flags = 0;
 559             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 560             break;
 561         }
 562     }
 563     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 564
 565     for (i = 0x80000000; i <= limit; i++) {
 566         c = &cpuid_data.entries[cpuid_i++];
 567
 568         c->function = i;
 569         c->flags = 0;
 570         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 571     }
 572
 573     /* Call Centaur's CPUID instructions they are supported. */
 574     if (env->cpuid_xlevel2 > 0) {
 575         cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
 576
 577         for (i = 0xC0000000; i <= limit; i++) {
 578             c = &cpuid_data.entries[cpuid_i++];
 579
 580             c->function = i;
 581             c->flags = 0;
 582             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 583         }
 584     }
 585
 586     cpuid_data.cpuid.nent = cpuid_i;
 587
 588     if (((env->cpuid_version >> 8)&0xF) >= 6
 589         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 590         && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
 591         uint64_t mcg_cap;
 592         int banks;
 593         int ret;
 594
 595         ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
 596         if (ret < 0) {
 597             fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
 598             return ret;
 599         }
 600
 601         if (banks > MCE_BANKS_DEF) {
 602             banks = MCE_BANKS_DEF;
 603         }
 604         mcg_cap &= MCE_CAP_DEF;
 605         mcg_cap |= banks;
 606         ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
 607         if (ret < 0) {
 608             fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
 609             return ret;
 610         }
 611
 612         env->mcg_cap = mcg_cap;
 613     }
 614
 615     qemu_add_vm_change_state_handler(cpu_update_state, env);
 616
 617     cpuid_data.cpuid.padding = 0;
 618     r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
 619     if (r) {
 620         return r;
 621     }
 622
 623     r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
 624     if (r && env->tsc_khz) {
 625         r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
 626         if (r < 0) {
 627             fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
 628             return r;
 629         }
 630     }
 631
 632     if (kvm_has_xsave()) {
 633         env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
 634     }
 635
 636     return 0;
 637 }
 638
 639 void kvm_arch_reset_vcpu(CPUState *cs)
 640 {
 641     X86CPU *cpu = X86_CPU(cs);
 642     CPUX86State *env = &cpu->env;
 643
 644     env->exception_injected = -1;
 645     env->interrupt_injected = -1;
 646     env->xcr0 = 1;
 647     if (kvm_irqchip_in_kernel()) {
 648         env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
 649                                           KVM_MP_STATE_UNINITIALIZED;
 650     } else {
 651         env->mp_state = KVM_MP_STATE_RUNNABLE;
 652     }
 653 }
 654
 655 static int kvm_get_supported_msrs(KVMState *s)
 656 {
 657     static int kvm_supported_msrs;
 658     int ret = 0;
 659
 660     /* first time */
 661     if (kvm_supported_msrs == 0) {
 662         struct kvm_msr_list msr_list, *kvm_msr_list;
 663
 664         kvm_supported_msrs = -1;
 665
 666         /* Obtain MSR list from KVM.  These are the MSRs that we must
 667          * save/restore */
 668         msr_list.nmsrs = 0;
 669         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 670         if (ret < 0 && ret != -E2BIG) {
 671             return ret;
 672         }
 673         /* Old kernel modules had a bug and could write beyond the provided
 674            memory. Allocate at least a safe amount of 1K. */
 675         kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
 676                                               msr_list.nmsrs *
 677                                               sizeof(msr_list.indices[0])));
 678
 679         kvm_msr_list->nmsrs = msr_list.nmsrs;
 680         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 681         if (ret >= 0) {
 682             int i;
 683
 684             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 685                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 686                     has_msr_star = true;
 687                     continue;
 688                 }
 689                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 690                     has_msr_hsave_pa = true;
 691                     continue;
 692                 }
 693                 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
 694                     has_msr_tsc_adjust = true;
 695                     continue;
 696                 }
 697                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
 698                     has_msr_tsc_deadline = true;
 699                     continue;
 700                 }
 701                 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
 702                     has_msr_misc_enable = true;
 703                     continue;
 704                 }
 705             }
 706         }
 707
 708         g_free(kvm_msr_list);
 709     }
 710
 711     return ret;
 712 }
 713
 714 int kvm_arch_init(KVMState *s)
 715 {
 716     QemuOptsList *list = qemu_find_opts("machine");
 717     uint64_t identity_base = 0xfffbc000;
 718     uint64_t shadow_mem;
 719     int ret;
 720     struct utsname utsname;
 721
 722     ret = kvm_get_supported_msrs(s);
 723     if (ret < 0) {
 724         return ret;
 725     }
 726
 727     uname(&utsname);
 728     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 729
 730     /*
 731      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 732      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 733      * Since these must be part of guest physical memory, we need to allocate
 734      * them, both by setting their start addresses in the kernel and by
 735      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 736      *
 737      * Older KVM versions may not support setting the identity map base. In
 738      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 739      * size.
 740      */
 741     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 742         /* Allows up to 16M BIOSes. */
 743         identity_base = 0xfeffc000;
 744
 745         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 746         if (ret < 0) {
 747             return ret;
 748         }
 749     }
 750
 751     /* Set TSS base one page after EPT identity map. */
 752     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 753     if (ret < 0) {
 754         return ret;
 755     }
 756
 757     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 758     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 759     if (ret < 0) {
 760         fprintf(stderr, "e820_add_entry() table is full\n");
 761         return ret;
 762     }
 763     qemu_register_reset(kvm_unpoison_all, NULL);
 764
 765     if (!QTAILQ_EMPTY(&list->head)) {
 766         shadow_mem = qemu_opt_get_size(QTAILQ_FIRST(&list->head),
 767                                        "kvm_shadow_mem", -1);
 768         if (shadow_mem != -1) {
 769             shadow_mem /= 4096;
 770             ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
 771             if (ret < 0) {
 772                 return ret;
 773             }
 774         }
 775     }
 776     return 0;
 777 }
 778
 779 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 780 {
 781     lhs->selector = rhs->selector;
 782     lhs->base = rhs->base;
 783     lhs->limit = rhs->limit;
 784     lhs->type = 3;
 785     lhs->present = 1;
 786     lhs->dpl = 3;
 787     lhs->db = 0;
 788     lhs->s = 1;
 789     lhs->l = 0;
 790     lhs->g = 0;
 791     lhs->avl = 0;
 792     lhs->unusable = 0;
 793 }
 794
 795 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 796 {
 797     unsigned flags = rhs->flags;
 798     lhs->selector = rhs->selector;
 799     lhs->base = rhs->base;
 800     lhs->limit = rhs->limit;
 801     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 802     lhs->present = (flags & DESC_P_MASK) != 0;
 803     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 804     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 805     lhs->s = (flags & DESC_S_MASK) != 0;
 806     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 807     lhs->g = (flags & DESC_G_MASK) != 0;
 808     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 809     lhs->unusable = 0;
 810     lhs->padding = 0;
 811 }
 812
 813 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 814 {
 815     lhs->selector = rhs->selector;
 816     lhs->base = rhs->base;
 817     lhs->limit = rhs->limit;
 818     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 819                  (rhs->present * DESC_P_MASK) |
 820                  (rhs->dpl << DESC_DPL_SHIFT) |
 821                  (rhs->db << DESC_B_SHIFT) |
 822                  (rhs->s * DESC_S_MASK) |
 823                  (rhs->l << DESC_L_SHIFT) |
 824                  (rhs->g * DESC_G_MASK) |
 825                  (rhs->avl * DESC_AVL_MASK);
 826 }
 827
 828 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 829 {
 830     if (set) {
 831         *kvm_reg = *qemu_reg;
 832     } else {
 833         *qemu_reg = *kvm_reg;
 834     }
 835 }
 836
 837 static int kvm_getput_regs(X86CPU *cpu, int set)
 838 {
 839     CPUX86State *env = &cpu->env;
 840     struct kvm_regs regs;
 841     int ret = 0;
 842
 843     if (!set) {
 844         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
 845         if (ret < 0) {
 846             return ret;
 847         }
 848     }
 849
 850     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 851     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 852     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 853     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 854     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 855     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 856     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 857     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 858 #ifdef TARGET_X86_64
 859     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 860     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 861     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 862     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 863     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 864     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 865     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 866     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 867 #endif
 868
 869     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 870     kvm_getput_reg(&regs.rip, &env->eip, set);
 871
 872     if (set) {
 873         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
 874     }
 875
 876     return ret;
 877 }
 878
 879 static int kvm_put_fpu(X86CPU *cpu)
 880 {
 881     CPUX86State *env = &cpu->env;
 882     struct kvm_fpu fpu;
 883     int i;
 884
 885     memset(&fpu, 0, sizeof fpu);
 886     fpu.fsw = env->fpus & ~(7 << 11);
 887     fpu.fsw |= (env->fpstt & 7) << 11;
 888     fpu.fcw = env->fpuc;
 889     fpu.last_opcode = env->fpop;
 890     fpu.last_ip = env->fpip;
 891     fpu.last_dp = env->fpdp;
 892     for (i = 0; i < 8; ++i) {
 893         fpu.ftwx |= (!env->fptags[i]) << i;
 894     }
 895     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 896     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 897     fpu.mxcsr = env->mxcsr;
 898
 899     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
 900 }
 901
 902 #define XSAVE_FCW_FSW     0
 903 #define XSAVE_FTW_FOP     1
 904 #define XSAVE_CWD_RIP     2
 905 #define XSAVE_CWD_RDP     4
 906 #define XSAVE_MXCSR       6
 907 #define XSAVE_ST_SPACE    8
 908 #define XSAVE_XMM_SPACE   40
 909 #define XSAVE_XSTATE_BV   128
 910 #define XSAVE_YMMH_SPACE  144
 911
 912 static int kvm_put_xsave(X86CPU *cpu)
 913 {
 914     CPUX86State *env = &cpu->env;
 915     struct kvm_xsave* xsave = env->kvm_xsave_buf;
 916     uint16_t cwd, swd, twd;
 917     int i, r;
 918
 919     if (!kvm_has_xsave()) {
 920         return kvm_put_fpu(cpu);
 921     }
 922
 923     memset(xsave, 0, sizeof(struct kvm_xsave));
 924     twd = 0;
 925     swd = env->fpus & ~(7 << 11);
 926     swd |= (env->fpstt & 7) << 11;
 927     cwd = env->fpuc;
 928     for (i = 0; i < 8; ++i) {
 929         twd |= (!env->fptags[i]) << i;
 930     }
 931     xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
 932     xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
 933     memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
 934     memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
 935     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 936             sizeof env->fpregs);
 937     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 938             sizeof env->xmm_regs);
 939     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 940     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 941     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 942             sizeof env->ymmh_regs);
 943     r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
 944     return r;
 945 }
 946
 947 static int kvm_put_xcrs(X86CPU *cpu)
 948 {
 949     CPUX86State *env = &cpu->env;
 950     struct kvm_xcrs xcrs;
 951
 952     if (!kvm_has_xcrs()) {
 953         return 0;
 954     }
 955
 956     xcrs.nr_xcrs = 1;
 957     xcrs.flags = 0;
 958     xcrs.xcrs[0].xcr = 0;
 959     xcrs.xcrs[0].value = env->xcr0;
 960     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
 961 }
 962
 963 static int kvm_put_sregs(X86CPU *cpu)
 964 {
 965     CPUX86State *env = &cpu->env;
 966     struct kvm_sregs sregs;
 967
 968     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 969     if (env->interrupt_injected >= 0) {
 970         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 971                 (uint64_t)1 << (env->interrupt_injected % 64);
 972     }
 973
 974     if ((env->eflags & VM_MASK)) {
 975         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 976         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 977         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 978         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 979         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 980         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 981     } else {
 982         set_seg(&sregs.cs, &env->segs[R_CS]);
 983         set_seg(&sregs.ds, &env->segs[R_DS]);
 984         set_seg(&sregs.es, &env->segs[R_ES]);
 985         set_seg(&sregs.fs, &env->segs[R_FS]);
 986         set_seg(&sregs.gs, &env->segs[R_GS]);
 987         set_seg(&sregs.ss, &env->segs[R_SS]);
 988     }
 989
 990     set_seg(&sregs.tr, &env->tr);
 991     set_seg(&sregs.ldt, &env->ldt);
 992
 993     sregs.idt.limit = env->idt.limit;
 994     sregs.idt.base = env->idt.base;
 995     memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
 996     sregs.gdt.limit = env->gdt.limit;
 997     sregs.gdt.base = env->gdt.base;
 998     memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
 999
1000     sregs.cr0 = env->cr[0];
1001     sregs.cr2 = env->cr[2];
1002     sregs.cr3 = env->cr[3];
1003     sregs.cr4 = env->cr[4];
1004
1005     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1006     sregs.apic_base = cpu_get_apic_base(env->apic_state);
1007
1008     sregs.efer = env->efer;
1009
1010     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1011 }
1012
1013 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1014                               uint32_t index, uint64_t value)
1015 {
1016     entry->index = index;
1017     entry->data = value;
1018 }
1019
1020 static int kvm_put_msrs(X86CPU *cpu, int level)
1021 {
1022     CPUX86State *env = &cpu->env;
1023     struct {
1024         struct kvm_msrs info;
1025         struct kvm_msr_entry entries[100];
1026     } msr_data;
1027     struct kvm_msr_entry *msrs = msr_data.entries;
1028     int n = 0;
1029
1030     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1031     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1032     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1033     kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1034     if (has_msr_star) {
1035         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1036     }
1037     if (has_msr_hsave_pa) {
1038         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1039     }
1040     if (has_msr_tsc_adjust) {
1041         kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1042     }
1043     if (has_msr_tsc_deadline) {
1044         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1045     }
1046     if (has_msr_misc_enable) {
1047         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1048                           env->msr_ia32_misc_enable);
1049     }
1050 #ifdef TARGET_X86_64
1051     if (lm_capable_kernel) {
1052         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1053         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1054         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1055         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1056     }
1057 #endif
1058     if (level == KVM_PUT_FULL_STATE) {
1059         /*
1060          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1061          * writeback. Until this is fixed, we only write the offset to SMP
1062          * guests after migration, desynchronizing the VCPUs, but avoiding
1063          * huge jump-backs that would occur without any writeback at all.
1064          */
1065         if (smp_cpus == 1 || env->tsc != 0) {
1066             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1067         }
1068     }
1069     /*
1070      * The following paravirtual MSRs have side effects on the guest or are
1071      * too heavy for normal writeback. Limit them to reset or full state
1072      * updates.
1073      */
1074     if (level >= KVM_PUT_RESET_STATE) {
1075         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1076                           env->system_time_msr);
1077         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1078         if (has_msr_async_pf_en) {
1079             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1080                               env->async_pf_en_msr);
1081         }
1082         if (has_msr_pv_eoi_en) {
1083             kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1084                               env->pv_eoi_en_msr);
1085         }
1086         if (hyperv_hypercall_available()) {
1087             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1088             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1089         }
1090         if (hyperv_vapic_recommended()) {
1091             kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1092         }
1093     }
1094     if (env->mcg_cap) {
1095         int i;
1096
1097         kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1098         kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1099         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1100             kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1101         }
1102     }
1103
1104     msr_data.info.nmsrs = n;
1105
1106     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1107
1108 }
1109
1110
1111 static int kvm_get_fpu(X86CPU *cpu)
1112 {
1113     CPUX86State *env = &cpu->env;
1114     struct kvm_fpu fpu;
1115     int i, ret;
1116
1117     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1118     if (ret < 0) {
1119         return ret;
1120     }
1121
1122     env->fpstt = (fpu.fsw >> 11) & 7;
1123     env->fpus = fpu.fsw;
1124     env->fpuc = fpu.fcw;
1125     env->fpop = fpu.last_opcode;
1126     env->fpip = fpu.last_ip;
1127     env->fpdp = fpu.last_dp;
1128     for (i = 0; i < 8; ++i) {
1129         env->fptags[i] = !((fpu.ftwx >> i) & 1);
1130     }
1131     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1132     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1133     env->mxcsr = fpu.mxcsr;
1134
1135     return 0;
1136 }
1137
1138 static int kvm_get_xsave(X86CPU *cpu)
1139 {
1140     CPUX86State *env = &cpu->env;
1141     struct kvm_xsave* xsave = env->kvm_xsave_buf;
1142     int ret, i;
1143     uint16_t cwd, swd, twd;
1144
1145     if (!kvm_has_xsave()) {
1146         return kvm_get_fpu(cpu);
1147     }
1148
1149     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1150     if (ret < 0) {
1151         return ret;
1152     }
1153
1154     cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1155     swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1156     twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1157     env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1158     env->fpstt = (swd >> 11) & 7;
1159     env->fpus = swd;
1160     env->fpuc = cwd;
1161     for (i = 0; i < 8; ++i) {
1162         env->fptags[i] = !((twd >> i) & 1);
1163     }
1164     memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1165     memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1166     env->mxcsr = xsave->region[XSAVE_MXCSR];
1167     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1168             sizeof env->fpregs);
1169     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1170             sizeof env->xmm_regs);
1171     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1172     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1173             sizeof env->ymmh_regs);
1174     return 0;
1175 }
1176
1177 static int kvm_get_xcrs(X86CPU *cpu)
1178 {
1179     CPUX86State *env = &cpu->env;
1180     int i, ret;
1181     struct kvm_xcrs xcrs;
1182
1183     if (!kvm_has_xcrs()) {
1184         return 0;
1185     }
1186
1187     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1188     if (ret < 0) {
1189         return ret;
1190     }
1191
1192     for (i = 0; i < xcrs.nr_xcrs; i++) {
1193         /* Only support xcr0 now */
1194         if (xcrs.xcrs[0].xcr == 0) {
1195             env->xcr0 = xcrs.xcrs[0].value;
1196             break;
1197         }
1198     }
1199     return 0;
1200 }
1201
1202 static int kvm_get_sregs(X86CPU *cpu)
1203 {
1204     CPUX86State *env = &cpu->env;
1205     struct kvm_sregs sregs;
1206     uint32_t hflags;
1207     int bit, i, ret;
1208
1209     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1210     if (ret < 0) {
1211         return ret;
1212     }
1213
1214     /* There can only be one pending IRQ set in the bitmap at a time, so try
1215        to find it and save its number instead (-1 for none). */
1216     env->interrupt_injected = -1;
1217     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1218         if (sregs.interrupt_bitmap[i]) {
1219             bit = ctz64(sregs.interrupt_bitmap[i]);
1220             env->interrupt_injected = i * 64 + bit;
1221             break;
1222         }
1223     }
1224
1225     get_seg(&env->segs[R_CS], &sregs.cs);
1226     get_seg(&env->segs[R_DS], &sregs.ds);
1227     get_seg(&env->segs[R_ES], &sregs.es);
1228     get_seg(&env->segs[R_FS], &sregs.fs);
1229     get_seg(&env->segs[R_GS], &sregs.gs);
1230     get_seg(&env->segs[R_SS], &sregs.ss);
1231
1232     get_seg(&env->tr, &sregs.tr);
1233     get_seg(&env->ldt, &sregs.ldt);
1234
1235     env->idt.limit = sregs.idt.limit;
1236     env->idt.base = sregs.idt.base;
1237     env->gdt.limit = sregs.gdt.limit;
1238     env->gdt.base = sregs.gdt.base;
1239
1240     env->cr[0] = sregs.cr0;
1241     env->cr[2] = sregs.cr2;
1242     env->cr[3] = sregs.cr3;
1243     env->cr[4] = sregs.cr4;
1244
1245     env->efer = sregs.efer;
1246
1247     /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1248
1249 #define HFLAG_COPY_MASK \
1250     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1251        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1252        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1253        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1254
1255     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1256     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1257     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1258                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1259     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1260     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1261                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1262
1263     if (env->efer & MSR_EFER_LMA) {
1264         hflags |= HF_LMA_MASK;
1265     }
1266
1267     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1268         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1269     } else {
1270         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1271                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1272         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1273                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1274         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1275             !(hflags & HF_CS32_MASK)) {
1276             hflags |= HF_ADDSEG_MASK;
1277         } else {
1278             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1279                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1280         }
1281     }
1282     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1283
1284     return 0;
1285 }
1286
1287 static int kvm_get_msrs(X86CPU *cpu)
1288 {
1289     CPUX86State *env = &cpu->env;
1290     struct {
1291         struct kvm_msrs info;
1292         struct kvm_msr_entry entries[100];
1293     } msr_data;
1294     struct kvm_msr_entry *msrs = msr_data.entries;
1295     int ret, i, n;
1296
1297     n = 0;
1298     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1299     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1300     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1301     msrs[n++].index = MSR_PAT;
1302     if (has_msr_star) {
1303         msrs[n++].index = MSR_STAR;
1304     }
1305     if (has_msr_hsave_pa) {
1306         msrs[n++].index = MSR_VM_HSAVE_PA;
1307     }
1308     if (has_msr_tsc_adjust) {
1309         msrs[n++].index = MSR_TSC_ADJUST;
1310     }
1311     if (has_msr_tsc_deadline) {
1312         msrs[n++].index = MSR_IA32_TSCDEADLINE;
1313     }
1314     if (has_msr_misc_enable) {
1315         msrs[n++].index = MSR_IA32_MISC_ENABLE;
1316     }
1317
1318     if (!env->tsc_valid) {
1319         msrs[n++].index = MSR_IA32_TSC;
1320         env->tsc_valid = !runstate_is_running();
1321     }
1322
1323 #ifdef TARGET_X86_64
1324     if (lm_capable_kernel) {
1325         msrs[n++].index = MSR_CSTAR;
1326         msrs[n++].index = MSR_KERNELGSBASE;
1327         msrs[n++].index = MSR_FMASK;
1328         msrs[n++].index = MSR_LSTAR;
1329     }
1330 #endif
1331     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1332     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1333     if (has_msr_async_pf_en) {
1334         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1335     }
1336     if (has_msr_pv_eoi_en) {
1337         msrs[n++].index = MSR_KVM_PV_EOI_EN;
1338     }
1339
1340     if (env->mcg_cap) {
1341         msrs[n++].index = MSR_MCG_STATUS;
1342         msrs[n++].index = MSR_MCG_CTL;
1343         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1344             msrs[n++].index = MSR_MC0_CTL + i;
1345         }
1346     }
1347
1348     msr_data.info.nmsrs = n;
1349     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1350     if (ret < 0) {
1351         return ret;
1352     }
1353
1354     for (i = 0; i < ret; i++) {
1355         switch (msrs[i].index) {
1356         case MSR_IA32_SYSENTER_CS:
1357             env->sysenter_cs = msrs[i].data;
1358             break;
1359         case MSR_IA32_SYSENTER_ESP:
1360             env->sysenter_esp = msrs[i].data;
1361             break;
1362         case MSR_IA32_SYSENTER_EIP:
1363             env->sysenter_eip = msrs[i].data;
1364             break;
1365         case MSR_PAT:
1366             env->pat = msrs[i].data;
1367             break;
1368         case MSR_STAR:
1369             env->star = msrs[i].data;
1370             break;
1371 #ifdef TARGET_X86_64
1372         case MSR_CSTAR:
1373             env->cstar = msrs[i].data;
1374             break;
1375         case MSR_KERNELGSBASE:
1376             env->kernelgsbase = msrs[i].data;
1377             break;
1378         case MSR_FMASK:
1379             env->fmask = msrs[i].data;
1380             break;
1381         case MSR_LSTAR:
1382             env->lstar = msrs[i].data;
1383             break;
1384 #endif
1385         case MSR_IA32_TSC:
1386             env->tsc = msrs[i].data;
1387             break;
1388         case MSR_TSC_ADJUST:
1389             env->tsc_adjust = msrs[i].data;
1390             break;
1391         case MSR_IA32_TSCDEADLINE:
1392             env->tsc_deadline = msrs[i].data;
1393             break;
1394         case MSR_VM_HSAVE_PA:
1395             env->vm_hsave = msrs[i].data;
1396             break;
1397         case MSR_KVM_SYSTEM_TIME:
1398             env->system_time_msr = msrs[i].data;
1399             break;
1400         case MSR_KVM_WALL_CLOCK:
1401             env->wall_clock_msr = msrs[i].data;
1402             break;
1403         case MSR_MCG_STATUS:
1404             env->mcg_status = msrs[i].data;
1405             break;
1406         case MSR_MCG_CTL:
1407             env->mcg_ctl = msrs[i].data;
1408             break;
1409         case MSR_IA32_MISC_ENABLE:
1410             env->msr_ia32_misc_enable = msrs[i].data;
1411             break;
1412         default:
1413             if (msrs[i].index >= MSR_MC0_CTL &&
1414                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1415                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1416             }
1417             break;
1418         case MSR_KVM_ASYNC_PF_EN:
1419             env->async_pf_en_msr = msrs[i].data;
1420             break;
1421         case MSR_KVM_PV_EOI_EN:
1422             env->pv_eoi_en_msr = msrs[i].data;
1423             break;
1424         }
1425     }
1426
1427     return 0;
1428 }
1429
1430 static int kvm_put_mp_state(X86CPU *cpu)
1431 {
1432     struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1433
1434     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1435 }
1436
1437 static int kvm_get_mp_state(X86CPU *cpu)
1438 {
1439     CPUX86State *env = &cpu->env;
1440     struct kvm_mp_state mp_state;
1441     int ret;
1442
1443     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MP_STATE, &mp_state);
1444     if (ret < 0) {
1445         return ret;
1446     }
1447     env->mp_state = mp_state.mp_state;
1448     if (kvm_irqchip_in_kernel()) {
1449         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1450     }
1451     return 0;
1452 }
1453
1454 static int kvm_get_apic(X86CPU *cpu)
1455 {
1456     CPUX86State *env = &cpu->env;
1457     DeviceState *apic = env->apic_state;
1458     struct kvm_lapic_state kapic;
1459     int ret;
1460
1461     if (apic && kvm_irqchip_in_kernel()) {
1462         ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1463         if (ret < 0) {
1464             return ret;
1465         }
1466
1467         kvm_get_apic_state(apic, &kapic);
1468     }
1469     return 0;
1470 }
1471
1472 static int kvm_put_apic(X86CPU *cpu)
1473 {
1474     CPUX86State *env = &cpu->env;
1475     DeviceState *apic = env->apic_state;
1476     struct kvm_lapic_state kapic;
1477
1478     if (apic && kvm_irqchip_in_kernel()) {
1479         kvm_put_apic_state(apic, &kapic);
1480
1481         return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1482     }
1483     return 0;
1484 }
1485
1486 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1487 {
1488     CPUX86State *env = &cpu->env;
1489     struct kvm_vcpu_events events;
1490
1491     if (!kvm_has_vcpu_events()) {
1492         return 0;
1493     }
1494
1495     events.exception.injected = (env->exception_injected >= 0);
1496     events.exception.nr = env->exception_injected;
1497     events.exception.has_error_code = env->has_error_code;
1498     events.exception.error_code = env->error_code;
1499     events.exception.pad = 0;
1500
1501     events.interrupt.injected = (env->interrupt_injected >= 0);
1502     events.interrupt.nr = env->interrupt_injected;
1503     events.interrupt.soft = env->soft_interrupt;
1504
1505     events.nmi.injected = env->nmi_injected;
1506     events.nmi.pending = env->nmi_pending;
1507     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1508     events.nmi.pad = 0;
1509
1510     events.sipi_vector = env->sipi_vector;
1511
1512     events.flags = 0;
1513     if (level >= KVM_PUT_RESET_STATE) {
1514         events.flags |=
1515             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1516     }
1517
1518     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1519 }
1520
1521 static int kvm_get_vcpu_events(X86CPU *cpu)
1522 {
1523     CPUX86State *env = &cpu->env;
1524     struct kvm_vcpu_events events;
1525     int ret;
1526
1527     if (!kvm_has_vcpu_events()) {
1528         return 0;
1529     }
1530
1531     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1532     if (ret < 0) {
1533        return ret;
1534     }
1535     env->exception_injected =
1536        events.exception.injected ? events.exception.nr : -1;
1537     env->has_error_code = events.exception.has_error_code;
1538     env->error_code = events.exception.error_code;
1539
1540     env->interrupt_injected =
1541         events.interrupt.injected ? events.interrupt.nr : -1;
1542     env->soft_interrupt = events.interrupt.soft;
1543
1544     env->nmi_injected = events.nmi.injected;
1545     env->nmi_pending = events.nmi.pending;
1546     if (events.nmi.masked) {
1547         env->hflags2 |= HF2_NMI_MASK;
1548     } else {
1549         env->hflags2 &= ~HF2_NMI_MASK;
1550     }
1551
1552     env->sipi_vector = events.sipi_vector;
1553
1554     return 0;
1555 }
1556
1557 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1558 {
1559     CPUX86State *env = &cpu->env;
1560     int ret = 0;
1561     unsigned long reinject_trap = 0;
1562
1563     if (!kvm_has_vcpu_events()) {
1564         if (env->exception_injected == 1) {
1565             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1566         } else if (env->exception_injected == 3) {
1567             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1568         }
1569         env->exception_injected = -1;
1570     }
1571
1572     /*
1573      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1574      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1575      * by updating the debug state once again if single-stepping is on.
1576      * Another reason to call kvm_update_guest_debug here is a pending debug
1577      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1578      * reinject them via SET_GUEST_DEBUG.
1579      */
1580     if (reinject_trap ||
1581         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1582         ret = kvm_update_guest_debug(env, reinject_trap);
1583     }
1584     return ret;
1585 }
1586
1587 static int kvm_put_debugregs(X86CPU *cpu)
1588 {
1589     CPUX86State *env = &cpu->env;
1590     struct kvm_debugregs dbgregs;
1591     int i;
1592
1593     if (!kvm_has_debugregs()) {
1594         return 0;
1595     }
1596
1597     for (i = 0; i < 4; i++) {
1598         dbgregs.db[i] = env->dr[i];
1599     }
1600     dbgregs.dr6 = env->dr[6];
1601     dbgregs.dr7 = env->dr[7];
1602     dbgregs.flags = 0;
1603
1604     return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1605 }
1606
1607 static int kvm_get_debugregs(X86CPU *cpu)
1608 {
1609     CPUX86State *env = &cpu->env;
1610     struct kvm_debugregs dbgregs;
1611     int i, ret;
1612
1613     if (!kvm_has_debugregs()) {
1614         return 0;
1615     }
1616
1617     ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1618     if (ret < 0) {
1619         return ret;
1620     }
1621     for (i = 0; i < 4; i++) {
1622         env->dr[i] = dbgregs.db[i];
1623     }
1624     env->dr[4] = env->dr[6] = dbgregs.dr6;
1625     env->dr[5] = env->dr[7] = dbgregs.dr7;
1626
1627     return 0;
1628 }
1629
1630 int kvm_arch_put_registers(CPUState *cpu, int level)
1631 {
1632     X86CPU *x86_cpu = X86_CPU(cpu);
1633     int ret;
1634
1635     assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1636
1637     ret = kvm_getput_regs(x86_cpu, 1);
1638     if (ret < 0) {
1639         return ret;
1640     }
1641     ret = kvm_put_xsave(x86_cpu);
1642     if (ret < 0) {
1643         return ret;
1644     }
1645     ret = kvm_put_xcrs(x86_cpu);
1646     if (ret < 0) {
1647         return ret;
1648     }
1649     ret = kvm_put_sregs(x86_cpu);
1650     if (ret < 0) {
1651         return ret;
1652     }
1653     /* must be before kvm_put_msrs */
1654     ret = kvm_inject_mce_oldstyle(x86_cpu);
1655     if (ret < 0) {
1656         return ret;
1657     }
1658     ret = kvm_put_msrs(x86_cpu, level);
1659     if (ret < 0) {
1660         return ret;
1661     }
1662     if (level >= KVM_PUT_RESET_STATE) {
1663         ret = kvm_put_mp_state(x86_cpu);
1664         if (ret < 0) {
1665             return ret;
1666         }
1667         ret = kvm_put_apic(x86_cpu);
1668         if (ret < 0) {
1669             return ret;
1670         }
1671     }
1672     ret = kvm_put_vcpu_events(x86_cpu, level);
1673     if (ret < 0) {
1674         return ret;
1675     }
1676     ret = kvm_put_debugregs(x86_cpu);
1677     if (ret < 0) {
1678         return ret;
1679     }
1680     /* must be last */
1681     ret = kvm_guest_debug_workarounds(x86_cpu);
1682     if (ret < 0) {
1683         return ret;
1684     }
1685     return 0;
1686 }
1687
1688 int kvm_arch_get_registers(CPUState *cs)
1689 {
1690     X86CPU *cpu = X86_CPU(cs);
1691     int ret;
1692
1693     assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1694
1695     ret = kvm_getput_regs(cpu, 0);
1696     if (ret < 0) {
1697         return ret;
1698     }
1699     ret = kvm_get_xsave(cpu);
1700     if (ret < 0) {
1701         return ret;
1702     }
1703     ret = kvm_get_xcrs(cpu);
1704     if (ret < 0) {
1705         return ret;
1706     }
1707     ret = kvm_get_sregs(cpu);
1708     if (ret < 0) {
1709         return ret;
1710     }
1711     ret = kvm_get_msrs(cpu);
1712     if (ret < 0) {
1713         return ret;
1714     }
1715     ret = kvm_get_mp_state(cpu);
1716     if (ret < 0) {
1717         return ret;
1718     }
1719     ret = kvm_get_apic(cpu);
1720     if (ret < 0) {
1721         return ret;
1722     }
1723     ret = kvm_get_vcpu_events(cpu);
1724     if (ret < 0) {
1725         return ret;
1726     }
1727     ret = kvm_get_debugregs(cpu);
1728     if (ret < 0) {
1729         return ret;
1730     }
1731     return 0;
1732 }
1733
1734 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1735 {
1736     X86CPU *x86_cpu = X86_CPU(cpu);
1737     CPUX86State *env = &x86_cpu->env;
1738     int ret;
1739
1740     /* Inject NMI */
1741     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1742         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1743         DPRINTF("injected NMI\n");
1744         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1745         if (ret < 0) {
1746             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1747                     strerror(-ret));
1748         }
1749     }
1750
1751     if (!kvm_irqchip_in_kernel()) {
1752         /* Force the VCPU out of its inner loop to process any INIT requests
1753          * or pending TPR access reports. */
1754         if (env->interrupt_request &
1755             (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1756             env->exit_request = 1;
1757         }
1758
1759         /* Try to inject an interrupt if the guest can accept it */
1760         if (run->ready_for_interrupt_injection &&
1761             (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1762             (env->eflags & IF_MASK)) {
1763             int irq;
1764
1765             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1766             irq = cpu_get_pic_interrupt(env);
1767             if (irq >= 0) {
1768                 struct kvm_interrupt intr;
1769
1770                 intr.irq = irq;
1771                 DPRINTF("injected interrupt %d\n", irq);
1772                 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1773                 if (ret < 0) {
1774                     fprintf(stderr,
1775                             "KVM: injection failed, interrupt lost (%s)\n",
1776                             strerror(-ret));
1777                 }
1778             }
1779         }
1780
1781         /* If we have an interrupt but the guest is not ready to receive an
1782          * interrupt, request an interrupt window exit.  This will
1783          * cause a return to userspace as soon as the guest is ready to
1784          * receive interrupts. */
1785         if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1786             run->request_interrupt_window = 1;
1787         } else {
1788             run->request_interrupt_window = 0;
1789         }
1790
1791         DPRINTF("setting tpr\n");
1792         run->cr8 = cpu_get_apic_tpr(env->apic_state);
1793     }
1794 }
1795
1796 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1797 {
1798     X86CPU *x86_cpu = X86_CPU(cpu);
1799     CPUX86State *env = &x86_cpu->env;
1800
1801     if (run->if_flag) {
1802         env->eflags |= IF_MASK;
1803     } else {
1804         env->eflags &= ~IF_MASK;
1805     }
1806     cpu_set_apic_tpr(env->apic_state, run->cr8);
1807     cpu_set_apic_base(env->apic_state, run->apic_base);
1808 }
1809
1810 int kvm_arch_process_async_events(CPUState *cs)
1811 {
1812     X86CPU *cpu = X86_CPU(cs);
1813     CPUX86State *env = &cpu->env;
1814
1815     if (env->interrupt_request & CPU_INTERRUPT_MCE) {
1816         /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1817         assert(env->mcg_cap);
1818
1819         env->interrupt_request &= ~CPU_INTERRUPT_MCE;
1820
1821         kvm_cpu_synchronize_state(env);
1822
1823         if (env->exception_injected == EXCP08_DBLE) {
1824             /* this means triple fault */
1825             qemu_system_reset_request();
1826             env->exit_request = 1;
1827             return 0;
1828         }
1829         env->exception_injected = EXCP12_MCHK;
1830         env->has_error_code = 0;
1831
1832         env->halted = 0;
1833         if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1834             env->mp_state = KVM_MP_STATE_RUNNABLE;
1835         }
1836     }
1837
1838     if (kvm_irqchip_in_kernel()) {
1839         return 0;
1840     }
1841
1842     if (env->interrupt_request & CPU_INTERRUPT_POLL) {
1843         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
1844         apic_poll_irq(env->apic_state);
1845     }
1846     if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1847          (env->eflags & IF_MASK)) ||
1848         (env->interrupt_request & CPU_INTERRUPT_NMI)) {
1849         env->halted = 0;
1850     }
1851     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1852         kvm_cpu_synchronize_state(env);
1853         do_cpu_init(cpu);
1854     }
1855     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1856         kvm_cpu_synchronize_state(env);
1857         do_cpu_sipi(cpu);
1858     }
1859     if (env->interrupt_request & CPU_INTERRUPT_TPR) {
1860         env->interrupt_request &= ~CPU_INTERRUPT_TPR;
1861         kvm_cpu_synchronize_state(env);
1862         apic_handle_tpr_access_report(env->apic_state, env->eip,
1863                                       env->tpr_access_type);
1864     }
1865
1866     return env->halted;
1867 }
1868
1869 static int kvm_handle_halt(X86CPU *cpu)
1870 {
1871     CPUX86State *env = &cpu->env;
1872
1873     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1874           (env->eflags & IF_MASK)) &&
1875         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1876         env->halted = 1;
1877         return EXCP_HLT;
1878     }
1879
1880     return 0;
1881 }
1882
1883 static int kvm_handle_tpr_access(X86CPU *cpu)
1884 {
1885     CPUX86State *env = &cpu->env;
1886     CPUState *cs = CPU(cpu);
1887     struct kvm_run *run = cs->kvm_run;
1888
1889     apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
1890                                   run->tpr_access.is_write ? TPR_ACCESS_WRITE
1891                                                            : TPR_ACCESS_READ);
1892     return 1;
1893 }
1894
1895 int kvm_arch_insert_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1896 {
1897     CPUX86State *env = &X86_CPU(cpu)->env;
1898     static const uint8_t int3 = 0xcc;
1899
1900     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1901         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1902         return -EINVAL;
1903     }
1904     return 0;
1905 }
1906
1907 int kvm_arch_remove_sw_breakpoint(CPUState *cpu, struct kvm_sw_breakpoint *bp)
1908 {
1909     CPUX86State *env = &X86_CPU(cpu)->env;
1910     uint8_t int3;
1911
1912     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1913         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1914         return -EINVAL;
1915     }
1916     return 0;
1917 }
1918
1919 static struct {
1920     target_ulong addr;
1921     int len;
1922     int type;
1923 } hw_breakpoint[4];
1924
1925 static int nb_hw_breakpoint;
1926
1927 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1928 {
1929     int n;
1930
1931     for (n = 0; n < nb_hw_breakpoint; n++) {
1932         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1933             (hw_breakpoint[n].len == len || len == -1)) {
1934             return n;
1935         }
1936     }
1937     return -1;
1938 }
1939
1940 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1941                                   target_ulong len, int type)
1942 {
1943     switch (type) {
1944     case GDB_BREAKPOINT_HW:
1945         len = 1;
1946         break;
1947     case GDB_WATCHPOINT_WRITE:
1948     case GDB_WATCHPOINT_ACCESS:
1949         switch (len) {
1950         case 1:
1951             break;
1952         case 2:
1953         case 4:
1954         case 8:
1955             if (addr & (len - 1)) {
1956                 return -EINVAL;
1957             }
1958             break;
1959         default:
1960             return -EINVAL;
1961         }
1962         break;
1963     default:
1964         return -ENOSYS;
1965     }
1966
1967     if (nb_hw_breakpoint == 4) {
1968         return -ENOBUFS;
1969     }
1970     if (find_hw_breakpoint(addr, len, type) >= 0) {
1971         return -EEXIST;
1972     }
1973     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1974     hw_breakpoint[nb_hw_breakpoint].len = len;
1975     hw_breakpoint[nb_hw_breakpoint].type = type;
1976     nb_hw_breakpoint++;
1977
1978     return 0;
1979 }
1980
1981 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1982                                   target_ulong len, int type)
1983 {
1984     int n;
1985
1986     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1987     if (n < 0) {
1988         return -ENOENT;
1989     }
1990     nb_hw_breakpoint--;
1991     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1992
1993     return 0;
1994 }
1995
1996 void kvm_arch_remove_all_hw_breakpoints(void)
1997 {
1998     nb_hw_breakpoint = 0;
1999 }
2000
2001 static CPUWatchpoint hw_watchpoint;
2002
2003 static int kvm_handle_debug(X86CPU *cpu,
2004                             struct kvm_debug_exit_arch *arch_info)
2005 {
2006     CPUX86State *env = &cpu->env;
2007     int ret = 0;
2008     int n;
2009
2010     if (arch_info->exception == 1) {
2011         if (arch_info->dr6 & (1 << 14)) {
2012             if (env->singlestep_enabled) {
2013                 ret = EXCP_DEBUG;
2014             }
2015         } else {
2016             for (n = 0; n < 4; n++) {
2017                 if (arch_info->dr6 & (1 << n)) {
2018                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2019                     case 0x0:
2020                         ret = EXCP_DEBUG;
2021                         break;
2022                     case 0x1:
2023                         ret = EXCP_DEBUG;
2024                         env->watchpoint_hit = &hw_watchpoint;
2025                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2026                         hw_watchpoint.flags = BP_MEM_WRITE;
2027                         break;
2028                     case 0x3:
2029                         ret = EXCP_DEBUG;
2030                         env->watchpoint_hit = &hw_watchpoint;
2031                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2032                         hw_watchpoint.flags = BP_MEM_ACCESS;
2033                         break;
2034                     }
2035                 }
2036             }
2037         }
2038     } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2039         ret = EXCP_DEBUG;
2040     }
2041     if (ret == 0) {
2042         cpu_synchronize_state(env);
2043         assert(env->exception_injected == -1);
2044
2045         /* pass to guest */
2046         env->exception_injected = arch_info->exception;
2047         env->has_error_code = 0;
2048     }
2049
2050     return ret;
2051 }
2052
2053 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2054 {
2055     const uint8_t type_code[] = {
2056         [GDB_BREAKPOINT_HW] = 0x0,
2057         [GDB_WATCHPOINT_WRITE] = 0x1,
2058         [GDB_WATCHPOINT_ACCESS] = 0x3
2059     };
2060     const uint8_t len_code[] = {
2061         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2062     };
2063     int n;
2064
2065     if (kvm_sw_breakpoints_active(cpu)) {
2066         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2067     }
2068     if (nb_hw_breakpoint > 0) {
2069         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2070         dbg->arch.debugreg[7] = 0x0600;
2071         for (n = 0; n < nb_hw_breakpoint; n++) {
2072             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2073             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2074                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2075                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2076         }
2077     }
2078 }
2079
2080 static bool host_supports_vmx(void)
2081 {
2082     uint32_t ecx, unused;
2083
2084     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2085     return ecx & CPUID_EXT_VMX;
2086 }
2087
2088 #define VMX_INVALID_GUEST_STATE 0x80000021
2089
2090 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2091 {
2092     X86CPU *cpu = X86_CPU(cs);
2093     uint64_t code;
2094     int ret;
2095
2096     switch (run->exit_reason) {
2097     case KVM_EXIT_HLT:
2098         DPRINTF("handle_hlt\n");
2099         ret = kvm_handle_halt(cpu);
2100         break;
2101     case KVM_EXIT_SET_TPR:
2102         ret = 0;
2103         break;
2104     case KVM_EXIT_TPR_ACCESS:
2105         ret = kvm_handle_tpr_access(cpu);
2106         break;
2107     case KVM_EXIT_FAIL_ENTRY:
2108         code = run->fail_entry.hardware_entry_failure_reason;
2109         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2110                 code);
2111         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2112             fprintf(stderr,
2113                     "\nIf you're running a guest on an Intel machine without "
2114                         "unrestricted mode\n"
2115                     "support, the failure can be most likely due to the guest "
2116                         "entering an invalid\n"
2117                     "state for Intel VT. For example, the guest maybe running "
2118                         "in big real mode\n"
2119                     "which is not supported on less recent Intel processors."
2120                         "\n\n");
2121         }
2122         ret = -1;
2123         break;
2124     case KVM_EXIT_EXCEPTION:
2125         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2126                 run->ex.exception, run->ex.error_code);
2127         ret = -1;
2128         break;
2129     case KVM_EXIT_DEBUG:
2130         DPRINTF("kvm_exit_debug\n");
2131         ret = kvm_handle_debug(cpu, &run->debug.arch);
2132         break;
2133     default:
2134         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2135         ret = -1;
2136         break;
2137     }
2138
2139     return ret;
2140 }
2141
2142 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2143 {
2144     X86CPU *cpu = X86_CPU(cs);
2145     CPUX86State *env = &cpu->env;
2146
2147     kvm_cpu_synchronize_state(env);
2148     return !(env->cr[0] & CR0_PE_MASK) ||
2149            ((env->segs[R_CS].selector  & 3) != 3);
2150 }
2151
2152 void kvm_arch_init_irq_routing(KVMState *s)
2153 {
2154     if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2155         /* If kernel can't do irq routing, interrupt source
2156          * override 0->2 cannot be set up as required by HPET.
2157          * So we have to disable it.
2158          */
2159         no_hpet = 1;
2160     }
2161     /* We know at this point that we're using the in-kernel
2162      * irqchip, so we can use irqfds, and on x86 we know
2163      * we can use msi via irqfd and GSI routing.
2164      */
2165     kvm_irqfds_allowed = true;
2166     kvm_msi_via_irqfd_allowed = true;
2167     kvm_gsi_routing_allowed = true;
2168 }
2169
2170 /* Classic KVM device assignment interface. Will remain x86 only. */
2171 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2172                           uint32_t flags, uint32_t *dev_id)
2173 {
2174     struct kvm_assigned_pci_dev dev_data = {
2175         .segnr = dev_addr->domain,
2176         .busnr = dev_addr->bus,
2177         .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2178         .flags = flags,
2179     };
2180     int ret;
2181
2182     dev_data.assigned_dev_id =
2183         (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2184
2185     ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2186     if (ret < 0) {
2187         return ret;
2188     }
2189
2190     *dev_id = dev_data.assigned_dev_id;
2191
2192     return 0;
2193 }
2194
2195 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2196 {
2197     struct kvm_assigned_pci_dev dev_data = {
2198         .assigned_dev_id = dev_id,
2199     };
2200
2201     return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2202 }
2203
2204 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2205                                    uint32_t irq_type, uint32_t guest_irq)
2206 {
2207     struct kvm_assigned_irq assigned_irq = {
2208         .assigned_dev_id = dev_id,
2209         .guest_irq = guest_irq,
2210         .flags = irq_type,
2211     };
2212
2213     if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2214         return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2215     } else {
2216         return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2217     }
2218 }
2219
2220 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2221                            uint32_t guest_irq)
2222 {
2223     uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2224         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2225
2226     return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2227 }
2228
2229 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2230 {
2231     struct kvm_assigned_pci_dev dev_data = {
2232         .assigned_dev_id = dev_id,
2233         .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2234     };
2235
2236     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2237 }
2238
2239 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2240                                      uint32_t type)
2241 {
2242     struct kvm_assigned_irq assigned_irq = {
2243         .assigned_dev_id = dev_id,
2244         .flags = type,
2245     };
2246
2247     return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2248 }
2249
2250 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2251 {
2252     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2253         (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2254 }
2255
2256 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2257 {
2258     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2259                                               KVM_DEV_IRQ_GUEST_MSI, virq);
2260 }
2261
2262 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2263 {
2264     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2265                                                 KVM_DEV_IRQ_HOST_MSI);
2266 }
2267
2268 bool kvm_device_msix_supported(KVMState *s)
2269 {
2270     /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2271      * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2272     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2273 }
2274
2275 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2276                                  uint32_t nr_vectors)
2277 {
2278     struct kvm_assigned_msix_nr msix_nr = {
2279         .assigned_dev_id = dev_id,
2280         .entry_nr = nr_vectors,
2281     };
2282
2283     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2284 }
2285
2286 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2287                                int virq)
2288 {
2289     struct kvm_assigned_msix_entry msix_entry = {
2290         .assigned_dev_id = dev_id,
2291         .gsi = virq,
2292         .entry = vector,
2293     };
2294
2295     return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2296 }
2297
2298 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2299 {
2300     return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2301                                               KVM_DEV_IRQ_GUEST_MSIX, 0);
2302 }
2303
2304 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2305 {
2306     return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2307                                                 KVM_DEV_IRQ_HOST_MSIX);
2308 }