4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
29 #include "host-utils.h"
39 #define DPRINTF(fmt, ...) \
40 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #define DPRINTF(fmt, ...) \
46 #define MSR_KVM_WALL_CLOCK 0x11
47 #define MSR_KVM_SYSTEM_TIME 0x12
50 #define BUS_MCEERR_AR 4
53 #define BUS_MCEERR_AO 5
56 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
57 KVM_CAP_INFO(SET_TSS_ADDR
),
58 KVM_CAP_INFO(EXT_CPUID
),
59 KVM_CAP_INFO(MP_STATE
),
63 static bool has_msr_star
;
64 static bool has_msr_hsave_pa
;
65 static bool has_msr_tsc_adjust
;
66 static bool has_msr_tsc_deadline
;
67 static bool has_msr_async_pf_en
;
68 static bool has_msr_pv_eoi_en
;
69 static bool has_msr_misc_enable
;
70 static int lm_capable_kernel
;
72 bool kvm_allows_irq0_override(void)
74 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
77 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
79 struct kvm_cpuid2
*cpuid
;
82 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
83 cpuid
= (struct kvm_cpuid2
*)g_malloc0(size
);
85 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
86 if (r
== 0 && cpuid
->nent
>= max
) {
94 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
102 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
105 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
107 struct kvm_cpuid2
*cpuid
;
109 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
115 struct kvm_para_features
{
118 } para_features
[] = {
119 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
120 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
121 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
122 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
126 static int get_para_features(KVMState
*s
)
130 for (i
= 0; i
< ARRAY_SIZE(para_features
) - 1; i
++) {
131 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
132 features
|= (1 << para_features
[i
].feature
);
140 /* Returns the value for a specific register on the cpuid entry
142 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
162 /* Find matching entry for function/index on kvm_cpuid2 struct
164 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
169 for (i
= 0; i
< cpuid
->nent
; ++i
) {
170 if (cpuid
->entries
[i
].function
== function
&&
171 cpuid
->entries
[i
].index
== index
) {
172 return &cpuid
->entries
[i
];
179 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
180 uint32_t index
, int reg
)
182 struct kvm_cpuid2
*cpuid
;
184 uint32_t cpuid_1_edx
;
187 cpuid
= get_supported_cpuid(s
);
189 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
192 ret
= cpuid_entry_get_reg(entry
, reg
);
195 /* Fixups for the data returned by KVM, below */
197 if (function
== 1 && reg
== R_EDX
) {
198 /* KVM before 2.6.30 misreports the following features */
199 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
200 } else if (function
== 1 && reg
== R_ECX
) {
201 /* We can set the hypervisor flag, even if KVM does not return it on
202 * GET_SUPPORTED_CPUID
204 ret
|= CPUID_EXT_HYPERVISOR
;
205 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
206 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
207 * and the irqchip is in the kernel.
209 if (kvm_irqchip_in_kernel() &&
210 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
211 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
214 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
215 * without the in-kernel irqchip
217 if (!kvm_irqchip_in_kernel()) {
218 ret
&= ~CPUID_EXT_X2APIC
;
220 } else if (function
== 0x80000001 && reg
== R_EDX
) {
221 /* On Intel, kvm returns cpuid according to the Intel spec,
222 * so add missing bits according to the AMD spec:
224 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
225 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
230 /* fallback for older kernels */
231 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
232 ret
= get_para_features(s
);
238 typedef struct HWPoisonPage
{
240 QLIST_ENTRY(HWPoisonPage
) list
;
243 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
244 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
246 static void kvm_unpoison_all(void *param
)
248 HWPoisonPage
*page
, *next_page
;
250 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
251 QLIST_REMOVE(page
, list
);
252 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
257 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
261 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
262 if (page
->ram_addr
== ram_addr
) {
266 page
= g_malloc(sizeof(HWPoisonPage
));
267 page
->ram_addr
= ram_addr
;
268 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
271 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
276 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
279 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
284 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
286 CPUX86State
*env
= &cpu
->env
;
287 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
288 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
289 uint64_t mcg_status
= MCG_STATUS_MCIP
;
291 if (code
== BUS_MCEERR_AR
) {
292 status
|= MCI_STATUS_AR
| 0x134;
293 mcg_status
|= MCG_STATUS_EIPV
;
296 mcg_status
|= MCG_STATUS_RIPV
;
298 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
299 (MCM_ADDR_PHYS
<< 6) | 0xc,
300 cpu_x86_support_mca_broadcast(env
) ?
301 MCE_INJECT_BROADCAST
: 0);
304 static void hardware_memory_error(void)
306 fprintf(stderr
, "Hardware memory error!\n");
310 int kvm_arch_on_sigbus_vcpu(CPUX86State
*env
, int code
, void *addr
)
312 X86CPU
*cpu
= x86_env_get_cpu(env
);
316 if ((env
->mcg_cap
& MCG_SER_P
) && addr
317 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
318 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
319 !kvm_physical_memory_addr_from_host(env
->kvm_state
, addr
, &paddr
)) {
320 fprintf(stderr
, "Hardware memory error for memory used by "
321 "QEMU itself instead of guest system!\n");
322 /* Hope we are lucky for AO MCE */
323 if (code
== BUS_MCEERR_AO
) {
326 hardware_memory_error();
329 kvm_hwpoison_page_add(ram_addr
);
330 kvm_mce_inject(cpu
, paddr
, code
);
332 if (code
== BUS_MCEERR_AO
) {
334 } else if (code
== BUS_MCEERR_AR
) {
335 hardware_memory_error();
343 int kvm_arch_on_sigbus(int code
, void *addr
)
345 if ((first_cpu
->mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
349 /* Hope we are lucky for AO MCE */
350 if (qemu_ram_addr_from_host(addr
, &ram_addr
) ||
351 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
, addr
,
353 fprintf(stderr
, "Hardware memory error for memory used by "
354 "QEMU itself instead of guest system!: %p\n", addr
);
357 kvm_hwpoison_page_add(ram_addr
);
358 kvm_mce_inject(x86_env_get_cpu(first_cpu
), paddr
, code
);
360 if (code
== BUS_MCEERR_AO
) {
362 } else if (code
== BUS_MCEERR_AR
) {
363 hardware_memory_error();
371 static int kvm_inject_mce_oldstyle(CPUX86State
*env
)
373 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
374 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
375 struct kvm_x86_mce mce
;
377 env
->exception_injected
= -1;
380 * There must be at least one bank in use if an MCE is pending.
381 * Find it and use its values for the event injection.
383 for (bank
= 0; bank
< bank_num
; bank
++) {
384 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
388 assert(bank
< bank_num
);
391 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
392 mce
.mcg_status
= env
->mcg_status
;
393 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
394 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
396 return kvm_vcpu_ioctl(env
, KVM_X86_SET_MCE
, &mce
);
401 static void cpu_update_state(void *opaque
, int running
, RunState state
)
403 CPUX86State
*env
= opaque
;
406 env
->tsc_valid
= false;
410 int kvm_arch_init_vcpu(CPUX86State
*env
)
413 struct kvm_cpuid2 cpuid
;
414 struct kvm_cpuid_entry2 entries
[100];
415 } QEMU_PACKED cpuid_data
;
416 uint32_t limit
, i
, j
, cpuid_i
;
418 struct kvm_cpuid_entry2
*c
;
419 uint32_t signature
[3];
424 /* Paravirtualization CPUIDs */
425 c
= &cpuid_data
.entries
[cpuid_i
++];
426 memset(c
, 0, sizeof(*c
));
427 c
->function
= KVM_CPUID_SIGNATURE
;
428 if (!hyperv_enabled()) {
429 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
432 memcpy(signature
, "Microsoft Hv", 12);
433 c
->eax
= HYPERV_CPUID_MIN
;
435 c
->ebx
= signature
[0];
436 c
->ecx
= signature
[1];
437 c
->edx
= signature
[2];
439 c
= &cpuid_data
.entries
[cpuid_i
++];
440 memset(c
, 0, sizeof(*c
));
441 c
->function
= KVM_CPUID_FEATURES
;
442 c
->eax
= env
->cpuid_kvm_features
;
444 if (hyperv_enabled()) {
445 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
446 c
->eax
= signature
[0];
448 c
= &cpuid_data
.entries
[cpuid_i
++];
449 memset(c
, 0, sizeof(*c
));
450 c
->function
= HYPERV_CPUID_VERSION
;
454 c
= &cpuid_data
.entries
[cpuid_i
++];
455 memset(c
, 0, sizeof(*c
));
456 c
->function
= HYPERV_CPUID_FEATURES
;
457 if (hyperv_relaxed_timing_enabled()) {
458 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
460 if (hyperv_vapic_recommended()) {
461 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
462 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
465 c
= &cpuid_data
.entries
[cpuid_i
++];
466 memset(c
, 0, sizeof(*c
));
467 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
468 if (hyperv_relaxed_timing_enabled()) {
469 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
471 if (hyperv_vapic_recommended()) {
472 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
474 c
->ebx
= hyperv_get_spinlock_retries();
476 c
= &cpuid_data
.entries
[cpuid_i
++];
477 memset(c
, 0, sizeof(*c
));
478 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
482 c
= &cpuid_data
.entries
[cpuid_i
++];
483 memset(c
, 0, sizeof(*c
));
484 c
->function
= KVM_CPUID_SIGNATURE_NEXT
;
485 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
487 c
->ebx
= signature
[0];
488 c
->ecx
= signature
[1];
489 c
->edx
= signature
[2];
492 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
494 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
496 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
498 for (i
= 0; i
<= limit
; i
++) {
499 c
= &cpuid_data
.entries
[cpuid_i
++];
503 /* Keep reading function 2 till all the input is received */
507 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
508 KVM_CPUID_FLAG_STATE_READ_NEXT
;
509 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
510 times
= c
->eax
& 0xff;
512 for (j
= 1; j
< times
; ++j
) {
513 c
= &cpuid_data
.entries
[cpuid_i
++];
515 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
516 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
524 if (i
== 0xd && j
== 64) {
528 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
530 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
532 if (i
== 4 && c
->eax
== 0) {
535 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
538 if (i
== 0xd && c
->eax
== 0) {
541 c
= &cpuid_data
.entries
[cpuid_i
++];
547 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
551 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
553 for (i
= 0x80000000; i
<= limit
; i
++) {
554 c
= &cpuid_data
.entries
[cpuid_i
++];
558 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
561 /* Call Centaur's CPUID instructions they are supported. */
562 if (env
->cpuid_xlevel2
> 0) {
563 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
565 for (i
= 0xC0000000; i
<= limit
; i
++) {
566 c
= &cpuid_data
.entries
[cpuid_i
++];
570 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
574 cpuid_data
.cpuid
.nent
= cpuid_i
;
576 if (((env
->cpuid_version
>> 8)&0xF) >= 6
577 && (env
->cpuid_features
&(CPUID_MCE
|CPUID_MCA
)) == (CPUID_MCE
|CPUID_MCA
)
578 && kvm_check_extension(env
->kvm_state
, KVM_CAP_MCE
) > 0) {
583 ret
= kvm_get_mce_cap_supported(env
->kvm_state
, &mcg_cap
, &banks
);
585 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
589 if (banks
> MCE_BANKS_DEF
) {
590 banks
= MCE_BANKS_DEF
;
592 mcg_cap
&= MCE_CAP_DEF
;
594 ret
= kvm_vcpu_ioctl(env
, KVM_X86_SETUP_MCE
, &mcg_cap
);
596 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
600 env
->mcg_cap
= mcg_cap
;
603 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
605 cpuid_data
.cpuid
.padding
= 0;
606 r
= kvm_vcpu_ioctl(env
, KVM_SET_CPUID2
, &cpuid_data
);
611 r
= kvm_check_extension(env
->kvm_state
, KVM_CAP_TSC_CONTROL
);
612 if (r
&& env
->tsc_khz
) {
613 r
= kvm_vcpu_ioctl(env
, KVM_SET_TSC_KHZ
, env
->tsc_khz
);
615 fprintf(stderr
, "KVM_SET_TSC_KHZ failed\n");
620 if (kvm_has_xsave()) {
621 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
627 void kvm_arch_reset_vcpu(CPUX86State
*env
)
629 X86CPU
*cpu
= x86_env_get_cpu(env
);
631 env
->exception_injected
= -1;
632 env
->interrupt_injected
= -1;
634 if (kvm_irqchip_in_kernel()) {
635 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
636 KVM_MP_STATE_UNINITIALIZED
;
638 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
642 static int kvm_get_supported_msrs(KVMState
*s
)
644 static int kvm_supported_msrs
;
648 if (kvm_supported_msrs
== 0) {
649 struct kvm_msr_list msr_list
, *kvm_msr_list
;
651 kvm_supported_msrs
= -1;
653 /* Obtain MSR list from KVM. These are the MSRs that we must
656 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
657 if (ret
< 0 && ret
!= -E2BIG
) {
660 /* Old kernel modules had a bug and could write beyond the provided
661 memory. Allocate at least a safe amount of 1K. */
662 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
664 sizeof(msr_list
.indices
[0])));
666 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
667 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
671 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
672 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
676 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
677 has_msr_hsave_pa
= true;
680 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
681 has_msr_tsc_adjust
= true;
684 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
685 has_msr_tsc_deadline
= true;
688 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
689 has_msr_misc_enable
= true;
695 g_free(kvm_msr_list
);
701 int kvm_arch_init(KVMState
*s
)
703 QemuOptsList
*list
= qemu_find_opts("machine");
704 uint64_t identity_base
= 0xfffbc000;
707 struct utsname utsname
;
709 ret
= kvm_get_supported_msrs(s
);
715 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
718 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
719 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
720 * Since these must be part of guest physical memory, we need to allocate
721 * them, both by setting their start addresses in the kernel and by
722 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
724 * Older KVM versions may not support setting the identity map base. In
725 * that case we need to stick with the default, i.e. a 256K maximum BIOS
728 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
729 /* Allows up to 16M BIOSes. */
730 identity_base
= 0xfeffc000;
732 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
738 /* Set TSS base one page after EPT identity map. */
739 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
744 /* Tell fw_cfg to notify the BIOS to reserve the range. */
745 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
747 fprintf(stderr
, "e820_add_entry() table is full\n");
750 qemu_register_reset(kvm_unpoison_all
, NULL
);
752 if (!QTAILQ_EMPTY(&list
->head
)) {
753 shadow_mem
= qemu_opt_get_size(QTAILQ_FIRST(&list
->head
),
754 "kvm_shadow_mem", -1);
755 if (shadow_mem
!= -1) {
757 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
766 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
768 lhs
->selector
= rhs
->selector
;
769 lhs
->base
= rhs
->base
;
770 lhs
->limit
= rhs
->limit
;
782 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
784 unsigned flags
= rhs
->flags
;
785 lhs
->selector
= rhs
->selector
;
786 lhs
->base
= rhs
->base
;
787 lhs
->limit
= rhs
->limit
;
788 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
789 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
790 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
791 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
792 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
793 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
794 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
795 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
800 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
802 lhs
->selector
= rhs
->selector
;
803 lhs
->base
= rhs
->base
;
804 lhs
->limit
= rhs
->limit
;
805 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
806 (rhs
->present
* DESC_P_MASK
) |
807 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
808 (rhs
->db
<< DESC_B_SHIFT
) |
809 (rhs
->s
* DESC_S_MASK
) |
810 (rhs
->l
<< DESC_L_SHIFT
) |
811 (rhs
->g
* DESC_G_MASK
) |
812 (rhs
->avl
* DESC_AVL_MASK
);
815 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
818 *kvm_reg
= *qemu_reg
;
820 *qemu_reg
= *kvm_reg
;
824 static int kvm_getput_regs(CPUX86State
*env
, int set
)
826 struct kvm_regs regs
;
830 ret
= kvm_vcpu_ioctl(env
, KVM_GET_REGS
, ®s
);
836 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
837 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
838 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
839 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
840 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
841 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
842 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
843 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
845 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
846 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
847 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
848 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
849 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
850 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
851 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
852 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
855 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
856 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
859 ret
= kvm_vcpu_ioctl(env
, KVM_SET_REGS
, ®s
);
865 static int kvm_put_fpu(CPUX86State
*env
)
870 memset(&fpu
, 0, sizeof fpu
);
871 fpu
.fsw
= env
->fpus
& ~(7 << 11);
872 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
874 fpu
.last_opcode
= env
->fpop
;
875 fpu
.last_ip
= env
->fpip
;
876 fpu
.last_dp
= env
->fpdp
;
877 for (i
= 0; i
< 8; ++i
) {
878 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
880 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
881 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
882 fpu
.mxcsr
= env
->mxcsr
;
884 return kvm_vcpu_ioctl(env
, KVM_SET_FPU
, &fpu
);
887 #define XSAVE_FCW_FSW 0
888 #define XSAVE_FTW_FOP 1
889 #define XSAVE_CWD_RIP 2
890 #define XSAVE_CWD_RDP 4
891 #define XSAVE_MXCSR 6
892 #define XSAVE_ST_SPACE 8
893 #define XSAVE_XMM_SPACE 40
894 #define XSAVE_XSTATE_BV 128
895 #define XSAVE_YMMH_SPACE 144
897 static int kvm_put_xsave(CPUX86State
*env
)
899 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
900 uint16_t cwd
, swd
, twd
;
903 if (!kvm_has_xsave()) {
904 return kvm_put_fpu(env
);
907 memset(xsave
, 0, sizeof(struct kvm_xsave
));
909 swd
= env
->fpus
& ~(7 << 11);
910 swd
|= (env
->fpstt
& 7) << 11;
912 for (i
= 0; i
< 8; ++i
) {
913 twd
|= (!env
->fptags
[i
]) << i
;
915 xsave
->region
[XSAVE_FCW_FSW
] = (uint32_t)(swd
<< 16) + cwd
;
916 xsave
->region
[XSAVE_FTW_FOP
] = (uint32_t)(env
->fpop
<< 16) + twd
;
917 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
918 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
919 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
921 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
922 sizeof env
->xmm_regs
);
923 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
924 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
925 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
926 sizeof env
->ymmh_regs
);
927 r
= kvm_vcpu_ioctl(env
, KVM_SET_XSAVE
, xsave
);
931 static int kvm_put_xcrs(CPUX86State
*env
)
933 struct kvm_xcrs xcrs
;
935 if (!kvm_has_xcrs()) {
941 xcrs
.xcrs
[0].xcr
= 0;
942 xcrs
.xcrs
[0].value
= env
->xcr0
;
943 return kvm_vcpu_ioctl(env
, KVM_SET_XCRS
, &xcrs
);
946 static int kvm_put_sregs(CPUX86State
*env
)
948 struct kvm_sregs sregs
;
950 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
951 if (env
->interrupt_injected
>= 0) {
952 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
953 (uint64_t)1 << (env
->interrupt_injected
% 64);
956 if ((env
->eflags
& VM_MASK
)) {
957 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
958 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
959 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
960 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
961 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
962 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
964 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
965 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
966 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
967 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
968 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
969 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
972 set_seg(&sregs
.tr
, &env
->tr
);
973 set_seg(&sregs
.ldt
, &env
->ldt
);
975 sregs
.idt
.limit
= env
->idt
.limit
;
976 sregs
.idt
.base
= env
->idt
.base
;
977 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
978 sregs
.gdt
.limit
= env
->gdt
.limit
;
979 sregs
.gdt
.base
= env
->gdt
.base
;
980 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
982 sregs
.cr0
= env
->cr
[0];
983 sregs
.cr2
= env
->cr
[2];
984 sregs
.cr3
= env
->cr
[3];
985 sregs
.cr4
= env
->cr
[4];
987 sregs
.cr8
= cpu_get_apic_tpr(env
->apic_state
);
988 sregs
.apic_base
= cpu_get_apic_base(env
->apic_state
);
990 sregs
.efer
= env
->efer
;
992 return kvm_vcpu_ioctl(env
, KVM_SET_SREGS
, &sregs
);
995 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
996 uint32_t index
, uint64_t value
)
998 entry
->index
= index
;
1002 static int kvm_put_msrs(CPUX86State
*env
, int level
)
1005 struct kvm_msrs info
;
1006 struct kvm_msr_entry entries
[100];
1008 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1011 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1012 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1013 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1014 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
1016 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
1018 if (has_msr_hsave_pa
) {
1019 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1021 if (has_msr_tsc_adjust
) {
1022 kvm_msr_entry_set(&msrs
[n
++], MSR_TSC_ADJUST
, env
->tsc_adjust
);
1024 if (has_msr_tsc_deadline
) {
1025 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1027 if (has_msr_misc_enable
) {
1028 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_MISC_ENABLE
,
1029 env
->msr_ia32_misc_enable
);
1031 #ifdef TARGET_X86_64
1032 if (lm_capable_kernel
) {
1033 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1034 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1035 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1036 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1039 if (level
== KVM_PUT_FULL_STATE
) {
1041 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1042 * writeback. Until this is fixed, we only write the offset to SMP
1043 * guests after migration, desynchronizing the VCPUs, but avoiding
1044 * huge jump-backs that would occur without any writeback at all.
1046 if (smp_cpus
== 1 || env
->tsc
!= 0) {
1047 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
1051 * The following paravirtual MSRs have side effects on the guest or are
1052 * too heavy for normal writeback. Limit them to reset or full state
1055 if (level
>= KVM_PUT_RESET_STATE
) {
1056 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
1057 env
->system_time_msr
);
1058 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1059 if (has_msr_async_pf_en
) {
1060 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
1061 env
->async_pf_en_msr
);
1063 if (has_msr_pv_eoi_en
) {
1064 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_PV_EOI_EN
,
1065 env
->pv_eoi_en_msr
);
1067 if (hyperv_hypercall_available()) {
1068 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_GUEST_OS_ID
, 0);
1069 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_HYPERCALL
, 0);
1071 if (hyperv_vapic_recommended()) {
1072 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_APIC_ASSIST_PAGE
, 0);
1078 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
1079 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
1080 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1081 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1085 msr_data
.info
.nmsrs
= n
;
1087 return kvm_vcpu_ioctl(env
, KVM_SET_MSRS
, &msr_data
);
1092 static int kvm_get_fpu(CPUX86State
*env
)
1097 ret
= kvm_vcpu_ioctl(env
, KVM_GET_FPU
, &fpu
);
1102 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1103 env
->fpus
= fpu
.fsw
;
1104 env
->fpuc
= fpu
.fcw
;
1105 env
->fpop
= fpu
.last_opcode
;
1106 env
->fpip
= fpu
.last_ip
;
1107 env
->fpdp
= fpu
.last_dp
;
1108 for (i
= 0; i
< 8; ++i
) {
1109 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1111 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1112 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1113 env
->mxcsr
= fpu
.mxcsr
;
1118 static int kvm_get_xsave(CPUX86State
*env
)
1120 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1122 uint16_t cwd
, swd
, twd
;
1124 if (!kvm_has_xsave()) {
1125 return kvm_get_fpu(env
);
1128 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XSAVE
, xsave
);
1133 cwd
= (uint16_t)xsave
->region
[XSAVE_FCW_FSW
];
1134 swd
= (uint16_t)(xsave
->region
[XSAVE_FCW_FSW
] >> 16);
1135 twd
= (uint16_t)xsave
->region
[XSAVE_FTW_FOP
];
1136 env
->fpop
= (uint16_t)(xsave
->region
[XSAVE_FTW_FOP
] >> 16);
1137 env
->fpstt
= (swd
>> 11) & 7;
1140 for (i
= 0; i
< 8; ++i
) {
1141 env
->fptags
[i
] = !((twd
>> i
) & 1);
1143 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1144 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1145 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1146 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1147 sizeof env
->fpregs
);
1148 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1149 sizeof env
->xmm_regs
);
1150 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1151 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1152 sizeof env
->ymmh_regs
);
1156 static int kvm_get_xcrs(CPUX86State
*env
)
1159 struct kvm_xcrs xcrs
;
1161 if (!kvm_has_xcrs()) {
1165 ret
= kvm_vcpu_ioctl(env
, KVM_GET_XCRS
, &xcrs
);
1170 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1171 /* Only support xcr0 now */
1172 if (xcrs
.xcrs
[0].xcr
== 0) {
1173 env
->xcr0
= xcrs
.xcrs
[0].value
;
1180 static int kvm_get_sregs(CPUX86State
*env
)
1182 struct kvm_sregs sregs
;
1186 ret
= kvm_vcpu_ioctl(env
, KVM_GET_SREGS
, &sregs
);
1191 /* There can only be one pending IRQ set in the bitmap at a time, so try
1192 to find it and save its number instead (-1 for none). */
1193 env
->interrupt_injected
= -1;
1194 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1195 if (sregs
.interrupt_bitmap
[i
]) {
1196 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1197 env
->interrupt_injected
= i
* 64 + bit
;
1202 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1203 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1204 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1205 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1206 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1207 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1209 get_seg(&env
->tr
, &sregs
.tr
);
1210 get_seg(&env
->ldt
, &sregs
.ldt
);
1212 env
->idt
.limit
= sregs
.idt
.limit
;
1213 env
->idt
.base
= sregs
.idt
.base
;
1214 env
->gdt
.limit
= sregs
.gdt
.limit
;
1215 env
->gdt
.base
= sregs
.gdt
.base
;
1217 env
->cr
[0] = sregs
.cr0
;
1218 env
->cr
[2] = sregs
.cr2
;
1219 env
->cr
[3] = sregs
.cr3
;
1220 env
->cr
[4] = sregs
.cr4
;
1222 env
->efer
= sregs
.efer
;
1224 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1226 #define HFLAG_COPY_MASK \
1227 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1228 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1229 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1230 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1232 hflags
= (env
->segs
[R_CS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1233 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1234 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1235 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1236 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1237 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1238 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1240 if (env
->efer
& MSR_EFER_LMA
) {
1241 hflags
|= HF_LMA_MASK
;
1244 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1245 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1247 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1248 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1249 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1250 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1251 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1252 !(hflags
& HF_CS32_MASK
)) {
1253 hflags
|= HF_ADDSEG_MASK
;
1255 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1256 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1259 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1264 static int kvm_get_msrs(CPUX86State
*env
)
1267 struct kvm_msrs info
;
1268 struct kvm_msr_entry entries
[100];
1270 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1274 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1275 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1276 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1277 msrs
[n
++].index
= MSR_PAT
;
1279 msrs
[n
++].index
= MSR_STAR
;
1281 if (has_msr_hsave_pa
) {
1282 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1284 if (has_msr_tsc_adjust
) {
1285 msrs
[n
++].index
= MSR_TSC_ADJUST
;
1287 if (has_msr_tsc_deadline
) {
1288 msrs
[n
++].index
= MSR_IA32_TSCDEADLINE
;
1290 if (has_msr_misc_enable
) {
1291 msrs
[n
++].index
= MSR_IA32_MISC_ENABLE
;
1294 if (!env
->tsc_valid
) {
1295 msrs
[n
++].index
= MSR_IA32_TSC
;
1296 env
->tsc_valid
= !runstate_is_running();
1299 #ifdef TARGET_X86_64
1300 if (lm_capable_kernel
) {
1301 msrs
[n
++].index
= MSR_CSTAR
;
1302 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1303 msrs
[n
++].index
= MSR_FMASK
;
1304 msrs
[n
++].index
= MSR_LSTAR
;
1307 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1308 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1309 if (has_msr_async_pf_en
) {
1310 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1312 if (has_msr_pv_eoi_en
) {
1313 msrs
[n
++].index
= MSR_KVM_PV_EOI_EN
;
1317 msrs
[n
++].index
= MSR_MCG_STATUS
;
1318 msrs
[n
++].index
= MSR_MCG_CTL
;
1319 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1320 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1324 msr_data
.info
.nmsrs
= n
;
1325 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MSRS
, &msr_data
);
1330 for (i
= 0; i
< ret
; i
++) {
1331 switch (msrs
[i
].index
) {
1332 case MSR_IA32_SYSENTER_CS
:
1333 env
->sysenter_cs
= msrs
[i
].data
;
1335 case MSR_IA32_SYSENTER_ESP
:
1336 env
->sysenter_esp
= msrs
[i
].data
;
1338 case MSR_IA32_SYSENTER_EIP
:
1339 env
->sysenter_eip
= msrs
[i
].data
;
1342 env
->pat
= msrs
[i
].data
;
1345 env
->star
= msrs
[i
].data
;
1347 #ifdef TARGET_X86_64
1349 env
->cstar
= msrs
[i
].data
;
1351 case MSR_KERNELGSBASE
:
1352 env
->kernelgsbase
= msrs
[i
].data
;
1355 env
->fmask
= msrs
[i
].data
;
1358 env
->lstar
= msrs
[i
].data
;
1362 env
->tsc
= msrs
[i
].data
;
1364 case MSR_TSC_ADJUST
:
1365 env
->tsc_adjust
= msrs
[i
].data
;
1367 case MSR_IA32_TSCDEADLINE
:
1368 env
->tsc_deadline
= msrs
[i
].data
;
1370 case MSR_VM_HSAVE_PA
:
1371 env
->vm_hsave
= msrs
[i
].data
;
1373 case MSR_KVM_SYSTEM_TIME
:
1374 env
->system_time_msr
= msrs
[i
].data
;
1376 case MSR_KVM_WALL_CLOCK
:
1377 env
->wall_clock_msr
= msrs
[i
].data
;
1379 case MSR_MCG_STATUS
:
1380 env
->mcg_status
= msrs
[i
].data
;
1383 env
->mcg_ctl
= msrs
[i
].data
;
1385 case MSR_IA32_MISC_ENABLE
:
1386 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
1389 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1390 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1391 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1394 case MSR_KVM_ASYNC_PF_EN
:
1395 env
->async_pf_en_msr
= msrs
[i
].data
;
1397 case MSR_KVM_PV_EOI_EN
:
1398 env
->pv_eoi_en_msr
= msrs
[i
].data
;
1406 static int kvm_put_mp_state(CPUX86State
*env
)
1408 struct kvm_mp_state mp_state
= { .mp_state
= env
->mp_state
};
1410 return kvm_vcpu_ioctl(env
, KVM_SET_MP_STATE
, &mp_state
);
1413 static int kvm_get_mp_state(X86CPU
*cpu
)
1415 CPUX86State
*env
= &cpu
->env
;
1416 struct kvm_mp_state mp_state
;
1419 ret
= kvm_vcpu_ioctl(env
, KVM_GET_MP_STATE
, &mp_state
);
1423 env
->mp_state
= mp_state
.mp_state
;
1424 if (kvm_irqchip_in_kernel()) {
1425 env
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1430 static int kvm_get_apic(CPUX86State
*env
)
1432 DeviceState
*apic
= env
->apic_state
;
1433 struct kvm_lapic_state kapic
;
1436 if (apic
&& kvm_irqchip_in_kernel()) {
1437 ret
= kvm_vcpu_ioctl(env
, KVM_GET_LAPIC
, &kapic
);
1442 kvm_get_apic_state(apic
, &kapic
);
1447 static int kvm_put_apic(CPUX86State
*env
)
1449 DeviceState
*apic
= env
->apic_state
;
1450 struct kvm_lapic_state kapic
;
1452 if (apic
&& kvm_irqchip_in_kernel()) {
1453 kvm_put_apic_state(apic
, &kapic
);
1455 return kvm_vcpu_ioctl(env
, KVM_SET_LAPIC
, &kapic
);
1460 static int kvm_put_vcpu_events(CPUX86State
*env
, int level
)
1462 struct kvm_vcpu_events events
;
1464 if (!kvm_has_vcpu_events()) {
1468 events
.exception
.injected
= (env
->exception_injected
>= 0);
1469 events
.exception
.nr
= env
->exception_injected
;
1470 events
.exception
.has_error_code
= env
->has_error_code
;
1471 events
.exception
.error_code
= env
->error_code
;
1472 events
.exception
.pad
= 0;
1474 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1475 events
.interrupt
.nr
= env
->interrupt_injected
;
1476 events
.interrupt
.soft
= env
->soft_interrupt
;
1478 events
.nmi
.injected
= env
->nmi_injected
;
1479 events
.nmi
.pending
= env
->nmi_pending
;
1480 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1483 events
.sipi_vector
= env
->sipi_vector
;
1486 if (level
>= KVM_PUT_RESET_STATE
) {
1488 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1491 return kvm_vcpu_ioctl(env
, KVM_SET_VCPU_EVENTS
, &events
);
1494 static int kvm_get_vcpu_events(CPUX86State
*env
)
1496 struct kvm_vcpu_events events
;
1499 if (!kvm_has_vcpu_events()) {
1503 ret
= kvm_vcpu_ioctl(env
, KVM_GET_VCPU_EVENTS
, &events
);
1507 env
->exception_injected
=
1508 events
.exception
.injected
? events
.exception
.nr
: -1;
1509 env
->has_error_code
= events
.exception
.has_error_code
;
1510 env
->error_code
= events
.exception
.error_code
;
1512 env
->interrupt_injected
=
1513 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1514 env
->soft_interrupt
= events
.interrupt
.soft
;
1516 env
->nmi_injected
= events
.nmi
.injected
;
1517 env
->nmi_pending
= events
.nmi
.pending
;
1518 if (events
.nmi
.masked
) {
1519 env
->hflags2
|= HF2_NMI_MASK
;
1521 env
->hflags2
&= ~HF2_NMI_MASK
;
1524 env
->sipi_vector
= events
.sipi_vector
;
1529 static int kvm_guest_debug_workarounds(CPUX86State
*env
)
1532 unsigned long reinject_trap
= 0;
1534 if (!kvm_has_vcpu_events()) {
1535 if (env
->exception_injected
== 1) {
1536 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1537 } else if (env
->exception_injected
== 3) {
1538 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1540 env
->exception_injected
= -1;
1544 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1545 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1546 * by updating the debug state once again if single-stepping is on.
1547 * Another reason to call kvm_update_guest_debug here is a pending debug
1548 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1549 * reinject them via SET_GUEST_DEBUG.
1551 if (reinject_trap
||
1552 (!kvm_has_robust_singlestep() && env
->singlestep_enabled
)) {
1553 ret
= kvm_update_guest_debug(env
, reinject_trap
);
1558 static int kvm_put_debugregs(CPUX86State
*env
)
1560 struct kvm_debugregs dbgregs
;
1563 if (!kvm_has_debugregs()) {
1567 for (i
= 0; i
< 4; i
++) {
1568 dbgregs
.db
[i
] = env
->dr
[i
];
1570 dbgregs
.dr6
= env
->dr
[6];
1571 dbgregs
.dr7
= env
->dr
[7];
1574 return kvm_vcpu_ioctl(env
, KVM_SET_DEBUGREGS
, &dbgregs
);
1577 static int kvm_get_debugregs(CPUX86State
*env
)
1579 struct kvm_debugregs dbgregs
;
1582 if (!kvm_has_debugregs()) {
1586 ret
= kvm_vcpu_ioctl(env
, KVM_GET_DEBUGREGS
, &dbgregs
);
1590 for (i
= 0; i
< 4; i
++) {
1591 env
->dr
[i
] = dbgregs
.db
[i
];
1593 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1594 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1599 int kvm_arch_put_registers(CPUX86State
*env
, int level
)
1601 CPUState
*cpu
= ENV_GET_CPU(env
);
1604 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
1606 ret
= kvm_getput_regs(env
, 1);
1610 ret
= kvm_put_xsave(env
);
1614 ret
= kvm_put_xcrs(env
);
1618 ret
= kvm_put_sregs(env
);
1622 /* must be before kvm_put_msrs */
1623 ret
= kvm_inject_mce_oldstyle(env
);
1627 ret
= kvm_put_msrs(env
, level
);
1631 if (level
>= KVM_PUT_RESET_STATE
) {
1632 ret
= kvm_put_mp_state(env
);
1636 ret
= kvm_put_apic(env
);
1641 ret
= kvm_put_vcpu_events(env
, level
);
1645 ret
= kvm_put_debugregs(env
);
1650 ret
= kvm_guest_debug_workarounds(env
);
1657 int kvm_arch_get_registers(CPUX86State
*env
)
1659 X86CPU
*cpu
= x86_env_get_cpu(env
);
1662 assert(cpu_is_stopped(CPU(cpu
)) || qemu_cpu_is_self(CPU(cpu
)));
1664 ret
= kvm_getput_regs(env
, 0);
1668 ret
= kvm_get_xsave(env
);
1672 ret
= kvm_get_xcrs(env
);
1676 ret
= kvm_get_sregs(env
);
1680 ret
= kvm_get_msrs(env
);
1684 ret
= kvm_get_mp_state(cpu
);
1688 ret
= kvm_get_apic(env
);
1692 ret
= kvm_get_vcpu_events(env
);
1696 ret
= kvm_get_debugregs(env
);
1703 void kvm_arch_pre_run(CPUX86State
*env
, struct kvm_run
*run
)
1708 if (env
->interrupt_request
& CPU_INTERRUPT_NMI
) {
1709 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
1710 DPRINTF("injected NMI\n");
1711 ret
= kvm_vcpu_ioctl(env
, KVM_NMI
);
1713 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
1718 if (!kvm_irqchip_in_kernel()) {
1719 /* Force the VCPU out of its inner loop to process any INIT requests
1720 * or pending TPR access reports. */
1721 if (env
->interrupt_request
&
1722 (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
1723 env
->exit_request
= 1;
1726 /* Try to inject an interrupt if the guest can accept it */
1727 if (run
->ready_for_interrupt_injection
&&
1728 (env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1729 (env
->eflags
& IF_MASK
)) {
1732 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
1733 irq
= cpu_get_pic_interrupt(env
);
1735 struct kvm_interrupt intr
;
1738 DPRINTF("injected interrupt %d\n", irq
);
1739 ret
= kvm_vcpu_ioctl(env
, KVM_INTERRUPT
, &intr
);
1742 "KVM: injection failed, interrupt lost (%s)\n",
1748 /* If we have an interrupt but the guest is not ready to receive an
1749 * interrupt, request an interrupt window exit. This will
1750 * cause a return to userspace as soon as the guest is ready to
1751 * receive interrupts. */
1752 if ((env
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
1753 run
->request_interrupt_window
= 1;
1755 run
->request_interrupt_window
= 0;
1758 DPRINTF("setting tpr\n");
1759 run
->cr8
= cpu_get_apic_tpr(env
->apic_state
);
1763 void kvm_arch_post_run(CPUX86State
*env
, struct kvm_run
*run
)
1766 env
->eflags
|= IF_MASK
;
1768 env
->eflags
&= ~IF_MASK
;
1770 cpu_set_apic_tpr(env
->apic_state
, run
->cr8
);
1771 cpu_set_apic_base(env
->apic_state
, run
->apic_base
);
1774 int kvm_arch_process_async_events(CPUX86State
*env
)
1776 X86CPU
*cpu
= x86_env_get_cpu(env
);
1778 if (env
->interrupt_request
& CPU_INTERRUPT_MCE
) {
1779 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1780 assert(env
->mcg_cap
);
1782 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
1784 kvm_cpu_synchronize_state(env
);
1786 if (env
->exception_injected
== EXCP08_DBLE
) {
1787 /* this means triple fault */
1788 qemu_system_reset_request();
1789 env
->exit_request
= 1;
1792 env
->exception_injected
= EXCP12_MCHK
;
1793 env
->has_error_code
= 0;
1796 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
1797 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
1801 if (kvm_irqchip_in_kernel()) {
1805 if (env
->interrupt_request
& CPU_INTERRUPT_POLL
) {
1806 env
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
1807 apic_poll_irq(env
->apic_state
);
1809 if (((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1810 (env
->eflags
& IF_MASK
)) ||
1811 (env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1814 if (env
->interrupt_request
& CPU_INTERRUPT_INIT
) {
1815 kvm_cpu_synchronize_state(env
);
1818 if (env
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
1819 kvm_cpu_synchronize_state(env
);
1822 if (env
->interrupt_request
& CPU_INTERRUPT_TPR
) {
1823 env
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
1824 kvm_cpu_synchronize_state(env
);
1825 apic_handle_tpr_access_report(env
->apic_state
, env
->eip
,
1826 env
->tpr_access_type
);
1832 static int kvm_handle_halt(X86CPU
*cpu
)
1834 CPUX86State
*env
= &cpu
->env
;
1836 if (!((env
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
1837 (env
->eflags
& IF_MASK
)) &&
1838 !(env
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
1846 static int kvm_handle_tpr_access(CPUX86State
*env
)
1848 struct kvm_run
*run
= env
->kvm_run
;
1850 apic_handle_tpr_access_report(env
->apic_state
, run
->tpr_access
.rip
,
1851 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
1856 int kvm_arch_insert_sw_breakpoint(CPUX86State
*env
, struct kvm_sw_breakpoint
*bp
)
1858 static const uint8_t int3
= 0xcc;
1860 if (cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
1861 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
1867 int kvm_arch_remove_sw_breakpoint(CPUX86State
*env
, struct kvm_sw_breakpoint
*bp
)
1871 if (cpu_memory_rw_debug(env
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
1872 cpu_memory_rw_debug(env
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
1884 static int nb_hw_breakpoint
;
1886 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
1890 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
1891 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
1892 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
1899 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
1900 target_ulong len
, int type
)
1903 case GDB_BREAKPOINT_HW
:
1906 case GDB_WATCHPOINT_WRITE
:
1907 case GDB_WATCHPOINT_ACCESS
:
1914 if (addr
& (len
- 1)) {
1926 if (nb_hw_breakpoint
== 4) {
1929 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
1932 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
1933 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
1934 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
1940 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
1941 target_ulong len
, int type
)
1945 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
1950 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
1955 void kvm_arch_remove_all_hw_breakpoints(void)
1957 nb_hw_breakpoint
= 0;
1960 static CPUWatchpoint hw_watchpoint
;
1962 static int kvm_handle_debug(CPUX86State
*env
,
1963 struct kvm_debug_exit_arch
*arch_info
)
1968 if (arch_info
->exception
== 1) {
1969 if (arch_info
->dr6
& (1 << 14)) {
1970 if (env
->singlestep_enabled
) {
1974 for (n
= 0; n
< 4; n
++) {
1975 if (arch_info
->dr6
& (1 << n
)) {
1976 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
1982 env
->watchpoint_hit
= &hw_watchpoint
;
1983 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1984 hw_watchpoint
.flags
= BP_MEM_WRITE
;
1988 env
->watchpoint_hit
= &hw_watchpoint
;
1989 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
1990 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
1996 } else if (kvm_find_sw_breakpoint(env
, arch_info
->pc
)) {
2000 cpu_synchronize_state(env
);
2001 assert(env
->exception_injected
== -1);
2004 env
->exception_injected
= arch_info
->exception
;
2005 env
->has_error_code
= 0;
2011 void kvm_arch_update_guest_debug(CPUX86State
*env
, struct kvm_guest_debug
*dbg
)
2013 const uint8_t type_code
[] = {
2014 [GDB_BREAKPOINT_HW
] = 0x0,
2015 [GDB_WATCHPOINT_WRITE
] = 0x1,
2016 [GDB_WATCHPOINT_ACCESS
] = 0x3
2018 const uint8_t len_code
[] = {
2019 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2023 if (kvm_sw_breakpoints_active(env
)) {
2024 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
2026 if (nb_hw_breakpoint
> 0) {
2027 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
2028 dbg
->arch
.debugreg
[7] = 0x0600;
2029 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2030 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
2031 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
2032 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
2033 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
2038 static bool host_supports_vmx(void)
2040 uint32_t ecx
, unused
;
2042 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
2043 return ecx
& CPUID_EXT_VMX
;
2046 #define VMX_INVALID_GUEST_STATE 0x80000021
2048 int kvm_arch_handle_exit(CPUX86State
*env
, struct kvm_run
*run
)
2050 X86CPU
*cpu
= x86_env_get_cpu(env
);
2054 switch (run
->exit_reason
) {
2056 DPRINTF("handle_hlt\n");
2057 ret
= kvm_handle_halt(cpu
);
2059 case KVM_EXIT_SET_TPR
:
2062 case KVM_EXIT_TPR_ACCESS
:
2063 ret
= kvm_handle_tpr_access(env
);
2065 case KVM_EXIT_FAIL_ENTRY
:
2066 code
= run
->fail_entry
.hardware_entry_failure_reason
;
2067 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
2069 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
2071 "\nIf you're running a guest on an Intel machine without "
2072 "unrestricted mode\n"
2073 "support, the failure can be most likely due to the guest "
2074 "entering an invalid\n"
2075 "state for Intel VT. For example, the guest maybe running "
2076 "in big real mode\n"
2077 "which is not supported on less recent Intel processors."
2082 case KVM_EXIT_EXCEPTION
:
2083 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
2084 run
->ex
.exception
, run
->ex
.error_code
);
2087 case KVM_EXIT_DEBUG
:
2088 DPRINTF("kvm_exit_debug\n");
2089 ret
= kvm_handle_debug(env
, &run
->debug
.arch
);
2092 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
2100 bool kvm_arch_stop_on_emulation_error(CPUX86State
*env
)
2102 kvm_cpu_synchronize_state(env
);
2103 return !(env
->cr
[0] & CR0_PE_MASK
) ||
2104 ((env
->segs
[R_CS
].selector
& 3) != 3);
2107 void kvm_arch_init_irq_routing(KVMState
*s
)
2109 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
2110 /* If kernel can't do irq routing, interrupt source
2111 * override 0->2 cannot be set up as required by HPET.
2112 * So we have to disable it.
2116 /* We know at this point that we're using the in-kernel
2117 * irqchip, so we can use irqfds, and on x86 we know
2118 * we can use msi via irqfd and GSI routing.
2120 kvm_irqfds_allowed
= true;
2121 kvm_msi_via_irqfd_allowed
= true;
2122 kvm_gsi_routing_allowed
= true;
2125 /* Classic KVM device assignment interface. Will remain x86 only. */
2126 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
2127 uint32_t flags
, uint32_t *dev_id
)
2129 struct kvm_assigned_pci_dev dev_data
= {
2130 .segnr
= dev_addr
->domain
,
2131 .busnr
= dev_addr
->bus
,
2132 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
2137 dev_data
.assigned_dev_id
=
2138 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
2140 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
2145 *dev_id
= dev_data
.assigned_dev_id
;
2150 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
2152 struct kvm_assigned_pci_dev dev_data
= {
2153 .assigned_dev_id
= dev_id
,
2156 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
2159 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2160 uint32_t irq_type
, uint32_t guest_irq
)
2162 struct kvm_assigned_irq assigned_irq
= {
2163 .assigned_dev_id
= dev_id
,
2164 .guest_irq
= guest_irq
,
2168 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
2169 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
2171 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
2175 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
2178 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
2179 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
2181 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
2184 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
2186 struct kvm_assigned_pci_dev dev_data
= {
2187 .assigned_dev_id
= dev_id
,
2188 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
2191 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
2194 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2197 struct kvm_assigned_irq assigned_irq
= {
2198 .assigned_dev_id
= dev_id
,
2202 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
2205 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
2207 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
2208 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
2211 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
2213 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
2214 KVM_DEV_IRQ_GUEST_MSI
, virq
);
2217 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
2219 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
2220 KVM_DEV_IRQ_HOST_MSI
);
2223 bool kvm_device_msix_supported(KVMState
*s
)
2225 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2226 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2227 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
2230 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
2231 uint32_t nr_vectors
)
2233 struct kvm_assigned_msix_nr msix_nr
= {
2234 .assigned_dev_id
= dev_id
,
2235 .entry_nr
= nr_vectors
,
2238 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
2241 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
2244 struct kvm_assigned_msix_entry msix_entry
= {
2245 .assigned_dev_id
= dev_id
,
2250 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
2253 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
2255 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
2256 KVM_DEV_IRQ_GUEST_MSIX
, 0);
2259 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
2261 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
2262 KVM_DEV_IRQ_HOST_MSIX
);