target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5 #include "host-utils.h"
   6
   7 #include "exec-all.h"
   8 #include "kvm.h"
   9
  10 static const VMStateDescription vmstate_segment = {
  11     .name = "segment",
  12     .version_id = 1,
  13     .minimum_version_id = 1,
  14     .minimum_version_id_old = 1,
  15     .fields      = (VMStateField []) {
  16         VMSTATE_UINT32(selector, SegmentCache),
  17         VMSTATE_UINTTL(base, SegmentCache),
  18         VMSTATE_UINT32(limit, SegmentCache),
  19         VMSTATE_UINT32(flags, SegmentCache),
  20         VMSTATE_END_OF_LIST()
  21     }
  22 };
  23
  24 static void cpu_put_seg(QEMUFile *f, SegmentCache *dt)
  25 {
  26     vmstate_save_state(f, &vmstate_segment, dt);
  27 }
  28
  29 static void cpu_get_seg(QEMUFile *f, SegmentCache *dt)
  30 {
  31     vmstate_load_state(f, &vmstate_segment, dt, vmstate_segment.version_id);
  32 }
  33
  34 void cpu_save(QEMUFile *f, void *opaque)
  35 {
  36     CPUState *env = opaque;
  37     int i, bit;
  38
  39     cpu_synchronize_state(env);
  40
  41     for(i = 0; i < CPU_NB_REGS; i++)
  42         qemu_put_betls(f, &env->regs[i]);
  43     qemu_put_betls(f, &env->eip);
  44     qemu_put_betls(f, &env->eflags);
  45     qemu_put_be32s(f, &env->hflags);
  46
  47     /* FPU */
  48     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
  49     env->fptag_vmstate = 0;
  50     for(i = 0; i < 8; i++) {
  51         env->fptag_vmstate |= ((!env->fptags[i]) << i);
  52     }
  53
  54     qemu_put_be16s(f, &env->fpuc);
  55     qemu_put_be16s(f, &env->fpus_vmstate);
  56     qemu_put_be16s(f, &env->fptag_vmstate);
  57
  58 #ifdef USE_X86LDOUBLE
  59     env->fpregs_format_vmstate = 0;
  60 #else
  61     env->fpregs_format_vmstate = 1;
  62 #endif
  63     qemu_put_be16s(f, &env->fpregs_format_vmstate);
  64
  65     for(i = 0; i < 8; i++) {
  66 #ifdef USE_X86LDOUBLE
  67         {
  68             uint64_t mant;
  69             uint16_t exp;
  70             /* we save the real CPU data (in case of MMX usage only 'mant'
  71                contains the MMX register */
  72             cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
  73             qemu_put_be64(f, mant);
  74             qemu_put_be16(f, exp);
  75         }
  76 #else
  77         /* if we use doubles for float emulation, we save the doubles to
  78            avoid losing information in case of MMX usage. It can give
  79            problems if the image is restored on a CPU where long
  80            doubles are used instead. */
  81         qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
  82 #endif
  83     }
  84
  85     for(i = 0; i < 6; i++)
  86         cpu_put_seg(f, &env->segs[i]);
  87     cpu_put_seg(f, &env->ldt);
  88     cpu_put_seg(f, &env->tr);
  89     cpu_put_seg(f, &env->gdt);
  90     cpu_put_seg(f, &env->idt);
  91
  92     qemu_put_be32s(f, &env->sysenter_cs);
  93     qemu_put_betls(f, &env->sysenter_esp);
  94     qemu_put_betls(f, &env->sysenter_eip);
  95
  96     qemu_put_betls(f, &env->cr[0]);
  97     qemu_put_betls(f, &env->cr[2]);
  98     qemu_put_betls(f, &env->cr[3]);
  99     qemu_put_betls(f, &env->cr[4]);
 100
 101     for(i = 0; i < 8; i++)
 102         qemu_put_betls(f, &env->dr[i]);
 103
 104     /* MMU */
 105     qemu_put_sbe32s(f, &env->a20_mask);
 106
 107     /* XMM */
 108     qemu_put_be32s(f, &env->mxcsr);
 109     for(i = 0; i < CPU_NB_REGS; i++) {
 110         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 111         qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 112     }
 113
 114 #ifdef TARGET_X86_64
 115     qemu_put_be64s(f, &env->efer);
 116     qemu_put_be64s(f, &env->star);
 117     qemu_put_be64s(f, &env->lstar);
 118     qemu_put_be64s(f, &env->cstar);
 119     qemu_put_be64s(f, &env->fmask);
 120     qemu_put_be64s(f, &env->kernelgsbase);
 121 #endif
 122     qemu_put_be32s(f, &env->smbase);
 123
 124     qemu_put_be64s(f, &env->pat);
 125     qemu_put_be32s(f, &env->hflags2);
 126
 127     qemu_put_be64s(f, &env->vm_hsave);
 128     qemu_put_be64s(f, &env->vm_vmcb);
 129     qemu_put_be64s(f, &env->tsc_offset);
 130     qemu_put_be64s(f, &env->intercept);
 131     qemu_put_be16s(f, &env->intercept_cr_read);
 132     qemu_put_be16s(f, &env->intercept_cr_write);
 133     qemu_put_be16s(f, &env->intercept_dr_read);
 134     qemu_put_be16s(f, &env->intercept_dr_write);
 135     qemu_put_be32s(f, &env->intercept_exceptions);
 136     qemu_put_8s(f, &env->v_tpr);
 137
 138     /* MTRRs */
 139     for(i = 0; i < 11; i++)
 140         qemu_put_be64s(f, &env->mtrr_fixed[i]);
 141     qemu_put_be64s(f, &env->mtrr_deftype);
 142     for(i = 0; i < 8; i++) {
 143         qemu_put_be64s(f, &env->mtrr_var[i].base);
 144         qemu_put_be64s(f, &env->mtrr_var[i].mask);
 145     }
 146
 147     /* KVM-related states */
 148
 149     /* There can only be one pending IRQ set in the bitmap at a time, so try
 150        to find it and save its number instead (-1 for none). */
 151     env->pending_irq_vmstate = -1;
 152     for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
 153         if (env->interrupt_bitmap[i]) {
 154             bit = ctz64(env->interrupt_bitmap[i]);
 155             env->pending_irq_vmstate = i * 64 + bit;
 156             break;
 157         }
 158     }
 159     qemu_put_sbe32s(f, &env->pending_irq_vmstate);
 160     qemu_put_be32s(f, &env->mp_state);
 161     qemu_put_be64s(f, &env->tsc);
 162
 163     /* MCE */
 164     qemu_put_be64s(f, &env->mcg_cap);
 165     qemu_put_be64s(f, &env->mcg_status);
 166     qemu_put_be64s(f, &env->mcg_ctl);
 167     for (i = 0; i < MCE_BANKS_DEF * 4; i++) {
 168         qemu_put_be64s(f, &env->mce_banks[i]);
 169     }
 170     qemu_put_be64s(f, &env->tsc_aux);
 171  }
 172
 173 #ifdef USE_X86LDOUBLE
 174 /* XXX: add that in a FPU generic layer */
 175 union x86_longdouble {
 176     uint64_t mant;
 177     uint16_t exp;
 178 };
 179
 180 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
 181 #define EXPBIAS1 1023
 182 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
 183 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
 184
 185 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
 186 {
 187     int e;
 188     /* mantissa */
 189     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 190     /* exponent + sign */
 191     e = EXPD1(temp) - EXPBIAS1 + 16383;
 192     e |= SIGND1(temp) >> 16;
 193     p->exp = e;
 194 }
 195 #endif
 196
 197 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 198 {
 199     CPUState *env = opaque;
 200     int i, guess_mmx;
 201
 202     cpu_synchronize_state(env);
 203     if (version_id < 3 || version_id > CPU_SAVE_VERSION)
 204         return -EINVAL;
 205     for(i = 0; i < CPU_NB_REGS; i++)
 206         qemu_get_betls(f, &env->regs[i]);
 207     qemu_get_betls(f, &env->eip);
 208     qemu_get_betls(f, &env->eflags);
 209     qemu_get_be32s(f, &env->hflags);
 210
 211     qemu_get_be16s(f, &env->fpuc);
 212     qemu_get_be16s(f, &env->fpus_vmstate);
 213     qemu_get_be16s(f, &env->fptag_vmstate);
 214     qemu_get_be16s(f, &env->fpregs_format_vmstate);
 215
 216     /* NOTE: we cannot always restore the FPU state if the image come
 217        from a host with a different 'USE_X86LDOUBLE' define. We guess
 218        if we are in an MMX state to restore correctly in that case. */
 219     guess_mmx = ((env->fptag_vmstate == 0xff) && (env->fpus_vmstate & 0x3800) == 0);
 220     for(i = 0; i < 8; i++) {
 221         uint64_t mant;
 222         uint16_t exp;
 223
 224         switch(env->fpregs_format_vmstate) {
 225         case 0:
 226             mant = qemu_get_be64(f);
 227             exp = qemu_get_be16(f);
 228 #ifdef USE_X86LDOUBLE
 229             env->fpregs[i].d = cpu_set_fp80(mant, exp);
 230 #else
 231             /* difficult case */
 232             if (guess_mmx)
 233                 env->fpregs[i].mmx.MMX_Q(0) = mant;
 234             else
 235                 env->fpregs[i].d = cpu_set_fp80(mant, exp);
 236 #endif
 237             break;
 238         case 1:
 239             mant = qemu_get_be64(f);
 240 #ifdef USE_X86LDOUBLE
 241             {
 242                 union x86_longdouble *p;
 243                 /* difficult case */
 244                 p = (void *)&env->fpregs[i];
 245                 if (guess_mmx) {
 246                     p->mant = mant;
 247                     p->exp = 0xffff;
 248                 } else {
 249                     fp64_to_fp80(p, mant);
 250                 }
 251             }
 252 #else
 253             env->fpregs[i].mmx.MMX_Q(0) = mant;
 254 #endif
 255             break;
 256         default:
 257             return -EINVAL;
 258         }
 259     }
 260
 261     /* XXX: restore FPU round state */
 262     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 263     env->fpus = env->fpus_vmstate & ~0x3800;
 264     env->fptag_vmstate ^= 0xff;
 265     for(i = 0; i < 8; i++) {
 266         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 267     }
 268
 269     for(i = 0; i < 6; i++)
 270         cpu_get_seg(f, &env->segs[i]);
 271     cpu_get_seg(f, &env->ldt);
 272     cpu_get_seg(f, &env->tr);
 273     cpu_get_seg(f, &env->gdt);
 274     cpu_get_seg(f, &env->idt);
 275
 276     qemu_get_be32s(f, &env->sysenter_cs);
 277     if (version_id >= 7) {
 278         qemu_get_betls(f, &env->sysenter_esp);
 279         qemu_get_betls(f, &env->sysenter_eip);
 280     } else {
 281         env->sysenter_esp = qemu_get_be32(f);
 282         env->sysenter_eip = qemu_get_be32(f);
 283     }
 284
 285     qemu_get_betls(f, &env->cr[0]);
 286     qemu_get_betls(f, &env->cr[2]);
 287     qemu_get_betls(f, &env->cr[3]);
 288     qemu_get_betls(f, &env->cr[4]);
 289
 290     for(i = 0; i < 8; i++)
 291         qemu_get_betls(f, &env->dr[i]);
 292     cpu_breakpoint_remove_all(env, BP_CPU);
 293     cpu_watchpoint_remove_all(env, BP_CPU);
 294     for (i = 0; i < 4; i++)
 295         hw_breakpoint_insert(env, i);
 296
 297     qemu_get_sbe32s(f, &env->a20_mask);
 298
 299     qemu_get_be32s(f, &env->mxcsr);
 300     for(i = 0; i < CPU_NB_REGS; i++) {
 301         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(0));
 302         qemu_get_be64s(f, &env->xmm_regs[i].XMM_Q(1));
 303     }
 304
 305 #ifdef TARGET_X86_64
 306     qemu_get_be64s(f, &env->efer);
 307     qemu_get_be64s(f, &env->star);
 308     qemu_get_be64s(f, &env->lstar);
 309     qemu_get_be64s(f, &env->cstar);
 310     qemu_get_be64s(f, &env->fmask);
 311     qemu_get_be64s(f, &env->kernelgsbase);
 312 #endif
 313     if (version_id >= 4) {
 314         qemu_get_be32s(f, &env->smbase);
 315     }
 316     if (version_id >= 5) {
 317         qemu_get_be64s(f, &env->pat);
 318         qemu_get_be32s(f, &env->hflags2);
 319         if (version_id < 6)
 320             qemu_get_be32s(f, &env->halted);
 321
 322         qemu_get_be64s(f, &env->vm_hsave);
 323         qemu_get_be64s(f, &env->vm_vmcb);
 324         qemu_get_be64s(f, &env->tsc_offset);
 325         qemu_get_be64s(f, &env->intercept);
 326         qemu_get_be16s(f, &env->intercept_cr_read);
 327         qemu_get_be16s(f, &env->intercept_cr_write);
 328         qemu_get_be16s(f, &env->intercept_dr_read);
 329         qemu_get_be16s(f, &env->intercept_dr_write);
 330         qemu_get_be32s(f, &env->intercept_exceptions);
 331         qemu_get_8s(f, &env->v_tpr);
 332     }
 333
 334     if (version_id >= 8) {
 335         /* MTRRs */
 336         for(i = 0; i < 11; i++)
 337             qemu_get_be64s(f, &env->mtrr_fixed[i]);
 338         qemu_get_be64s(f, &env->mtrr_deftype);
 339         for(i = 0; i < 8; i++) {
 340             qemu_get_be64s(f, &env->mtrr_var[i].base);
 341             qemu_get_be64s(f, &env->mtrr_var[i].mask);
 342         }
 343     }
 344
 345     if (version_id >= 9) {
 346         qemu_get_sbe32s(f, &env->pending_irq_vmstate);
 347         memset(&env->interrupt_bitmap, 0, sizeof(env->interrupt_bitmap));
 348         if (env->pending_irq_vmstate >= 0) {
 349             env->interrupt_bitmap[env->pending_irq_vmstate / 64] |=
 350                 (uint64_t)1 << (env->pending_irq_vmstate % 64);
 351         }
 352         qemu_get_be32s(f, &env->mp_state);
 353         qemu_get_be64s(f, &env->tsc);
 354     }
 355
 356     if (version_id >= 10) {
 357         qemu_get_be64s(f, &env->mcg_cap);
 358         qemu_get_be64s(f, &env->mcg_status);
 359         qemu_get_be64s(f, &env->mcg_ctl);
 360         for (i = 0; i < MCE_BANKS_DEF * 4; i++) {
 361             qemu_get_be64s(f, &env->mce_banks[i]);
 362         }
 363     }
 364
 365     if (version_id >= 11) {
 366         qemu_get_be64s(f, &env->tsc_aux);
 367     }
 368
 369     tlb_flush(env, 1);
 370     return 0;
 371 }