4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "dyngen-exec.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
29 /* check if Port I/O is allowed in TSS */
30 static inline void check_io(int addr
, int size
)
32 int io_offset
, val
, mask
;
34 /* TSS must be a valid 32 bit one */
35 if (!(env
->tr
.flags
& DESC_P_MASK
) ||
36 ((env
->tr
.flags
>> DESC_TYPE_SHIFT
) & 0xf) != 9 ||
37 env
->tr
.limit
< 103) {
40 io_offset
= lduw_kernel(env
->tr
.base
+ 0x66);
41 io_offset
+= (addr
>> 3);
42 /* Note: the check needs two bytes */
43 if ((io_offset
+ 1) > env
->tr
.limit
) {
46 val
= lduw_kernel(env
->tr
.base
+ io_offset
);
48 mask
= (1 << size
) - 1;
49 /* all bits must be zero to allow the I/O */
50 if ((val
& mask
) != 0) {
52 raise_exception_err(env
, EXCP0D_GPF
, 0);
56 void helper_check_iob(uint32_t t0
)
61 void helper_check_iow(uint32_t t0
)
66 void helper_check_iol(uint32_t t0
)
71 void helper_outb(uint32_t port
, uint32_t data
)
73 cpu_outb(port
, data
& 0xff);
76 target_ulong
helper_inb(uint32_t port
)
81 void helper_outw(uint32_t port
, uint32_t data
)
83 cpu_outw(port
, data
& 0xffff);
86 target_ulong
helper_inw(uint32_t port
)
91 void helper_outl(uint32_t port
, uint32_t data
)
96 target_ulong
helper_inl(uint32_t port
)
101 void helper_into(int next_eip_addend
)
105 eflags
= helper_cc_compute_all(CC_OP
);
107 raise_interrupt(env
, EXCP04_INTO
, 1, 0, next_eip_addend
);
111 void helper_single_step(void)
113 #ifndef CONFIG_USER_ONLY
114 check_hw_breakpoints(env
, 1);
115 env
->dr
[6] |= DR6_BS
;
117 raise_exception(env
, EXCP01_DB
);
120 void helper_cpuid(void)
122 uint32_t eax
, ebx
, ecx
, edx
;
124 cpu_svm_check_intercept_param(env
, SVM_EXIT_CPUID
, 0);
126 cpu_x86_cpuid(env
, (uint32_t)EAX
, (uint32_t)ECX
, &eax
, &ebx
, &ecx
, &edx
);
133 #if defined(CONFIG_USER_ONLY)
134 target_ulong
helper_read_crN(int reg
)
139 void helper_write_crN(int reg
, target_ulong t0
)
143 void helper_movl_drN_T0(int reg
, target_ulong t0
)
147 target_ulong
helper_read_crN(int reg
)
151 cpu_svm_check_intercept_param(env
, SVM_EXIT_READ_CR0
+ reg
, 0);
157 if (!(env
->hflags2
& HF2_VINTR_MASK
)) {
158 val
= cpu_get_apic_tpr(env
->apic_state
);
167 void helper_write_crN(int reg
, target_ulong t0
)
169 cpu_svm_check_intercept_param(env
, SVM_EXIT_WRITE_CR0
+ reg
, 0);
172 cpu_x86_update_cr0(env
, t0
);
175 cpu_x86_update_cr3(env
, t0
);
178 cpu_x86_update_cr4(env
, t0
);
181 if (!(env
->hflags2
& HF2_VINTR_MASK
)) {
182 cpu_set_apic_tpr(env
->apic_state
, t0
);
184 env
->v_tpr
= t0
& 0x0f;
192 void helper_movl_drN_T0(int reg
, target_ulong t0
)
197 hw_breakpoint_remove(env
, reg
);
199 hw_breakpoint_insert(env
, reg
);
200 } else if (reg
== 7) {
201 for (i
= 0; i
< 4; i
++) {
202 hw_breakpoint_remove(env
, i
);
205 for (i
= 0; i
< 4; i
++) {
206 hw_breakpoint_insert(env
, i
);
214 void helper_lmsw(target_ulong t0
)
216 /* only 4 lower bits of CR0 are modified. PE cannot be set to zero
217 if already set to one. */
218 t0
= (env
->cr
[0] & ~0xe) | (t0
& 0xf);
219 helper_write_crN(0, t0
);
222 void helper_invlpg(target_ulong addr
)
224 cpu_svm_check_intercept_param(env
, SVM_EXIT_INVLPG
, 0);
225 tlb_flush_page(env
, addr
);
228 void helper_rdtsc(void)
232 if ((env
->cr
[4] & CR4_TSD_MASK
) && ((env
->hflags
& HF_CPL_MASK
) != 0)) {
233 raise_exception(env
, EXCP0D_GPF
);
235 cpu_svm_check_intercept_param(env
, SVM_EXIT_RDTSC
, 0);
237 val
= cpu_get_tsc(env
) + env
->tsc_offset
;
238 EAX
= (uint32_t)(val
);
239 EDX
= (uint32_t)(val
>> 32);
242 void helper_rdtscp(void)
245 ECX
= (uint32_t)(env
->tsc_aux
);
248 void helper_rdpmc(void)
250 if ((env
->cr
[4] & CR4_PCE_MASK
) && ((env
->hflags
& HF_CPL_MASK
) != 0)) {
251 raise_exception(env
, EXCP0D_GPF
);
253 cpu_svm_check_intercept_param(env
, SVM_EXIT_RDPMC
, 0);
255 /* currently unimplemented */
256 qemu_log_mask(LOG_UNIMP
, "x86: unimplemented rdpmc\n");
257 raise_exception_err(env
, EXCP06_ILLOP
, 0);
260 #if defined(CONFIG_USER_ONLY)
261 void helper_wrmsr(void)
265 void helper_rdmsr(void)
269 void helper_wrmsr(void)
273 cpu_svm_check_intercept_param(env
, SVM_EXIT_MSR
, 1);
275 val
= ((uint32_t)EAX
) | ((uint64_t)((uint32_t)EDX
) << 32);
277 switch ((uint32_t)ECX
) {
278 case MSR_IA32_SYSENTER_CS
:
279 env
->sysenter_cs
= val
& 0xffff;
281 case MSR_IA32_SYSENTER_ESP
:
282 env
->sysenter_esp
= val
;
284 case MSR_IA32_SYSENTER_EIP
:
285 env
->sysenter_eip
= val
;
287 case MSR_IA32_APICBASE
:
288 cpu_set_apic_base(env
->apic_state
, val
);
292 uint64_t update_mask
;
295 if (env
->cpuid_ext2_features
& CPUID_EXT2_SYSCALL
) {
296 update_mask
|= MSR_EFER_SCE
;
298 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
299 update_mask
|= MSR_EFER_LME
;
301 if (env
->cpuid_ext2_features
& CPUID_EXT2_FFXSR
) {
302 update_mask
|= MSR_EFER_FFXSR
;
304 if (env
->cpuid_ext2_features
& CPUID_EXT2_NX
) {
305 update_mask
|= MSR_EFER_NXE
;
307 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
308 update_mask
|= MSR_EFER_SVME
;
310 if (env
->cpuid_ext2_features
& CPUID_EXT2_FFXSR
) {
311 update_mask
|= MSR_EFER_FFXSR
;
313 cpu_load_efer(env
, (env
->efer
& ~update_mask
) |
314 (val
& update_mask
));
323 case MSR_VM_HSAVE_PA
:
337 env
->segs
[R_FS
].base
= val
;
340 env
->segs
[R_GS
].base
= val
;
342 case MSR_KERNELGSBASE
:
343 env
->kernelgsbase
= val
;
346 case MSR_MTRRphysBase(0):
347 case MSR_MTRRphysBase(1):
348 case MSR_MTRRphysBase(2):
349 case MSR_MTRRphysBase(3):
350 case MSR_MTRRphysBase(4):
351 case MSR_MTRRphysBase(5):
352 case MSR_MTRRphysBase(6):
353 case MSR_MTRRphysBase(7):
354 env
->mtrr_var
[((uint32_t)ECX
- MSR_MTRRphysBase(0)) / 2].base
= val
;
356 case MSR_MTRRphysMask(0):
357 case MSR_MTRRphysMask(1):
358 case MSR_MTRRphysMask(2):
359 case MSR_MTRRphysMask(3):
360 case MSR_MTRRphysMask(4):
361 case MSR_MTRRphysMask(5):
362 case MSR_MTRRphysMask(6):
363 case MSR_MTRRphysMask(7):
364 env
->mtrr_var
[((uint32_t)ECX
- MSR_MTRRphysMask(0)) / 2].mask
= val
;
366 case MSR_MTRRfix64K_00000
:
367 env
->mtrr_fixed
[(uint32_t)ECX
- MSR_MTRRfix64K_00000
] = val
;
369 case MSR_MTRRfix16K_80000
:
370 case MSR_MTRRfix16K_A0000
:
371 env
->mtrr_fixed
[(uint32_t)ECX
- MSR_MTRRfix16K_80000
+ 1] = val
;
373 case MSR_MTRRfix4K_C0000
:
374 case MSR_MTRRfix4K_C8000
:
375 case MSR_MTRRfix4K_D0000
:
376 case MSR_MTRRfix4K_D8000
:
377 case MSR_MTRRfix4K_E0000
:
378 case MSR_MTRRfix4K_E8000
:
379 case MSR_MTRRfix4K_F0000
:
380 case MSR_MTRRfix4K_F8000
:
381 env
->mtrr_fixed
[(uint32_t)ECX
- MSR_MTRRfix4K_C0000
+ 3] = val
;
383 case MSR_MTRRdefType
:
384 env
->mtrr_deftype
= val
;
387 env
->mcg_status
= val
;
390 if ((env
->mcg_cap
& MCG_CTL_P
)
391 && (val
== 0 || val
== ~(uint64_t)0)) {
398 case MSR_IA32_MISC_ENABLE
:
399 env
->msr_ia32_misc_enable
= val
;
402 if ((uint32_t)ECX
>= MSR_MC0_CTL
403 && (uint32_t)ECX
< MSR_MC0_CTL
+ (4 * env
->mcg_cap
& 0xff)) {
404 uint32_t offset
= (uint32_t)ECX
- MSR_MC0_CTL
;
405 if ((offset
& 0x3) != 0
406 || (val
== 0 || val
== ~(uint64_t)0)) {
407 env
->mce_banks
[offset
] = val
;
411 /* XXX: exception? */
416 void helper_rdmsr(void)
420 cpu_svm_check_intercept_param(env
, SVM_EXIT_MSR
, 0);
422 switch ((uint32_t)ECX
) {
423 case MSR_IA32_SYSENTER_CS
:
424 val
= env
->sysenter_cs
;
426 case MSR_IA32_SYSENTER_ESP
:
427 val
= env
->sysenter_esp
;
429 case MSR_IA32_SYSENTER_EIP
:
430 val
= env
->sysenter_eip
;
432 case MSR_IA32_APICBASE
:
433 val
= cpu_get_apic_base(env
->apic_state
);
444 case MSR_VM_HSAVE_PA
:
447 case MSR_IA32_PERF_STATUS
:
448 /* tsc_increment_by_tick */
451 val
|= (((uint64_t)4ULL) << 40);
464 val
= env
->segs
[R_FS
].base
;
467 val
= env
->segs
[R_GS
].base
;
469 case MSR_KERNELGSBASE
:
470 val
= env
->kernelgsbase
;
476 case MSR_MTRRphysBase(0):
477 case MSR_MTRRphysBase(1):
478 case MSR_MTRRphysBase(2):
479 case MSR_MTRRphysBase(3):
480 case MSR_MTRRphysBase(4):
481 case MSR_MTRRphysBase(5):
482 case MSR_MTRRphysBase(6):
483 case MSR_MTRRphysBase(7):
484 val
= env
->mtrr_var
[((uint32_t)ECX
- MSR_MTRRphysBase(0)) / 2].base
;
486 case MSR_MTRRphysMask(0):
487 case MSR_MTRRphysMask(1):
488 case MSR_MTRRphysMask(2):
489 case MSR_MTRRphysMask(3):
490 case MSR_MTRRphysMask(4):
491 case MSR_MTRRphysMask(5):
492 case MSR_MTRRphysMask(6):
493 case MSR_MTRRphysMask(7):
494 val
= env
->mtrr_var
[((uint32_t)ECX
- MSR_MTRRphysMask(0)) / 2].mask
;
496 case MSR_MTRRfix64K_00000
:
497 val
= env
->mtrr_fixed
[0];
499 case MSR_MTRRfix16K_80000
:
500 case MSR_MTRRfix16K_A0000
:
501 val
= env
->mtrr_fixed
[(uint32_t)ECX
- MSR_MTRRfix16K_80000
+ 1];
503 case MSR_MTRRfix4K_C0000
:
504 case MSR_MTRRfix4K_C8000
:
505 case MSR_MTRRfix4K_D0000
:
506 case MSR_MTRRfix4K_D8000
:
507 case MSR_MTRRfix4K_E0000
:
508 case MSR_MTRRfix4K_E8000
:
509 case MSR_MTRRfix4K_F0000
:
510 case MSR_MTRRfix4K_F8000
:
511 val
= env
->mtrr_fixed
[(uint32_t)ECX
- MSR_MTRRfix4K_C0000
+ 3];
513 case MSR_MTRRdefType
:
514 val
= env
->mtrr_deftype
;
517 if (env
->cpuid_features
& CPUID_MTRR
) {
518 val
= MSR_MTRRcap_VCNT
| MSR_MTRRcap_FIXRANGE_SUPPORT
|
519 MSR_MTRRcap_WC_SUPPORTED
;
521 /* XXX: exception? */
529 if (env
->mcg_cap
& MCG_CTL_P
) {
536 val
= env
->mcg_status
;
538 case MSR_IA32_MISC_ENABLE
:
539 val
= env
->msr_ia32_misc_enable
;
542 if ((uint32_t)ECX
>= MSR_MC0_CTL
543 && (uint32_t)ECX
< MSR_MC0_CTL
+ (4 * env
->mcg_cap
& 0xff)) {
544 uint32_t offset
= (uint32_t)ECX
- MSR_MC0_CTL
;
545 val
= env
->mce_banks
[offset
];
548 /* XXX: exception? */
552 EAX
= (uint32_t)(val
);
553 EDX
= (uint32_t)(val
>> 32);
557 static void do_hlt(void)
559 env
->hflags
&= ~HF_INHIBIT_IRQ_MASK
; /* needed if sti is just before */
561 env
->exception_index
= EXCP_HLT
;
565 void helper_hlt(int next_eip_addend
)
567 cpu_svm_check_intercept_param(env
, SVM_EXIT_HLT
, 0);
568 EIP
+= next_eip_addend
;
573 void helper_monitor(target_ulong ptr
)
575 if ((uint32_t)ECX
!= 0) {
576 raise_exception(env
, EXCP0D_GPF
);
578 /* XXX: store address? */
579 cpu_svm_check_intercept_param(env
, SVM_EXIT_MONITOR
, 0);
582 void helper_mwait(int next_eip_addend
)
584 if ((uint32_t)ECX
!= 0) {
585 raise_exception(env
, EXCP0D_GPF
);
587 cpu_svm_check_intercept_param(env
, SVM_EXIT_MWAIT
, 0);
588 EIP
+= next_eip_addend
;
590 /* XXX: not complete but not completely erroneous */
591 if (env
->cpu_index
!= 0 || env
->next_cpu
!= NULL
) {
592 /* more than one CPU: do not sleep because another CPU may
599 void helper_debug(void)
601 env
->exception_index
= EXCP_DEBUG
;