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x86: use wrappers for memory access helpers
[qemu.git] / target-i386 / seg_helper.c
1 /*
2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "dyngen-exec.h"
23 #include "qemu-log.h"
24 #include "helper.h"
25
26 //#define DEBUG_PCALL
27
28 #ifdef DEBUG_PCALL
29 # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
30 # define LOG_PCALL_STATE(env) \
31 log_cpu_state_mask(CPU_LOG_PCALL, (env), X86_DUMP_CCOP)
32 #else
33 # define LOG_PCALL(...) do { } while (0)
34 # define LOG_PCALL_STATE(env) do { } while (0)
35 #endif
36
37 /* return non zero if error */
38 static inline int load_segment(uint32_t *e1_ptr, uint32_t *e2_ptr,
39 int selector)
40 {
41 SegmentCache *dt;
42 int index;
43 target_ulong ptr;
44
45 if (selector & 0x4) {
46 dt = &env->ldt;
47 } else {
48 dt = &env->gdt;
49 }
50 index = selector & ~7;
51 if ((index + 7) > dt->limit) {
52 return -1;
53 }
54 ptr = dt->base + index;
55 *e1_ptr = cpu_ldl_kernel(env, ptr);
56 *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
57 return 0;
58 }
59
60 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
61 {
62 unsigned int limit;
63
64 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
65 if (e2 & DESC_G_MASK) {
66 limit = (limit << 12) | 0xfff;
67 }
68 return limit;
69 }
70
71 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
72 {
73 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
74 }
75
76 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
77 uint32_t e2)
78 {
79 sc->base = get_seg_base(e1, e2);
80 sc->limit = get_seg_limit(e1, e2);
81 sc->flags = e2;
82 }
83
84 /* init the segment cache in vm86 mode. */
85 static inline void load_seg_vm(int seg, int selector)
86 {
87 selector &= 0xffff;
88 cpu_x86_load_seg_cache(env, seg, selector,
89 (selector << 4), 0xffff, 0);
90 }
91
92 static inline void get_ss_esp_from_tss(uint32_t *ss_ptr,
93 uint32_t *esp_ptr, int dpl)
94 {
95 int type, index, shift;
96
97 #if 0
98 {
99 int i;
100 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
101 for (i = 0; i < env->tr.limit; i++) {
102 printf("%02x ", env->tr.base[i]);
103 if ((i & 7) == 7) {
104 printf("\n");
105 }
106 }
107 printf("\n");
108 }
109 #endif
110
111 if (!(env->tr.flags & DESC_P_MASK)) {
112 cpu_abort(env, "invalid tss");
113 }
114 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
115 if ((type & 7) != 1) {
116 cpu_abort(env, "invalid tss type");
117 }
118 shift = type >> 3;
119 index = (dpl * 4 + 2) << shift;
120 if (index + (4 << shift) - 1 > env->tr.limit) {
121 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
122 }
123 if (shift == 0) {
124 *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index);
125 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
126 } else {
127 *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index);
128 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
129 }
130 }
131
132 /* XXX: merge with load_seg() */
133 static void tss_load_seg(int seg_reg, int selector)
134 {
135 uint32_t e1, e2;
136 int rpl, dpl, cpl;
137
138 if ((selector & 0xfffc) != 0) {
139 if (load_segment(&e1, &e2, selector) != 0) {
140 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
141 }
142 if (!(e2 & DESC_S_MASK)) {
143 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
144 }
145 rpl = selector & 3;
146 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
147 cpl = env->hflags & HF_CPL_MASK;
148 if (seg_reg == R_CS) {
149 if (!(e2 & DESC_CS_MASK)) {
150 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
151 }
152 /* XXX: is it correct? */
153 if (dpl != rpl) {
154 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
155 }
156 if ((e2 & DESC_C_MASK) && dpl > rpl) {
157 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
158 }
159 } else if (seg_reg == R_SS) {
160 /* SS must be writable data */
161 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
162 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
163 }
164 if (dpl != cpl || dpl != rpl) {
165 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
166 }
167 } else {
168 /* not readable code */
169 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
170 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
171 }
172 /* if data or non conforming code, checks the rights */
173 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
174 if (dpl < cpl || dpl < rpl) {
175 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
176 }
177 }
178 }
179 if (!(e2 & DESC_P_MASK)) {
180 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
181 }
182 cpu_x86_load_seg_cache(env, seg_reg, selector,
183 get_seg_base(e1, e2),
184 get_seg_limit(e1, e2),
185 e2);
186 } else {
187 if (seg_reg == R_SS || seg_reg == R_CS) {
188 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
189 }
190 }
191 }
192
193 #define SWITCH_TSS_JMP 0
194 #define SWITCH_TSS_IRET 1
195 #define SWITCH_TSS_CALL 2
196
197 /* XXX: restore CPU state in registers (PowerPC case) */
198 static void switch_tss(int tss_selector,
199 uint32_t e1, uint32_t e2, int source,
200 uint32_t next_eip)
201 {
202 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
203 target_ulong tss_base;
204 uint32_t new_regs[8], new_segs[6];
205 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
206 uint32_t old_eflags, eflags_mask;
207 SegmentCache *dt;
208 int index;
209 target_ulong ptr;
210
211 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
212 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
213 source);
214
215 /* if task gate, we read the TSS segment and we load it */
216 if (type == 5) {
217 if (!(e2 & DESC_P_MASK)) {
218 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
219 }
220 tss_selector = e1 >> 16;
221 if (tss_selector & 4) {
222 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
223 }
224 if (load_segment(&e1, &e2, tss_selector) != 0) {
225 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
226 }
227 if (e2 & DESC_S_MASK) {
228 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
229 }
230 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
231 if ((type & 7) != 1) {
232 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
233 }
234 }
235
236 if (!(e2 & DESC_P_MASK)) {
237 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
238 }
239
240 if (type & 8) {
241 tss_limit_max = 103;
242 } else {
243 tss_limit_max = 43;
244 }
245 tss_limit = get_seg_limit(e1, e2);
246 tss_base = get_seg_base(e1, e2);
247 if ((tss_selector & 4) != 0 ||
248 tss_limit < tss_limit_max) {
249 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
250 }
251 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
252 if (old_type & 8) {
253 old_tss_limit_max = 103;
254 } else {
255 old_tss_limit_max = 43;
256 }
257
258 /* read all the registers from the new TSS */
259 if (type & 8) {
260 /* 32 bit */
261 new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
262 new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
263 new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
264 for (i = 0; i < 8; i++) {
265 new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4));
266 }
267 for (i = 0; i < 6; i++) {
268 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4));
269 }
270 new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
271 new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
272 } else {
273 /* 16 bit */
274 new_cr3 = 0;
275 new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
276 new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
277 for (i = 0; i < 8; i++) {
278 new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) |
279 0xffff0000;
280 }
281 for (i = 0; i < 4; i++) {
282 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4));
283 }
284 new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
285 new_segs[R_FS] = 0;
286 new_segs[R_GS] = 0;
287 new_trap = 0;
288 }
289 /* XXX: avoid a compiler warning, see
290 http://support.amd.com/us/Processor_TechDocs/24593.pdf
291 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
292 (void)new_trap;
293
294 /* NOTE: we must avoid memory exceptions during the task switch,
295 so we make dummy accesses before */
296 /* XXX: it can still fail in some cases, so a bigger hack is
297 necessary to valid the TLB after having done the accesses */
298
299 v1 = cpu_ldub_kernel(env, env->tr.base);
300 v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max);
301 cpu_stb_kernel(env, env->tr.base, v1);
302 cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2);
303
304 /* clear busy bit (it is restartable) */
305 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
306 target_ulong ptr;
307 uint32_t e2;
308
309 ptr = env->gdt.base + (env->tr.selector & ~7);
310 e2 = cpu_ldl_kernel(env, ptr + 4);
311 e2 &= ~DESC_TSS_BUSY_MASK;
312 cpu_stl_kernel(env, ptr + 4, e2);
313 }
314 old_eflags = cpu_compute_eflags(env);
315 if (source == SWITCH_TSS_IRET) {
316 old_eflags &= ~NT_MASK;
317 }
318
319 /* save the current state in the old TSS */
320 if (type & 8) {
321 /* 32 bit */
322 cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
323 cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
324 cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), EAX);
325 cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX);
326 cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX);
327 cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), EBX);
328 cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP);
329 cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP);
330 cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI);
331 cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI);
332 for (i = 0; i < 6; i++) {
333 cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
334 env->segs[i].selector);
335 }
336 } else {
337 /* 16 bit */
338 cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
339 cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
340 cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), EAX);
341 cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX);
342 cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX);
343 cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), EBX);
344 cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP);
345 cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP);
346 cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI);
347 cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI);
348 for (i = 0; i < 4; i++) {
349 cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
350 env->segs[i].selector);
351 }
352 }
353
354 /* now if an exception occurs, it will occurs in the next task
355 context */
356
357 if (source == SWITCH_TSS_CALL) {
358 cpu_stw_kernel(env, tss_base, env->tr.selector);
359 new_eflags |= NT_MASK;
360 }
361
362 /* set busy bit */
363 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
364 target_ulong ptr;
365 uint32_t e2;
366
367 ptr = env->gdt.base + (tss_selector & ~7);
368 e2 = cpu_ldl_kernel(env, ptr + 4);
369 e2 |= DESC_TSS_BUSY_MASK;
370 cpu_stl_kernel(env, ptr + 4, e2);
371 }
372
373 /* set the new CPU state */
374 /* from this point, any exception which occurs can give problems */
375 env->cr[0] |= CR0_TS_MASK;
376 env->hflags |= HF_TS_MASK;
377 env->tr.selector = tss_selector;
378 env->tr.base = tss_base;
379 env->tr.limit = tss_limit;
380 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
381
382 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
383 cpu_x86_update_cr3(env, new_cr3);
384 }
385
386 /* load all registers without an exception, then reload them with
387 possible exception */
388 env->eip = new_eip;
389 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
390 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
391 if (!(type & 8)) {
392 eflags_mask &= 0xffff;
393 }
394 cpu_load_eflags(env, new_eflags, eflags_mask);
395 /* XXX: what to do in 16 bit case? */
396 EAX = new_regs[0];
397 ECX = new_regs[1];
398 EDX = new_regs[2];
399 EBX = new_regs[3];
400 ESP = new_regs[4];
401 EBP = new_regs[5];
402 ESI = new_regs[6];
403 EDI = new_regs[7];
404 if (new_eflags & VM_MASK) {
405 for (i = 0; i < 6; i++) {
406 load_seg_vm(i, new_segs[i]);
407 }
408 /* in vm86, CPL is always 3 */
409 cpu_x86_set_cpl(env, 3);
410 } else {
411 /* CPL is set the RPL of CS */
412 cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
413 /* first just selectors as the rest may trigger exceptions */
414 for (i = 0; i < 6; i++) {
415 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
416 }
417 }
418
419 env->ldt.selector = new_ldt & ~4;
420 env->ldt.base = 0;
421 env->ldt.limit = 0;
422 env->ldt.flags = 0;
423
424 /* load the LDT */
425 if (new_ldt & 4) {
426 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
427 }
428
429 if ((new_ldt & 0xfffc) != 0) {
430 dt = &env->gdt;
431 index = new_ldt & ~7;
432 if ((index + 7) > dt->limit) {
433 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
434 }
435 ptr = dt->base + index;
436 e1 = cpu_ldl_kernel(env, ptr);
437 e2 = cpu_ldl_kernel(env, ptr + 4);
438 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
439 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
440 }
441 if (!(e2 & DESC_P_MASK)) {
442 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
443 }
444 load_seg_cache_raw_dt(&env->ldt, e1, e2);
445 }
446
447 /* load the segments */
448 if (!(new_eflags & VM_MASK)) {
449 tss_load_seg(R_CS, new_segs[R_CS]);
450 tss_load_seg(R_SS, new_segs[R_SS]);
451 tss_load_seg(R_ES, new_segs[R_ES]);
452 tss_load_seg(R_DS, new_segs[R_DS]);
453 tss_load_seg(R_FS, new_segs[R_FS]);
454 tss_load_seg(R_GS, new_segs[R_GS]);
455 }
456
457 /* check that EIP is in the CS segment limits */
458 if (new_eip > env->segs[R_CS].limit) {
459 /* XXX: different exception if CALL? */
460 raise_exception_err(env, EXCP0D_GPF, 0);
461 }
462
463 #ifndef CONFIG_USER_ONLY
464 /* reset local breakpoints */
465 if (env->dr[7] & 0x55) {
466 for (i = 0; i < 4; i++) {
467 if (hw_breakpoint_enabled(env->dr[7], i) == 0x1) {
468 hw_breakpoint_remove(env, i);
469 }
470 }
471 env->dr[7] &= ~0x55;
472 }
473 #endif
474 }
475
476 static inline unsigned int get_sp_mask(unsigned int e2)
477 {
478 if (e2 & DESC_B_MASK) {
479 return 0xffffffff;
480 } else {
481 return 0xffff;
482 }
483 }
484
485 static int exception_has_error_code(int intno)
486 {
487 switch (intno) {
488 case 8:
489 case 10:
490 case 11:
491 case 12:
492 case 13:
493 case 14:
494 case 17:
495 return 1;
496 }
497 return 0;
498 }
499
500 #ifdef TARGET_X86_64
501 #define SET_ESP(val, sp_mask) \
502 do { \
503 if ((sp_mask) == 0xffff) { \
504 ESP = (ESP & ~0xffff) | ((val) & 0xffff); \
505 } else if ((sp_mask) == 0xffffffffLL) { \
506 ESP = (uint32_t)(val); \
507 } else { \
508 ESP = (val); \
509 } \
510 } while (0)
511 #else
512 #define SET_ESP(val, sp_mask) \
513 do { \
514 ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \
515 } while (0)
516 #endif
517
518 /* in 64-bit machines, this can overflow. So this segment addition macro
519 * can be used to trim the value to 32-bit whenever needed */
520 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
521
522 /* XXX: add a is_user flag to have proper security support */
523 #define PUSHW(ssp, sp, sp_mask, val) \
524 { \
525 sp -= 2; \
526 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
527 }
528
529 #define PUSHL(ssp, sp, sp_mask, val) \
530 { \
531 sp -= 4; \
532 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
533 }
534
535 #define POPW(ssp, sp, sp_mask, val) \
536 { \
537 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
538 sp += 2; \
539 }
540
541 #define POPL(ssp, sp, sp_mask, val) \
542 { \
543 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
544 sp += 4; \
545 }
546
547 /* protected mode interrupt */
548 static void do_interrupt_protected(int intno, int is_int, int error_code,
549 unsigned int next_eip, int is_hw)
550 {
551 SegmentCache *dt;
552 target_ulong ptr, ssp;
553 int type, dpl, selector, ss_dpl, cpl;
554 int has_error_code, new_stack, shift;
555 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
556 uint32_t old_eip, sp_mask;
557
558 has_error_code = 0;
559 if (!is_int && !is_hw) {
560 has_error_code = exception_has_error_code(intno);
561 }
562 if (is_int) {
563 old_eip = next_eip;
564 } else {
565 old_eip = env->eip;
566 }
567
568 dt = &env->idt;
569 if (intno * 8 + 7 > dt->limit) {
570 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
571 }
572 ptr = dt->base + intno * 8;
573 e1 = cpu_ldl_kernel(env, ptr);
574 e2 = cpu_ldl_kernel(env, ptr + 4);
575 /* check gate type */
576 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
577 switch (type) {
578 case 5: /* task gate */
579 /* must do that check here to return the correct error code */
580 if (!(e2 & DESC_P_MASK)) {
581 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
582 }
583 switch_tss(intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
584 if (has_error_code) {
585 int type;
586 uint32_t mask;
587
588 /* push the error code */
589 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
590 shift = type >> 3;
591 if (env->segs[R_SS].flags & DESC_B_MASK) {
592 mask = 0xffffffff;
593 } else {
594 mask = 0xffff;
595 }
596 esp = (ESP - (2 << shift)) & mask;
597 ssp = env->segs[R_SS].base + esp;
598 if (shift) {
599 cpu_stl_kernel(env, ssp, error_code);
600 } else {
601 cpu_stw_kernel(env, ssp, error_code);
602 }
603 SET_ESP(esp, mask);
604 }
605 return;
606 case 6: /* 286 interrupt gate */
607 case 7: /* 286 trap gate */
608 case 14: /* 386 interrupt gate */
609 case 15: /* 386 trap gate */
610 break;
611 default:
612 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
613 break;
614 }
615 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
616 cpl = env->hflags & HF_CPL_MASK;
617 /* check privilege if software int */
618 if (is_int && dpl < cpl) {
619 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
620 }
621 /* check valid bit */
622 if (!(e2 & DESC_P_MASK)) {
623 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
624 }
625 selector = e1 >> 16;
626 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
627 if ((selector & 0xfffc) == 0) {
628 raise_exception_err(env, EXCP0D_GPF, 0);
629 }
630 if (load_segment(&e1, &e2, selector) != 0) {
631 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
632 }
633 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
634 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
635 }
636 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
637 if (dpl > cpl) {
638 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
639 }
640 if (!(e2 & DESC_P_MASK)) {
641 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
642 }
643 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
644 /* to inner privilege */
645 get_ss_esp_from_tss(&ss, &esp, dpl);
646 if ((ss & 0xfffc) == 0) {
647 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
648 }
649 if ((ss & 3) != dpl) {
650 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
651 }
652 if (load_segment(&ss_e1, &ss_e2, ss) != 0) {
653 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
654 }
655 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
656 if (ss_dpl != dpl) {
657 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
658 }
659 if (!(ss_e2 & DESC_S_MASK) ||
660 (ss_e2 & DESC_CS_MASK) ||
661 !(ss_e2 & DESC_W_MASK)) {
662 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
663 }
664 if (!(ss_e2 & DESC_P_MASK)) {
665 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
666 }
667 new_stack = 1;
668 sp_mask = get_sp_mask(ss_e2);
669 ssp = get_seg_base(ss_e1, ss_e2);
670 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
671 /* to same privilege */
672 if (env->eflags & VM_MASK) {
673 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
674 }
675 new_stack = 0;
676 sp_mask = get_sp_mask(env->segs[R_SS].flags);
677 ssp = env->segs[R_SS].base;
678 esp = ESP;
679 dpl = cpl;
680 } else {
681 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
682 new_stack = 0; /* avoid warning */
683 sp_mask = 0; /* avoid warning */
684 ssp = 0; /* avoid warning */
685 esp = 0; /* avoid warning */
686 }
687
688 shift = type >> 3;
689
690 #if 0
691 /* XXX: check that enough room is available */
692 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
693 if (env->eflags & VM_MASK) {
694 push_size += 8;
695 }
696 push_size <<= shift;
697 #endif
698 if (shift == 1) {
699 if (new_stack) {
700 if (env->eflags & VM_MASK) {
701 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
702 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
703 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
704 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
705 }
706 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
707 PUSHL(ssp, esp, sp_mask, ESP);
708 }
709 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
710 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
711 PUSHL(ssp, esp, sp_mask, old_eip);
712 if (has_error_code) {
713 PUSHL(ssp, esp, sp_mask, error_code);
714 }
715 } else {
716 if (new_stack) {
717 if (env->eflags & VM_MASK) {
718 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
719 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
720 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
721 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
722 }
723 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
724 PUSHW(ssp, esp, sp_mask, ESP);
725 }
726 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
727 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
728 PUSHW(ssp, esp, sp_mask, old_eip);
729 if (has_error_code) {
730 PUSHW(ssp, esp, sp_mask, error_code);
731 }
732 }
733
734 if (new_stack) {
735 if (env->eflags & VM_MASK) {
736 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
737 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
738 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
739 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
740 }
741 ss = (ss & ~3) | dpl;
742 cpu_x86_load_seg_cache(env, R_SS, ss,
743 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
744 }
745 SET_ESP(esp, sp_mask);
746
747 selector = (selector & ~3) | dpl;
748 cpu_x86_load_seg_cache(env, R_CS, selector,
749 get_seg_base(e1, e2),
750 get_seg_limit(e1, e2),
751 e2);
752 cpu_x86_set_cpl(env, dpl);
753 env->eip = offset;
754
755 /* interrupt gate clear IF mask */
756 if ((type & 1) == 0) {
757 env->eflags &= ~IF_MASK;
758 }
759 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
760 }
761
762 #ifdef TARGET_X86_64
763
764 #define PUSHQ(sp, val) \
765 { \
766 sp -= 8; \
767 cpu_stq_kernel(env, sp, (val)); \
768 }
769
770 #define POPQ(sp, val) \
771 { \
772 val = cpu_ldq_kernel(env, sp); \
773 sp += 8; \
774 }
775
776 static inline target_ulong get_rsp_from_tss(int level)
777 {
778 int index;
779
780 #if 0
781 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
782 env->tr.base, env->tr.limit);
783 #endif
784
785 if (!(env->tr.flags & DESC_P_MASK)) {
786 cpu_abort(env, "invalid tss");
787 }
788 index = 8 * level + 4;
789 if ((index + 7) > env->tr.limit) {
790 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
791 }
792 return cpu_ldq_kernel(env, env->tr.base + index);
793 }
794
795 /* 64 bit interrupt */
796 static void do_interrupt64(int intno, int is_int, int error_code,
797 target_ulong next_eip, int is_hw)
798 {
799 SegmentCache *dt;
800 target_ulong ptr;
801 int type, dpl, selector, cpl, ist;
802 int has_error_code, new_stack;
803 uint32_t e1, e2, e3, ss;
804 target_ulong old_eip, esp, offset;
805
806 has_error_code = 0;
807 if (!is_int && !is_hw) {
808 has_error_code = exception_has_error_code(intno);
809 }
810 if (is_int) {
811 old_eip = next_eip;
812 } else {
813 old_eip = env->eip;
814 }
815
816 dt = &env->idt;
817 if (intno * 16 + 15 > dt->limit) {
818 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
819 }
820 ptr = dt->base + intno * 16;
821 e1 = cpu_ldl_kernel(env, ptr);
822 e2 = cpu_ldl_kernel(env, ptr + 4);
823 e3 = cpu_ldl_kernel(env, ptr + 8);
824 /* check gate type */
825 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
826 switch (type) {
827 case 14: /* 386 interrupt gate */
828 case 15: /* 386 trap gate */
829 break;
830 default:
831 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
832 break;
833 }
834 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
835 cpl = env->hflags & HF_CPL_MASK;
836 /* check privilege if software int */
837 if (is_int && dpl < cpl) {
838 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
839 }
840 /* check valid bit */
841 if (!(e2 & DESC_P_MASK)) {
842 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
843 }
844 selector = e1 >> 16;
845 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
846 ist = e2 & 7;
847 if ((selector & 0xfffc) == 0) {
848 raise_exception_err(env, EXCP0D_GPF, 0);
849 }
850
851 if (load_segment(&e1, &e2, selector) != 0) {
852 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
853 }
854 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
855 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
856 }
857 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
858 if (dpl > cpl) {
859 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
860 }
861 if (!(e2 & DESC_P_MASK)) {
862 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
863 }
864 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
865 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
866 }
867 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
868 /* to inner privilege */
869 if (ist != 0) {
870 esp = get_rsp_from_tss(ist + 3);
871 } else {
872 esp = get_rsp_from_tss(dpl);
873 }
874 esp &= ~0xfLL; /* align stack */
875 ss = 0;
876 new_stack = 1;
877 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
878 /* to same privilege */
879 if (env->eflags & VM_MASK) {
880 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
881 }
882 new_stack = 0;
883 if (ist != 0) {
884 esp = get_rsp_from_tss(ist + 3);
885 } else {
886 esp = ESP;
887 }
888 esp &= ~0xfLL; /* align stack */
889 dpl = cpl;
890 } else {
891 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
892 new_stack = 0; /* avoid warning */
893 esp = 0; /* avoid warning */
894 }
895
896 PUSHQ(esp, env->segs[R_SS].selector);
897 PUSHQ(esp, ESP);
898 PUSHQ(esp, cpu_compute_eflags(env));
899 PUSHQ(esp, env->segs[R_CS].selector);
900 PUSHQ(esp, old_eip);
901 if (has_error_code) {
902 PUSHQ(esp, error_code);
903 }
904
905 if (new_stack) {
906 ss = 0 | dpl;
907 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
908 }
909 ESP = esp;
910
911 selector = (selector & ~3) | dpl;
912 cpu_x86_load_seg_cache(env, R_CS, selector,
913 get_seg_base(e1, e2),
914 get_seg_limit(e1, e2),
915 e2);
916 cpu_x86_set_cpl(env, dpl);
917 env->eip = offset;
918
919 /* interrupt gate clear IF mask */
920 if ((type & 1) == 0) {
921 env->eflags &= ~IF_MASK;
922 }
923 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
924 }
925 #endif
926
927 #ifdef TARGET_X86_64
928 #if defined(CONFIG_USER_ONLY)
929 void helper_syscall(int next_eip_addend)
930 {
931 env->exception_index = EXCP_SYSCALL;
932 env->exception_next_eip = env->eip + next_eip_addend;
933 cpu_loop_exit(env);
934 }
935 #else
936 void helper_syscall(int next_eip_addend)
937 {
938 int selector;
939
940 if (!(env->efer & MSR_EFER_SCE)) {
941 raise_exception_err(env, EXCP06_ILLOP, 0);
942 }
943 selector = (env->star >> 32) & 0xffff;
944 if (env->hflags & HF_LMA_MASK) {
945 int code64;
946
947 ECX = env->eip + next_eip_addend;
948 env->regs[11] = cpu_compute_eflags(env);
949
950 code64 = env->hflags & HF_CS64_MASK;
951
952 cpu_x86_set_cpl(env, 0);
953 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
954 0, 0xffffffff,
955 DESC_G_MASK | DESC_P_MASK |
956 DESC_S_MASK |
957 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
958 DESC_L_MASK);
959 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
960 0, 0xffffffff,
961 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
962 DESC_S_MASK |
963 DESC_W_MASK | DESC_A_MASK);
964 env->eflags &= ~env->fmask;
965 cpu_load_eflags(env, env->eflags, 0);
966 if (code64) {
967 env->eip = env->lstar;
968 } else {
969 env->eip = env->cstar;
970 }
971 } else {
972 ECX = (uint32_t)(env->eip + next_eip_addend);
973
974 cpu_x86_set_cpl(env, 0);
975 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
976 0, 0xffffffff,
977 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
978 DESC_S_MASK |
979 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
980 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
981 0, 0xffffffff,
982 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
983 DESC_S_MASK |
984 DESC_W_MASK | DESC_A_MASK);
985 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
986 env->eip = (uint32_t)env->star;
987 }
988 }
989 #endif
990 #endif
991
992 #ifdef TARGET_X86_64
993 void helper_sysret(int dflag)
994 {
995 int cpl, selector;
996
997 if (!(env->efer & MSR_EFER_SCE)) {
998 raise_exception_err(env, EXCP06_ILLOP, 0);
999 }
1000 cpl = env->hflags & HF_CPL_MASK;
1001 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1002 raise_exception_err(env, EXCP0D_GPF, 0);
1003 }
1004 selector = (env->star >> 48) & 0xffff;
1005 if (env->hflags & HF_LMA_MASK) {
1006 if (dflag == 2) {
1007 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1008 0, 0xffffffff,
1009 DESC_G_MASK | DESC_P_MASK |
1010 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1011 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1012 DESC_L_MASK);
1013 env->eip = ECX;
1014 } else {
1015 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1016 0, 0xffffffff,
1017 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1018 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1019 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1020 env->eip = (uint32_t)ECX;
1021 }
1022 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1023 0, 0xffffffff,
1024 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1025 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1026 DESC_W_MASK | DESC_A_MASK);
1027 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1028 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1029 NT_MASK);
1030 cpu_x86_set_cpl(env, 3);
1031 } else {
1032 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1033 0, 0xffffffff,
1034 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1035 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1036 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1037 env->eip = (uint32_t)ECX;
1038 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1039 0, 0xffffffff,
1040 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1041 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1042 DESC_W_MASK | DESC_A_MASK);
1043 env->eflags |= IF_MASK;
1044 cpu_x86_set_cpl(env, 3);
1045 }
1046 }
1047 #endif
1048
1049 /* real mode interrupt */
1050 static void do_interrupt_real(int intno, int is_int, int error_code,
1051 unsigned int next_eip)
1052 {
1053 SegmentCache *dt;
1054 target_ulong ptr, ssp;
1055 int selector;
1056 uint32_t offset, esp;
1057 uint32_t old_cs, old_eip;
1058
1059 /* real mode (simpler!) */
1060 dt = &env->idt;
1061 if (intno * 4 + 3 > dt->limit) {
1062 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
1063 }
1064 ptr = dt->base + intno * 4;
1065 offset = cpu_lduw_kernel(env, ptr);
1066 selector = cpu_lduw_kernel(env, ptr + 2);
1067 esp = ESP;
1068 ssp = env->segs[R_SS].base;
1069 if (is_int) {
1070 old_eip = next_eip;
1071 } else {
1072 old_eip = env->eip;
1073 }
1074 old_cs = env->segs[R_CS].selector;
1075 /* XXX: use SS segment size? */
1076 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
1077 PUSHW(ssp, esp, 0xffff, old_cs);
1078 PUSHW(ssp, esp, 0xffff, old_eip);
1079
1080 /* update processor state */
1081 ESP = (ESP & ~0xffff) | (esp & 0xffff);
1082 env->eip = offset;
1083 env->segs[R_CS].selector = selector;
1084 env->segs[R_CS].base = (selector << 4);
1085 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1086 }
1087
1088 #if defined(CONFIG_USER_ONLY)
1089 /* fake user mode interrupt */
1090 static void do_interrupt_user(int intno, int is_int, int error_code,
1091 target_ulong next_eip)
1092 {
1093 SegmentCache *dt;
1094 target_ulong ptr;
1095 int dpl, cpl, shift;
1096 uint32_t e2;
1097
1098 dt = &env->idt;
1099 if (env->hflags & HF_LMA_MASK) {
1100 shift = 4;
1101 } else {
1102 shift = 3;
1103 }
1104 ptr = dt->base + (intno << shift);
1105 e2 = cpu_ldl_kernel(env, ptr + 4);
1106
1107 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1108 cpl = env->hflags & HF_CPL_MASK;
1109 /* check privilege if software int */
1110 if (is_int && dpl < cpl) {
1111 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
1112 }
1113
1114 /* Since we emulate only user space, we cannot do more than
1115 exiting the emulation with the suitable exception and error
1116 code */
1117 if (is_int) {
1118 EIP = next_eip;
1119 }
1120 }
1121
1122 #else
1123
1124 static void handle_even_inj(int intno, int is_int, int error_code,
1125 int is_hw, int rm)
1126 {
1127 uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
1128 control.event_inj));
1129
1130 if (!(event_inj & SVM_EVTINJ_VALID)) {
1131 int type;
1132
1133 if (is_int) {
1134 type = SVM_EVTINJ_TYPE_SOFT;
1135 } else {
1136 type = SVM_EVTINJ_TYPE_EXEPT;
1137 }
1138 event_inj = intno | type | SVM_EVTINJ_VALID;
1139 if (!rm && exception_has_error_code(intno)) {
1140 event_inj |= SVM_EVTINJ_VALID_ERR;
1141 stl_phys(env->vm_vmcb + offsetof(struct vmcb,
1142 control.event_inj_err),
1143 error_code);
1144 }
1145 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1146 event_inj);
1147 }
1148 }
1149 #endif
1150
1151 /*
1152 * Begin execution of an interruption. is_int is TRUE if coming from
1153 * the int instruction. next_eip is the EIP value AFTER the interrupt
1154 * instruction. It is only relevant if is_int is TRUE.
1155 */
1156 static void do_interrupt_all(int intno, int is_int, int error_code,
1157 target_ulong next_eip, int is_hw)
1158 {
1159 if (qemu_loglevel_mask(CPU_LOG_INT)) {
1160 if ((env->cr[0] & CR0_PE_MASK)) {
1161 static int count;
1162
1163 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1164 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1165 count, intno, error_code, is_int,
1166 env->hflags & HF_CPL_MASK,
1167 env->segs[R_CS].selector, EIP,
1168 (int)env->segs[R_CS].base + EIP,
1169 env->segs[R_SS].selector, ESP);
1170 if (intno == 0x0e) {
1171 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
1172 } else {
1173 qemu_log(" EAX=" TARGET_FMT_lx, EAX);
1174 }
1175 qemu_log("\n");
1176 log_cpu_state(env, X86_DUMP_CCOP);
1177 #if 0
1178 {
1179 int i;
1180 target_ulong ptr;
1181
1182 qemu_log(" code=");
1183 ptr = env->segs[R_CS].base + env->eip;
1184 for (i = 0; i < 16; i++) {
1185 qemu_log(" %02x", ldub(ptr + i));
1186 }
1187 qemu_log("\n");
1188 }
1189 #endif
1190 count++;
1191 }
1192 }
1193 if (env->cr[0] & CR0_PE_MASK) {
1194 #if !defined(CONFIG_USER_ONLY)
1195 if (env->hflags & HF_SVMI_MASK) {
1196 handle_even_inj(intno, is_int, error_code, is_hw, 0);
1197 }
1198 #endif
1199 #ifdef TARGET_X86_64
1200 if (env->hflags & HF_LMA_MASK) {
1201 do_interrupt64(intno, is_int, error_code, next_eip, is_hw);
1202 } else
1203 #endif
1204 {
1205 do_interrupt_protected(intno, is_int, error_code, next_eip, is_hw);
1206 }
1207 } else {
1208 #if !defined(CONFIG_USER_ONLY)
1209 if (env->hflags & HF_SVMI_MASK) {
1210 handle_even_inj(intno, is_int, error_code, is_hw, 1);
1211 }
1212 #endif
1213 do_interrupt_real(intno, is_int, error_code, next_eip);
1214 }
1215
1216 #if !defined(CONFIG_USER_ONLY)
1217 if (env->hflags & HF_SVMI_MASK) {
1218 uint32_t event_inj = ldl_phys(env->vm_vmcb +
1219 offsetof(struct vmcb,
1220 control.event_inj));
1221
1222 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1223 event_inj & ~SVM_EVTINJ_VALID);
1224 }
1225 #endif
1226 }
1227
1228 void do_interrupt(CPUX86State *env1)
1229 {
1230 CPUX86State *saved_env;
1231
1232 saved_env = env;
1233 env = env1;
1234 #if defined(CONFIG_USER_ONLY)
1235 /* if user mode only, we simulate a fake exception
1236 which will be handled outside the cpu execution
1237 loop */
1238 do_interrupt_user(env->exception_index,
1239 env->exception_is_int,
1240 env->error_code,
1241 env->exception_next_eip);
1242 /* successfully delivered */
1243 env->old_exception = -1;
1244 #else
1245 /* simulate a real cpu exception. On i386, it can
1246 trigger new exceptions, but we do not handle
1247 double or triple faults yet. */
1248 do_interrupt_all(env->exception_index,
1249 env->exception_is_int,
1250 env->error_code,
1251 env->exception_next_eip, 0);
1252 /* successfully delivered */
1253 env->old_exception = -1;
1254 #endif
1255 env = saved_env;
1256 }
1257
1258 void do_interrupt_x86_hardirq(CPUX86State *env1, int intno, int is_hw)
1259 {
1260 CPUX86State *saved_env;
1261
1262 saved_env = env;
1263 env = env1;
1264 do_interrupt_all(intno, 0, 0, 0, is_hw);
1265 env = saved_env;
1266 }
1267
1268 void helper_enter_level(int level, int data32, target_ulong t1)
1269 {
1270 target_ulong ssp;
1271 uint32_t esp_mask, esp, ebp;
1272
1273 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1274 ssp = env->segs[R_SS].base;
1275 ebp = EBP;
1276 esp = ESP;
1277 if (data32) {
1278 /* 32 bit */
1279 esp -= 4;
1280 while (--level) {
1281 esp -= 4;
1282 ebp -= 4;
1283 cpu_stl_data(env, ssp + (esp & esp_mask),
1284 cpu_ldl_data(env, ssp + (ebp & esp_mask)));
1285 }
1286 esp -= 4;
1287 cpu_stl_data(env, ssp + (esp & esp_mask), t1);
1288 } else {
1289 /* 16 bit */
1290 esp -= 2;
1291 while (--level) {
1292 esp -= 2;
1293 ebp -= 2;
1294 cpu_stw_data(env, ssp + (esp & esp_mask),
1295 cpu_lduw_data(env, ssp + (ebp & esp_mask)));
1296 }
1297 esp -= 2;
1298 cpu_stw_data(env, ssp + (esp & esp_mask), t1);
1299 }
1300 }
1301
1302 #ifdef TARGET_X86_64
1303 void helper_enter64_level(int level, int data64, target_ulong t1)
1304 {
1305 target_ulong esp, ebp;
1306
1307 ebp = EBP;
1308 esp = ESP;
1309
1310 if (data64) {
1311 /* 64 bit */
1312 esp -= 8;
1313 while (--level) {
1314 esp -= 8;
1315 ebp -= 8;
1316 cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
1317 }
1318 esp -= 8;
1319 cpu_stq_data(env, esp, t1);
1320 } else {
1321 /* 16 bit */
1322 esp -= 2;
1323 while (--level) {
1324 esp -= 2;
1325 ebp -= 2;
1326 cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
1327 }
1328 esp -= 2;
1329 cpu_stw_data(env, esp, t1);
1330 }
1331 }
1332 #endif
1333
1334 void helper_lldt(int selector)
1335 {
1336 SegmentCache *dt;
1337 uint32_t e1, e2;
1338 int index, entry_limit;
1339 target_ulong ptr;
1340
1341 selector &= 0xffff;
1342 if ((selector & 0xfffc) == 0) {
1343 /* XXX: NULL selector case: invalid LDT */
1344 env->ldt.base = 0;
1345 env->ldt.limit = 0;
1346 } else {
1347 if (selector & 0x4) {
1348 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1349 }
1350 dt = &env->gdt;
1351 index = selector & ~7;
1352 #ifdef TARGET_X86_64
1353 if (env->hflags & HF_LMA_MASK) {
1354 entry_limit = 15;
1355 } else
1356 #endif
1357 {
1358 entry_limit = 7;
1359 }
1360 if ((index + entry_limit) > dt->limit) {
1361 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1362 }
1363 ptr = dt->base + index;
1364 e1 = cpu_ldl_kernel(env, ptr);
1365 e2 = cpu_ldl_kernel(env, ptr + 4);
1366 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
1367 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1368 }
1369 if (!(e2 & DESC_P_MASK)) {
1370 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1371 }
1372 #ifdef TARGET_X86_64
1373 if (env->hflags & HF_LMA_MASK) {
1374 uint32_t e3;
1375
1376 e3 = cpu_ldl_kernel(env, ptr + 8);
1377 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1378 env->ldt.base |= (target_ulong)e3 << 32;
1379 } else
1380 #endif
1381 {
1382 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1383 }
1384 }
1385 env->ldt.selector = selector;
1386 }
1387
1388 void helper_ltr(int selector)
1389 {
1390 SegmentCache *dt;
1391 uint32_t e1, e2;
1392 int index, type, entry_limit;
1393 target_ulong ptr;
1394
1395 selector &= 0xffff;
1396 if ((selector & 0xfffc) == 0) {
1397 /* NULL selector case: invalid TR */
1398 env->tr.base = 0;
1399 env->tr.limit = 0;
1400 env->tr.flags = 0;
1401 } else {
1402 if (selector & 0x4) {
1403 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1404 }
1405 dt = &env->gdt;
1406 index = selector & ~7;
1407 #ifdef TARGET_X86_64
1408 if (env->hflags & HF_LMA_MASK) {
1409 entry_limit = 15;
1410 } else
1411 #endif
1412 {
1413 entry_limit = 7;
1414 }
1415 if ((index + entry_limit) > dt->limit) {
1416 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1417 }
1418 ptr = dt->base + index;
1419 e1 = cpu_ldl_kernel(env, ptr);
1420 e2 = cpu_ldl_kernel(env, ptr + 4);
1421 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1422 if ((e2 & DESC_S_MASK) ||
1423 (type != 1 && type != 9)) {
1424 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1425 }
1426 if (!(e2 & DESC_P_MASK)) {
1427 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1428 }
1429 #ifdef TARGET_X86_64
1430 if (env->hflags & HF_LMA_MASK) {
1431 uint32_t e3, e4;
1432
1433 e3 = cpu_ldl_kernel(env, ptr + 8);
1434 e4 = cpu_ldl_kernel(env, ptr + 12);
1435 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
1436 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1437 }
1438 load_seg_cache_raw_dt(&env->tr, e1, e2);
1439 env->tr.base |= (target_ulong)e3 << 32;
1440 } else
1441 #endif
1442 {
1443 load_seg_cache_raw_dt(&env->tr, e1, e2);
1444 }
1445 e2 |= DESC_TSS_BUSY_MASK;
1446 cpu_stl_kernel(env, ptr + 4, e2);
1447 }
1448 env->tr.selector = selector;
1449 }
1450
1451 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1452 void helper_load_seg(int seg_reg, int selector)
1453 {
1454 uint32_t e1, e2;
1455 int cpl, dpl, rpl;
1456 SegmentCache *dt;
1457 int index;
1458 target_ulong ptr;
1459
1460 selector &= 0xffff;
1461 cpl = env->hflags & HF_CPL_MASK;
1462 if ((selector & 0xfffc) == 0) {
1463 /* null selector case */
1464 if (seg_reg == R_SS
1465 #ifdef TARGET_X86_64
1466 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1467 #endif
1468 ) {
1469 raise_exception_err(env, EXCP0D_GPF, 0);
1470 }
1471 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1472 } else {
1473
1474 if (selector & 0x4) {
1475 dt = &env->ldt;
1476 } else {
1477 dt = &env->gdt;
1478 }
1479 index = selector & ~7;
1480 if ((index + 7) > dt->limit) {
1481 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1482 }
1483 ptr = dt->base + index;
1484 e1 = cpu_ldl_kernel(env, ptr);
1485 e2 = cpu_ldl_kernel(env, ptr + 4);
1486
1487 if (!(e2 & DESC_S_MASK)) {
1488 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1489 }
1490 rpl = selector & 3;
1491 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1492 if (seg_reg == R_SS) {
1493 /* must be writable segment */
1494 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
1495 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1496 }
1497 if (rpl != cpl || dpl != cpl) {
1498 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1499 }
1500 } else {
1501 /* must be readable segment */
1502 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
1503 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1504 }
1505
1506 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1507 /* if not conforming code, test rights */
1508 if (dpl < cpl || dpl < rpl) {
1509 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1510 }
1511 }
1512 }
1513
1514 if (!(e2 & DESC_P_MASK)) {
1515 if (seg_reg == R_SS) {
1516 raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
1517 } else {
1518 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1519 }
1520 }
1521
1522 /* set the access bit if not already set */
1523 if (!(e2 & DESC_A_MASK)) {
1524 e2 |= DESC_A_MASK;
1525 cpu_stl_kernel(env, ptr + 4, e2);
1526 }
1527
1528 cpu_x86_load_seg_cache(env, seg_reg, selector,
1529 get_seg_base(e1, e2),
1530 get_seg_limit(e1, e2),
1531 e2);
1532 #if 0
1533 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1534 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1535 #endif
1536 }
1537 }
1538
1539 /* protected mode jump */
1540 void helper_ljmp_protected(int new_cs, target_ulong new_eip,
1541 int next_eip_addend)
1542 {
1543 int gate_cs, type;
1544 uint32_t e1, e2, cpl, dpl, rpl, limit;
1545 target_ulong next_eip;
1546
1547 if ((new_cs & 0xfffc) == 0) {
1548 raise_exception_err(env, EXCP0D_GPF, 0);
1549 }
1550 if (load_segment(&e1, &e2, new_cs) != 0) {
1551 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1552 }
1553 cpl = env->hflags & HF_CPL_MASK;
1554 if (e2 & DESC_S_MASK) {
1555 if (!(e2 & DESC_CS_MASK)) {
1556 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1557 }
1558 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1559 if (e2 & DESC_C_MASK) {
1560 /* conforming code segment */
1561 if (dpl > cpl) {
1562 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1563 }
1564 } else {
1565 /* non conforming code segment */
1566 rpl = new_cs & 3;
1567 if (rpl > cpl) {
1568 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1569 }
1570 if (dpl != cpl) {
1571 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1572 }
1573 }
1574 if (!(e2 & DESC_P_MASK)) {
1575 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1576 }
1577 limit = get_seg_limit(e1, e2);
1578 if (new_eip > limit &&
1579 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
1580 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1581 }
1582 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1583 get_seg_base(e1, e2), limit, e2);
1584 EIP = new_eip;
1585 } else {
1586 /* jump to call or task gate */
1587 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1588 rpl = new_cs & 3;
1589 cpl = env->hflags & HF_CPL_MASK;
1590 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1591 switch (type) {
1592 case 1: /* 286 TSS */
1593 case 9: /* 386 TSS */
1594 case 5: /* task gate */
1595 if (dpl < cpl || dpl < rpl) {
1596 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1597 }
1598 next_eip = env->eip + next_eip_addend;
1599 switch_tss(new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1600 CC_OP = CC_OP_EFLAGS;
1601 break;
1602 case 4: /* 286 call gate */
1603 case 12: /* 386 call gate */
1604 if ((dpl < cpl) || (dpl < rpl)) {
1605 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1606 }
1607 if (!(e2 & DESC_P_MASK)) {
1608 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1609 }
1610 gate_cs = e1 >> 16;
1611 new_eip = (e1 & 0xffff);
1612 if (type == 12) {
1613 new_eip |= (e2 & 0xffff0000);
1614 }
1615 if (load_segment(&e1, &e2, gate_cs) != 0) {
1616 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1617 }
1618 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1619 /* must be code segment */
1620 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1621 (DESC_S_MASK | DESC_CS_MASK))) {
1622 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1623 }
1624 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1625 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
1626 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1627 }
1628 if (!(e2 & DESC_P_MASK)) {
1629 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1630 }
1631 limit = get_seg_limit(e1, e2);
1632 if (new_eip > limit) {
1633 raise_exception_err(env, EXCP0D_GPF, 0);
1634 }
1635 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1636 get_seg_base(e1, e2), limit, e2);
1637 EIP = new_eip;
1638 break;
1639 default:
1640 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1641 break;
1642 }
1643 }
1644 }
1645
1646 /* real mode call */
1647 void helper_lcall_real(int new_cs, target_ulong new_eip1,
1648 int shift, int next_eip)
1649 {
1650 int new_eip;
1651 uint32_t esp, esp_mask;
1652 target_ulong ssp;
1653
1654 new_eip = new_eip1;
1655 esp = ESP;
1656 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1657 ssp = env->segs[R_SS].base;
1658 if (shift) {
1659 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1660 PUSHL(ssp, esp, esp_mask, next_eip);
1661 } else {
1662 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1663 PUSHW(ssp, esp, esp_mask, next_eip);
1664 }
1665
1666 SET_ESP(esp, esp_mask);
1667 env->eip = new_eip;
1668 env->segs[R_CS].selector = new_cs;
1669 env->segs[R_CS].base = (new_cs << 4);
1670 }
1671
1672 /* protected mode call */
1673 void helper_lcall_protected(int new_cs, target_ulong new_eip,
1674 int shift, int next_eip_addend)
1675 {
1676 int new_stack, i;
1677 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1678 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
1679 uint32_t val, limit, old_sp_mask;
1680 target_ulong ssp, old_ssp, next_eip;
1681
1682 next_eip = env->eip + next_eip_addend;
1683 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
1684 LOG_PCALL_STATE(env);
1685 if ((new_cs & 0xfffc) == 0) {
1686 raise_exception_err(env, EXCP0D_GPF, 0);
1687 }
1688 if (load_segment(&e1, &e2, new_cs) != 0) {
1689 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1690 }
1691 cpl = env->hflags & HF_CPL_MASK;
1692 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
1693 if (e2 & DESC_S_MASK) {
1694 if (!(e2 & DESC_CS_MASK)) {
1695 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1696 }
1697 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1698 if (e2 & DESC_C_MASK) {
1699 /* conforming code segment */
1700 if (dpl > cpl) {
1701 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1702 }
1703 } else {
1704 /* non conforming code segment */
1705 rpl = new_cs & 3;
1706 if (rpl > cpl) {
1707 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1708 }
1709 if (dpl != cpl) {
1710 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1711 }
1712 }
1713 if (!(e2 & DESC_P_MASK)) {
1714 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1715 }
1716
1717 #ifdef TARGET_X86_64
1718 /* XXX: check 16/32 bit cases in long mode */
1719 if (shift == 2) {
1720 target_ulong rsp;
1721
1722 /* 64 bit case */
1723 rsp = ESP;
1724 PUSHQ(rsp, env->segs[R_CS].selector);
1725 PUSHQ(rsp, next_eip);
1726 /* from this point, not restartable */
1727 ESP = rsp;
1728 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1729 get_seg_base(e1, e2),
1730 get_seg_limit(e1, e2), e2);
1731 EIP = new_eip;
1732 } else
1733 #endif
1734 {
1735 sp = ESP;
1736 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1737 ssp = env->segs[R_SS].base;
1738 if (shift) {
1739 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1740 PUSHL(ssp, sp, sp_mask, next_eip);
1741 } else {
1742 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1743 PUSHW(ssp, sp, sp_mask, next_eip);
1744 }
1745
1746 limit = get_seg_limit(e1, e2);
1747 if (new_eip > limit) {
1748 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1749 }
1750 /* from this point, not restartable */
1751 SET_ESP(sp, sp_mask);
1752 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1753 get_seg_base(e1, e2), limit, e2);
1754 EIP = new_eip;
1755 }
1756 } else {
1757 /* check gate type */
1758 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1759 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1760 rpl = new_cs & 3;
1761 switch (type) {
1762 case 1: /* available 286 TSS */
1763 case 9: /* available 386 TSS */
1764 case 5: /* task gate */
1765 if (dpl < cpl || dpl < rpl) {
1766 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1767 }
1768 switch_tss(new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1769 CC_OP = CC_OP_EFLAGS;
1770 return;
1771 case 4: /* 286 call gate */
1772 case 12: /* 386 call gate */
1773 break;
1774 default:
1775 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1776 break;
1777 }
1778 shift = type >> 3;
1779
1780 if (dpl < cpl || dpl < rpl) {
1781 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1782 }
1783 /* check valid bit */
1784 if (!(e2 & DESC_P_MASK)) {
1785 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1786 }
1787 selector = e1 >> 16;
1788 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1789 param_count = e2 & 0x1f;
1790 if ((selector & 0xfffc) == 0) {
1791 raise_exception_err(env, EXCP0D_GPF, 0);
1792 }
1793
1794 if (load_segment(&e1, &e2, selector) != 0) {
1795 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1796 }
1797 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
1798 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1799 }
1800 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1801 if (dpl > cpl) {
1802 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1803 }
1804 if (!(e2 & DESC_P_MASK)) {
1805 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1806 }
1807
1808 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1809 /* to inner privilege */
1810 get_ss_esp_from_tss(&ss, &sp, dpl);
1811 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
1812 "\n",
1813 ss, sp, param_count, ESP);
1814 if ((ss & 0xfffc) == 0) {
1815 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1816 }
1817 if ((ss & 3) != dpl) {
1818 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1819 }
1820 if (load_segment(&ss_e1, &ss_e2, ss) != 0) {
1821 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1822 }
1823 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1824 if (ss_dpl != dpl) {
1825 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1826 }
1827 if (!(ss_e2 & DESC_S_MASK) ||
1828 (ss_e2 & DESC_CS_MASK) ||
1829 !(ss_e2 & DESC_W_MASK)) {
1830 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1831 }
1832 if (!(ss_e2 & DESC_P_MASK)) {
1833 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1834 }
1835
1836 /* push_size = ((param_count * 2) + 8) << shift; */
1837
1838 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1839 old_ssp = env->segs[R_SS].base;
1840
1841 sp_mask = get_sp_mask(ss_e2);
1842 ssp = get_seg_base(ss_e1, ss_e2);
1843 if (shift) {
1844 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1845 PUSHL(ssp, sp, sp_mask, ESP);
1846 for (i = param_count - 1; i >= 0; i--) {
1847 val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
1848 old_sp_mask));
1849 PUSHL(ssp, sp, sp_mask, val);
1850 }
1851 } else {
1852 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1853 PUSHW(ssp, sp, sp_mask, ESP);
1854 for (i = param_count - 1; i >= 0; i--) {
1855 val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
1856 old_sp_mask));
1857 PUSHW(ssp, sp, sp_mask, val);
1858 }
1859 }
1860 new_stack = 1;
1861 } else {
1862 /* to same privilege */
1863 sp = ESP;
1864 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1865 ssp = env->segs[R_SS].base;
1866 /* push_size = (4 << shift); */
1867 new_stack = 0;
1868 }
1869
1870 if (shift) {
1871 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1872 PUSHL(ssp, sp, sp_mask, next_eip);
1873 } else {
1874 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1875 PUSHW(ssp, sp, sp_mask, next_eip);
1876 }
1877
1878 /* from this point, not restartable */
1879
1880 if (new_stack) {
1881 ss = (ss & ~3) | dpl;
1882 cpu_x86_load_seg_cache(env, R_SS, ss,
1883 ssp,
1884 get_seg_limit(ss_e1, ss_e2),
1885 ss_e2);
1886 }
1887
1888 selector = (selector & ~3) | dpl;
1889 cpu_x86_load_seg_cache(env, R_CS, selector,
1890 get_seg_base(e1, e2),
1891 get_seg_limit(e1, e2),
1892 e2);
1893 cpu_x86_set_cpl(env, dpl);
1894 SET_ESP(sp, sp_mask);
1895 EIP = offset;
1896 }
1897 }
1898
1899 /* real and vm86 mode iret */
1900 void helper_iret_real(int shift)
1901 {
1902 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1903 target_ulong ssp;
1904 int eflags_mask;
1905
1906 sp_mask = 0xffff; /* XXXX: use SS segment size? */
1907 sp = ESP;
1908 ssp = env->segs[R_SS].base;
1909 if (shift == 1) {
1910 /* 32 bits */
1911 POPL(ssp, sp, sp_mask, new_eip);
1912 POPL(ssp, sp, sp_mask, new_cs);
1913 new_cs &= 0xffff;
1914 POPL(ssp, sp, sp_mask, new_eflags);
1915 } else {
1916 /* 16 bits */
1917 POPW(ssp, sp, sp_mask, new_eip);
1918 POPW(ssp, sp, sp_mask, new_cs);
1919 POPW(ssp, sp, sp_mask, new_eflags);
1920 }
1921 ESP = (ESP & ~sp_mask) | (sp & sp_mask);
1922 env->segs[R_CS].selector = new_cs;
1923 env->segs[R_CS].base = (new_cs << 4);
1924 env->eip = new_eip;
1925 if (env->eflags & VM_MASK) {
1926 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1927 NT_MASK;
1928 } else {
1929 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1930 RF_MASK | NT_MASK;
1931 }
1932 if (shift == 0) {
1933 eflags_mask &= 0xffff;
1934 }
1935 cpu_load_eflags(env, new_eflags, eflags_mask);
1936 env->hflags2 &= ~HF2_NMI_MASK;
1937 }
1938
1939 static inline void validate_seg(int seg_reg, int cpl)
1940 {
1941 int dpl;
1942 uint32_t e2;
1943
1944 /* XXX: on x86_64, we do not want to nullify FS and GS because
1945 they may still contain a valid base. I would be interested to
1946 know how a real x86_64 CPU behaves */
1947 if ((seg_reg == R_FS || seg_reg == R_GS) &&
1948 (env->segs[seg_reg].selector & 0xfffc) == 0) {
1949 return;
1950 }
1951
1952 e2 = env->segs[seg_reg].flags;
1953 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1954 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1955 /* data or non conforming code segment */
1956 if (dpl < cpl) {
1957 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1958 }
1959 }
1960 }
1961
1962 /* protected mode iret */
1963 static inline void helper_ret_protected(int shift, int is_iret, int addend)
1964 {
1965 uint32_t new_cs, new_eflags, new_ss;
1966 uint32_t new_es, new_ds, new_fs, new_gs;
1967 uint32_t e1, e2, ss_e1, ss_e2;
1968 int cpl, dpl, rpl, eflags_mask, iopl;
1969 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1970
1971 #ifdef TARGET_X86_64
1972 if (shift == 2) {
1973 sp_mask = -1;
1974 } else
1975 #endif
1976 {
1977 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1978 }
1979 sp = ESP;
1980 ssp = env->segs[R_SS].base;
1981 new_eflags = 0; /* avoid warning */
1982 #ifdef TARGET_X86_64
1983 if (shift == 2) {
1984 POPQ(sp, new_eip);
1985 POPQ(sp, new_cs);
1986 new_cs &= 0xffff;
1987 if (is_iret) {
1988 POPQ(sp, new_eflags);
1989 }
1990 } else
1991 #endif
1992 {
1993 if (shift == 1) {
1994 /* 32 bits */
1995 POPL(ssp, sp, sp_mask, new_eip);
1996 POPL(ssp, sp, sp_mask, new_cs);
1997 new_cs &= 0xffff;
1998 if (is_iret) {
1999 POPL(ssp, sp, sp_mask, new_eflags);
2000 if (new_eflags & VM_MASK) {
2001 goto return_to_vm86;
2002 }
2003 }
2004 } else {
2005 /* 16 bits */
2006 POPW(ssp, sp, sp_mask, new_eip);
2007 POPW(ssp, sp, sp_mask, new_cs);
2008 if (is_iret) {
2009 POPW(ssp, sp, sp_mask, new_eflags);
2010 }
2011 }
2012 }
2013 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2014 new_cs, new_eip, shift, addend);
2015 LOG_PCALL_STATE(env);
2016 if ((new_cs & 0xfffc) == 0) {
2017 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2018 }
2019 if (load_segment(&e1, &e2, new_cs) != 0) {
2020 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2021 }
2022 if (!(e2 & DESC_S_MASK) ||
2023 !(e2 & DESC_CS_MASK)) {
2024 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2025 }
2026 cpl = env->hflags & HF_CPL_MASK;
2027 rpl = new_cs & 3;
2028 if (rpl < cpl) {
2029 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2030 }
2031 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2032 if (e2 & DESC_C_MASK) {
2033 if (dpl > rpl) {
2034 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2035 }
2036 } else {
2037 if (dpl != rpl) {
2038 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2039 }
2040 }
2041 if (!(e2 & DESC_P_MASK)) {
2042 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
2043 }
2044
2045 sp += addend;
2046 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2047 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2048 /* return to same privilege level */
2049 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2050 get_seg_base(e1, e2),
2051 get_seg_limit(e1, e2),
2052 e2);
2053 } else {
2054 /* return to different privilege level */
2055 #ifdef TARGET_X86_64
2056 if (shift == 2) {
2057 POPQ(sp, new_esp);
2058 POPQ(sp, new_ss);
2059 new_ss &= 0xffff;
2060 } else
2061 #endif
2062 {
2063 if (shift == 1) {
2064 /* 32 bits */
2065 POPL(ssp, sp, sp_mask, new_esp);
2066 POPL(ssp, sp, sp_mask, new_ss);
2067 new_ss &= 0xffff;
2068 } else {
2069 /* 16 bits */
2070 POPW(ssp, sp, sp_mask, new_esp);
2071 POPW(ssp, sp, sp_mask, new_ss);
2072 }
2073 }
2074 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
2075 new_ss, new_esp);
2076 if ((new_ss & 0xfffc) == 0) {
2077 #ifdef TARGET_X86_64
2078 /* NULL ss is allowed in long mode if cpl != 3 */
2079 /* XXX: test CS64? */
2080 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2081 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2082 0, 0xffffffff,
2083 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2084 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2085 DESC_W_MASK | DESC_A_MASK);
2086 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
2087 } else
2088 #endif
2089 {
2090 raise_exception_err(env, EXCP0D_GPF, 0);
2091 }
2092 } else {
2093 if ((new_ss & 3) != rpl) {
2094 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2095 }
2096 if (load_segment(&ss_e1, &ss_e2, new_ss) != 0) {
2097 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2098 }
2099 if (!(ss_e2 & DESC_S_MASK) ||
2100 (ss_e2 & DESC_CS_MASK) ||
2101 !(ss_e2 & DESC_W_MASK)) {
2102 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2103 }
2104 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2105 if (dpl != rpl) {
2106 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2107 }
2108 if (!(ss_e2 & DESC_P_MASK)) {
2109 raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
2110 }
2111 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2112 get_seg_base(ss_e1, ss_e2),
2113 get_seg_limit(ss_e1, ss_e2),
2114 ss_e2);
2115 }
2116
2117 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2118 get_seg_base(e1, e2),
2119 get_seg_limit(e1, e2),
2120 e2);
2121 cpu_x86_set_cpl(env, rpl);
2122 sp = new_esp;
2123 #ifdef TARGET_X86_64
2124 if (env->hflags & HF_CS64_MASK) {
2125 sp_mask = -1;
2126 } else
2127 #endif
2128 {
2129 sp_mask = get_sp_mask(ss_e2);
2130 }
2131
2132 /* validate data segments */
2133 validate_seg(R_ES, rpl);
2134 validate_seg(R_DS, rpl);
2135 validate_seg(R_FS, rpl);
2136 validate_seg(R_GS, rpl);
2137
2138 sp += addend;
2139 }
2140 SET_ESP(sp, sp_mask);
2141 env->eip = new_eip;
2142 if (is_iret) {
2143 /* NOTE: 'cpl' is the _old_ CPL */
2144 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2145 if (cpl == 0) {
2146 eflags_mask |= IOPL_MASK;
2147 }
2148 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2149 if (cpl <= iopl) {
2150 eflags_mask |= IF_MASK;
2151 }
2152 if (shift == 0) {
2153 eflags_mask &= 0xffff;
2154 }
2155 cpu_load_eflags(env, new_eflags, eflags_mask);
2156 }
2157 return;
2158
2159 return_to_vm86:
2160 POPL(ssp, sp, sp_mask, new_esp);
2161 POPL(ssp, sp, sp_mask, new_ss);
2162 POPL(ssp, sp, sp_mask, new_es);
2163 POPL(ssp, sp, sp_mask, new_ds);
2164 POPL(ssp, sp, sp_mask, new_fs);
2165 POPL(ssp, sp, sp_mask, new_gs);
2166
2167 /* modify processor state */
2168 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2169 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2170 VIP_MASK);
2171 load_seg_vm(R_CS, new_cs & 0xffff);
2172 cpu_x86_set_cpl(env, 3);
2173 load_seg_vm(R_SS, new_ss & 0xffff);
2174 load_seg_vm(R_ES, new_es & 0xffff);
2175 load_seg_vm(R_DS, new_ds & 0xffff);
2176 load_seg_vm(R_FS, new_fs & 0xffff);
2177 load_seg_vm(R_GS, new_gs & 0xffff);
2178
2179 env->eip = new_eip & 0xffff;
2180 ESP = new_esp;
2181 }
2182
2183 void helper_iret_protected(int shift, int next_eip)
2184 {
2185 int tss_selector, type;
2186 uint32_t e1, e2;
2187
2188 /* specific case for TSS */
2189 if (env->eflags & NT_MASK) {
2190 #ifdef TARGET_X86_64
2191 if (env->hflags & HF_LMA_MASK) {
2192 raise_exception_err(env, EXCP0D_GPF, 0);
2193 }
2194 #endif
2195 tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
2196 if (tss_selector & 4) {
2197 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2198 }
2199 if (load_segment(&e1, &e2, tss_selector) != 0) {
2200 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2201 }
2202 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2203 /* NOTE: we check both segment and busy TSS */
2204 if (type != 3) {
2205 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2206 }
2207 switch_tss(tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2208 } else {
2209 helper_ret_protected(shift, 1, 0);
2210 }
2211 env->hflags2 &= ~HF2_NMI_MASK;
2212 }
2213
2214 void helper_lret_protected(int shift, int addend)
2215 {
2216 helper_ret_protected(shift, 0, addend);
2217 }
2218
2219 void helper_sysenter(void)
2220 {
2221 if (env->sysenter_cs == 0) {
2222 raise_exception_err(env, EXCP0D_GPF, 0);
2223 }
2224 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2225 cpu_x86_set_cpl(env, 0);
2226
2227 #ifdef TARGET_X86_64
2228 if (env->hflags & HF_LMA_MASK) {
2229 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2230 0, 0xffffffff,
2231 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2232 DESC_S_MASK |
2233 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2234 DESC_L_MASK);
2235 } else
2236 #endif
2237 {
2238 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2239 0, 0xffffffff,
2240 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2241 DESC_S_MASK |
2242 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2243 }
2244 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2245 0, 0xffffffff,
2246 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2247 DESC_S_MASK |
2248 DESC_W_MASK | DESC_A_MASK);
2249 ESP = env->sysenter_esp;
2250 EIP = env->sysenter_eip;
2251 }
2252
2253 void helper_sysexit(int dflag)
2254 {
2255 int cpl;
2256
2257 cpl = env->hflags & HF_CPL_MASK;
2258 if (env->sysenter_cs == 0 || cpl != 0) {
2259 raise_exception_err(env, EXCP0D_GPF, 0);
2260 }
2261 cpu_x86_set_cpl(env, 3);
2262 #ifdef TARGET_X86_64
2263 if (dflag == 2) {
2264 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2265 3, 0, 0xffffffff,
2266 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2267 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2268 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2269 DESC_L_MASK);
2270 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2271 3, 0, 0xffffffff,
2272 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2273 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2274 DESC_W_MASK | DESC_A_MASK);
2275 } else
2276 #endif
2277 {
2278 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2279 3, 0, 0xffffffff,
2280 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2281 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2282 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2283 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2284 3, 0, 0xffffffff,
2285 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2286 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2287 DESC_W_MASK | DESC_A_MASK);
2288 }
2289 ESP = ECX;
2290 EIP = EDX;
2291 }
2292
2293 target_ulong helper_lsl(target_ulong selector1)
2294 {
2295 unsigned int limit;
2296 uint32_t e1, e2, eflags, selector;
2297 int rpl, dpl, cpl, type;
2298
2299 selector = selector1 & 0xffff;
2300 eflags = cpu_cc_compute_all(env, CC_OP);
2301 if ((selector & 0xfffc) == 0) {
2302 goto fail;
2303 }
2304 if (load_segment(&e1, &e2, selector) != 0) {
2305 goto fail;
2306 }
2307 rpl = selector & 3;
2308 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2309 cpl = env->hflags & HF_CPL_MASK;
2310 if (e2 & DESC_S_MASK) {
2311 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2312 /* conforming */
2313 } else {
2314 if (dpl < cpl || dpl < rpl) {
2315 goto fail;
2316 }
2317 }
2318 } else {
2319 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2320 switch (type) {
2321 case 1:
2322 case 2:
2323 case 3:
2324 case 9:
2325 case 11:
2326 break;
2327 default:
2328 goto fail;
2329 }
2330 if (dpl < cpl || dpl < rpl) {
2331 fail:
2332 CC_SRC = eflags & ~CC_Z;
2333 return 0;
2334 }
2335 }
2336 limit = get_seg_limit(e1, e2);
2337 CC_SRC = eflags | CC_Z;
2338 return limit;
2339 }
2340
2341 target_ulong helper_lar(target_ulong selector1)
2342 {
2343 uint32_t e1, e2, eflags, selector;
2344 int rpl, dpl, cpl, type;
2345
2346 selector = selector1 & 0xffff;
2347 eflags = cpu_cc_compute_all(env, CC_OP);
2348 if ((selector & 0xfffc) == 0) {
2349 goto fail;
2350 }
2351 if (load_segment(&e1, &e2, selector) != 0) {
2352 goto fail;
2353 }
2354 rpl = selector & 3;
2355 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2356 cpl = env->hflags & HF_CPL_MASK;
2357 if (e2 & DESC_S_MASK) {
2358 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2359 /* conforming */
2360 } else {
2361 if (dpl < cpl || dpl < rpl) {
2362 goto fail;
2363 }
2364 }
2365 } else {
2366 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2367 switch (type) {
2368 case 1:
2369 case 2:
2370 case 3:
2371 case 4:
2372 case 5:
2373 case 9:
2374 case 11:
2375 case 12:
2376 break;
2377 default:
2378 goto fail;
2379 }
2380 if (dpl < cpl || dpl < rpl) {
2381 fail:
2382 CC_SRC = eflags & ~CC_Z;
2383 return 0;
2384 }
2385 }
2386 CC_SRC = eflags | CC_Z;
2387 return e2 & 0x00f0ff00;
2388 }
2389
2390 void helper_verr(target_ulong selector1)
2391 {
2392 uint32_t e1, e2, eflags, selector;
2393 int rpl, dpl, cpl;
2394
2395 selector = selector1 & 0xffff;
2396 eflags = cpu_cc_compute_all(env, CC_OP);
2397 if ((selector & 0xfffc) == 0) {
2398 goto fail;
2399 }
2400 if (load_segment(&e1, &e2, selector) != 0) {
2401 goto fail;
2402 }
2403 if (!(e2 & DESC_S_MASK)) {
2404 goto fail;
2405 }
2406 rpl = selector & 3;
2407 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2408 cpl = env->hflags & HF_CPL_MASK;
2409 if (e2 & DESC_CS_MASK) {
2410 if (!(e2 & DESC_R_MASK)) {
2411 goto fail;
2412 }
2413 if (!(e2 & DESC_C_MASK)) {
2414 if (dpl < cpl || dpl < rpl) {
2415 goto fail;
2416 }
2417 }
2418 } else {
2419 if (dpl < cpl || dpl < rpl) {
2420 fail:
2421 CC_SRC = eflags & ~CC_Z;
2422 return;
2423 }
2424 }
2425 CC_SRC = eflags | CC_Z;
2426 }
2427
2428 void helper_verw(target_ulong selector1)
2429 {
2430 uint32_t e1, e2, eflags, selector;
2431 int rpl, dpl, cpl;
2432
2433 selector = selector1 & 0xffff;
2434 eflags = cpu_cc_compute_all(env, CC_OP);
2435 if ((selector & 0xfffc) == 0) {
2436 goto fail;
2437 }
2438 if (load_segment(&e1, &e2, selector) != 0) {
2439 goto fail;
2440 }
2441 if (!(e2 & DESC_S_MASK)) {
2442 goto fail;
2443 }
2444 rpl = selector & 3;
2445 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2446 cpl = env->hflags & HF_CPL_MASK;
2447 if (e2 & DESC_CS_MASK) {
2448 goto fail;
2449 } else {
2450 if (dpl < cpl || dpl < rpl) {
2451 goto fail;
2452 }
2453 if (!(e2 & DESC_W_MASK)) {
2454 fail:
2455 CC_SRC = eflags & ~CC_Z;
2456 return;
2457 }
2458 }
2459 CC_SRC = eflags | CC_Z;
2460 }
2461
2462 #if defined(CONFIG_USER_ONLY)
2463 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
2464 {
2465 CPUX86State *saved_env;
2466
2467 saved_env = env;
2468 env = s;
2469 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
2470 selector &= 0xffff;
2471 cpu_x86_load_seg_cache(env, seg_reg, selector,
2472 (selector << 4), 0xffff, 0);
2473 } else {
2474 helper_load_seg(seg_reg, selector);
2475 }
2476 env = saved_env;
2477 }
2478 #endif
Qemu copy for testing