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target-i386: expand cmov via movcond
[qemu.git] / target-i386 / translate.c
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "qemu/host-utils.h"
27 #include "cpu.h"
28 #include "disas/disas.h"
29 #include "tcg-op.h"
30
31 #include "helper.h"
32 #define GEN_HELPER 1
33 #include "helper.h"
34
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40
41 #ifdef TARGET_X86_64
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
45 #else
46 #define CODE64(s) 0
47 #define REX_X(s) 0
48 #define REX_B(s) 0
49 #endif
50
51 #ifdef TARGET_X86_64
52 # define ctztl ctz64
53 # define clztl clz64
54 #else
55 # define ctztl ctz32
56 # define clztl clz32
57 #endif
58
59 //#define MACRO_TEST 1
60
61 /* global register indexes */
62 static TCGv_ptr cpu_env;
63 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst;
64 static TCGv_i32 cpu_cc_op;
65 static TCGv cpu_regs[CPU_NB_REGS];
66 /* local temps */
67 static TCGv cpu_T[2], cpu_T3;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0, cpu_tmp4;
70 static TCGv_ptr cpu_ptr0, cpu_ptr1;
71 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
72 static TCGv_i64 cpu_tmp1_i64;
73 static TCGv cpu_tmp5;
74
75 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
76
77 #include "exec/gen-icount.h"
78
79 #ifdef TARGET_X86_64
80 static int x86_64_hregs;
81 #endif
82
83 typedef struct DisasContext {
84 /* current insn context */
85 int override; /* -1 if no override */
86 int prefix;
87 int aflag, dflag;
88 target_ulong pc; /* pc = eip + cs_base */
89 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
90 static state change (stop translation) */
91 /* current block context */
92 target_ulong cs_base; /* base of CS segment */
93 int pe; /* protected mode */
94 int code32; /* 32 bit code segment */
95 #ifdef TARGET_X86_64
96 int lma; /* long mode active */
97 int code64; /* 64 bit code segment */
98 int rex_x, rex_b;
99 #endif
100 int ss32; /* 32 bit stack segment */
101 CCOp cc_op; /* current CC operation */
102 bool cc_op_dirty;
103 int addseg; /* non zero if either DS/ES/SS have a non zero base */
104 int f_st; /* currently unused */
105 int vm86; /* vm86 mode */
106 int cpl;
107 int iopl;
108 int tf; /* TF cpu flag */
109 int singlestep_enabled; /* "hardware" single step enabled */
110 int jmp_opt; /* use direct block chaining for direct jumps */
111 int mem_index; /* select memory access functions */
112 uint64_t flags; /* all execution flags */
113 struct TranslationBlock *tb;
114 int popl_esp_hack; /* for correct popl with esp base handling */
115 int rip_offset; /* only used in x86_64, but left for simplicity */
116 int cpuid_features;
117 int cpuid_ext_features;
118 int cpuid_ext2_features;
119 int cpuid_ext3_features;
120 int cpuid_7_0_ebx_features;
121 } DisasContext;
122
123 static void gen_eob(DisasContext *s);
124 static void gen_jmp(DisasContext *s, target_ulong eip);
125 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
126
127 /* i386 arith/logic operations */
128 enum {
129 OP_ADDL,
130 OP_ORL,
131 OP_ADCL,
132 OP_SBBL,
133 OP_ANDL,
134 OP_SUBL,
135 OP_XORL,
136 OP_CMPL,
137 };
138
139 /* i386 shift ops */
140 enum {
141 OP_ROL,
142 OP_ROR,
143 OP_RCL,
144 OP_RCR,
145 OP_SHL,
146 OP_SHR,
147 OP_SHL1, /* undocumented */
148 OP_SAR = 7,
149 };
150
151 enum {
152 JCC_O,
153 JCC_B,
154 JCC_Z,
155 JCC_BE,
156 JCC_S,
157 JCC_P,
158 JCC_L,
159 JCC_LE,
160 };
161
162 /* operand size */
163 enum {
164 OT_BYTE = 0,
165 OT_WORD,
166 OT_LONG,
167 OT_QUAD,
168 };
169
170 enum {
171 /* I386 int registers */
172 OR_EAX, /* MUST be even numbered */
173 OR_ECX,
174 OR_EDX,
175 OR_EBX,
176 OR_ESP,
177 OR_EBP,
178 OR_ESI,
179 OR_EDI,
180
181 OR_TMP0 = 16, /* temporary operand register */
182 OR_TMP1,
183 OR_A0, /* temporary register used when doing address evaluation */
184 };
185
186 enum {
187 USES_CC_DST = 1,
188 USES_CC_SRC = 2,
189 };
190
191 /* Bit set if the global variable is live after setting CC_OP to X. */
192 static const uint8_t cc_op_live[CC_OP_NB] = {
193 [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC,
194 [CC_OP_EFLAGS] = USES_CC_SRC,
195 [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC,
196 [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC,
197 [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC,
198 [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC,
199 [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC,
200 [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST,
201 [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC,
202 [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC,
203 [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
204 [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
205 };
206
207 static void set_cc_op(DisasContext *s, CCOp op)
208 {
209 int dead;
210
211 if (s->cc_op == op) {
212 return;
213 }
214
215 /* Discard CC computation that will no longer be used. */
216 dead = cc_op_live[s->cc_op] & ~cc_op_live[op];
217 if (dead & USES_CC_DST) {
218 tcg_gen_discard_tl(cpu_cc_dst);
219 }
220 if (dead & USES_CC_SRC) {
221 tcg_gen_discard_tl(cpu_cc_src);
222 }
223
224 s->cc_op = op;
225 /* The DYNAMIC setting is translator only, and should never be
226 stored. Thus we always consider it clean. */
227 s->cc_op_dirty = (op != CC_OP_DYNAMIC);
228 }
229
230 static void gen_update_cc_op(DisasContext *s)
231 {
232 if (s->cc_op_dirty) {
233 tcg_gen_movi_i32(cpu_cc_op, s->cc_op);
234 s->cc_op_dirty = false;
235 }
236 }
237
238 static inline void gen_op_movl_T0_0(void)
239 {
240 tcg_gen_movi_tl(cpu_T[0], 0);
241 }
242
243 static inline void gen_op_movl_T0_im(int32_t val)
244 {
245 tcg_gen_movi_tl(cpu_T[0], val);
246 }
247
248 static inline void gen_op_movl_T0_imu(uint32_t val)
249 {
250 tcg_gen_movi_tl(cpu_T[0], val);
251 }
252
253 static inline void gen_op_movl_T1_im(int32_t val)
254 {
255 tcg_gen_movi_tl(cpu_T[1], val);
256 }
257
258 static inline void gen_op_movl_T1_imu(uint32_t val)
259 {
260 tcg_gen_movi_tl(cpu_T[1], val);
261 }
262
263 static inline void gen_op_movl_A0_im(uint32_t val)
264 {
265 tcg_gen_movi_tl(cpu_A0, val);
266 }
267
268 #ifdef TARGET_X86_64
269 static inline void gen_op_movq_A0_im(int64_t val)
270 {
271 tcg_gen_movi_tl(cpu_A0, val);
272 }
273 #endif
274
275 static inline void gen_movtl_T0_im(target_ulong val)
276 {
277 tcg_gen_movi_tl(cpu_T[0], val);
278 }
279
280 static inline void gen_movtl_T1_im(target_ulong val)
281 {
282 tcg_gen_movi_tl(cpu_T[1], val);
283 }
284
285 static inline void gen_op_andl_T0_ffff(void)
286 {
287 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
288 }
289
290 static inline void gen_op_andl_T0_im(uint32_t val)
291 {
292 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
293 }
294
295 static inline void gen_op_movl_T0_T1(void)
296 {
297 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
298 }
299
300 static inline void gen_op_andl_A0_ffff(void)
301 {
302 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
303 }
304
305 #ifdef TARGET_X86_64
306
307 #define NB_OP_SIZES 4
308
309 #else /* !TARGET_X86_64 */
310
311 #define NB_OP_SIZES 3
312
313 #endif /* !TARGET_X86_64 */
314
315 #if defined(HOST_WORDS_BIGENDIAN)
316 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
317 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
318 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
319 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
320 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
321 #else
322 #define REG_B_OFFSET 0
323 #define REG_H_OFFSET 1
324 #define REG_W_OFFSET 0
325 #define REG_L_OFFSET 0
326 #define REG_LH_OFFSET 4
327 #endif
328
329 /* In instruction encodings for byte register accesses the
330 * register number usually indicates "low 8 bits of register N";
331 * however there are some special cases where N 4..7 indicates
332 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
333 * true for this special case, false otherwise.
334 */
335 static inline bool byte_reg_is_xH(int reg)
336 {
337 if (reg < 4) {
338 return false;
339 }
340 #ifdef TARGET_X86_64
341 if (reg >= 8 || x86_64_hregs) {
342 return false;
343 }
344 #endif
345 return true;
346 }
347
348 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
349 {
350 switch(ot) {
351 case OT_BYTE:
352 if (!byte_reg_is_xH(reg)) {
353 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
354 } else {
355 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
356 }
357 break;
358 case OT_WORD:
359 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
360 break;
361 default: /* XXX this shouldn't be reached; abort? */
362 case OT_LONG:
363 /* For x86_64, this sets the higher half of register to zero.
364 For i386, this is equivalent to a mov. */
365 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
366 break;
367 #ifdef TARGET_X86_64
368 case OT_QUAD:
369 tcg_gen_mov_tl(cpu_regs[reg], t0);
370 break;
371 #endif
372 }
373 }
374
375 static inline void gen_op_mov_reg_T0(int ot, int reg)
376 {
377 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
378 }
379
380 static inline void gen_op_mov_reg_T1(int ot, int reg)
381 {
382 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
383 }
384
385 static inline void gen_op_mov_reg_A0(int size, int reg)
386 {
387 switch(size) {
388 case OT_BYTE:
389 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
390 break;
391 default: /* XXX this shouldn't be reached; abort? */
392 case OT_WORD:
393 /* For x86_64, this sets the higher half of register to zero.
394 For i386, this is equivalent to a mov. */
395 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
396 break;
397 #ifdef TARGET_X86_64
398 case OT_LONG:
399 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
400 break;
401 #endif
402 }
403 }
404
405 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
406 {
407 if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
408 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
409 tcg_gen_ext8u_tl(t0, t0);
410 } else {
411 tcg_gen_mov_tl(t0, cpu_regs[reg]);
412 }
413 }
414
415 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
416 {
417 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
418 }
419
420 static inline void gen_op_movl_A0_reg(int reg)
421 {
422 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
423 }
424
425 static inline void gen_op_addl_A0_im(int32_t val)
426 {
427 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
428 #ifdef TARGET_X86_64
429 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
430 #endif
431 }
432
433 #ifdef TARGET_X86_64
434 static inline void gen_op_addq_A0_im(int64_t val)
435 {
436 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
437 }
438 #endif
439
440 static void gen_add_A0_im(DisasContext *s, int val)
441 {
442 #ifdef TARGET_X86_64
443 if (CODE64(s))
444 gen_op_addq_A0_im(val);
445 else
446 #endif
447 gen_op_addl_A0_im(val);
448 }
449
450 static inline void gen_op_addl_T0_T1(void)
451 {
452 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
453 }
454
455 static inline void gen_op_jmp_T0(void)
456 {
457 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
458 }
459
460 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
461 {
462 switch(size) {
463 case OT_BYTE:
464 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
465 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
466 break;
467 case OT_WORD:
468 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
469 /* For x86_64, this sets the higher half of register to zero.
470 For i386, this is equivalent to a nop. */
471 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
472 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
473 break;
474 #ifdef TARGET_X86_64
475 case OT_LONG:
476 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
477 break;
478 #endif
479 }
480 }
481
482 static inline void gen_op_add_reg_T0(int size, int reg)
483 {
484 switch(size) {
485 case OT_BYTE:
486 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
487 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
488 break;
489 case OT_WORD:
490 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
491 /* For x86_64, this sets the higher half of register to zero.
492 For i386, this is equivalent to a nop. */
493 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
494 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
495 break;
496 #ifdef TARGET_X86_64
497 case OT_LONG:
498 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
499 break;
500 #endif
501 }
502 }
503
504 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
505 {
506 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
507 if (shift != 0)
508 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
509 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
510 /* For x86_64, this sets the higher half of register to zero.
511 For i386, this is equivalent to a nop. */
512 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
513 }
514
515 static inline void gen_op_movl_A0_seg(int reg)
516 {
517 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
518 }
519
520 static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
521 {
522 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
523 #ifdef TARGET_X86_64
524 if (CODE64(s)) {
525 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
526 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
527 } else {
528 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
529 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
530 }
531 #else
532 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
533 #endif
534 }
535
536 #ifdef TARGET_X86_64
537 static inline void gen_op_movq_A0_seg(int reg)
538 {
539 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
540 }
541
542 static inline void gen_op_addq_A0_seg(int reg)
543 {
544 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
545 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
546 }
547
548 static inline void gen_op_movq_A0_reg(int reg)
549 {
550 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
551 }
552
553 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
554 {
555 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
556 if (shift != 0)
557 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
558 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
559 }
560 #endif
561
562 static inline void gen_op_lds_T0_A0(int idx)
563 {
564 int mem_index = (idx >> 2) - 1;
565 switch(idx & 3) {
566 case OT_BYTE:
567 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
568 break;
569 case OT_WORD:
570 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
571 break;
572 default:
573 case OT_LONG:
574 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
575 break;
576 }
577 }
578
579 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
580 {
581 int mem_index = (idx >> 2) - 1;
582 switch(idx & 3) {
583 case OT_BYTE:
584 tcg_gen_qemu_ld8u(t0, a0, mem_index);
585 break;
586 case OT_WORD:
587 tcg_gen_qemu_ld16u(t0, a0, mem_index);
588 break;
589 case OT_LONG:
590 tcg_gen_qemu_ld32u(t0, a0, mem_index);
591 break;
592 default:
593 case OT_QUAD:
594 /* Should never happen on 32-bit targets. */
595 #ifdef TARGET_X86_64
596 tcg_gen_qemu_ld64(t0, a0, mem_index);
597 #endif
598 break;
599 }
600 }
601
602 /* XXX: always use ldu or lds */
603 static inline void gen_op_ld_T0_A0(int idx)
604 {
605 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
606 }
607
608 static inline void gen_op_ldu_T0_A0(int idx)
609 {
610 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
611 }
612
613 static inline void gen_op_ld_T1_A0(int idx)
614 {
615 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
616 }
617
618 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
619 {
620 int mem_index = (idx >> 2) - 1;
621 switch(idx & 3) {
622 case OT_BYTE:
623 tcg_gen_qemu_st8(t0, a0, mem_index);
624 break;
625 case OT_WORD:
626 tcg_gen_qemu_st16(t0, a0, mem_index);
627 break;
628 case OT_LONG:
629 tcg_gen_qemu_st32(t0, a0, mem_index);
630 break;
631 default:
632 case OT_QUAD:
633 /* Should never happen on 32-bit targets. */
634 #ifdef TARGET_X86_64
635 tcg_gen_qemu_st64(t0, a0, mem_index);
636 #endif
637 break;
638 }
639 }
640
641 static inline void gen_op_st_T0_A0(int idx)
642 {
643 gen_op_st_v(idx, cpu_T[0], cpu_A0);
644 }
645
646 static inline void gen_op_st_T1_A0(int idx)
647 {
648 gen_op_st_v(idx, cpu_T[1], cpu_A0);
649 }
650
651 static inline void gen_jmp_im(target_ulong pc)
652 {
653 tcg_gen_movi_tl(cpu_tmp0, pc);
654 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
655 }
656
657 static inline void gen_string_movl_A0_ESI(DisasContext *s)
658 {
659 int override;
660
661 override = s->override;
662 #ifdef TARGET_X86_64
663 if (s->aflag == 2) {
664 if (override >= 0) {
665 gen_op_movq_A0_seg(override);
666 gen_op_addq_A0_reg_sN(0, R_ESI);
667 } else {
668 gen_op_movq_A0_reg(R_ESI);
669 }
670 } else
671 #endif
672 if (s->aflag) {
673 /* 32 bit address */
674 if (s->addseg && override < 0)
675 override = R_DS;
676 if (override >= 0) {
677 gen_op_movl_A0_seg(override);
678 gen_op_addl_A0_reg_sN(0, R_ESI);
679 } else {
680 gen_op_movl_A0_reg(R_ESI);
681 }
682 } else {
683 /* 16 address, always override */
684 if (override < 0)
685 override = R_DS;
686 gen_op_movl_A0_reg(R_ESI);
687 gen_op_andl_A0_ffff();
688 gen_op_addl_A0_seg(s, override);
689 }
690 }
691
692 static inline void gen_string_movl_A0_EDI(DisasContext *s)
693 {
694 #ifdef TARGET_X86_64
695 if (s->aflag == 2) {
696 gen_op_movq_A0_reg(R_EDI);
697 } else
698 #endif
699 if (s->aflag) {
700 if (s->addseg) {
701 gen_op_movl_A0_seg(R_ES);
702 gen_op_addl_A0_reg_sN(0, R_EDI);
703 } else {
704 gen_op_movl_A0_reg(R_EDI);
705 }
706 } else {
707 gen_op_movl_A0_reg(R_EDI);
708 gen_op_andl_A0_ffff();
709 gen_op_addl_A0_seg(s, R_ES);
710 }
711 }
712
713 static inline void gen_op_movl_T0_Dshift(int ot)
714 {
715 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
716 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
717 };
718
719 static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
720 {
721 switch (size) {
722 case OT_BYTE:
723 if (sign) {
724 tcg_gen_ext8s_tl(dst, src);
725 } else {
726 tcg_gen_ext8u_tl(dst, src);
727 }
728 return dst;
729 case OT_WORD:
730 if (sign) {
731 tcg_gen_ext16s_tl(dst, src);
732 } else {
733 tcg_gen_ext16u_tl(dst, src);
734 }
735 return dst;
736 #ifdef TARGET_X86_64
737 case OT_LONG:
738 if (sign) {
739 tcg_gen_ext32s_tl(dst, src);
740 } else {
741 tcg_gen_ext32u_tl(dst, src);
742 }
743 return dst;
744 #endif
745 default:
746 return src;
747 }
748 }
749
750 static void gen_extu(int ot, TCGv reg)
751 {
752 gen_ext_tl(reg, reg, ot, false);
753 }
754
755 static void gen_exts(int ot, TCGv reg)
756 {
757 gen_ext_tl(reg, reg, ot, true);
758 }
759
760 static inline void gen_op_jnz_ecx(int size, int label1)
761 {
762 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
763 gen_extu(size + 1, cpu_tmp0);
764 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
765 }
766
767 static inline void gen_op_jz_ecx(int size, int label1)
768 {
769 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
770 gen_extu(size + 1, cpu_tmp0);
771 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
772 }
773
774 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
775 {
776 switch (ot) {
777 case OT_BYTE:
778 gen_helper_inb(v, n);
779 break;
780 case OT_WORD:
781 gen_helper_inw(v, n);
782 break;
783 case OT_LONG:
784 gen_helper_inl(v, n);
785 break;
786 }
787 }
788
789 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
790 {
791 switch (ot) {
792 case OT_BYTE:
793 gen_helper_outb(v, n);
794 break;
795 case OT_WORD:
796 gen_helper_outw(v, n);
797 break;
798 case OT_LONG:
799 gen_helper_outl(v, n);
800 break;
801 }
802 }
803
804 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
805 uint32_t svm_flags)
806 {
807 int state_saved;
808 target_ulong next_eip;
809
810 state_saved = 0;
811 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
812 gen_update_cc_op(s);
813 gen_jmp_im(cur_eip);
814 state_saved = 1;
815 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
816 switch (ot) {
817 case OT_BYTE:
818 gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
819 break;
820 case OT_WORD:
821 gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
822 break;
823 case OT_LONG:
824 gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
825 break;
826 }
827 }
828 if(s->flags & HF_SVMI_MASK) {
829 if (!state_saved) {
830 gen_update_cc_op(s);
831 gen_jmp_im(cur_eip);
832 }
833 svm_flags |= (1 << (4 + ot));
834 next_eip = s->pc - s->cs_base;
835 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
836 gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32,
837 tcg_const_i32(svm_flags),
838 tcg_const_i32(next_eip - cur_eip));
839 }
840 }
841
842 static inline void gen_movs(DisasContext *s, int ot)
843 {
844 gen_string_movl_A0_ESI(s);
845 gen_op_ld_T0_A0(ot + s->mem_index);
846 gen_string_movl_A0_EDI(s);
847 gen_op_st_T0_A0(ot + s->mem_index);
848 gen_op_movl_T0_Dshift(ot);
849 gen_op_add_reg_T0(s->aflag, R_ESI);
850 gen_op_add_reg_T0(s->aflag, R_EDI);
851 }
852
853 static void gen_op_update1_cc(void)
854 {
855 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
856 }
857
858 static void gen_op_update2_cc(void)
859 {
860 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
861 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
862 }
863
864 static inline void gen_op_cmpl_T0_T1_cc(void)
865 {
866 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
867 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
868 }
869
870 static inline void gen_op_testl_T0_T1_cc(void)
871 {
872 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
873 }
874
875 static void gen_op_update_neg_cc(void)
876 {
877 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
878 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
879 }
880
881 /* compute all eflags to cc_src */
882 static void gen_compute_eflags(DisasContext *s)
883 {
884 if (s->cc_op == CC_OP_EFLAGS) {
885 return;
886 }
887 gen_update_cc_op(s);
888 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op);
889 set_cc_op(s, CC_OP_EFLAGS);
890 tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
891 }
892
893 typedef struct CCPrepare {
894 TCGCond cond;
895 TCGv reg;
896 TCGv reg2;
897 target_ulong imm;
898 target_ulong mask;
899 bool use_reg2;
900 bool no_setcond;
901 } CCPrepare;
902
903 /* compute eflags.C to reg */
904 static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
905 {
906 TCGv t0, t1;
907 int size, shift;
908
909 switch (s->cc_op) {
910 case CC_OP_SUBB ... CC_OP_SUBQ:
911 /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
912 size = s->cc_op - CC_OP_SUBB;
913 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
914 /* If no temporary was used, be careful not to alias t1 and t0. */
915 t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
916 tcg_gen_add_tl(t0, cpu_cc_dst, cpu_cc_src);
917 gen_extu(size, t0);
918 goto add_sub;
919
920 case CC_OP_ADDB ... CC_OP_ADDQ:
921 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
922 size = s->cc_op - CC_OP_ADDB;
923 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
924 t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
925 add_sub:
926 return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0,
927 .reg2 = t1, .mask = -1, .use_reg2 = true };
928
929 case CC_OP_SBBB ... CC_OP_SBBQ:
930 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
931 size = s->cc_op - CC_OP_SBBB;
932 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
933 if (TCGV_EQUAL(t1, reg) && TCGV_EQUAL(reg, cpu_cc_src)) {
934 tcg_gen_mov_tl(cpu_tmp0, cpu_cc_src);
935 t1 = cpu_tmp0;
936 }
937
938 tcg_gen_add_tl(reg, cpu_cc_dst, cpu_cc_src);
939 tcg_gen_addi_tl(reg, reg, 1);
940 gen_extu(size, reg);
941 t0 = reg;
942 goto adc_sbb;
943
944 case CC_OP_ADCB ... CC_OP_ADCQ:
945 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
946 size = s->cc_op - CC_OP_ADCB;
947 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
948 t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
949 adc_sbb:
950 return (CCPrepare) { .cond = TCG_COND_LEU, .reg = t0,
951 .reg2 = t1, .mask = -1, .use_reg2 = true };
952
953 case CC_OP_LOGICB ... CC_OP_LOGICQ:
954 return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 };
955
956 case CC_OP_INCB ... CC_OP_INCQ:
957 case CC_OP_DECB ... CC_OP_DECQ:
958 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
959 .mask = -1, .no_setcond = true };
960
961 case CC_OP_SHLB ... CC_OP_SHLQ:
962 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
963 size = s->cc_op - CC_OP_SHLB;
964 shift = (8 << size) - 1;
965 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
966 .mask = (target_ulong)1 << shift };
967
968 case CC_OP_MULB ... CC_OP_MULQ:
969 return (CCPrepare) { .cond = TCG_COND_NE,
970 .reg = cpu_cc_src, .mask = -1 };
971
972 case CC_OP_EFLAGS:
973 case CC_OP_SARB ... CC_OP_SARQ:
974 /* CC_SRC & 1 */
975 return (CCPrepare) { .cond = TCG_COND_NE,
976 .reg = cpu_cc_src, .mask = CC_C };
977
978 default:
979 /* The need to compute only C from CC_OP_DYNAMIC is important
980 in efficiently implementing e.g. INC at the start of a TB. */
981 gen_update_cc_op(s);
982 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
983 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
984 return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
985 .mask = -1, .no_setcond = true };
986 }
987 }
988
989 /* compute eflags.P to reg */
990 static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg)
991 {
992 gen_compute_eflags(s);
993 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
994 .mask = CC_P };
995 }
996
997 /* compute eflags.S to reg */
998 static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg)
999 {
1000 switch (s->cc_op) {
1001 case CC_OP_DYNAMIC:
1002 gen_compute_eflags(s);
1003 /* FALLTHRU */
1004 case CC_OP_EFLAGS:
1005 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
1006 .mask = CC_S };
1007 default:
1008 {
1009 int size = (s->cc_op - CC_OP_ADDB) & 3;
1010 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
1011 return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 };
1012 }
1013 }
1014 }
1015
1016 /* compute eflags.O to reg */
1017 static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg)
1018 {
1019 gen_compute_eflags(s);
1020 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
1021 .mask = CC_O };
1022 }
1023
1024 /* compute eflags.Z to reg */
1025 static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
1026 {
1027 switch (s->cc_op) {
1028 case CC_OP_DYNAMIC:
1029 gen_compute_eflags(s);
1030 /* FALLTHRU */
1031 case CC_OP_EFLAGS:
1032 return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
1033 .mask = CC_Z };
1034 default:
1035 {
1036 int size = (s->cc_op - CC_OP_ADDB) & 3;
1037 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
1038 return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 };
1039 }
1040 }
1041 }
1042
1043 /* perform a conditional store into register 'reg' according to jump opcode
1044 value 'b'. In the fast case, T0 is guaranted not to be used. */
1045 static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg)
1046 {
1047 int inv, jcc_op, size, cond;
1048 CCPrepare cc;
1049 TCGv t0;
1050
1051 inv = b & 1;
1052 jcc_op = (b >> 1) & 7;
1053
1054 switch (s->cc_op) {
1055 case CC_OP_SUBB ... CC_OP_SUBQ:
1056 /* We optimize relational operators for the cmp/jcc case. */
1057 size = s->cc_op - CC_OP_SUBB;
1058 switch (jcc_op) {
1059 case JCC_BE:
1060 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1061 gen_extu(size, cpu_tmp4);
1062 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
1063 cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4,
1064 .reg2 = t0, .mask = -1, .use_reg2 = true };
1065 break;
1066
1067 case JCC_L:
1068 cond = TCG_COND_LT;
1069 goto fast_jcc_l;
1070 case JCC_LE:
1071 cond = TCG_COND_LE;
1072 fast_jcc_l:
1073 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1074 gen_exts(size, cpu_tmp4);
1075 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true);
1076 cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4,
1077 .reg2 = t0, .mask = -1, .use_reg2 = true };
1078 break;
1079
1080 default:
1081 goto slow_jcc;
1082 }
1083 break;
1084
1085 default:
1086 slow_jcc:
1087 /* This actually generates good code for JC, JZ and JS. */
1088 switch (jcc_op) {
1089 case JCC_O:
1090 cc = gen_prepare_eflags_o(s, reg);
1091 break;
1092 case JCC_B:
1093 cc = gen_prepare_eflags_c(s, reg);
1094 break;
1095 case JCC_Z:
1096 cc = gen_prepare_eflags_z(s, reg);
1097 break;
1098 case JCC_BE:
1099 gen_compute_eflags(s);
1100 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src,
1101 .mask = CC_Z | CC_C };
1102 break;
1103 case JCC_S:
1104 cc = gen_prepare_eflags_s(s, reg);
1105 break;
1106 case JCC_P:
1107 cc = gen_prepare_eflags_p(s, reg);
1108 break;
1109 case JCC_L:
1110 gen_compute_eflags(s);
1111 if (TCGV_EQUAL(reg, cpu_cc_src)) {
1112 reg = cpu_tmp0;
1113 }
1114 tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
1115 tcg_gen_xor_tl(reg, reg, cpu_cc_src);
1116 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
1117 .mask = CC_S };
1118 break;
1119 default:
1120 case JCC_LE:
1121 gen_compute_eflags(s);
1122 if (TCGV_EQUAL(reg, cpu_cc_src)) {
1123 reg = cpu_tmp0;
1124 }
1125 tcg_gen_shri_tl(reg, cpu_cc_src, 4); /* CC_O -> CC_S */
1126 tcg_gen_xor_tl(reg, reg, cpu_cc_src);
1127 cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg,
1128 .mask = CC_S | CC_Z };
1129 break;
1130 }
1131 break;
1132 }
1133
1134 if (inv) {
1135 cc.cond = tcg_invert_cond(cc.cond);
1136 }
1137 return cc;
1138 }
1139
1140 static void gen_setcc1(DisasContext *s, int b, TCGv reg)
1141 {
1142 CCPrepare cc = gen_prepare_cc(s, b, reg);
1143
1144 if (cc.no_setcond) {
1145 if (cc.cond == TCG_COND_EQ) {
1146 tcg_gen_xori_tl(reg, cc.reg, 1);
1147 } else {
1148 tcg_gen_mov_tl(reg, cc.reg);
1149 }
1150 return;
1151 }
1152
1153 if (cc.cond == TCG_COND_NE && !cc.use_reg2 && cc.imm == 0 &&
1154 cc.mask != 0 && (cc.mask & (cc.mask - 1)) == 0) {
1155 tcg_gen_shri_tl(reg, cc.reg, ctztl(cc.mask));
1156 tcg_gen_andi_tl(reg, reg, 1);
1157 return;
1158 }
1159 if (cc.mask != -1) {
1160 tcg_gen_andi_tl(reg, cc.reg, cc.mask);
1161 cc.reg = reg;
1162 }
1163 if (cc.use_reg2) {
1164 tcg_gen_setcond_tl(cc.cond, reg, cc.reg, cc.reg2);
1165 } else {
1166 tcg_gen_setcondi_tl(cc.cond, reg, cc.reg, cc.imm);
1167 }
1168 }
1169
1170 static inline void gen_compute_eflags_c(DisasContext *s, TCGv reg)
1171 {
1172 gen_setcc1(s, JCC_B << 1, reg);
1173 }
1174
1175 /* generate a conditional jump to label 'l1' according to jump opcode
1176 value 'b'. In the fast case, T0 is guaranted not to be used. */
1177 static inline void gen_jcc1(DisasContext *s, int b, int l1)
1178 {
1179 CCPrepare cc = gen_prepare_cc(s, b, cpu_T[0]);
1180
1181 if (cc.mask != -1) {
1182 tcg_gen_andi_tl(cpu_T[0], cc.reg, cc.mask);
1183 cc.reg = cpu_T[0];
1184 }
1185 if (cc.use_reg2) {
1186 tcg_gen_brcond_tl(cc.cond, cc.reg, cc.reg2, l1);
1187 } else {
1188 tcg_gen_brcondi_tl(cc.cond, cc.reg, cc.imm, l1);
1189 }
1190 }
1191
1192 /* XXX: does not work with gdbstub "ice" single step - not a
1193 serious problem */
1194 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1195 {
1196 int l1, l2;
1197
1198 l1 = gen_new_label();
1199 l2 = gen_new_label();
1200 gen_op_jnz_ecx(s->aflag, l1);
1201 gen_set_label(l2);
1202 gen_jmp_tb(s, next_eip, 1);
1203 gen_set_label(l1);
1204 return l2;
1205 }
1206
1207 static inline void gen_stos(DisasContext *s, int ot)
1208 {
1209 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1210 gen_string_movl_A0_EDI(s);
1211 gen_op_st_T0_A0(ot + s->mem_index);
1212 gen_op_movl_T0_Dshift(ot);
1213 gen_op_add_reg_T0(s->aflag, R_EDI);
1214 }
1215
1216 static inline void gen_lods(DisasContext *s, int ot)
1217 {
1218 gen_string_movl_A0_ESI(s);
1219 gen_op_ld_T0_A0(ot + s->mem_index);
1220 gen_op_mov_reg_T0(ot, R_EAX);
1221 gen_op_movl_T0_Dshift(ot);
1222 gen_op_add_reg_T0(s->aflag, R_ESI);
1223 }
1224
1225 static inline void gen_scas(DisasContext *s, int ot)
1226 {
1227 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1228 gen_string_movl_A0_EDI(s);
1229 gen_op_ld_T1_A0(ot + s->mem_index);
1230 gen_op_cmpl_T0_T1_cc();
1231 gen_op_movl_T0_Dshift(ot);
1232 gen_op_add_reg_T0(s->aflag, R_EDI);
1233 set_cc_op(s, CC_OP_SUBB + ot);
1234 }
1235
1236 static inline void gen_cmps(DisasContext *s, int ot)
1237 {
1238 gen_string_movl_A0_ESI(s);
1239 gen_op_ld_T0_A0(ot + s->mem_index);
1240 gen_string_movl_A0_EDI(s);
1241 gen_op_ld_T1_A0(ot + s->mem_index);
1242 gen_op_cmpl_T0_T1_cc();
1243 gen_op_movl_T0_Dshift(ot);
1244 gen_op_add_reg_T0(s->aflag, R_ESI);
1245 gen_op_add_reg_T0(s->aflag, R_EDI);
1246 set_cc_op(s, CC_OP_SUBB + ot);
1247 }
1248
1249 static inline void gen_ins(DisasContext *s, int ot)
1250 {
1251 if (use_icount)
1252 gen_io_start();
1253 gen_string_movl_A0_EDI(s);
1254 /* Note: we must do this dummy write first to be restartable in
1255 case of page fault. */
1256 gen_op_movl_T0_0();
1257 gen_op_st_T0_A0(ot + s->mem_index);
1258 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1259 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1260 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1261 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1262 gen_op_st_T0_A0(ot + s->mem_index);
1263 gen_op_movl_T0_Dshift(ot);
1264 gen_op_add_reg_T0(s->aflag, R_EDI);
1265 if (use_icount)
1266 gen_io_end();
1267 }
1268
1269 static inline void gen_outs(DisasContext *s, int ot)
1270 {
1271 if (use_icount)
1272 gen_io_start();
1273 gen_string_movl_A0_ESI(s);
1274 gen_op_ld_T0_A0(ot + s->mem_index);
1275
1276 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1277 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1278 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1279 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1280 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1281
1282 gen_op_movl_T0_Dshift(ot);
1283 gen_op_add_reg_T0(s->aflag, R_ESI);
1284 if (use_icount)
1285 gen_io_end();
1286 }
1287
1288 /* same method as Valgrind : we generate jumps to current or next
1289 instruction */
1290 #define GEN_REPZ(op) \
1291 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1292 target_ulong cur_eip, target_ulong next_eip) \
1293 { \
1294 int l2;\
1295 gen_update_cc_op(s); \
1296 l2 = gen_jz_ecx_string(s, next_eip); \
1297 gen_ ## op(s, ot); \
1298 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1299 /* a loop would cause two single step exceptions if ECX = 1 \
1300 before rep string_insn */ \
1301 if (!s->jmp_opt) \
1302 gen_op_jz_ecx(s->aflag, l2); \
1303 gen_jmp(s, cur_eip); \
1304 }
1305
1306 #define GEN_REPZ2(op) \
1307 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1308 target_ulong cur_eip, \
1309 target_ulong next_eip, \
1310 int nz) \
1311 { \
1312 int l2;\
1313 gen_update_cc_op(s); \
1314 l2 = gen_jz_ecx_string(s, next_eip); \
1315 gen_ ## op(s, ot); \
1316 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1317 gen_update_cc_op(s); \
1318 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1319 if (!s->jmp_opt) \
1320 gen_op_jz_ecx(s->aflag, l2); \
1321 gen_jmp(s, cur_eip); \
1322 set_cc_op(s, CC_OP_DYNAMIC); \
1323 }
1324
1325 GEN_REPZ(movs)
1326 GEN_REPZ(stos)
1327 GEN_REPZ(lods)
1328 GEN_REPZ(ins)
1329 GEN_REPZ(outs)
1330 GEN_REPZ2(scas)
1331 GEN_REPZ2(cmps)
1332
1333 static void gen_helper_fp_arith_ST0_FT0(int op)
1334 {
1335 switch (op) {
1336 case 0:
1337 gen_helper_fadd_ST0_FT0(cpu_env);
1338 break;
1339 case 1:
1340 gen_helper_fmul_ST0_FT0(cpu_env);
1341 break;
1342 case 2:
1343 gen_helper_fcom_ST0_FT0(cpu_env);
1344 break;
1345 case 3:
1346 gen_helper_fcom_ST0_FT0(cpu_env);
1347 break;
1348 case 4:
1349 gen_helper_fsub_ST0_FT0(cpu_env);
1350 break;
1351 case 5:
1352 gen_helper_fsubr_ST0_FT0(cpu_env);
1353 break;
1354 case 6:
1355 gen_helper_fdiv_ST0_FT0(cpu_env);
1356 break;
1357 case 7:
1358 gen_helper_fdivr_ST0_FT0(cpu_env);
1359 break;
1360 }
1361 }
1362
1363 /* NOTE the exception in "r" op ordering */
1364 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1365 {
1366 TCGv_i32 tmp = tcg_const_i32(opreg);
1367 switch (op) {
1368 case 0:
1369 gen_helper_fadd_STN_ST0(cpu_env, tmp);
1370 break;
1371 case 1:
1372 gen_helper_fmul_STN_ST0(cpu_env, tmp);
1373 break;
1374 case 4:
1375 gen_helper_fsubr_STN_ST0(cpu_env, tmp);
1376 break;
1377 case 5:
1378 gen_helper_fsub_STN_ST0(cpu_env, tmp);
1379 break;
1380 case 6:
1381 gen_helper_fdivr_STN_ST0(cpu_env, tmp);
1382 break;
1383 case 7:
1384 gen_helper_fdiv_STN_ST0(cpu_env, tmp);
1385 break;
1386 }
1387 }
1388
1389 /* if d == OR_TMP0, it means memory operand (address in A0) */
1390 static void gen_op(DisasContext *s1, int op, int ot, int d)
1391 {
1392 if (d != OR_TMP0) {
1393 gen_op_mov_TN_reg(ot, 0, d);
1394 } else {
1395 gen_op_ld_T0_A0(ot + s1->mem_index);
1396 }
1397 switch(op) {
1398 case OP_ADCL:
1399 gen_compute_eflags_c(s1, cpu_tmp4);
1400 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1401 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1402 if (d != OR_TMP0)
1403 gen_op_mov_reg_T0(ot, d);
1404 else
1405 gen_op_st_T0_A0(ot + s1->mem_index);
1406 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1407 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1408 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1409 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1410 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1411 set_cc_op(s1, CC_OP_DYNAMIC);
1412 break;
1413 case OP_SBBL:
1414 gen_compute_eflags_c(s1, cpu_tmp4);
1415 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1416 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1417 if (d != OR_TMP0)
1418 gen_op_mov_reg_T0(ot, d);
1419 else
1420 gen_op_st_T0_A0(ot + s1->mem_index);
1421 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1422 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1423 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1424 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1425 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1426 set_cc_op(s1, CC_OP_DYNAMIC);
1427 break;
1428 case OP_ADDL:
1429 gen_op_addl_T0_T1();
1430 if (d != OR_TMP0)
1431 gen_op_mov_reg_T0(ot, d);
1432 else
1433 gen_op_st_T0_A0(ot + s1->mem_index);
1434 gen_op_update2_cc();
1435 set_cc_op(s1, CC_OP_ADDB + ot);
1436 break;
1437 case OP_SUBL:
1438 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1439 if (d != OR_TMP0)
1440 gen_op_mov_reg_T0(ot, d);
1441 else
1442 gen_op_st_T0_A0(ot + s1->mem_index);
1443 gen_op_update2_cc();
1444 set_cc_op(s1, CC_OP_SUBB + ot);
1445 break;
1446 default:
1447 case OP_ANDL:
1448 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1449 if (d != OR_TMP0)
1450 gen_op_mov_reg_T0(ot, d);
1451 else
1452 gen_op_st_T0_A0(ot + s1->mem_index);
1453 gen_op_update1_cc();
1454 set_cc_op(s1, CC_OP_LOGICB + ot);
1455 break;
1456 case OP_ORL:
1457 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1458 if (d != OR_TMP0)
1459 gen_op_mov_reg_T0(ot, d);
1460 else
1461 gen_op_st_T0_A0(ot + s1->mem_index);
1462 gen_op_update1_cc();
1463 set_cc_op(s1, CC_OP_LOGICB + ot);
1464 break;
1465 case OP_XORL:
1466 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1467 if (d != OR_TMP0)
1468 gen_op_mov_reg_T0(ot, d);
1469 else
1470 gen_op_st_T0_A0(ot + s1->mem_index);
1471 gen_op_update1_cc();
1472 set_cc_op(s1, CC_OP_LOGICB + ot);
1473 break;
1474 case OP_CMPL:
1475 gen_op_cmpl_T0_T1_cc();
1476 set_cc_op(s1, CC_OP_SUBB + ot);
1477 break;
1478 }
1479 }
1480
1481 /* if d == OR_TMP0, it means memory operand (address in A0) */
1482 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1483 {
1484 if (d != OR_TMP0)
1485 gen_op_mov_TN_reg(ot, 0, d);
1486 else
1487 gen_op_ld_T0_A0(ot + s1->mem_index);
1488 gen_compute_eflags_c(s1, cpu_cc_src);
1489 if (c > 0) {
1490 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1491 set_cc_op(s1, CC_OP_INCB + ot);
1492 } else {
1493 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1494 set_cc_op(s1, CC_OP_DECB + ot);
1495 }
1496 if (d != OR_TMP0)
1497 gen_op_mov_reg_T0(ot, d);
1498 else
1499 gen_op_st_T0_A0(ot + s1->mem_index);
1500 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1501 }
1502
1503 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1504 int is_right, int is_arith)
1505 {
1506 target_ulong mask;
1507 int shift_label;
1508 TCGv t0, t1, t2;
1509
1510 if (ot == OT_QUAD) {
1511 mask = 0x3f;
1512 } else {
1513 mask = 0x1f;
1514 }
1515
1516 /* load */
1517 if (op1 == OR_TMP0) {
1518 gen_op_ld_T0_A0(ot + s->mem_index);
1519 } else {
1520 gen_op_mov_TN_reg(ot, 0, op1);
1521 }
1522
1523 t0 = tcg_temp_local_new();
1524 t1 = tcg_temp_local_new();
1525 t2 = tcg_temp_local_new();
1526
1527 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1528
1529 if (is_right) {
1530 if (is_arith) {
1531 gen_exts(ot, cpu_T[0]);
1532 tcg_gen_mov_tl(t0, cpu_T[0]);
1533 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1534 } else {
1535 gen_extu(ot, cpu_T[0]);
1536 tcg_gen_mov_tl(t0, cpu_T[0]);
1537 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1538 }
1539 } else {
1540 tcg_gen_mov_tl(t0, cpu_T[0]);
1541 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1542 }
1543
1544 /* store */
1545 if (op1 == OR_TMP0) {
1546 gen_op_st_T0_A0(ot + s->mem_index);
1547 } else {
1548 gen_op_mov_reg_T0(ot, op1);
1549 }
1550
1551 /* update eflags */
1552 gen_update_cc_op(s);
1553
1554 tcg_gen_mov_tl(t1, cpu_T[0]);
1555
1556 shift_label = gen_new_label();
1557 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1558
1559 tcg_gen_addi_tl(t2, t2, -1);
1560 tcg_gen_mov_tl(cpu_cc_dst, t1);
1561
1562 if (is_right) {
1563 if (is_arith) {
1564 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1565 } else {
1566 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1567 }
1568 } else {
1569 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1570 }
1571
1572 if (is_right) {
1573 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1574 } else {
1575 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1576 }
1577
1578 gen_set_label(shift_label);
1579 set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */
1580
1581 tcg_temp_free(t0);
1582 tcg_temp_free(t1);
1583 tcg_temp_free(t2);
1584 }
1585
1586 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1587 int is_right, int is_arith)
1588 {
1589 int mask;
1590
1591 if (ot == OT_QUAD)
1592 mask = 0x3f;
1593 else
1594 mask = 0x1f;
1595
1596 /* load */
1597 if (op1 == OR_TMP0)
1598 gen_op_ld_T0_A0(ot + s->mem_index);
1599 else
1600 gen_op_mov_TN_reg(ot, 0, op1);
1601
1602 op2 &= mask;
1603 if (op2 != 0) {
1604 if (is_right) {
1605 if (is_arith) {
1606 gen_exts(ot, cpu_T[0]);
1607 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1608 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1609 } else {
1610 gen_extu(ot, cpu_T[0]);
1611 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1612 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1613 }
1614 } else {
1615 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1616 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1617 }
1618 }
1619
1620 /* store */
1621 if (op1 == OR_TMP0)
1622 gen_op_st_T0_A0(ot + s->mem_index);
1623 else
1624 gen_op_mov_reg_T0(ot, op1);
1625
1626 /* update eflags if non zero shift */
1627 if (op2 != 0) {
1628 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1629 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1630 set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
1631 }
1632 }
1633
1634 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1635 {
1636 if (arg2 >= 0)
1637 tcg_gen_shli_tl(ret, arg1, arg2);
1638 else
1639 tcg_gen_shri_tl(ret, arg1, -arg2);
1640 }
1641
1642 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1643 int is_right)
1644 {
1645 target_ulong mask;
1646 int label1, label2, data_bits;
1647 TCGv t0, t1, t2, a0;
1648
1649 /* XXX: inefficient, but we must use local temps */
1650 t0 = tcg_temp_local_new();
1651 t1 = tcg_temp_local_new();
1652 t2 = tcg_temp_local_new();
1653 a0 = tcg_temp_local_new();
1654
1655 if (ot == OT_QUAD)
1656 mask = 0x3f;
1657 else
1658 mask = 0x1f;
1659
1660 /* load */
1661 if (op1 == OR_TMP0) {
1662 tcg_gen_mov_tl(a0, cpu_A0);
1663 gen_op_ld_v(ot + s->mem_index, t0, a0);
1664 } else {
1665 gen_op_mov_v_reg(ot, t0, op1);
1666 }
1667
1668 tcg_gen_mov_tl(t1, cpu_T[1]);
1669
1670 tcg_gen_andi_tl(t1, t1, mask);
1671
1672 /* Must test zero case to avoid using undefined behaviour in TCG
1673 shifts. */
1674 label1 = gen_new_label();
1675 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1676
1677 if (ot <= OT_WORD)
1678 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1679 else
1680 tcg_gen_mov_tl(cpu_tmp0, t1);
1681
1682 gen_extu(ot, t0);
1683 tcg_gen_mov_tl(t2, t0);
1684
1685 data_bits = 8 << ot;
1686 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1687 fix TCG definition) */
1688 if (is_right) {
1689 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1690 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1691 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1692 } else {
1693 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1694 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1695 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1696 }
1697 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1698
1699 gen_set_label(label1);
1700 /* store */
1701 if (op1 == OR_TMP0) {
1702 gen_op_st_v(ot + s->mem_index, t0, a0);
1703 } else {
1704 gen_op_mov_reg_v(ot, op1, t0);
1705 }
1706
1707 /* update eflags. It is needed anyway most of the time, do it always. */
1708 gen_compute_eflags(s);
1709 assert(s->cc_op == CC_OP_EFLAGS);
1710
1711 label2 = gen_new_label();
1712 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1713
1714 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1715 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1716 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1717 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1718 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1719 if (is_right) {
1720 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1721 }
1722 tcg_gen_andi_tl(t0, t0, CC_C);
1723 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1724
1725 gen_set_label(label2);
1726
1727 tcg_temp_free(t0);
1728 tcg_temp_free(t1);
1729 tcg_temp_free(t2);
1730 tcg_temp_free(a0);
1731 }
1732
1733 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1734 int is_right)
1735 {
1736 int mask;
1737 int data_bits;
1738 TCGv t0, t1, a0;
1739
1740 /* XXX: inefficient, but we must use local temps */
1741 t0 = tcg_temp_local_new();
1742 t1 = tcg_temp_local_new();
1743 a0 = tcg_temp_local_new();
1744
1745 if (ot == OT_QUAD)
1746 mask = 0x3f;
1747 else
1748 mask = 0x1f;
1749
1750 /* load */
1751 if (op1 == OR_TMP0) {
1752 tcg_gen_mov_tl(a0, cpu_A0);
1753 gen_op_ld_v(ot + s->mem_index, t0, a0);
1754 } else {
1755 gen_op_mov_v_reg(ot, t0, op1);
1756 }
1757
1758 gen_extu(ot, t0);
1759 tcg_gen_mov_tl(t1, t0);
1760
1761 op2 &= mask;
1762 data_bits = 8 << ot;
1763 if (op2 != 0) {
1764 int shift = op2 & ((1 << (3 + ot)) - 1);
1765 if (is_right) {
1766 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1767 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1768 }
1769 else {
1770 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1771 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1772 }
1773 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1774 }
1775
1776 /* store */
1777 if (op1 == OR_TMP0) {
1778 gen_op_st_v(ot + s->mem_index, t0, a0);
1779 } else {
1780 gen_op_mov_reg_v(ot, op1, t0);
1781 }
1782
1783 if (op2 != 0) {
1784 /* update eflags */
1785 gen_compute_eflags(s);
1786 assert(s->cc_op == CC_OP_EFLAGS);
1787
1788 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1789 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1790 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1791 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1792 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1793 if (is_right) {
1794 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1795 }
1796 tcg_gen_andi_tl(t0, t0, CC_C);
1797 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1798 }
1799
1800 tcg_temp_free(t0);
1801 tcg_temp_free(t1);
1802 tcg_temp_free(a0);
1803 }
1804
1805 /* XXX: add faster immediate = 1 case */
1806 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1807 int is_right)
1808 {
1809 gen_compute_eflags(s);
1810 assert(s->cc_op == CC_OP_EFLAGS);
1811
1812 /* load */
1813 if (op1 == OR_TMP0)
1814 gen_op_ld_T0_A0(ot + s->mem_index);
1815 else
1816 gen_op_mov_TN_reg(ot, 0, op1);
1817
1818 if (is_right) {
1819 switch (ot) {
1820 case OT_BYTE:
1821 gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1822 break;
1823 case OT_WORD:
1824 gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1825 break;
1826 case OT_LONG:
1827 gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1828 break;
1829 #ifdef TARGET_X86_64
1830 case OT_QUAD:
1831 gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1832 break;
1833 #endif
1834 }
1835 } else {
1836 switch (ot) {
1837 case OT_BYTE:
1838 gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1839 break;
1840 case OT_WORD:
1841 gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1842 break;
1843 case OT_LONG:
1844 gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1845 break;
1846 #ifdef TARGET_X86_64
1847 case OT_QUAD:
1848 gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1849 break;
1850 #endif
1851 }
1852 }
1853 /* store */
1854 if (op1 == OR_TMP0)
1855 gen_op_st_T0_A0(ot + s->mem_index);
1856 else
1857 gen_op_mov_reg_T0(ot, op1);
1858 }
1859
1860 /* XXX: add faster immediate case */
1861 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1862 int is_right)
1863 {
1864 int label1, label2, data_bits;
1865 target_ulong mask;
1866 TCGv t0, t1, t2, a0;
1867
1868 t0 = tcg_temp_local_new();
1869 t1 = tcg_temp_local_new();
1870 t2 = tcg_temp_local_new();
1871 a0 = tcg_temp_local_new();
1872
1873 if (ot == OT_QUAD)
1874 mask = 0x3f;
1875 else
1876 mask = 0x1f;
1877
1878 /* load */
1879 if (op1 == OR_TMP0) {
1880 tcg_gen_mov_tl(a0, cpu_A0);
1881 gen_op_ld_v(ot + s->mem_index, t0, a0);
1882 } else {
1883 gen_op_mov_v_reg(ot, t0, op1);
1884 }
1885
1886 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1887
1888 tcg_gen_mov_tl(t1, cpu_T[1]);
1889 tcg_gen_mov_tl(t2, cpu_T3);
1890
1891 /* Must test zero case to avoid using undefined behaviour in TCG
1892 shifts. */
1893 label1 = gen_new_label();
1894 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1895
1896 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1897 if (ot == OT_WORD) {
1898 /* Note: we implement the Intel behaviour for shift count > 16 */
1899 if (is_right) {
1900 tcg_gen_andi_tl(t0, t0, 0xffff);
1901 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1902 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1903 tcg_gen_ext32u_tl(t0, t0);
1904
1905 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1906
1907 /* only needed if count > 16, but a test would complicate */
1908 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1909 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1910
1911 tcg_gen_shr_tl(t0, t0, t2);
1912
1913 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1914 } else {
1915 /* XXX: not optimal */
1916 tcg_gen_andi_tl(t0, t0, 0xffff);
1917 tcg_gen_shli_tl(t1, t1, 16);
1918 tcg_gen_or_tl(t1, t1, t0);
1919 tcg_gen_ext32u_tl(t1, t1);
1920
1921 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1922 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1923 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1924 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1925
1926 tcg_gen_shl_tl(t0, t0, t2);
1927 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1928 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1929 tcg_gen_or_tl(t0, t0, t1);
1930 }
1931 } else {
1932 data_bits = 8 << ot;
1933 if (is_right) {
1934 if (ot == OT_LONG)
1935 tcg_gen_ext32u_tl(t0, t0);
1936
1937 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1938
1939 tcg_gen_shr_tl(t0, t0, t2);
1940 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1941 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1942 tcg_gen_or_tl(t0, t0, t1);
1943
1944 } else {
1945 if (ot == OT_LONG)
1946 tcg_gen_ext32u_tl(t1, t1);
1947
1948 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1949
1950 tcg_gen_shl_tl(t0, t0, t2);
1951 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1952 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1953 tcg_gen_or_tl(t0, t0, t1);
1954 }
1955 }
1956 tcg_gen_mov_tl(t1, cpu_tmp4);
1957
1958 gen_set_label(label1);
1959 /* store */
1960 if (op1 == OR_TMP0) {
1961 gen_op_st_v(ot + s->mem_index, t0, a0);
1962 } else {
1963 gen_op_mov_reg_v(ot, op1, t0);
1964 }
1965
1966 /* update eflags */
1967 gen_update_cc_op(s);
1968
1969 label2 = gen_new_label();
1970 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1971
1972 tcg_gen_mov_tl(cpu_cc_src, t1);
1973 tcg_gen_mov_tl(cpu_cc_dst, t0);
1974 if (is_right) {
1975 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1976 } else {
1977 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1978 }
1979 gen_set_label(label2);
1980 set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */
1981
1982 tcg_temp_free(t0);
1983 tcg_temp_free(t1);
1984 tcg_temp_free(t2);
1985 tcg_temp_free(a0);
1986 }
1987
1988 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1989 {
1990 if (s != OR_TMP1)
1991 gen_op_mov_TN_reg(ot, 1, s);
1992 switch(op) {
1993 case OP_ROL:
1994 gen_rot_rm_T1(s1, ot, d, 0);
1995 break;
1996 case OP_ROR:
1997 gen_rot_rm_T1(s1, ot, d, 1);
1998 break;
1999 case OP_SHL:
2000 case OP_SHL1:
2001 gen_shift_rm_T1(s1, ot, d, 0, 0);
2002 break;
2003 case OP_SHR:
2004 gen_shift_rm_T1(s1, ot, d, 1, 0);
2005 break;
2006 case OP_SAR:
2007 gen_shift_rm_T1(s1, ot, d, 1, 1);
2008 break;
2009 case OP_RCL:
2010 gen_rotc_rm_T1(s1, ot, d, 0);
2011 break;
2012 case OP_RCR:
2013 gen_rotc_rm_T1(s1, ot, d, 1);
2014 break;
2015 }
2016 }
2017
2018 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
2019 {
2020 switch(op) {
2021 case OP_ROL:
2022 gen_rot_rm_im(s1, ot, d, c, 0);
2023 break;
2024 case OP_ROR:
2025 gen_rot_rm_im(s1, ot, d, c, 1);
2026 break;
2027 case OP_SHL:
2028 case OP_SHL1:
2029 gen_shift_rm_im(s1, ot, d, c, 0, 0);
2030 break;
2031 case OP_SHR:
2032 gen_shift_rm_im(s1, ot, d, c, 1, 0);
2033 break;
2034 case OP_SAR:
2035 gen_shift_rm_im(s1, ot, d, c, 1, 1);
2036 break;
2037 default:
2038 /* currently not optimized */
2039 gen_op_movl_T1_im(c);
2040 gen_shift(s1, op, ot, d, OR_TMP1);
2041 break;
2042 }
2043 }
2044
2045 static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
2046 int *reg_ptr, int *offset_ptr)
2047 {
2048 target_long disp;
2049 int havesib;
2050 int base;
2051 int index;
2052 int scale;
2053 int opreg;
2054 int mod, rm, code, override, must_add_seg;
2055
2056 override = s->override;
2057 must_add_seg = s->addseg;
2058 if (override >= 0)
2059 must_add_seg = 1;
2060 mod = (modrm >> 6) & 3;
2061 rm = modrm & 7;
2062
2063 if (s->aflag) {
2064
2065 havesib = 0;
2066 base = rm;
2067 index = 0;
2068 scale = 0;
2069
2070 if (base == 4) {
2071 havesib = 1;
2072 code = cpu_ldub_code(env, s->pc++);
2073 scale = (code >> 6) & 3;
2074 index = ((code >> 3) & 7) | REX_X(s);
2075 base = (code & 7);
2076 }
2077 base |= REX_B(s);
2078
2079 switch (mod) {
2080 case 0:
2081 if ((base & 7) == 5) {
2082 base = -1;
2083 disp = (int32_t)cpu_ldl_code(env, s->pc);
2084 s->pc += 4;
2085 if (CODE64(s) && !havesib) {
2086 disp += s->pc + s->rip_offset;
2087 }
2088 } else {
2089 disp = 0;
2090 }
2091 break;
2092 case 1:
2093 disp = (int8_t)cpu_ldub_code(env, s->pc++);
2094 break;
2095 default:
2096 case 2:
2097 disp = (int32_t)cpu_ldl_code(env, s->pc);
2098 s->pc += 4;
2099 break;
2100 }
2101
2102 if (base >= 0) {
2103 /* for correct popl handling with esp */
2104 if (base == 4 && s->popl_esp_hack)
2105 disp += s->popl_esp_hack;
2106 #ifdef TARGET_X86_64
2107 if (s->aflag == 2) {
2108 gen_op_movq_A0_reg(base);
2109 if (disp != 0) {
2110 gen_op_addq_A0_im(disp);
2111 }
2112 } else
2113 #endif
2114 {
2115 gen_op_movl_A0_reg(base);
2116 if (disp != 0)
2117 gen_op_addl_A0_im(disp);
2118 }
2119 } else {
2120 #ifdef TARGET_X86_64
2121 if (s->aflag == 2) {
2122 gen_op_movq_A0_im(disp);
2123 } else
2124 #endif
2125 {
2126 gen_op_movl_A0_im(disp);
2127 }
2128 }
2129 /* index == 4 means no index */
2130 if (havesib && (index != 4)) {
2131 #ifdef TARGET_X86_64
2132 if (s->aflag == 2) {
2133 gen_op_addq_A0_reg_sN(scale, index);
2134 } else
2135 #endif
2136 {
2137 gen_op_addl_A0_reg_sN(scale, index);
2138 }
2139 }
2140 if (must_add_seg) {
2141 if (override < 0) {
2142 if (base == R_EBP || base == R_ESP)
2143 override = R_SS;
2144 else
2145 override = R_DS;
2146 }
2147 #ifdef TARGET_X86_64
2148 if (s->aflag == 2) {
2149 gen_op_addq_A0_seg(override);
2150 } else
2151 #endif
2152 {
2153 gen_op_addl_A0_seg(s, override);
2154 }
2155 }
2156 } else {
2157 switch (mod) {
2158 case 0:
2159 if (rm == 6) {
2160 disp = cpu_lduw_code(env, s->pc);
2161 s->pc += 2;
2162 gen_op_movl_A0_im(disp);
2163 rm = 0; /* avoid SS override */
2164 goto no_rm;
2165 } else {
2166 disp = 0;
2167 }
2168 break;
2169 case 1:
2170 disp = (int8_t)cpu_ldub_code(env, s->pc++);
2171 break;
2172 default:
2173 case 2:
2174 disp = cpu_lduw_code(env, s->pc);
2175 s->pc += 2;
2176 break;
2177 }
2178 switch(rm) {
2179 case 0:
2180 gen_op_movl_A0_reg(R_EBX);
2181 gen_op_addl_A0_reg_sN(0, R_ESI);
2182 break;
2183 case 1:
2184 gen_op_movl_A0_reg(R_EBX);
2185 gen_op_addl_A0_reg_sN(0, R_EDI);
2186 break;
2187 case 2:
2188 gen_op_movl_A0_reg(R_EBP);
2189 gen_op_addl_A0_reg_sN(0, R_ESI);
2190 break;
2191 case 3:
2192 gen_op_movl_A0_reg(R_EBP);
2193 gen_op_addl_A0_reg_sN(0, R_EDI);
2194 break;
2195 case 4:
2196 gen_op_movl_A0_reg(R_ESI);
2197 break;
2198 case 5:
2199 gen_op_movl_A0_reg(R_EDI);
2200 break;
2201 case 6:
2202 gen_op_movl_A0_reg(R_EBP);
2203 break;
2204 default:
2205 case 7:
2206 gen_op_movl_A0_reg(R_EBX);
2207 break;
2208 }
2209 if (disp != 0)
2210 gen_op_addl_A0_im(disp);
2211 gen_op_andl_A0_ffff();
2212 no_rm:
2213 if (must_add_seg) {
2214 if (override < 0) {
2215 if (rm == 2 || rm == 3 || rm == 6)
2216 override = R_SS;
2217 else
2218 override = R_DS;
2219 }
2220 gen_op_addl_A0_seg(s, override);
2221 }
2222 }
2223
2224 opreg = OR_A0;
2225 disp = 0;
2226 *reg_ptr = opreg;
2227 *offset_ptr = disp;
2228 }
2229
2230 static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
2231 {
2232 int mod, rm, base, code;
2233
2234 mod = (modrm >> 6) & 3;
2235 if (mod == 3)
2236 return;
2237 rm = modrm & 7;
2238
2239 if (s->aflag) {
2240
2241 base = rm;
2242
2243 if (base == 4) {
2244 code = cpu_ldub_code(env, s->pc++);
2245 base = (code & 7);
2246 }
2247
2248 switch (mod) {
2249 case 0:
2250 if (base == 5) {
2251 s->pc += 4;
2252 }
2253 break;
2254 case 1:
2255 s->pc++;
2256 break;
2257 default:
2258 case 2:
2259 s->pc += 4;
2260 break;
2261 }
2262 } else {
2263 switch (mod) {
2264 case 0:
2265 if (rm == 6) {
2266 s->pc += 2;
2267 }
2268 break;
2269 case 1:
2270 s->pc++;
2271 break;
2272 default:
2273 case 2:
2274 s->pc += 2;
2275 break;
2276 }
2277 }
2278 }
2279
2280 /* used for LEA and MOV AX, mem */
2281 static void gen_add_A0_ds_seg(DisasContext *s)
2282 {
2283 int override, must_add_seg;
2284 must_add_seg = s->addseg;
2285 override = R_DS;
2286 if (s->override >= 0) {
2287 override = s->override;
2288 must_add_seg = 1;
2289 }
2290 if (must_add_seg) {
2291 #ifdef TARGET_X86_64
2292 if (CODE64(s)) {
2293 gen_op_addq_A0_seg(override);
2294 } else
2295 #endif
2296 {
2297 gen_op_addl_A0_seg(s, override);
2298 }
2299 }
2300 }
2301
2302 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2303 OR_TMP0 */
2304 static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
2305 int ot, int reg, int is_store)
2306 {
2307 int mod, rm, opreg, disp;
2308
2309 mod = (modrm >> 6) & 3;
2310 rm = (modrm & 7) | REX_B(s);
2311 if (mod == 3) {
2312 if (is_store) {
2313 if (reg != OR_TMP0)
2314 gen_op_mov_TN_reg(ot, 0, reg);
2315 gen_op_mov_reg_T0(ot, rm);
2316 } else {
2317 gen_op_mov_TN_reg(ot, 0, rm);
2318 if (reg != OR_TMP0)
2319 gen_op_mov_reg_T0(ot, reg);
2320 }
2321 } else {
2322 gen_lea_modrm(env, s, modrm, &opreg, &disp);
2323 if (is_store) {
2324 if (reg != OR_TMP0)
2325 gen_op_mov_TN_reg(ot, 0, reg);
2326 gen_op_st_T0_A0(ot + s->mem_index);
2327 } else {
2328 gen_op_ld_T0_A0(ot + s->mem_index);
2329 if (reg != OR_TMP0)
2330 gen_op_mov_reg_T0(ot, reg);
2331 }
2332 }
2333 }
2334
2335 static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
2336 {
2337 uint32_t ret;
2338
2339 switch(ot) {
2340 case OT_BYTE:
2341 ret = cpu_ldub_code(env, s->pc);
2342 s->pc++;
2343 break;
2344 case OT_WORD:
2345 ret = cpu_lduw_code(env, s->pc);
2346 s->pc += 2;
2347 break;
2348 default:
2349 case OT_LONG:
2350 ret = cpu_ldl_code(env, s->pc);
2351 s->pc += 4;
2352 break;
2353 }
2354 return ret;
2355 }
2356
2357 static inline int insn_const_size(unsigned int ot)
2358 {
2359 if (ot <= OT_LONG)
2360 return 1 << ot;
2361 else
2362 return 4;
2363 }
2364
2365 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2366 {
2367 TranslationBlock *tb;
2368 target_ulong pc;
2369
2370 pc = s->cs_base + eip;
2371 tb = s->tb;
2372 /* NOTE: we handle the case where the TB spans two pages here */
2373 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2374 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2375 /* jump to same page: we can use a direct jump */
2376 tcg_gen_goto_tb(tb_num);
2377 gen_jmp_im(eip);
2378 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2379 } else {
2380 /* jump to another page: currently not optimized */
2381 gen_jmp_im(eip);
2382 gen_eob(s);
2383 }
2384 }
2385
2386 static inline void gen_jcc(DisasContext *s, int b,
2387 target_ulong val, target_ulong next_eip)
2388 {
2389 int l1, l2;
2390
2391 if (s->jmp_opt) {
2392 gen_update_cc_op(s);
2393 l1 = gen_new_label();
2394 gen_jcc1(s, b, l1);
2395 set_cc_op(s, CC_OP_DYNAMIC);
2396
2397 gen_goto_tb(s, 0, next_eip);
2398
2399 gen_set_label(l1);
2400 gen_goto_tb(s, 1, val);
2401 s->is_jmp = DISAS_TB_JUMP;
2402 } else {
2403 l1 = gen_new_label();
2404 l2 = gen_new_label();
2405 gen_jcc1(s, b, l1);
2406
2407 gen_jmp_im(next_eip);
2408 tcg_gen_br(l2);
2409
2410 gen_set_label(l1);
2411 gen_jmp_im(val);
2412 gen_set_label(l2);
2413 gen_eob(s);
2414 }
2415 }
2416
2417 static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b,
2418 int modrm, int reg)
2419 {
2420 CCPrepare cc;
2421
2422 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
2423
2424 cc = gen_prepare_cc(s, b, cpu_T[1]);
2425 if (cc.mask != -1) {
2426 TCGv t0 = tcg_temp_new();
2427 tcg_gen_andi_tl(t0, cc.reg, cc.mask);
2428 cc.reg = t0;
2429 }
2430 if (!cc.use_reg2) {
2431 cc.reg2 = tcg_const_tl(cc.imm);
2432 }
2433
2434 tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
2435 cpu_T[0], cpu_regs[reg]);
2436 gen_op_mov_reg_T0(ot, reg);
2437
2438 if (cc.mask != -1) {
2439 tcg_temp_free(cc.reg);
2440 }
2441 if (!cc.use_reg2) {
2442 tcg_temp_free(cc.reg2);
2443 }
2444 }
2445
2446 static inline void gen_op_movl_T0_seg(int seg_reg)
2447 {
2448 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2449 offsetof(CPUX86State,segs[seg_reg].selector));
2450 }
2451
2452 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2453 {
2454 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2455 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2456 offsetof(CPUX86State,segs[seg_reg].selector));
2457 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2458 tcg_gen_st_tl(cpu_T[0], cpu_env,
2459 offsetof(CPUX86State,segs[seg_reg].base));
2460 }
2461
2462 /* move T0 to seg_reg and compute if the CPU state may change. Never
2463 call this function with seg_reg == R_CS */
2464 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2465 {
2466 if (s->pe && !s->vm86) {
2467 /* XXX: optimize by finding processor state dynamically */
2468 gen_update_cc_op(s);
2469 gen_jmp_im(cur_eip);
2470 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2471 gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2472 /* abort translation because the addseg value may change or
2473 because ss32 may change. For R_SS, translation must always
2474 stop as a special handling must be done to disable hardware
2475 interrupts for the next instruction */
2476 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2477 s->is_jmp = DISAS_TB_JUMP;
2478 } else {
2479 gen_op_movl_seg_T0_vm(seg_reg);
2480 if (seg_reg == R_SS)
2481 s->is_jmp = DISAS_TB_JUMP;
2482 }
2483 }
2484
2485 static inline int svm_is_rep(int prefixes)
2486 {
2487 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2488 }
2489
2490 static inline void
2491 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2492 uint32_t type, uint64_t param)
2493 {
2494 /* no SVM activated; fast case */
2495 if (likely(!(s->flags & HF_SVMI_MASK)))
2496 return;
2497 gen_update_cc_op(s);
2498 gen_jmp_im(pc_start - s->cs_base);
2499 gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type),
2500 tcg_const_i64(param));
2501 }
2502
2503 static inline void
2504 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2505 {
2506 gen_svm_check_intercept_param(s, pc_start, type, 0);
2507 }
2508
2509 static inline void gen_stack_update(DisasContext *s, int addend)
2510 {
2511 #ifdef TARGET_X86_64
2512 if (CODE64(s)) {
2513 gen_op_add_reg_im(2, R_ESP, addend);
2514 } else
2515 #endif
2516 if (s->ss32) {
2517 gen_op_add_reg_im(1, R_ESP, addend);
2518 } else {
2519 gen_op_add_reg_im(0, R_ESP, addend);
2520 }
2521 }
2522
2523 /* generate a push. It depends on ss32, addseg and dflag */
2524 static void gen_push_T0(DisasContext *s)
2525 {
2526 #ifdef TARGET_X86_64
2527 if (CODE64(s)) {
2528 gen_op_movq_A0_reg(R_ESP);
2529 if (s->dflag) {
2530 gen_op_addq_A0_im(-8);
2531 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2532 } else {
2533 gen_op_addq_A0_im(-2);
2534 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2535 }
2536 gen_op_mov_reg_A0(2, R_ESP);
2537 } else
2538 #endif
2539 {
2540 gen_op_movl_A0_reg(R_ESP);
2541 if (!s->dflag)
2542 gen_op_addl_A0_im(-2);
2543 else
2544 gen_op_addl_A0_im(-4);
2545 if (s->ss32) {
2546 if (s->addseg) {
2547 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2548 gen_op_addl_A0_seg(s, R_SS);
2549 }
2550 } else {
2551 gen_op_andl_A0_ffff();
2552 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2553 gen_op_addl_A0_seg(s, R_SS);
2554 }
2555 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2556 if (s->ss32 && !s->addseg)
2557 gen_op_mov_reg_A0(1, R_ESP);
2558 else
2559 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2560 }
2561 }
2562
2563 /* generate a push. It depends on ss32, addseg and dflag */
2564 /* slower version for T1, only used for call Ev */
2565 static void gen_push_T1(DisasContext *s)
2566 {
2567 #ifdef TARGET_X86_64
2568 if (CODE64(s)) {
2569 gen_op_movq_A0_reg(R_ESP);
2570 if (s->dflag) {
2571 gen_op_addq_A0_im(-8);
2572 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2573 } else {
2574 gen_op_addq_A0_im(-2);
2575 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2576 }
2577 gen_op_mov_reg_A0(2, R_ESP);
2578 } else
2579 #endif
2580 {
2581 gen_op_movl_A0_reg(R_ESP);
2582 if (!s->dflag)
2583 gen_op_addl_A0_im(-2);
2584 else
2585 gen_op_addl_A0_im(-4);
2586 if (s->ss32) {
2587 if (s->addseg) {
2588 gen_op_addl_A0_seg(s, R_SS);
2589 }
2590 } else {
2591 gen_op_andl_A0_ffff();
2592 gen_op_addl_A0_seg(s, R_SS);
2593 }
2594 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2595
2596 if (s->ss32 && !s->addseg)
2597 gen_op_mov_reg_A0(1, R_ESP);
2598 else
2599 gen_stack_update(s, (-2) << s->dflag);
2600 }
2601 }
2602
2603 /* two step pop is necessary for precise exceptions */
2604 static void gen_pop_T0(DisasContext *s)
2605 {
2606 #ifdef TARGET_X86_64
2607 if (CODE64(s)) {
2608 gen_op_movq_A0_reg(R_ESP);
2609 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2610 } else
2611 #endif
2612 {
2613 gen_op_movl_A0_reg(R_ESP);
2614 if (s->ss32) {
2615 if (s->addseg)
2616 gen_op_addl_A0_seg(s, R_SS);
2617 } else {
2618 gen_op_andl_A0_ffff();
2619 gen_op_addl_A0_seg(s, R_SS);
2620 }
2621 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2622 }
2623 }
2624
2625 static void gen_pop_update(DisasContext *s)
2626 {
2627 #ifdef TARGET_X86_64
2628 if (CODE64(s) && s->dflag) {
2629 gen_stack_update(s, 8);
2630 } else
2631 #endif
2632 {
2633 gen_stack_update(s, 2 << s->dflag);
2634 }
2635 }
2636
2637 static void gen_stack_A0(DisasContext *s)
2638 {
2639 gen_op_movl_A0_reg(R_ESP);
2640 if (!s->ss32)
2641 gen_op_andl_A0_ffff();
2642 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2643 if (s->addseg)
2644 gen_op_addl_A0_seg(s, R_SS);
2645 }
2646
2647 /* NOTE: wrap around in 16 bit not fully handled */
2648 static void gen_pusha(DisasContext *s)
2649 {
2650 int i;
2651 gen_op_movl_A0_reg(R_ESP);
2652 gen_op_addl_A0_im(-16 << s->dflag);
2653 if (!s->ss32)
2654 gen_op_andl_A0_ffff();
2655 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2656 if (s->addseg)
2657 gen_op_addl_A0_seg(s, R_SS);
2658 for(i = 0;i < 8; i++) {
2659 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2660 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2661 gen_op_addl_A0_im(2 << s->dflag);
2662 }
2663 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2664 }
2665
2666 /* NOTE: wrap around in 16 bit not fully handled */
2667 static void gen_popa(DisasContext *s)
2668 {
2669 int i;
2670 gen_op_movl_A0_reg(R_ESP);
2671 if (!s->ss32)
2672 gen_op_andl_A0_ffff();
2673 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2674 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2675 if (s->addseg)
2676 gen_op_addl_A0_seg(s, R_SS);
2677 for(i = 0;i < 8; i++) {
2678 /* ESP is not reloaded */
2679 if (i != 3) {
2680 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2681 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2682 }
2683 gen_op_addl_A0_im(2 << s->dflag);
2684 }
2685 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2686 }
2687
2688 static void gen_enter(DisasContext *s, int esp_addend, int level)
2689 {
2690 int ot, opsize;
2691
2692 level &= 0x1f;
2693 #ifdef TARGET_X86_64
2694 if (CODE64(s)) {
2695 ot = s->dflag ? OT_QUAD : OT_WORD;
2696 opsize = 1 << ot;
2697
2698 gen_op_movl_A0_reg(R_ESP);
2699 gen_op_addq_A0_im(-opsize);
2700 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2701
2702 /* push bp */
2703 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2704 gen_op_st_T0_A0(ot + s->mem_index);
2705 if (level) {
2706 /* XXX: must save state */
2707 gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
2708 tcg_const_i32((ot == OT_QUAD)),
2709 cpu_T[1]);
2710 }
2711 gen_op_mov_reg_T1(ot, R_EBP);
2712 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2713 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2714 } else
2715 #endif
2716 {
2717 ot = s->dflag + OT_WORD;
2718 opsize = 2 << s->dflag;
2719
2720 gen_op_movl_A0_reg(R_ESP);
2721 gen_op_addl_A0_im(-opsize);
2722 if (!s->ss32)
2723 gen_op_andl_A0_ffff();
2724 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2725 if (s->addseg)
2726 gen_op_addl_A0_seg(s, R_SS);
2727 /* push bp */
2728 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2729 gen_op_st_T0_A0(ot + s->mem_index);
2730 if (level) {
2731 /* XXX: must save state */
2732 gen_helper_enter_level(cpu_env, tcg_const_i32(level),
2733 tcg_const_i32(s->dflag),
2734 cpu_T[1]);
2735 }
2736 gen_op_mov_reg_T1(ot, R_EBP);
2737 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2738 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2739 }
2740 }
2741
2742 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2743 {
2744 gen_update_cc_op(s);
2745 gen_jmp_im(cur_eip);
2746 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2747 s->is_jmp = DISAS_TB_JUMP;
2748 }
2749
2750 /* an interrupt is different from an exception because of the
2751 privilege checks */
2752 static void gen_interrupt(DisasContext *s, int intno,
2753 target_ulong cur_eip, target_ulong next_eip)
2754 {
2755 gen_update_cc_op(s);
2756 gen_jmp_im(cur_eip);
2757 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2758 tcg_const_i32(next_eip - cur_eip));
2759 s->is_jmp = DISAS_TB_JUMP;
2760 }
2761
2762 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2763 {
2764 gen_update_cc_op(s);
2765 gen_jmp_im(cur_eip);
2766 gen_helper_debug(cpu_env);
2767 s->is_jmp = DISAS_TB_JUMP;
2768 }
2769
2770 /* generate a generic end of block. Trace exception is also generated
2771 if needed */
2772 static void gen_eob(DisasContext *s)
2773 {
2774 gen_update_cc_op(s);
2775 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2776 gen_helper_reset_inhibit_irq(cpu_env);
2777 }
2778 if (s->tb->flags & HF_RF_MASK) {
2779 gen_helper_reset_rf(cpu_env);
2780 }
2781 if (s->singlestep_enabled) {
2782 gen_helper_debug(cpu_env);
2783 } else if (s->tf) {
2784 gen_helper_single_step(cpu_env);
2785 } else {
2786 tcg_gen_exit_tb(0);
2787 }
2788 s->is_jmp = DISAS_TB_JUMP;
2789 }
2790
2791 /* generate a jump to eip. No segment change must happen before as a
2792 direct call to the next block may occur */
2793 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2794 {
2795 if (s->jmp_opt) {
2796 gen_update_cc_op(s);
2797 gen_goto_tb(s, tb_num, eip);
2798 s->is_jmp = DISAS_TB_JUMP;
2799 } else {
2800 gen_jmp_im(eip);
2801 gen_eob(s);
2802 }
2803 }
2804
2805 static void gen_jmp(DisasContext *s, target_ulong eip)
2806 {
2807 gen_jmp_tb(s, eip, 0);
2808 }
2809
2810 static inline void gen_ldq_env_A0(int idx, int offset)
2811 {
2812 int mem_index = (idx >> 2) - 1;
2813 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2814 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2815 }
2816
2817 static inline void gen_stq_env_A0(int idx, int offset)
2818 {
2819 int mem_index = (idx >> 2) - 1;
2820 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2821 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2822 }
2823
2824 static inline void gen_ldo_env_A0(int idx, int offset)
2825 {
2826 int mem_index = (idx >> 2) - 1;
2827 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2828 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2829 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2830 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2831 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2832 }
2833
2834 static inline void gen_sto_env_A0(int idx, int offset)
2835 {
2836 int mem_index = (idx >> 2) - 1;
2837 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2838 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2839 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2840 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2841 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2842 }
2843
2844 static inline void gen_op_movo(int d_offset, int s_offset)
2845 {
2846 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2847 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2848 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2849 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2850 }
2851
2852 static inline void gen_op_movq(int d_offset, int s_offset)
2853 {
2854 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2855 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2856 }
2857
2858 static inline void gen_op_movl(int d_offset, int s_offset)
2859 {
2860 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2861 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2862 }
2863
2864 static inline void gen_op_movq_env_0(int d_offset)
2865 {
2866 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2867 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2868 }
2869
2870 typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
2871 typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
2872 typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val);
2873 typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
2874 typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
2875 typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2876 TCGv_i32 val);
2877 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2878 typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2879 TCGv val);
2880
2881 #define SSE_SPECIAL ((void *)1)
2882 #define SSE_DUMMY ((void *)2)
2883
2884 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2885 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2886 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2887
2888 static const SSEFunc_0_epp sse_op_table1[256][4] = {
2889 /* 3DNow! extensions */
2890 [0x0e] = { SSE_DUMMY }, /* femms */
2891 [0x0f] = { SSE_DUMMY }, /* pf... */
2892 /* pure SSE operations */
2893 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2894 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2895 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2896 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2897 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2898 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2899 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2900 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2901
2902 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2903 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2904 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2905 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2906 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2907 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2908 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2909 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2910 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2911 [0x51] = SSE_FOP(sqrt),
2912 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2913 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2914 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2915 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2916 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2917 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2918 [0x58] = SSE_FOP(add),
2919 [0x59] = SSE_FOP(mul),
2920 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2921 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2922 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2923 [0x5c] = SSE_FOP(sub),
2924 [0x5d] = SSE_FOP(min),
2925 [0x5e] = SSE_FOP(div),
2926 [0x5f] = SSE_FOP(max),
2927
2928 [0xc2] = SSE_FOP(cmpeq),
2929 [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
2930 (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
2931
2932 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2933 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2934
2935 /* MMX ops and their SSE extensions */
2936 [0x60] = MMX_OP2(punpcklbw),
2937 [0x61] = MMX_OP2(punpcklwd),
2938 [0x62] = MMX_OP2(punpckldq),
2939 [0x63] = MMX_OP2(packsswb),
2940 [0x64] = MMX_OP2(pcmpgtb),
2941 [0x65] = MMX_OP2(pcmpgtw),
2942 [0x66] = MMX_OP2(pcmpgtl),
2943 [0x67] = MMX_OP2(packuswb),
2944 [0x68] = MMX_OP2(punpckhbw),
2945 [0x69] = MMX_OP2(punpckhwd),
2946 [0x6a] = MMX_OP2(punpckhdq),
2947 [0x6b] = MMX_OP2(packssdw),
2948 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2949 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2950 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2951 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2952 [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx,
2953 (SSEFunc_0_epp)gen_helper_pshufd_xmm,
2954 (SSEFunc_0_epp)gen_helper_pshufhw_xmm,
2955 (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2956 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2957 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2958 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2959 [0x74] = MMX_OP2(pcmpeqb),
2960 [0x75] = MMX_OP2(pcmpeqw),
2961 [0x76] = MMX_OP2(pcmpeql),
2962 [0x77] = { SSE_DUMMY }, /* emms */
2963 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2964 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2965 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2966 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2967 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2968 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2969 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2970 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2971 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2972 [0xd1] = MMX_OP2(psrlw),
2973 [0xd2] = MMX_OP2(psrld),
2974 [0xd3] = MMX_OP2(psrlq),
2975 [0xd4] = MMX_OP2(paddq),
2976 [0xd5] = MMX_OP2(pmullw),
2977 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2978 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2979 [0xd8] = MMX_OP2(psubusb),
2980 [0xd9] = MMX_OP2(psubusw),
2981 [0xda] = MMX_OP2(pminub),
2982 [0xdb] = MMX_OP2(pand),
2983 [0xdc] = MMX_OP2(paddusb),
2984 [0xdd] = MMX_OP2(paddusw),
2985 [0xde] = MMX_OP2(pmaxub),
2986 [0xdf] = MMX_OP2(pandn),
2987 [0xe0] = MMX_OP2(pavgb),
2988 [0xe1] = MMX_OP2(psraw),
2989 [0xe2] = MMX_OP2(psrad),
2990 [0xe3] = MMX_OP2(pavgw),
2991 [0xe4] = MMX_OP2(pmulhuw),
2992 [0xe5] = MMX_OP2(pmulhw),
2993 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2994 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2995 [0xe8] = MMX_OP2(psubsb),
2996 [0xe9] = MMX_OP2(psubsw),
2997 [0xea] = MMX_OP2(pminsw),
2998 [0xeb] = MMX_OP2(por),
2999 [0xec] = MMX_OP2(paddsb),
3000 [0xed] = MMX_OP2(paddsw),
3001 [0xee] = MMX_OP2(pmaxsw),
3002 [0xef] = MMX_OP2(pxor),
3003 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
3004 [0xf1] = MMX_OP2(psllw),
3005 [0xf2] = MMX_OP2(pslld),
3006 [0xf3] = MMX_OP2(psllq),
3007 [0xf4] = MMX_OP2(pmuludq),
3008 [0xf5] = MMX_OP2(pmaddwd),
3009 [0xf6] = MMX_OP2(psadbw),
3010 [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx,
3011 (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */
3012 [0xf8] = MMX_OP2(psubb),
3013 [0xf9] = MMX_OP2(psubw),
3014 [0xfa] = MMX_OP2(psubl),
3015 [0xfb] = MMX_OP2(psubq),
3016 [0xfc] = MMX_OP2(paddb),
3017 [0xfd] = MMX_OP2(paddw),
3018 [0xfe] = MMX_OP2(paddl),
3019 };
3020
3021 static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
3022 [0 + 2] = MMX_OP2(psrlw),
3023 [0 + 4] = MMX_OP2(psraw),
3024 [0 + 6] = MMX_OP2(psllw),
3025 [8 + 2] = MMX_OP2(psrld),
3026 [8 + 4] = MMX_OP2(psrad),
3027 [8 + 6] = MMX_OP2(pslld),
3028 [16 + 2] = MMX_OP2(psrlq),
3029 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
3030 [16 + 6] = MMX_OP2(psllq),
3031 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
3032 };
3033
3034 static const SSEFunc_0_epi sse_op_table3ai[] = {
3035 gen_helper_cvtsi2ss,
3036 gen_helper_cvtsi2sd
3037 };
3038
3039 #ifdef TARGET_X86_64
3040 static const SSEFunc_0_epl sse_op_table3aq[] = {
3041 gen_helper_cvtsq2ss,
3042 gen_helper_cvtsq2sd
3043 };
3044 #endif
3045
3046 static const SSEFunc_i_ep sse_op_table3bi[] = {
3047 gen_helper_cvttss2si,
3048 gen_helper_cvtss2si,
3049 gen_helper_cvttsd2si,
3050 gen_helper_cvtsd2si
3051 };
3052
3053 #ifdef TARGET_X86_64
3054 static const SSEFunc_l_ep sse_op_table3bq[] = {
3055 gen_helper_cvttss2sq,
3056 gen_helper_cvtss2sq,
3057 gen_helper_cvttsd2sq,
3058 gen_helper_cvtsd2sq
3059 };
3060 #endif
3061
3062 static const SSEFunc_0_epp sse_op_table4[8][4] = {
3063 SSE_FOP(cmpeq),
3064 SSE_FOP(cmplt),
3065 SSE_FOP(cmple),
3066 SSE_FOP(cmpunord),
3067 SSE_FOP(cmpneq),
3068 SSE_FOP(cmpnlt),
3069 SSE_FOP(cmpnle),
3070 SSE_FOP(cmpord),
3071 };
3072
3073 static const SSEFunc_0_epp sse_op_table5[256] = {
3074 [0x0c] = gen_helper_pi2fw,
3075 [0x0d] = gen_helper_pi2fd,
3076 [0x1c] = gen_helper_pf2iw,
3077 [0x1d] = gen_helper_pf2id,
3078 [0x8a] = gen_helper_pfnacc,
3079 [0x8e] = gen_helper_pfpnacc,
3080 [0x90] = gen_helper_pfcmpge,
3081 [0x94] = gen_helper_pfmin,
3082 [0x96] = gen_helper_pfrcp,
3083 [0x97] = gen_helper_pfrsqrt,
3084 [0x9a] = gen_helper_pfsub,
3085 [0x9e] = gen_helper_pfadd,
3086 [0xa0] = gen_helper_pfcmpgt,
3087 [0xa4] = gen_helper_pfmax,
3088 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3089 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3090 [0xaa] = gen_helper_pfsubr,
3091 [0xae] = gen_helper_pfacc,
3092 [0xb0] = gen_helper_pfcmpeq,
3093 [0xb4] = gen_helper_pfmul,
3094 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3095 [0xb7] = gen_helper_pmulhrw_mmx,
3096 [0xbb] = gen_helper_pswapd,
3097 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3098 };
3099
3100 struct SSEOpHelper_epp {
3101 SSEFunc_0_epp op[2];
3102 uint32_t ext_mask;
3103 };
3104
3105 struct SSEOpHelper_eppi {
3106 SSEFunc_0_eppi op[2];
3107 uint32_t ext_mask;
3108 };
3109
3110 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3111 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3112 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3113 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3114
3115 static const struct SSEOpHelper_epp sse_op_table6[256] = {
3116 [0x00] = SSSE3_OP(pshufb),
3117 [0x01] = SSSE3_OP(phaddw),
3118 [0x02] = SSSE3_OP(phaddd),
3119 [0x03] = SSSE3_OP(phaddsw),
3120 [0x04] = SSSE3_OP(pmaddubsw),
3121 [0x05] = SSSE3_OP(phsubw),
3122 [0x06] = SSSE3_OP(phsubd),
3123 [0x07] = SSSE3_OP(phsubsw),
3124 [0x08] = SSSE3_OP(psignb),
3125 [0x09] = SSSE3_OP(psignw),
3126 [0x0a] = SSSE3_OP(psignd),
3127 [0x0b] = SSSE3_OP(pmulhrsw),
3128 [0x10] = SSE41_OP(pblendvb),
3129 [0x14] = SSE41_OP(blendvps),
3130 [0x15] = SSE41_OP(blendvpd),
3131 [0x17] = SSE41_OP(ptest),
3132 [0x1c] = SSSE3_OP(pabsb),
3133 [0x1d] = SSSE3_OP(pabsw),
3134 [0x1e] = SSSE3_OP(pabsd),
3135 [0x20] = SSE41_OP(pmovsxbw),
3136 [0x21] = SSE41_OP(pmovsxbd),
3137 [0x22] = SSE41_OP(pmovsxbq),
3138 [0x23] = SSE41_OP(pmovsxwd),
3139 [0x24] = SSE41_OP(pmovsxwq),
3140 [0x25] = SSE41_OP(pmovsxdq),
3141 [0x28] = SSE41_OP(pmuldq),
3142 [0x29] = SSE41_OP(pcmpeqq),
3143 [0x2a] = SSE41_SPECIAL, /* movntqda */
3144 [0x2b] = SSE41_OP(packusdw),
3145 [0x30] = SSE41_OP(pmovzxbw),
3146 [0x31] = SSE41_OP(pmovzxbd),
3147 [0x32] = SSE41_OP(pmovzxbq),
3148 [0x33] = SSE41_OP(pmovzxwd),
3149 [0x34] = SSE41_OP(pmovzxwq),
3150 [0x35] = SSE41_OP(pmovzxdq),
3151 [0x37] = SSE42_OP(pcmpgtq),
3152 [0x38] = SSE41_OP(pminsb),
3153 [0x39] = SSE41_OP(pminsd),
3154 [0x3a] = SSE41_OP(pminuw),
3155 [0x3b] = SSE41_OP(pminud),
3156 [0x3c] = SSE41_OP(pmaxsb),
3157 [0x3d] = SSE41_OP(pmaxsd),
3158 [0x3e] = SSE41_OP(pmaxuw),
3159 [0x3f] = SSE41_OP(pmaxud),
3160 [0x40] = SSE41_OP(pmulld),
3161 [0x41] = SSE41_OP(phminposuw),
3162 };
3163
3164 static const struct SSEOpHelper_eppi sse_op_table7[256] = {
3165 [0x08] = SSE41_OP(roundps),
3166 [0x09] = SSE41_OP(roundpd),
3167 [0x0a] = SSE41_OP(roundss),
3168 [0x0b] = SSE41_OP(roundsd),
3169 [0x0c] = SSE41_OP(blendps),
3170 [0x0d] = SSE41_OP(blendpd),
3171 [0x0e] = SSE41_OP(pblendw),
3172 [0x0f] = SSSE3_OP(palignr),
3173 [0x14] = SSE41_SPECIAL, /* pextrb */
3174 [0x15] = SSE41_SPECIAL, /* pextrw */
3175 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3176 [0x17] = SSE41_SPECIAL, /* extractps */
3177 [0x20] = SSE41_SPECIAL, /* pinsrb */
3178 [0x21] = SSE41_SPECIAL, /* insertps */
3179 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3180 [0x40] = SSE41_OP(dpps),
3181 [0x41] = SSE41_OP(dppd),
3182 [0x42] = SSE41_OP(mpsadbw),
3183 [0x60] = SSE42_OP(pcmpestrm),
3184 [0x61] = SSE42_OP(pcmpestri),
3185 [0x62] = SSE42_OP(pcmpistrm),
3186 [0x63] = SSE42_OP(pcmpistri),
3187 };
3188
3189 static void gen_sse(CPUX86State *env, DisasContext *s, int b,
3190 target_ulong pc_start, int rex_r)
3191 {
3192 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3193 int modrm, mod, rm, reg, reg_addr, offset_addr;
3194 SSEFunc_0_epp sse_fn_epp;
3195 SSEFunc_0_eppi sse_fn_eppi;
3196 SSEFunc_0_ppi sse_fn_ppi;
3197 SSEFunc_0_eppt sse_fn_eppt;
3198
3199 b &= 0xff;
3200 if (s->prefix & PREFIX_DATA)
3201 b1 = 1;
3202 else if (s->prefix & PREFIX_REPZ)
3203 b1 = 2;
3204 else if (s->prefix & PREFIX_REPNZ)
3205 b1 = 3;
3206 else
3207 b1 = 0;
3208 sse_fn_epp = sse_op_table1[b][b1];
3209 if (!sse_fn_epp) {
3210 goto illegal_op;
3211 }
3212 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3213 is_xmm = 1;
3214 } else {
3215 if (b1 == 0) {
3216 /* MMX case */
3217 is_xmm = 0;
3218 } else {
3219 is_xmm = 1;
3220 }
3221 }
3222 /* simple MMX/SSE operation */
3223 if (s->flags & HF_TS_MASK) {
3224 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3225 return;
3226 }
3227 if (s->flags & HF_EM_MASK) {
3228 illegal_op:
3229 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3230 return;
3231 }
3232 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3233 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3234 goto illegal_op;
3235 if (b == 0x0e) {
3236 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3237 goto illegal_op;
3238 /* femms */
3239 gen_helper_emms(cpu_env);
3240 return;
3241 }
3242 if (b == 0x77) {
3243 /* emms */
3244 gen_helper_emms(cpu_env);
3245 return;
3246 }
3247 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3248 the static cpu state) */
3249 if (!is_xmm) {
3250 gen_helper_enter_mmx(cpu_env);
3251 }
3252
3253 modrm = cpu_ldub_code(env, s->pc++);
3254 reg = ((modrm >> 3) & 7);
3255 if (is_xmm)
3256 reg |= rex_r;
3257 mod = (modrm >> 6) & 3;
3258 if (sse_fn_epp == SSE_SPECIAL) {
3259 b |= (b1 << 8);
3260 switch(b) {
3261 case 0x0e7: /* movntq */
3262 if (mod == 3)
3263 goto illegal_op;
3264 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3265 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3266 break;
3267 case 0x1e7: /* movntdq */
3268 case 0x02b: /* movntps */
3269 case 0x12b: /* movntps */
3270 if (mod == 3)
3271 goto illegal_op;
3272 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3273 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3274 break;
3275 case 0x3f0: /* lddqu */
3276 if (mod == 3)
3277 goto illegal_op;
3278 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3279 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3280 break;
3281 case 0x22b: /* movntss */
3282 case 0x32b: /* movntsd */
3283 if (mod == 3)
3284 goto illegal_op;
3285 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3286 if (b1 & 1) {
3287 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3288 xmm_regs[reg]));
3289 } else {
3290 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3291 xmm_regs[reg].XMM_L(0)));
3292 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3293 }
3294 break;
3295 case 0x6e: /* movd mm, ea */
3296 #ifdef TARGET_X86_64
3297 if (s->dflag == 2) {
3298 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
3299 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3300 } else
3301 #endif
3302 {
3303 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
3304 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3305 offsetof(CPUX86State,fpregs[reg].mmx));
3306 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3307 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3308 }
3309 break;
3310 case 0x16e: /* movd xmm, ea */
3311 #ifdef TARGET_X86_64
3312 if (s->dflag == 2) {
3313 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
3314 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3315 offsetof(CPUX86State,xmm_regs[reg]));
3316 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3317 } else
3318 #endif
3319 {
3320 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
3321 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3322 offsetof(CPUX86State,xmm_regs[reg]));
3323 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3324 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3325 }
3326 break;
3327 case 0x6f: /* movq mm, ea */
3328 if (mod != 3) {
3329 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3330 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3331 } else {
3332 rm = (modrm & 7);
3333 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3334 offsetof(CPUX86State,fpregs[rm].mmx));
3335 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3336 offsetof(CPUX86State,fpregs[reg].mmx));
3337 }
3338 break;
3339 case 0x010: /* movups */
3340 case 0x110: /* movupd */
3341 case 0x028: /* movaps */
3342 case 0x128: /* movapd */
3343 case 0x16f: /* movdqa xmm, ea */
3344 case 0x26f: /* movdqu xmm, ea */
3345 if (mod != 3) {
3346 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3347 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3348 } else {
3349 rm = (modrm & 7) | REX_B(s);
3350 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3351 offsetof(CPUX86State,xmm_regs[rm]));
3352 }
3353 break;
3354 case 0x210: /* movss xmm, ea */
3355 if (mod != 3) {
3356 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3357 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3358 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3359 gen_op_movl_T0_0();
3360 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3361 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3362 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3363 } else {
3364 rm = (modrm & 7) | REX_B(s);
3365 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3366 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3367 }
3368 break;
3369 case 0x310: /* movsd xmm, ea */
3370 if (mod != 3) {
3371 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3372 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3373 gen_op_movl_T0_0();
3374 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3375 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3376 } else {
3377 rm = (modrm & 7) | REX_B(s);
3378 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3379 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3380 }
3381 break;
3382 case 0x012: /* movlps */
3383 case 0x112: /* movlpd */
3384 if (mod != 3) {
3385 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3386 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3387 } else {
3388 /* movhlps */
3389 rm = (modrm & 7) | REX_B(s);
3390 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3391 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3392 }
3393 break;
3394 case 0x212: /* movsldup */
3395 if (mod != 3) {
3396 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3397 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3398 } else {
3399 rm = (modrm & 7) | REX_B(s);
3400 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3401 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3402 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3403 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3404 }
3405 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3406 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3407 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3408 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3409 break;
3410 case 0x312: /* movddup */
3411 if (mod != 3) {
3412 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3413 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3414 } else {
3415 rm = (modrm & 7) | REX_B(s);
3416 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3417 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3418 }
3419 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3420 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3421 break;
3422 case 0x016: /* movhps */
3423 case 0x116: /* movhpd */
3424 if (mod != 3) {
3425 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3426 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3427 } else {
3428 /* movlhps */
3429 rm = (modrm & 7) | REX_B(s);
3430 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3431 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3432 }
3433 break;
3434 case 0x216: /* movshdup */
3435 if (mod != 3) {
3436 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3437 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3438 } else {
3439 rm = (modrm & 7) | REX_B(s);
3440 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3441 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3442 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3443 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3444 }
3445 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3446 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3447 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3448 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3449 break;
3450 case 0x178:
3451 case 0x378:
3452 {
3453 int bit_index, field_length;
3454
3455 if (b1 == 1 && reg != 0)
3456 goto illegal_op;
3457 field_length = cpu_ldub_code(env, s->pc++) & 0x3F;
3458 bit_index = cpu_ldub_code(env, s->pc++) & 0x3F;
3459 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3460 offsetof(CPUX86State,xmm_regs[reg]));
3461 if (b1 == 1)
3462 gen_helper_extrq_i(cpu_env, cpu_ptr0,
3463 tcg_const_i32(bit_index),
3464 tcg_const_i32(field_length));
3465 else
3466 gen_helper_insertq_i(cpu_env, cpu_ptr0,
3467 tcg_const_i32(bit_index),
3468 tcg_const_i32(field_length));
3469 }
3470 break;
3471 case 0x7e: /* movd ea, mm */
3472 #ifdef TARGET_X86_64
3473 if (s->dflag == 2) {
3474 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3475 offsetof(CPUX86State,fpregs[reg].mmx));
3476 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
3477 } else
3478 #endif
3479 {
3480 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3481 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3482 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
3483 }
3484 break;
3485 case 0x17e: /* movd ea, xmm */
3486 #ifdef TARGET_X86_64
3487 if (s->dflag == 2) {
3488 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3489 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3490 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
3491 } else
3492 #endif
3493 {
3494 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3495 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3496 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
3497 }
3498 break;
3499 case 0x27e: /* movq xmm, ea */
3500 if (mod != 3) {
3501 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3502 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3503 } else {
3504 rm = (modrm & 7) | REX_B(s);
3505 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3506 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3507 }
3508 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3509 break;
3510 case 0x7f: /* movq ea, mm */
3511 if (mod != 3) {
3512 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3513 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3514 } else {
3515 rm = (modrm & 7);
3516 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3517 offsetof(CPUX86State,fpregs[reg].mmx));
3518 }
3519 break;
3520 case 0x011: /* movups */
3521 case 0x111: /* movupd */
3522 case 0x029: /* movaps */
3523 case 0x129: /* movapd */
3524 case 0x17f: /* movdqa ea, xmm */
3525 case 0x27f: /* movdqu ea, xmm */
3526 if (mod != 3) {
3527 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3528 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3529 } else {
3530 rm = (modrm & 7) | REX_B(s);
3531 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3532 offsetof(CPUX86State,xmm_regs[reg]));
3533 }
3534 break;
3535 case 0x211: /* movss ea, xmm */
3536 if (mod != 3) {
3537 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3538 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3539 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3540 } else {
3541 rm = (modrm & 7) | REX_B(s);
3542 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3543 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3544 }
3545 break;
3546 case 0x311: /* movsd ea, xmm */
3547 if (mod != 3) {
3548 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3549 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3550 } else {
3551 rm = (modrm & 7) | REX_B(s);
3552 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3553 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3554 }
3555 break;
3556 case 0x013: /* movlps */
3557 case 0x113: /* movlpd */
3558 if (mod != 3) {
3559 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3560 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3561 } else {
3562 goto illegal_op;
3563 }
3564 break;
3565 case 0x017: /* movhps */
3566 case 0x117: /* movhpd */
3567 if (mod != 3) {
3568 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3569 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3570 } else {
3571 goto illegal_op;
3572 }
3573 break;
3574 case 0x71: /* shift mm, im */
3575 case 0x72:
3576 case 0x73:
3577 case 0x171: /* shift xmm, im */
3578 case 0x172:
3579 case 0x173:
3580 if (b1 >= 2) {
3581 goto illegal_op;
3582 }
3583 val = cpu_ldub_code(env, s->pc++);
3584 if (is_xmm) {
3585 gen_op_movl_T0_im(val);
3586 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3587 gen_op_movl_T0_0();
3588 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3589 op1_offset = offsetof(CPUX86State,xmm_t0);
3590 } else {
3591 gen_op_movl_T0_im(val);
3592 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3593 gen_op_movl_T0_0();
3594 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3595 op1_offset = offsetof(CPUX86State,mmx_t0);
3596 }
3597 sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
3598 (((modrm >> 3)) & 7)][b1];
3599 if (!sse_fn_epp) {
3600 goto illegal_op;
3601 }
3602 if (is_xmm) {
3603 rm = (modrm & 7) | REX_B(s);
3604 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3605 } else {
3606 rm = (modrm & 7);
3607 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3608 }
3609 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3610 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3611 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3612 break;
3613 case 0x050: /* movmskps */
3614 rm = (modrm & 7) | REX_B(s);
3615 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3616 offsetof(CPUX86State,xmm_regs[rm]));
3617 gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3618 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3619 gen_op_mov_reg_T0(OT_LONG, reg);
3620 break;
3621 case 0x150: /* movmskpd */
3622 rm = (modrm & 7) | REX_B(s);
3623 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3624 offsetof(CPUX86State,xmm_regs[rm]));
3625 gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3626 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3627 gen_op_mov_reg_T0(OT_LONG, reg);
3628 break;
3629 case 0x02a: /* cvtpi2ps */
3630 case 0x12a: /* cvtpi2pd */
3631 gen_helper_enter_mmx(cpu_env);
3632 if (mod != 3) {
3633 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3634 op2_offset = offsetof(CPUX86State,mmx_t0);
3635 gen_ldq_env_A0(s->mem_index, op2_offset);
3636 } else {
3637 rm = (modrm & 7);
3638 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3639 }
3640 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3641 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3642 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3643 switch(b >> 8) {
3644 case 0x0:
3645 gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1);
3646 break;
3647 default:
3648 case 0x1:
3649 gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1);
3650 break;
3651 }
3652 break;
3653 case 0x22a: /* cvtsi2ss */
3654 case 0x32a: /* cvtsi2sd */
3655 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3656 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3657 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3658 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3659 if (ot == OT_LONG) {
3660 SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
3661 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3662 sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
3663 } else {
3664 #ifdef TARGET_X86_64
3665 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
3666 sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
3667 #else
3668 goto illegal_op;
3669 #endif
3670 }
3671 break;
3672 case 0x02c: /* cvttps2pi */
3673 case 0x12c: /* cvttpd2pi */
3674 case 0x02d: /* cvtps2pi */
3675 case 0x12d: /* cvtpd2pi */
3676 gen_helper_enter_mmx(cpu_env);
3677 if (mod != 3) {
3678 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3679 op2_offset = offsetof(CPUX86State,xmm_t0);
3680 gen_ldo_env_A0(s->mem_index, op2_offset);
3681 } else {
3682 rm = (modrm & 7) | REX_B(s);
3683 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3684 }
3685 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3686 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3687 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3688 switch(b) {
3689 case 0x02c:
3690 gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3691 break;
3692 case 0x12c:
3693 gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3694 break;
3695 case 0x02d:
3696 gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3697 break;
3698 case 0x12d:
3699 gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3700 break;
3701 }
3702 break;
3703 case 0x22c: /* cvttss2si */
3704 case 0x32c: /* cvttsd2si */
3705 case 0x22d: /* cvtss2si */
3706 case 0x32d: /* cvtsd2si */
3707 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3708 if (mod != 3) {
3709 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3710 if ((b >> 8) & 1) {
3711 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3712 } else {
3713 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3714 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3715 }
3716 op2_offset = offsetof(CPUX86State,xmm_t0);
3717 } else {
3718 rm = (modrm & 7) | REX_B(s);
3719 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3720 }
3721 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3722 if (ot == OT_LONG) {
3723 SSEFunc_i_ep sse_fn_i_ep =
3724 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3725 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3726 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3727 } else {
3728 #ifdef TARGET_X86_64
3729 SSEFunc_l_ep sse_fn_l_ep =
3730 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3731 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3732 #else
3733 goto illegal_op;
3734 #endif
3735 }
3736 gen_op_mov_reg_T0(ot, reg);
3737 break;
3738 case 0xc4: /* pinsrw */
3739 case 0x1c4:
3740 s->rip_offset = 1;
3741 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
3742 val = cpu_ldub_code(env, s->pc++);
3743 if (b1) {
3744 val &= 7;
3745 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3746 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3747 } else {
3748 val &= 3;
3749 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3750 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3751 }
3752 break;
3753 case 0xc5: /* pextrw */
3754 case 0x1c5:
3755 if (mod != 3)
3756 goto illegal_op;
3757 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3758 val = cpu_ldub_code(env, s->pc++);
3759 if (b1) {
3760 val &= 7;
3761 rm = (modrm & 7) | REX_B(s);
3762 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3763 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3764 } else {
3765 val &= 3;
3766 rm = (modrm & 7);
3767 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3768 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3769 }
3770 reg = ((modrm >> 3) & 7) | rex_r;
3771 gen_op_mov_reg_T0(ot, reg);
3772 break;
3773 case 0x1d6: /* movq ea, xmm */
3774 if (mod != 3) {
3775 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3776 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3777 } else {
3778 rm = (modrm & 7) | REX_B(s);
3779 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3780 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3781 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3782 }
3783 break;
3784 case 0x2d6: /* movq2dq */
3785 gen_helper_enter_mmx(cpu_env);
3786 rm = (modrm & 7);
3787 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3788 offsetof(CPUX86State,fpregs[rm].mmx));
3789 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3790 break;
3791 case 0x3d6: /* movdq2q */
3792 gen_helper_enter_mmx(cpu_env);
3793 rm = (modrm & 7) | REX_B(s);
3794 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3795 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3796 break;
3797 case 0xd7: /* pmovmskb */
3798 case 0x1d7:
3799 if (mod != 3)
3800 goto illegal_op;
3801 if (b1) {
3802 rm = (modrm & 7) | REX_B(s);
3803 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3804 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3805 } else {
3806 rm = (modrm & 7);
3807 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3808 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3809 }
3810 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3811 reg = ((modrm >> 3) & 7) | rex_r;
3812 gen_op_mov_reg_T0(OT_LONG, reg);
3813 break;
3814 case 0x138:
3815 if (s->prefix & PREFIX_REPNZ)
3816 goto crc32;
3817 case 0x038:
3818 b = modrm;
3819 modrm = cpu_ldub_code(env, s->pc++);
3820 rm = modrm & 7;
3821 reg = ((modrm >> 3) & 7) | rex_r;
3822 mod = (modrm >> 6) & 3;
3823 if (b1 >= 2) {
3824 goto illegal_op;
3825 }
3826
3827 sse_fn_epp = sse_op_table6[b].op[b1];
3828 if (!sse_fn_epp) {
3829 goto illegal_op;
3830 }
3831 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3832 goto illegal_op;
3833
3834 if (b1) {
3835 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3836 if (mod == 3) {
3837 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3838 } else {
3839 op2_offset = offsetof(CPUX86State,xmm_t0);
3840 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3841 switch (b) {
3842 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3843 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3844 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3845 gen_ldq_env_A0(s->mem_index, op2_offset +
3846 offsetof(XMMReg, XMM_Q(0)));
3847 break;
3848 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3849 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3850 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3851 (s->mem_index >> 2) - 1);
3852 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3853 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3854 offsetof(XMMReg, XMM_L(0)));
3855 break;
3856 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3857 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3858 (s->mem_index >> 2) - 1);
3859 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3860 offsetof(XMMReg, XMM_W(0)));
3861 break;
3862 case 0x2a: /* movntqda */
3863 gen_ldo_env_A0(s->mem_index, op1_offset);
3864 return;
3865 default:
3866 gen_ldo_env_A0(s->mem_index, op2_offset);
3867 }
3868 }
3869 } else {
3870 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3871 if (mod == 3) {
3872 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3873 } else {
3874 op2_offset = offsetof(CPUX86State,mmx_t0);
3875 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3876 gen_ldq_env_A0(s->mem_index, op2_offset);
3877 }
3878 }
3879 if (sse_fn_epp == SSE_SPECIAL) {
3880 goto illegal_op;
3881 }
3882
3883 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3884 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3885 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3886
3887 if (b == 0x17) {
3888 set_cc_op(s, CC_OP_EFLAGS);
3889 }
3890 break;
3891 case 0x338: /* crc32 */
3892 crc32:
3893 b = modrm;
3894 modrm = cpu_ldub_code(env, s->pc++);
3895 reg = ((modrm >> 3) & 7) | rex_r;
3896
3897 if (b != 0xf0 && b != 0xf1)
3898 goto illegal_op;
3899 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3900 goto illegal_op;
3901
3902 if (b == 0xf0)
3903 ot = OT_BYTE;
3904 else if (b == 0xf1 && s->dflag != 2)
3905 if (s->prefix & PREFIX_DATA)
3906 ot = OT_WORD;
3907 else
3908 ot = OT_LONG;
3909 else
3910 ot = OT_QUAD;
3911
3912 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3913 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3914 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3915 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3916 cpu_T[0], tcg_const_i32(8 << ot));
3917
3918 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3919 gen_op_mov_reg_T0(ot, reg);
3920 break;
3921 case 0x03a:
3922 case 0x13a:
3923 b = modrm;
3924 modrm = cpu_ldub_code(env, s->pc++);
3925 rm = modrm & 7;
3926 reg = ((modrm >> 3) & 7) | rex_r;
3927 mod = (modrm >> 6) & 3;
3928 if (b1 >= 2) {
3929 goto illegal_op;
3930 }
3931
3932 sse_fn_eppi = sse_op_table7[b].op[b1];
3933 if (!sse_fn_eppi) {
3934 goto illegal_op;
3935 }
3936 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3937 goto illegal_op;
3938
3939 if (sse_fn_eppi == SSE_SPECIAL) {
3940 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3941 rm = (modrm & 7) | REX_B(s);
3942 if (mod != 3)
3943 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3944 reg = ((modrm >> 3) & 7) | rex_r;
3945 val = cpu_ldub_code(env, s->pc++);
3946 switch (b) {
3947 case 0x14: /* pextrb */
3948 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3949 xmm_regs[reg].XMM_B(val & 15)));
3950 if (mod == 3)
3951 gen_op_mov_reg_T0(ot, rm);
3952 else
3953 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3954 (s->mem_index >> 2) - 1);
3955 break;
3956 case 0x15: /* pextrw */
3957 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3958 xmm_regs[reg].XMM_W(val & 7)));
3959 if (mod == 3)
3960 gen_op_mov_reg_T0(ot, rm);
3961 else
3962 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3963 (s->mem_index >> 2) - 1);
3964 break;
3965 case 0x16:
3966 if (ot == OT_LONG) { /* pextrd */
3967 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3968 offsetof(CPUX86State,
3969 xmm_regs[reg].XMM_L(val & 3)));
3970 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3971 if (mod == 3)
3972 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3973 else
3974 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3975 (s->mem_index >> 2) - 1);
3976 } else { /* pextrq */
3977 #ifdef TARGET_X86_64
3978 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3979 offsetof(CPUX86State,
3980 xmm_regs[reg].XMM_Q(val & 1)));
3981 if (mod == 3)
3982 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3983 else
3984 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3985 (s->mem_index >> 2) - 1);
3986 #else
3987 goto illegal_op;
3988 #endif
3989 }
3990 break;
3991 case 0x17: /* extractps */
3992 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3993 xmm_regs[reg].XMM_L(val & 3)));
3994 if (mod == 3)
3995 gen_op_mov_reg_T0(ot, rm);
3996 else
3997 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3998 (s->mem_index >> 2) - 1);
3999 break;
4000 case 0x20: /* pinsrb */
4001 if (mod == 3)
4002 gen_op_mov_TN_reg(OT_LONG, 0, rm);
4003 else
4004 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
4005 (s->mem_index >> 2) - 1);
4006 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
4007 xmm_regs[reg].XMM_B(val & 15)));
4008 break;
4009 case 0x21: /* insertps */
4010 if (mod == 3) {
4011 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4012 offsetof(CPUX86State,xmm_regs[rm]
4013 .XMM_L((val >> 6) & 3)));
4014 } else {
4015 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4016 (s->mem_index >> 2) - 1);
4017 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4018 }
4019 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4020 offsetof(CPUX86State,xmm_regs[reg]
4021 .XMM_L((val >> 4) & 3)));
4022 if ((val >> 0) & 1)
4023 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4024 cpu_env, offsetof(CPUX86State,
4025 xmm_regs[reg].XMM_L(0)));
4026 if ((val >> 1) & 1)
4027 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4028 cpu_env, offsetof(CPUX86State,
4029 xmm_regs[reg].XMM_L(1)));
4030 if ((val >> 2) & 1)
4031 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4032 cpu_env, offsetof(CPUX86State,
4033 xmm_regs[reg].XMM_L(2)));
4034 if ((val >> 3) & 1)
4035 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4036 cpu_env, offsetof(CPUX86State,
4037 xmm_regs[reg].XMM_L(3)));
4038 break;
4039 case 0x22:
4040 if (ot == OT_LONG) { /* pinsrd */
4041 if (mod == 3)
4042 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
4043 else
4044 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4045 (s->mem_index >> 2) - 1);
4046 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4047 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4048 offsetof(CPUX86State,
4049 xmm_regs[reg].XMM_L(val & 3)));
4050 } else { /* pinsrq */
4051 #ifdef TARGET_X86_64
4052 if (mod == 3)
4053 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
4054 else
4055 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4056 (s->mem_index >> 2) - 1);
4057 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4058 offsetof(CPUX86State,
4059 xmm_regs[reg].XMM_Q(val & 1)));
4060 #else
4061 goto illegal_op;
4062 #endif
4063 }
4064 break;
4065 }
4066 return;
4067 }
4068
4069 if (b1) {
4070 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4071 if (mod == 3) {
4072 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
4073 } else {
4074 op2_offset = offsetof(CPUX86State,xmm_t0);
4075 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4076 gen_ldo_env_A0(s->mem_index, op2_offset);
4077 }
4078 } else {
4079 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4080 if (mod == 3) {
4081 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4082 } else {
4083 op2_offset = offsetof(CPUX86State,mmx_t0);
4084 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4085 gen_ldq_env_A0(s->mem_index, op2_offset);
4086 }
4087 }
4088 val = cpu_ldub_code(env, s->pc++);
4089
4090 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4091 set_cc_op(s, CC_OP_EFLAGS);
4092
4093 if (s->dflag == 2)
4094 /* The helper must use entire 64-bit gp registers */
4095 val |= 1 << 8;
4096 }
4097
4098 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4099 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4100 sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4101 break;
4102 default:
4103 goto illegal_op;
4104 }
4105 } else {
4106 /* generic MMX or SSE operation */
4107 switch(b) {
4108 case 0x70: /* pshufx insn */
4109 case 0xc6: /* pshufx insn */
4110 case 0xc2: /* compare insns */
4111 s->rip_offset = 1;
4112 break;
4113 default:
4114 break;
4115 }
4116 if (is_xmm) {
4117 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4118 if (mod != 3) {
4119 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4120 op2_offset = offsetof(CPUX86State,xmm_t0);
4121 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4122 b == 0xc2)) {
4123 /* specific case for SSE single instructions */
4124 if (b1 == 2) {
4125 /* 32 bit access */
4126 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4127 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4128 } else {
4129 /* 64 bit access */
4130 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4131 }
4132 } else {
4133 gen_ldo_env_A0(s->mem_index, op2_offset);
4134 }
4135 } else {
4136 rm = (modrm & 7) | REX_B(s);
4137 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4138 }
4139 } else {
4140 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4141 if (mod != 3) {
4142 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4143 op2_offset = offsetof(CPUX86State,mmx_t0);
4144 gen_ldq_env_A0(s->mem_index, op2_offset);
4145 } else {
4146 rm = (modrm & 7);
4147 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4148 }
4149 }
4150 switch(b) {
4151 case 0x0f: /* 3DNow! data insns */
4152 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4153 goto illegal_op;
4154 val = cpu_ldub_code(env, s->pc++);
4155 sse_fn_epp = sse_op_table5[val];
4156 if (!sse_fn_epp) {
4157 goto illegal_op;
4158 }
4159 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4160 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4161 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4162 break;
4163 case 0x70: /* pshufx insn */
4164 case 0xc6: /* pshufx insn */
4165 val = cpu_ldub_code(env, s->pc++);
4166 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4167 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4168 /* XXX: introduce a new table? */
4169 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
4170 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4171 break;
4172 case 0xc2:
4173 /* compare insns */
4174 val = cpu_ldub_code(env, s->pc++);
4175 if (val >= 8)
4176 goto illegal_op;
4177 sse_fn_epp = sse_op_table4[val][b1];
4178
4179 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4180 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4181 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4182 break;
4183 case 0xf7:
4184 /* maskmov : we must prepare A0 */
4185 if (mod != 3)
4186 goto illegal_op;
4187 #ifdef TARGET_X86_64
4188 if (s->aflag == 2) {
4189 gen_op_movq_A0_reg(R_EDI);
4190 } else
4191 #endif
4192 {
4193 gen_op_movl_A0_reg(R_EDI);
4194 if (s->aflag == 0)
4195 gen_op_andl_A0_ffff();
4196 }
4197 gen_add_A0_ds_seg(s);
4198
4199 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4200 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4201 /* XXX: introduce a new table? */
4202 sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
4203 sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0);
4204 break;
4205 default:
4206 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4207 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4208 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4209 break;
4210 }
4211 if (b == 0x2e || b == 0x2f) {
4212 set_cc_op(s, CC_OP_EFLAGS);
4213 }
4214 }
4215 }
4216
4217 /* convert one instruction. s->is_jmp is set if the translation must
4218 be stopped. Return the next pc value */
4219 static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
4220 target_ulong pc_start)
4221 {
4222 int b, prefixes, aflag, dflag;
4223 int shift, ot;
4224 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4225 target_ulong next_eip, tval;
4226 int rex_w, rex_r;
4227
4228 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4229 tcg_gen_debug_insn_start(pc_start);
4230 }
4231 s->pc = pc_start;
4232 prefixes = 0;
4233 aflag = s->code32;
4234 dflag = s->code32;
4235 s->override = -1;
4236 rex_w = -1;
4237 rex_r = 0;
4238 #ifdef TARGET_X86_64
4239 s->rex_x = 0;
4240 s->rex_b = 0;
4241 x86_64_hregs = 0;
4242 #endif
4243 s->rip_offset = 0; /* for relative ip address */
4244 next_byte:
4245 b = cpu_ldub_code(env, s->pc);
4246 s->pc++;
4247 /* check prefixes */
4248 #ifdef TARGET_X86_64
4249 if (CODE64(s)) {
4250 switch (b) {
4251 case 0xf3:
4252 prefixes |= PREFIX_REPZ;
4253 goto next_byte;
4254 case 0xf2:
4255 prefixes |= PREFIX_REPNZ;
4256 goto next_byte;
4257 case 0xf0:
4258 prefixes |= PREFIX_LOCK;
4259 goto next_byte;
4260 case 0x2e:
4261 s->override = R_CS;
4262 goto next_byte;
4263 case 0x36:
4264 s->override = R_SS;
4265 goto next_byte;
4266 case 0x3e:
4267 s->override = R_DS;
4268 goto next_byte;
4269 case 0x26:
4270 s->override = R_ES;
4271 goto next_byte;
4272 case 0x64:
4273 s->override = R_FS;
4274 goto next_byte;
4275 case 0x65:
4276 s->override = R_GS;
4277 goto next_byte;
4278 case 0x66:
4279 prefixes |= PREFIX_DATA;
4280 goto next_byte;
4281 case 0x67:
4282 prefixes |= PREFIX_ADR;
4283 goto next_byte;
4284 case 0x40 ... 0x4f:
4285 /* REX prefix */
4286 rex_w = (b >> 3) & 1;
4287 rex_r = (b & 0x4) << 1;
4288 s->rex_x = (b & 0x2) << 2;
4289 REX_B(s) = (b & 0x1) << 3;
4290 x86_64_hregs = 1; /* select uniform byte register addressing */
4291 goto next_byte;
4292 }
4293 if (rex_w == 1) {
4294 /* 0x66 is ignored if rex.w is set */
4295 dflag = 2;
4296 } else {
4297 if (prefixes & PREFIX_DATA)
4298 dflag ^= 1;
4299 }
4300 if (!(prefixes & PREFIX_ADR))
4301 aflag = 2;
4302 } else
4303 #endif
4304 {
4305 switch (b) {
4306 case 0xf3:
4307 prefixes |= PREFIX_REPZ;
4308 goto next_byte;
4309 case 0xf2:
4310 prefixes |= PREFIX_REPNZ;
4311 goto next_byte;
4312 case 0xf0:
4313 prefixes |= PREFIX_LOCK;
4314 goto next_byte;
4315 case 0x2e:
4316 s->override = R_CS;
4317 goto next_byte;
4318 case 0x36:
4319 s->override = R_SS;
4320 goto next_byte;
4321 case 0x3e:
4322 s->override = R_DS;
4323 goto next_byte;
4324 case 0x26:
4325 s->override = R_ES;
4326 goto next_byte;
4327 case 0x64:
4328 s->override = R_FS;
4329 goto next_byte;
4330 case 0x65:
4331 s->override = R_GS;
4332 goto next_byte;
4333 case 0x66:
4334 prefixes |= PREFIX_DATA;
4335 goto next_byte;
4336 case 0x67:
4337 prefixes |= PREFIX_ADR;
4338 goto next_byte;
4339 }
4340 if (prefixes & PREFIX_DATA)
4341 dflag ^= 1;
4342 if (prefixes & PREFIX_ADR)
4343 aflag ^= 1;
4344 }
4345
4346 s->prefix = prefixes;
4347 s->aflag = aflag;
4348 s->dflag = dflag;
4349
4350 /* lock generation */
4351 if (prefixes & PREFIX_LOCK)
4352 gen_helper_lock();
4353
4354 /* now check op code */
4355 reswitch:
4356 switch(b) {
4357 case 0x0f:
4358 /**************************/
4359 /* extended op code */
4360 b = cpu_ldub_code(env, s->pc++) | 0x100;
4361 goto reswitch;
4362
4363 /**************************/
4364 /* arith & logic */
4365 case 0x00 ... 0x05:
4366 case 0x08 ... 0x0d:
4367 case 0x10 ... 0x15:
4368 case 0x18 ... 0x1d:
4369 case 0x20 ... 0x25:
4370 case 0x28 ... 0x2d:
4371 case 0x30 ... 0x35:
4372 case 0x38 ... 0x3d:
4373 {
4374 int op, f, val;
4375 op = (b >> 3) & 7;
4376 f = (b >> 1) & 3;
4377
4378 if ((b & 1) == 0)
4379 ot = OT_BYTE;
4380 else
4381 ot = dflag + OT_WORD;
4382
4383 switch(f) {
4384 case 0: /* OP Ev, Gv */
4385 modrm = cpu_ldub_code(env, s->pc++);
4386 reg = ((modrm >> 3) & 7) | rex_r;
4387 mod = (modrm >> 6) & 3;
4388 rm = (modrm & 7) | REX_B(s);
4389 if (mod != 3) {
4390 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4391 opreg = OR_TMP0;
4392 } else if (op == OP_XORL && rm == reg) {
4393 xor_zero:
4394 /* xor reg, reg optimisation */
4395 gen_op_movl_T0_0();
4396 set_cc_op(s, CC_OP_LOGICB + ot);
4397 gen_op_mov_reg_T0(ot, reg);
4398 gen_op_update1_cc();
4399 break;
4400 } else {
4401 opreg = rm;
4402 }
4403 gen_op_mov_TN_reg(ot, 1, reg);
4404 gen_op(s, op, ot, opreg);
4405 break;
4406 case 1: /* OP Gv, Ev */
4407 modrm = cpu_ldub_code(env, s->pc++);
4408 mod = (modrm >> 6) & 3;
4409 reg = ((modrm >> 3) & 7) | rex_r;
4410 rm = (modrm & 7) | REX_B(s);
4411 if (mod != 3) {
4412 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4413 gen_op_ld_T1_A0(ot + s->mem_index);
4414 } else if (op == OP_XORL && rm == reg) {
4415 goto xor_zero;
4416 } else {
4417 gen_op_mov_TN_reg(ot, 1, rm);
4418 }
4419 gen_op(s, op, ot, reg);
4420 break;
4421 case 2: /* OP A, Iv */
4422 val = insn_get(env, s, ot);
4423 gen_op_movl_T1_im(val);
4424 gen_op(s, op, ot, OR_EAX);
4425 break;
4426 }
4427 }
4428 break;
4429
4430 case 0x82:
4431 if (CODE64(s))
4432 goto illegal_op;
4433 case 0x80: /* GRP1 */
4434 case 0x81:
4435 case 0x83:
4436 {
4437 int val;
4438
4439 if ((b & 1) == 0)
4440 ot = OT_BYTE;
4441 else
4442 ot = dflag + OT_WORD;
4443
4444 modrm = cpu_ldub_code(env, s->pc++);
4445 mod = (modrm >> 6) & 3;
4446 rm = (modrm & 7) | REX_B(s);
4447 op = (modrm >> 3) & 7;
4448
4449 if (mod != 3) {
4450 if (b == 0x83)
4451 s->rip_offset = 1;
4452 else
4453 s->rip_offset = insn_const_size(ot);
4454 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4455 opreg = OR_TMP0;
4456 } else {
4457 opreg = rm;
4458 }
4459
4460 switch(b) {
4461 default:
4462 case 0x80:
4463 case 0x81:
4464 case 0x82:
4465 val = insn_get(env, s, ot);
4466 break;
4467 case 0x83:
4468 val = (int8_t)insn_get(env, s, OT_BYTE);
4469 break;
4470 }
4471 gen_op_movl_T1_im(val);
4472 gen_op(s, op, ot, opreg);
4473 }
4474 break;
4475
4476 /**************************/
4477 /* inc, dec, and other misc arith */
4478 case 0x40 ... 0x47: /* inc Gv */
4479 ot = dflag ? OT_LONG : OT_WORD;
4480 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4481 break;
4482 case 0x48 ... 0x4f: /* dec Gv */
4483 ot = dflag ? OT_LONG : OT_WORD;
4484 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4485 break;
4486 case 0xf6: /* GRP3 */
4487 case 0xf7:
4488 if ((b & 1) == 0)
4489 ot = OT_BYTE;
4490 else
4491 ot = dflag + OT_WORD;
4492
4493 modrm = cpu_ldub_code(env, s->pc++);
4494 mod = (modrm >> 6) & 3;
4495 rm = (modrm & 7) | REX_B(s);
4496 op = (modrm >> 3) & 7;
4497 if (mod != 3) {
4498 if (op == 0)
4499 s->rip_offset = insn_const_size(ot);
4500 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4501 gen_op_ld_T0_A0(ot + s->mem_index);
4502 } else {
4503 gen_op_mov_TN_reg(ot, 0, rm);
4504 }
4505
4506 switch(op) {
4507 case 0: /* test */
4508 val = insn_get(env, s, ot);
4509 gen_op_movl_T1_im(val);
4510 gen_op_testl_T0_T1_cc();
4511 set_cc_op(s, CC_OP_LOGICB + ot);
4512 break;
4513 case 2: /* not */
4514 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4515 if (mod != 3) {
4516 gen_op_st_T0_A0(ot + s->mem_index);
4517 } else {
4518 gen_op_mov_reg_T0(ot, rm);
4519 }
4520 break;
4521 case 3: /* neg */
4522 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4523 if (mod != 3) {
4524 gen_op_st_T0_A0(ot + s->mem_index);
4525 } else {
4526 gen_op_mov_reg_T0(ot, rm);
4527 }
4528 gen_op_update_neg_cc();
4529 set_cc_op(s, CC_OP_SUBB + ot);
4530 break;
4531 case 4: /* mul */
4532 switch(ot) {
4533 case OT_BYTE:
4534 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4535 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4536 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4537 /* XXX: use 32 bit mul which could be faster */
4538 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4539 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4540 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4541 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4542 set_cc_op(s, CC_OP_MULB);
4543 break;
4544 case OT_WORD:
4545 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4546 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4547 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4548 /* XXX: use 32 bit mul which could be faster */
4549 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4550 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4551 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4552 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4553 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4554 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4555 set_cc_op(s, CC_OP_MULW);
4556 break;
4557 default:
4558 case OT_LONG:
4559 #ifdef TARGET_X86_64
4560 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4561 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4562 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4563 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4564 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4565 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4566 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4567 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4568 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4569 #else
4570 {
4571 TCGv_i64 t0, t1;
4572 t0 = tcg_temp_new_i64();
4573 t1 = tcg_temp_new_i64();
4574 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4575 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4576 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4577 tcg_gen_mul_i64(t0, t0, t1);
4578 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4579 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4580 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4581 tcg_gen_shri_i64(t0, t0, 32);
4582 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4583 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4584 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4585 }
4586 #endif
4587 set_cc_op(s, CC_OP_MULL);
4588 break;
4589 #ifdef TARGET_X86_64
4590 case OT_QUAD:
4591 gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]);
4592 set_cc_op(s, CC_OP_MULQ);
4593 break;
4594 #endif
4595 }
4596 break;
4597 case 5: /* imul */
4598 switch(ot) {
4599 case OT_BYTE:
4600 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4601 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4602 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4603 /* XXX: use 32 bit mul which could be faster */
4604 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4605 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4606 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4607 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4608 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4609 set_cc_op(s, CC_OP_MULB);
4610 break;
4611 case OT_WORD:
4612 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4613 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4614 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4615 /* XXX: use 32 bit mul which could be faster */
4616 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4617 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4618 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4619 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4620 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4621 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4622 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4623 set_cc_op(s, CC_OP_MULW);
4624 break;
4625 default:
4626 case OT_LONG:
4627 #ifdef TARGET_X86_64
4628 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4629 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4630 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4631 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4632 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4633 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4634 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4635 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4636 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4637 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4638 #else
4639 {
4640 TCGv_i64 t0, t1;
4641 t0 = tcg_temp_new_i64();
4642 t1 = tcg_temp_new_i64();
4643 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4644 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4645 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4646 tcg_gen_mul_i64(t0, t0, t1);
4647 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4648 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4649 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4650 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4651 tcg_gen_shri_i64(t0, t0, 32);
4652 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4653 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4654 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4655 }
4656 #endif
4657 set_cc_op(s, CC_OP_MULL);
4658 break;
4659 #ifdef TARGET_X86_64
4660 case OT_QUAD:
4661 gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]);
4662 set_cc_op(s, CC_OP_MULQ);
4663 break;
4664 #endif
4665 }
4666 break;
4667 case 6: /* div */
4668 switch(ot) {
4669 case OT_BYTE:
4670 gen_jmp_im(pc_start - s->cs_base);
4671 gen_helper_divb_AL(cpu_env, cpu_T[0]);
4672 break;
4673 case OT_WORD:
4674 gen_jmp_im(pc_start - s->cs_base);
4675 gen_helper_divw_AX(cpu_env, cpu_T[0]);
4676 break;
4677 default:
4678 case OT_LONG:
4679 gen_jmp_im(pc_start - s->cs_base);
4680 gen_helper_divl_EAX(cpu_env, cpu_T[0]);
4681 break;
4682 #ifdef TARGET_X86_64
4683 case OT_QUAD:
4684 gen_jmp_im(pc_start - s->cs_base);
4685 gen_helper_divq_EAX(cpu_env, cpu_T[0]);
4686 break;
4687 #endif
4688 }
4689 break;
4690 case 7: /* idiv */
4691 switch(ot) {
4692 case OT_BYTE:
4693 gen_jmp_im(pc_start - s->cs_base);
4694 gen_helper_idivb_AL(cpu_env, cpu_T[0]);
4695 break;
4696 case OT_WORD:
4697 gen_jmp_im(pc_start - s->cs_base);
4698 gen_helper_idivw_AX(cpu_env, cpu_T[0]);
4699 break;
4700 default:
4701 case OT_LONG:
4702 gen_jmp_im(pc_start - s->cs_base);
4703 gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
4704 break;
4705 #ifdef TARGET_X86_64
4706 case OT_QUAD:
4707 gen_jmp_im(pc_start - s->cs_base);
4708 gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
4709 break;
4710 #endif
4711 }
4712 break;
4713 default:
4714 goto illegal_op;
4715 }
4716 break;
4717
4718 case 0xfe: /* GRP4 */
4719 case 0xff: /* GRP5 */
4720 if ((b & 1) == 0)
4721 ot = OT_BYTE;
4722 else
4723 ot = dflag + OT_WORD;
4724
4725 modrm = cpu_ldub_code(env, s->pc++);
4726 mod = (modrm >> 6) & 3;
4727 rm = (modrm & 7) | REX_B(s);
4728 op = (modrm >> 3) & 7;
4729 if (op >= 2 && b == 0xfe) {
4730 goto illegal_op;
4731 }
4732 if (CODE64(s)) {
4733 if (op == 2 || op == 4) {
4734 /* operand size for jumps is 64 bit */
4735 ot = OT_QUAD;
4736 } else if (op == 3 || op == 5) {
4737 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4738 } else if (op == 6) {
4739 /* default push size is 64 bit */
4740 ot = dflag ? OT_QUAD : OT_WORD;
4741 }
4742 }
4743 if (mod != 3) {
4744 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4745 if (op >= 2 && op != 3 && op != 5)
4746 gen_op_ld_T0_A0(ot + s->mem_index);
4747 } else {
4748 gen_op_mov_TN_reg(ot, 0, rm);
4749 }
4750
4751 switch(op) {
4752 case 0: /* inc Ev */
4753 if (mod != 3)
4754 opreg = OR_TMP0;
4755 else
4756 opreg = rm;
4757 gen_inc(s, ot, opreg, 1);
4758 break;
4759 case 1: /* dec Ev */
4760 if (mod != 3)
4761 opreg = OR_TMP0;
4762 else
4763 opreg = rm;
4764 gen_inc(s, ot, opreg, -1);
4765 break;
4766 case 2: /* call Ev */
4767 /* XXX: optimize if memory (no 'and' is necessary) */
4768 if (s->dflag == 0)
4769 gen_op_andl_T0_ffff();
4770 next_eip = s->pc - s->cs_base;
4771 gen_movtl_T1_im(next_eip);
4772 gen_push_T1(s);
4773 gen_op_jmp_T0();
4774 gen_eob(s);
4775 break;
4776 case 3: /* lcall Ev */
4777 gen_op_ld_T1_A0(ot + s->mem_index);
4778 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4779 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4780 do_lcall:
4781 if (s->pe && !s->vm86) {
4782 gen_update_cc_op(s);
4783 gen_jmp_im(pc_start - s->cs_base);
4784 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4785 gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4786 tcg_const_i32(dflag),
4787 tcg_const_i32(s->pc - pc_start));
4788 } else {
4789 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4790 gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
4791 tcg_const_i32(dflag),
4792 tcg_const_i32(s->pc - s->cs_base));
4793 }
4794 gen_eob(s);
4795 break;
4796 case 4: /* jmp Ev */
4797 if (s->dflag == 0)
4798 gen_op_andl_T0_ffff();
4799 gen_op_jmp_T0();
4800 gen_eob(s);
4801 break;
4802 case 5: /* ljmp Ev */
4803 gen_op_ld_T1_A0(ot + s->mem_index);
4804 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4805 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4806 do_ljmp:
4807 if (s->pe && !s->vm86) {
4808 gen_update_cc_op(s);
4809 gen_jmp_im(pc_start - s->cs_base);
4810 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4811 gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4812 tcg_const_i32(s->pc - pc_start));
4813 } else {
4814 gen_op_movl_seg_T0_vm(R_CS);
4815 gen_op_movl_T0_T1();
4816 gen_op_jmp_T0();
4817 }
4818 gen_eob(s);
4819 break;
4820 case 6: /* push Ev */
4821 gen_push_T0(s);
4822 break;
4823 default:
4824 goto illegal_op;
4825 }
4826 break;
4827
4828 case 0x84: /* test Ev, Gv */
4829 case 0x85:
4830 if ((b & 1) == 0)
4831 ot = OT_BYTE;
4832 else
4833 ot = dflag + OT_WORD;
4834
4835 modrm = cpu_ldub_code(env, s->pc++);
4836 reg = ((modrm >> 3) & 7) | rex_r;
4837
4838 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4839 gen_op_mov_TN_reg(ot, 1, reg);
4840 gen_op_testl_T0_T1_cc();
4841 set_cc_op(s, CC_OP_LOGICB + ot);
4842 break;
4843
4844 case 0xa8: /* test eAX, Iv */
4845 case 0xa9:
4846 if ((b & 1) == 0)
4847 ot = OT_BYTE;
4848 else
4849 ot = dflag + OT_WORD;
4850 val = insn_get(env, s, ot);
4851
4852 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4853 gen_op_movl_T1_im(val);
4854 gen_op_testl_T0_T1_cc();
4855 set_cc_op(s, CC_OP_LOGICB + ot);
4856 break;
4857
4858 case 0x98: /* CWDE/CBW */
4859 #ifdef TARGET_X86_64
4860 if (dflag == 2) {
4861 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4862 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4863 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4864 } else
4865 #endif
4866 if (dflag == 1) {
4867 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4868 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4869 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4870 } else {
4871 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4872 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4873 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4874 }
4875 break;
4876 case 0x99: /* CDQ/CWD */
4877 #ifdef TARGET_X86_64
4878 if (dflag == 2) {
4879 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4880 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4881 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4882 } else
4883 #endif
4884 if (dflag == 1) {
4885 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4886 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4887 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4888 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4889 } else {
4890 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4891 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4892 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4893 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4894 }
4895 break;
4896 case 0x1af: /* imul Gv, Ev */
4897 case 0x69: /* imul Gv, Ev, I */
4898 case 0x6b:
4899 ot = dflag + OT_WORD;
4900 modrm = cpu_ldub_code(env, s->pc++);
4901 reg = ((modrm >> 3) & 7) | rex_r;
4902 if (b == 0x69)
4903 s->rip_offset = insn_const_size(ot);
4904 else if (b == 0x6b)
4905 s->rip_offset = 1;
4906 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4907 if (b == 0x69) {
4908 val = insn_get(env, s, ot);
4909 gen_op_movl_T1_im(val);
4910 } else if (b == 0x6b) {
4911 val = (int8_t)insn_get(env, s, OT_BYTE);
4912 gen_op_movl_T1_im(val);
4913 } else {
4914 gen_op_mov_TN_reg(ot, 1, reg);
4915 }
4916
4917 #ifdef TARGET_X86_64
4918 if (ot == OT_QUAD) {
4919 gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
4920 } else
4921 #endif
4922 if (ot == OT_LONG) {
4923 #ifdef TARGET_X86_64
4924 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4925 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4926 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4927 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4928 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4929 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4930 #else
4931 {
4932 TCGv_i64 t0, t1;
4933 t0 = tcg_temp_new_i64();
4934 t1 = tcg_temp_new_i64();
4935 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4936 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4937 tcg_gen_mul_i64(t0, t0, t1);
4938 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4939 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4940 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4941 tcg_gen_shri_i64(t0, t0, 32);
4942 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4943 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4944 }
4945 #endif
4946 } else {
4947 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4948 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4949 /* XXX: use 32 bit mul which could be faster */
4950 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4951 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4952 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4953 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4954 }
4955 gen_op_mov_reg_T0(ot, reg);
4956 set_cc_op(s, CC_OP_MULB + ot);
4957 break;
4958 case 0x1c0:
4959 case 0x1c1: /* xadd Ev, Gv */
4960 if ((b & 1) == 0)
4961 ot = OT_BYTE;
4962 else
4963 ot = dflag + OT_WORD;
4964 modrm = cpu_ldub_code(env, s->pc++);
4965 reg = ((modrm >> 3) & 7) | rex_r;
4966 mod = (modrm >> 6) & 3;
4967 if (mod == 3) {
4968 rm = (modrm & 7) | REX_B(s);
4969 gen_op_mov_TN_reg(ot, 0, reg);
4970 gen_op_mov_TN_reg(ot, 1, rm);
4971 gen_op_addl_T0_T1();
4972 gen_op_mov_reg_T1(ot, reg);
4973 gen_op_mov_reg_T0(ot, rm);
4974 } else {
4975 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4976 gen_op_mov_TN_reg(ot, 0, reg);
4977 gen_op_ld_T1_A0(ot + s->mem_index);
4978 gen_op_addl_T0_T1();
4979 gen_op_st_T0_A0(ot + s->mem_index);
4980 gen_op_mov_reg_T1(ot, reg);
4981 }
4982 gen_op_update2_cc();
4983 set_cc_op(s, CC_OP_ADDB + ot);
4984 break;
4985 case 0x1b0:
4986 case 0x1b1: /* cmpxchg Ev, Gv */
4987 {
4988 int label1, label2;
4989 TCGv t0, t1, t2, a0;
4990
4991 if ((b & 1) == 0)
4992 ot = OT_BYTE;
4993 else
4994 ot = dflag + OT_WORD;
4995 modrm = cpu_ldub_code(env, s->pc++);
4996 reg = ((modrm >> 3) & 7) | rex_r;
4997 mod = (modrm >> 6) & 3;
4998 t0 = tcg_temp_local_new();
4999 t1 = tcg_temp_local_new();
5000 t2 = tcg_temp_local_new();
5001 a0 = tcg_temp_local_new();
5002 gen_op_mov_v_reg(ot, t1, reg);
5003 if (mod == 3) {
5004 rm = (modrm & 7) | REX_B(s);
5005 gen_op_mov_v_reg(ot, t0, rm);
5006 } else {
5007 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5008 tcg_gen_mov_tl(a0, cpu_A0);
5009 gen_op_ld_v(ot + s->mem_index, t0, a0);
5010 rm = 0; /* avoid warning */
5011 }
5012 label1 = gen_new_label();
5013 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
5014 gen_extu(ot, t2);
5015 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
5016 label2 = gen_new_label();
5017 if (mod == 3) {
5018 gen_op_mov_reg_v(ot, R_EAX, t0);
5019 tcg_gen_br(label2);
5020 gen_set_label(label1);
5021 gen_op_mov_reg_v(ot, rm, t1);
5022 } else {
5023 /* perform no-op store cycle like physical cpu; must be
5024 before changing accumulator to ensure idempotency if
5025 the store faults and the instruction is restarted */
5026 gen_op_st_v(ot + s->mem_index, t0, a0);
5027 gen_op_mov_reg_v(ot, R_EAX, t0);
5028 tcg_gen_br(label2);
5029 gen_set_label(label1);
5030 gen_op_st_v(ot + s->mem_index, t1, a0);
5031 }
5032 gen_set_label(label2);
5033 tcg_gen_mov_tl(cpu_cc_src, t0);
5034 tcg_gen_mov_tl(cpu_cc_dst, t2);
5035 set_cc_op(s, CC_OP_SUBB + ot);
5036 tcg_temp_free(t0);
5037 tcg_temp_free(t1);
5038 tcg_temp_free(t2);
5039 tcg_temp_free(a0);
5040 }
5041 break;
5042 case 0x1c7: /* cmpxchg8b */
5043 modrm = cpu_ldub_code(env, s->pc++);
5044 mod = (modrm >> 6) & 3;
5045 if ((mod == 3) || ((modrm & 0x38) != 0x8))
5046 goto illegal_op;
5047 #ifdef TARGET_X86_64
5048 if (dflag == 2) {
5049 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
5050 goto illegal_op;
5051 gen_jmp_im(pc_start - s->cs_base);
5052 gen_update_cc_op(s);
5053 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5054 gen_helper_cmpxchg16b(cpu_env, cpu_A0);
5055 } else
5056 #endif
5057 {
5058 if (!(s->cpuid_features & CPUID_CX8))
5059 goto illegal_op;
5060 gen_jmp_im(pc_start - s->cs_base);
5061 gen_update_cc_op(s);
5062 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5063 gen_helper_cmpxchg8b(cpu_env, cpu_A0);
5064 }
5065 set_cc_op(s, CC_OP_EFLAGS);
5066 break;
5067
5068 /**************************/
5069 /* push/pop */
5070 case 0x50 ... 0x57: /* push */
5071 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
5072 gen_push_T0(s);
5073 break;
5074 case 0x58 ... 0x5f: /* pop */
5075 if (CODE64(s)) {
5076 ot = dflag ? OT_QUAD : OT_WORD;
5077 } else {
5078 ot = dflag + OT_WORD;
5079 }
5080 gen_pop_T0(s);
5081 /* NOTE: order is important for pop %sp */
5082 gen_pop_update(s);
5083 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
5084 break;
5085 case 0x60: /* pusha */
5086 if (CODE64(s))
5087 goto illegal_op;
5088 gen_pusha(s);
5089 break;
5090 case 0x61: /* popa */
5091 if (CODE64(s))
5092 goto illegal_op;
5093 gen_popa(s);
5094 break;
5095 case 0x68: /* push Iv */
5096 case 0x6a:
5097 if (CODE64(s)) {
5098 ot = dflag ? OT_QUAD : OT_WORD;
5099 } else {
5100 ot = dflag + OT_WORD;
5101 }
5102 if (b == 0x68)
5103 val = insn_get(env, s, ot);
5104 else
5105 val = (int8_t)insn_get(env, s, OT_BYTE);
5106 gen_op_movl_T0_im(val);
5107 gen_push_T0(s);
5108 break;
5109 case 0x8f: /* pop Ev */
5110 if (CODE64(s)) {
5111 ot = dflag ? OT_QUAD : OT_WORD;
5112 } else {
5113 ot = dflag + OT_WORD;
5114 }
5115 modrm = cpu_ldub_code(env, s->pc++);
5116 mod = (modrm >> 6) & 3;
5117 gen_pop_T0(s);
5118 if (mod == 3) {
5119 /* NOTE: order is important for pop %sp */
5120 gen_pop_update(s);
5121 rm = (modrm & 7) | REX_B(s);
5122 gen_op_mov_reg_T0(ot, rm);
5123 } else {
5124 /* NOTE: order is important too for MMU exceptions */
5125 s->popl_esp_hack = 1 << ot;
5126 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5127 s->popl_esp_hack = 0;
5128 gen_pop_update(s);
5129 }
5130 break;
5131 case 0xc8: /* enter */
5132 {
5133 int level;
5134 val = cpu_lduw_code(env, s->pc);
5135 s->pc += 2;
5136 level = cpu_ldub_code(env, s->pc++);
5137 gen_enter(s, val, level);
5138 }
5139 break;
5140 case 0xc9: /* leave */
5141 /* XXX: exception not precise (ESP is updated before potential exception) */
5142 if (CODE64(s)) {
5143 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5144 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5145 } else if (s->ss32) {
5146 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5147 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5148 } else {
5149 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5150 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5151 }
5152 gen_pop_T0(s);
5153 if (CODE64(s)) {
5154 ot = dflag ? OT_QUAD : OT_WORD;
5155 } else {
5156 ot = dflag + OT_WORD;
5157 }
5158 gen_op_mov_reg_T0(ot, R_EBP);
5159 gen_pop_update(s);
5160 break;
5161 case 0x06: /* push es */
5162 case 0x0e: /* push cs */
5163 case 0x16: /* push ss */
5164 case 0x1e: /* push ds */
5165 if (CODE64(s))
5166 goto illegal_op;
5167 gen_op_movl_T0_seg(b >> 3);
5168 gen_push_T0(s);
5169 break;
5170 case 0x1a0: /* push fs */
5171 case 0x1a8: /* push gs */
5172 gen_op_movl_T0_seg((b >> 3) & 7);
5173 gen_push_T0(s);
5174 break;
5175 case 0x07: /* pop es */
5176 case 0x17: /* pop ss */
5177 case 0x1f: /* pop ds */
5178 if (CODE64(s))
5179 goto illegal_op;
5180 reg = b >> 3;
5181 gen_pop_T0(s);
5182 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5183 gen_pop_update(s);
5184 if (reg == R_SS) {
5185 /* if reg == SS, inhibit interrupts/trace. */
5186 /* If several instructions disable interrupts, only the
5187 _first_ does it */
5188 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5189 gen_helper_set_inhibit_irq(cpu_env);
5190 s->tf = 0;
5191 }
5192 if (s->is_jmp) {
5193 gen_jmp_im(s->pc - s->cs_base);
5194 gen_eob(s);
5195 }
5196 break;
5197 case 0x1a1: /* pop fs */
5198 case 0x1a9: /* pop gs */
5199 gen_pop_T0(s);
5200 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5201 gen_pop_update(s);
5202 if (s->is_jmp) {
5203 gen_jmp_im(s->pc - s->cs_base);
5204 gen_eob(s);
5205 }
5206 break;
5207
5208 /**************************/
5209 /* mov */
5210 case 0x88:
5211 case 0x89: /* mov Gv, Ev */
5212 if ((b & 1) == 0)
5213 ot = OT_BYTE;
5214 else
5215 ot = dflag + OT_WORD;
5216 modrm = cpu_ldub_code(env, s->pc++);
5217 reg = ((modrm >> 3) & 7) | rex_r;
5218
5219 /* generate a generic store */
5220 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
5221 break;
5222 case 0xc6:
5223 case 0xc7: /* mov Ev, Iv */
5224 if ((b & 1) == 0)
5225 ot = OT_BYTE;
5226 else
5227 ot = dflag + OT_WORD;
5228 modrm = cpu_ldub_code(env, s->pc++);
5229 mod = (modrm >> 6) & 3;
5230 if (mod != 3) {
5231 s->rip_offset = insn_const_size(ot);
5232 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5233 }
5234 val = insn_get(env, s, ot);
5235 gen_op_movl_T0_im(val);
5236 if (mod != 3)
5237 gen_op_st_T0_A0(ot + s->mem_index);
5238 else
5239 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5240 break;
5241 case 0x8a:
5242 case 0x8b: /* mov Ev, Gv */
5243 if ((b & 1) == 0)
5244 ot = OT_BYTE;
5245 else
5246 ot = OT_WORD + dflag;
5247 modrm = cpu_ldub_code(env, s->pc++);
5248 reg = ((modrm >> 3) & 7) | rex_r;
5249
5250 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
5251 gen_op_mov_reg_T0(ot, reg);
5252 break;
5253 case 0x8e: /* mov seg, Gv */
5254 modrm = cpu_ldub_code(env, s->pc++);
5255 reg = (modrm >> 3) & 7;
5256 if (reg >= 6 || reg == R_CS)
5257 goto illegal_op;
5258 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
5259 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5260 if (reg == R_SS) {
5261 /* if reg == SS, inhibit interrupts/trace */
5262 /* If several instructions disable interrupts, only the
5263 _first_ does it */
5264 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5265 gen_helper_set_inhibit_irq(cpu_env);
5266 s->tf = 0;
5267 }
5268 if (s->is_jmp) {
5269 gen_jmp_im(s->pc - s->cs_base);
5270 gen_eob(s);
5271 }
5272 break;
5273 case 0x8c: /* mov Gv, seg */
5274 modrm = cpu_ldub_code(env, s->pc++);
5275 reg = (modrm >> 3) & 7;
5276 mod = (modrm >> 6) & 3;
5277 if (reg >= 6)
5278 goto illegal_op;
5279 gen_op_movl_T0_seg(reg);
5280 if (mod == 3)
5281 ot = OT_WORD + dflag;
5282 else
5283 ot = OT_WORD;
5284 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5285 break;
5286
5287 case 0x1b6: /* movzbS Gv, Eb */
5288 case 0x1b7: /* movzwS Gv, Eb */
5289 case 0x1be: /* movsbS Gv, Eb */
5290 case 0x1bf: /* movswS Gv, Eb */
5291 {
5292 int d_ot;
5293 /* d_ot is the size of destination */
5294 d_ot = dflag + OT_WORD;
5295 /* ot is the size of source */
5296 ot = (b & 1) + OT_BYTE;
5297 modrm = cpu_ldub_code(env, s->pc++);
5298 reg = ((modrm >> 3) & 7) | rex_r;
5299 mod = (modrm >> 6) & 3;
5300 rm = (modrm & 7) | REX_B(s);
5301
5302 if (mod == 3) {
5303 gen_op_mov_TN_reg(ot, 0, rm);
5304 switch(ot | (b & 8)) {
5305 case OT_BYTE:
5306 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5307 break;
5308 case OT_BYTE | 8:
5309 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5310 break;
5311 case OT_WORD:
5312 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5313 break;
5314 default:
5315 case OT_WORD | 8:
5316 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5317 break;
5318 }
5319 gen_op_mov_reg_T0(d_ot, reg);
5320 } else {
5321 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5322 if (b & 8) {
5323 gen_op_lds_T0_A0(ot + s->mem_index);
5324 } else {
5325 gen_op_ldu_T0_A0(ot + s->mem_index);
5326 }
5327 gen_op_mov_reg_T0(d_ot, reg);
5328 }
5329 }
5330 break;
5331
5332 case 0x8d: /* lea */
5333 ot = dflag + OT_WORD;
5334 modrm = cpu_ldub_code(env, s->pc++);
5335 mod = (modrm >> 6) & 3;
5336 if (mod == 3)
5337 goto illegal_op;
5338 reg = ((modrm >> 3) & 7) | rex_r;
5339 /* we must ensure that no segment is added */
5340 s->override = -1;
5341 val = s->addseg;
5342 s->addseg = 0;
5343 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5344 s->addseg = val;
5345 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5346 break;
5347
5348 case 0xa0: /* mov EAX, Ov */
5349 case 0xa1:
5350 case 0xa2: /* mov Ov, EAX */
5351 case 0xa3:
5352 {
5353 target_ulong offset_addr;
5354
5355 if ((b & 1) == 0)
5356 ot = OT_BYTE;
5357 else
5358 ot = dflag + OT_WORD;
5359 #ifdef TARGET_X86_64
5360 if (s->aflag == 2) {
5361 offset_addr = cpu_ldq_code(env, s->pc);
5362 s->pc += 8;
5363 gen_op_movq_A0_im(offset_addr);
5364 } else
5365 #endif
5366 {
5367 if (s->aflag) {
5368 offset_addr = insn_get(env, s, OT_LONG);
5369 } else {
5370 offset_addr = insn_get(env, s, OT_WORD);
5371 }
5372 gen_op_movl_A0_im(offset_addr);
5373 }
5374 gen_add_A0_ds_seg(s);
5375 if ((b & 2) == 0) {
5376 gen_op_ld_T0_A0(ot + s->mem_index);
5377 gen_op_mov_reg_T0(ot, R_EAX);
5378 } else {
5379 gen_op_mov_TN_reg(ot, 0, R_EAX);
5380 gen_op_st_T0_A0(ot + s->mem_index);
5381 }
5382 }
5383 break;
5384 case 0xd7: /* xlat */
5385 #ifdef TARGET_X86_64
5386 if (s->aflag == 2) {
5387 gen_op_movq_A0_reg(R_EBX);
5388 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5389 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5390 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5391 } else
5392 #endif
5393 {
5394 gen_op_movl_A0_reg(R_EBX);
5395 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5396 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5397 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5398 if (s->aflag == 0)
5399 gen_op_andl_A0_ffff();
5400 else
5401 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5402 }
5403 gen_add_A0_ds_seg(s);
5404 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5405 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5406 break;
5407 case 0xb0 ... 0xb7: /* mov R, Ib */
5408 val = insn_get(env, s, OT_BYTE);
5409 gen_op_movl_T0_im(val);
5410 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5411 break;
5412 case 0xb8 ... 0xbf: /* mov R, Iv */
5413 #ifdef TARGET_X86_64
5414 if (dflag == 2) {
5415 uint64_t tmp;
5416 /* 64 bit case */
5417 tmp = cpu_ldq_code(env, s->pc);
5418 s->pc += 8;
5419 reg = (b & 7) | REX_B(s);
5420 gen_movtl_T0_im(tmp);
5421 gen_op_mov_reg_T0(OT_QUAD, reg);
5422 } else
5423 #endif
5424 {
5425 ot = dflag ? OT_LONG : OT_WORD;
5426 val = insn_get(env, s, ot);
5427 reg = (b & 7) | REX_B(s);
5428 gen_op_movl_T0_im(val);
5429 gen_op_mov_reg_T0(ot, reg);
5430 }
5431 break;
5432
5433 case 0x91 ... 0x97: /* xchg R, EAX */
5434 do_xchg_reg_eax:
5435 ot = dflag + OT_WORD;
5436 reg = (b & 7) | REX_B(s);
5437 rm = R_EAX;
5438 goto do_xchg_reg;
5439 case 0x86:
5440 case 0x87: /* xchg Ev, Gv */
5441 if ((b & 1) == 0)
5442 ot = OT_BYTE;
5443 else
5444 ot = dflag + OT_WORD;
5445 modrm = cpu_ldub_code(env, s->pc++);
5446 reg = ((modrm >> 3) & 7) | rex_r;
5447 mod = (modrm >> 6) & 3;
5448 if (mod == 3) {
5449 rm = (modrm & 7) | REX_B(s);
5450 do_xchg_reg:
5451 gen_op_mov_TN_reg(ot, 0, reg);
5452 gen_op_mov_TN_reg(ot, 1, rm);
5453 gen_op_mov_reg_T0(ot, rm);
5454 gen_op_mov_reg_T1(ot, reg);
5455 } else {
5456 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5457 gen_op_mov_TN_reg(ot, 0, reg);
5458 /* for xchg, lock is implicit */
5459 if (!(prefixes & PREFIX_LOCK))
5460 gen_helper_lock();
5461 gen_op_ld_T1_A0(ot + s->mem_index);
5462 gen_op_st_T0_A0(ot + s->mem_index);
5463 if (!(prefixes & PREFIX_LOCK))
5464 gen_helper_unlock();
5465 gen_op_mov_reg_T1(ot, reg);
5466 }
5467 break;
5468 case 0xc4: /* les Gv */
5469 if (CODE64(s))
5470 goto illegal_op;
5471 op = R_ES;
5472 goto do_lxx;
5473 case 0xc5: /* lds Gv */
5474 if (CODE64(s))
5475 goto illegal_op;
5476 op = R_DS;
5477 goto do_lxx;
5478 case 0x1b2: /* lss Gv */
5479 op = R_SS;
5480 goto do_lxx;
5481 case 0x1b4: /* lfs Gv */
5482 op = R_FS;
5483 goto do_lxx;
5484 case 0x1b5: /* lgs Gv */
5485 op = R_GS;
5486 do_lxx:
5487 ot = dflag ? OT_LONG : OT_WORD;
5488 modrm = cpu_ldub_code(env, s->pc++);
5489 reg = ((modrm >> 3) & 7) | rex_r;
5490 mod = (modrm >> 6) & 3;
5491 if (mod == 3)
5492 goto illegal_op;
5493 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5494 gen_op_ld_T1_A0(ot + s->mem_index);
5495 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5496 /* load the segment first to handle exceptions properly */
5497 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5498 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5499 /* then put the data */
5500 gen_op_mov_reg_T1(ot, reg);
5501 if (s->is_jmp) {
5502 gen_jmp_im(s->pc - s->cs_base);
5503 gen_eob(s);
5504 }
5505 break;
5506
5507 /************************/
5508 /* shifts */
5509 case 0xc0:
5510 case 0xc1:
5511 /* shift Ev,Ib */
5512 shift = 2;
5513 grp2:
5514 {
5515 if ((b & 1) == 0)
5516 ot = OT_BYTE;
5517 else
5518 ot = dflag + OT_WORD;
5519
5520 modrm = cpu_ldub_code(env, s->pc++);
5521 mod = (modrm >> 6) & 3;
5522 op = (modrm >> 3) & 7;
5523
5524 if (mod != 3) {
5525 if (shift == 2) {
5526 s->rip_offset = 1;
5527 }
5528 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5529 opreg = OR_TMP0;
5530 } else {
5531 opreg = (modrm & 7) | REX_B(s);
5532 }
5533
5534 /* simpler op */
5535 if (shift == 0) {
5536 gen_shift(s, op, ot, opreg, OR_ECX);
5537 } else {
5538 if (shift == 2) {
5539 shift = cpu_ldub_code(env, s->pc++);
5540 }
5541 gen_shifti(s, op, ot, opreg, shift);
5542 }
5543 }
5544 break;
5545 case 0xd0:
5546 case 0xd1:
5547 /* shift Ev,1 */
5548 shift = 1;
5549 goto grp2;
5550 case 0xd2:
5551 case 0xd3:
5552 /* shift Ev,cl */
5553 shift = 0;
5554 goto grp2;
5555
5556 case 0x1a4: /* shld imm */
5557 op = 0;
5558 shift = 1;
5559 goto do_shiftd;
5560 case 0x1a5: /* shld cl */
5561 op = 0;
5562 shift = 0;
5563 goto do_shiftd;
5564 case 0x1ac: /* shrd imm */
5565 op = 1;
5566 shift = 1;
5567 goto do_shiftd;
5568 case 0x1ad: /* shrd cl */
5569 op = 1;
5570 shift = 0;
5571 do_shiftd:
5572 ot = dflag + OT_WORD;
5573 modrm = cpu_ldub_code(env, s->pc++);
5574 mod = (modrm >> 6) & 3;
5575 rm = (modrm & 7) | REX_B(s);
5576 reg = ((modrm >> 3) & 7) | rex_r;
5577 if (mod != 3) {
5578 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5579 opreg = OR_TMP0;
5580 } else {
5581 opreg = rm;
5582 }
5583 gen_op_mov_TN_reg(ot, 1, reg);
5584
5585 if (shift) {
5586 val = cpu_ldub_code(env, s->pc++);
5587 tcg_gen_movi_tl(cpu_T3, val);
5588 } else {
5589 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5590 }
5591 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5592 break;
5593
5594 /************************/
5595 /* floats */
5596 case 0xd8 ... 0xdf:
5597 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5598 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5599 /* XXX: what to do if illegal op ? */
5600 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5601 break;
5602 }
5603 modrm = cpu_ldub_code(env, s->pc++);
5604 mod = (modrm >> 6) & 3;
5605 rm = modrm & 7;
5606 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5607 if (mod != 3) {
5608 /* memory op */
5609 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5610 switch(op) {
5611 case 0x00 ... 0x07: /* fxxxs */
5612 case 0x10 ... 0x17: /* fixxxl */
5613 case 0x20 ... 0x27: /* fxxxl */
5614 case 0x30 ... 0x37: /* fixxx */
5615 {
5616 int op1;
5617 op1 = op & 7;
5618
5619 switch(op >> 4) {
5620 case 0:
5621 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5622 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5623 gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
5624 break;
5625 case 1:
5626 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5627 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5628 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5629 break;
5630 case 2:
5631 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5632 (s->mem_index >> 2) - 1);
5633 gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
5634 break;
5635 case 3:
5636 default:
5637 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5638 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5639 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5640 break;
5641 }
5642
5643 gen_helper_fp_arith_ST0_FT0(op1);
5644 if (op1 == 3) {
5645 /* fcomp needs pop */
5646 gen_helper_fpop(cpu_env);
5647 }
5648 }
5649 break;
5650 case 0x08: /* flds */
5651 case 0x0a: /* fsts */
5652 case 0x0b: /* fstps */
5653 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5654 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5655 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5656 switch(op & 7) {
5657 case 0:
5658 switch(op >> 4) {
5659 case 0:
5660 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5661 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5662 gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
5663 break;
5664 case 1:
5665 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5666 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5667 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5668 break;
5669 case 2:
5670 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5671 (s->mem_index >> 2) - 1);
5672 gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
5673 break;
5674 case 3:
5675 default:
5676 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5677 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5678 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5679 break;
5680 }
5681 break;
5682 case 1:
5683 /* XXX: the corresponding CPUID bit must be tested ! */
5684 switch(op >> 4) {
5685 case 1:
5686 gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
5687 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5688 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5689 break;
5690 case 2:
5691 gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
5692 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5693 (s->mem_index >> 2) - 1);
5694 break;
5695 case 3:
5696 default:
5697 gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
5698 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5699 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5700 break;
5701 }
5702 gen_helper_fpop(cpu_env);
5703 break;
5704 default:
5705 switch(op >> 4) {
5706 case 0:
5707 gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
5708 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5709 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5710 break;
5711 case 1:
5712 gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
5713 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5714 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5715 break;
5716 case 2:
5717 gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
5718 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5719 (s->mem_index >> 2) - 1);
5720 break;
5721 case 3:
5722 default:
5723 gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
5724 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5725 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5726 break;
5727 }
5728 if ((op & 7) == 3)
5729 gen_helper_fpop(cpu_env);
5730 break;
5731 }
5732 break;
5733 case 0x0c: /* fldenv mem */
5734 gen_update_cc_op(s);
5735 gen_jmp_im(pc_start - s->cs_base);
5736 gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5737 break;
5738 case 0x0d: /* fldcw mem */
5739 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5740 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5741 gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
5742 break;
5743 case 0x0e: /* fnstenv mem */
5744 gen_update_cc_op(s);
5745 gen_jmp_im(pc_start - s->cs_base);
5746 gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5747 break;
5748 case 0x0f: /* fnstcw mem */
5749 gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
5750 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5751 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5752 break;
5753 case 0x1d: /* fldt mem */
5754 gen_update_cc_op(s);
5755 gen_jmp_im(pc_start - s->cs_base);
5756 gen_helper_fldt_ST0(cpu_env, cpu_A0);
5757 break;
5758 case 0x1f: /* fstpt mem */
5759 gen_update_cc_op(s);
5760 gen_jmp_im(pc_start - s->cs_base);
5761 gen_helper_fstt_ST0(cpu_env, cpu_A0);
5762 gen_helper_fpop(cpu_env);
5763 break;
5764 case 0x2c: /* frstor mem */
5765 gen_update_cc_op(s);
5766 gen_jmp_im(pc_start - s->cs_base);
5767 gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5768 break;
5769 case 0x2e: /* fnsave mem */
5770 gen_update_cc_op(s);
5771 gen_jmp_im(pc_start - s->cs_base);
5772 gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5773 break;
5774 case 0x2f: /* fnstsw mem */
5775 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
5776 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5777 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5778 break;
5779 case 0x3c: /* fbld */
5780 gen_update_cc_op(s);
5781 gen_jmp_im(pc_start - s->cs_base);
5782 gen_helper_fbld_ST0(cpu_env, cpu_A0);
5783 break;
5784 case 0x3e: /* fbstp */
5785 gen_update_cc_op(s);
5786 gen_jmp_im(pc_start - s->cs_base);
5787 gen_helper_fbst_ST0(cpu_env, cpu_A0);
5788 gen_helper_fpop(cpu_env);
5789 break;
5790 case 0x3d: /* fildll */
5791 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5792 (s->mem_index >> 2) - 1);
5793 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
5794 break;
5795 case 0x3f: /* fistpll */
5796 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
5797 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5798 (s->mem_index >> 2) - 1);
5799 gen_helper_fpop(cpu_env);
5800 break;
5801 default:
5802 goto illegal_op;
5803 }
5804 } else {
5805 /* register float ops */
5806 opreg = rm;
5807
5808 switch(op) {
5809 case 0x08: /* fld sti */
5810 gen_helper_fpush(cpu_env);
5811 gen_helper_fmov_ST0_STN(cpu_env,
5812 tcg_const_i32((opreg + 1) & 7));
5813 break;
5814 case 0x09: /* fxchg sti */
5815 case 0x29: /* fxchg4 sti, undocumented op */
5816 case 0x39: /* fxchg7 sti, undocumented op */
5817 gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
5818 break;
5819 case 0x0a: /* grp d9/2 */
5820 switch(rm) {
5821 case 0: /* fnop */
5822 /* check exceptions (FreeBSD FPU probe) */
5823 gen_update_cc_op(s);
5824 gen_jmp_im(pc_start - s->cs_base);
5825 gen_helper_fwait(cpu_env);
5826 break;
5827 default:
5828 goto illegal_op;
5829 }
5830 break;
5831 case 0x0c: /* grp d9/4 */
5832 switch(rm) {
5833 case 0: /* fchs */
5834 gen_helper_fchs_ST0(cpu_env);
5835 break;
5836 case 1: /* fabs */
5837 gen_helper_fabs_ST0(cpu_env);
5838 break;
5839 case 4: /* ftst */
5840 gen_helper_fldz_FT0(cpu_env);
5841 gen_helper_fcom_ST0_FT0(cpu_env);
5842 break;
5843 case 5: /* fxam */
5844 gen_helper_fxam_ST0(cpu_env);
5845 break;
5846 default:
5847 goto illegal_op;
5848 }
5849 break;
5850 case 0x0d: /* grp d9/5 */
5851 {
5852 switch(rm) {
5853 case 0:
5854 gen_helper_fpush(cpu_env);
5855 gen_helper_fld1_ST0(cpu_env);
5856 break;
5857 case 1:
5858 gen_helper_fpush(cpu_env);
5859 gen_helper_fldl2t_ST0(cpu_env);
5860 break;
5861 case 2:
5862 gen_helper_fpush(cpu_env);
5863 gen_helper_fldl2e_ST0(cpu_env);
5864 break;
5865 case 3:
5866 gen_helper_fpush(cpu_env);
5867 gen_helper_fldpi_ST0(cpu_env);
5868 break;
5869 case 4:
5870 gen_helper_fpush(cpu_env);
5871 gen_helper_fldlg2_ST0(cpu_env);
5872 break;
5873 case 5:
5874 gen_helper_fpush(cpu_env);
5875 gen_helper_fldln2_ST0(cpu_env);
5876 break;
5877 case 6:
5878 gen_helper_fpush(cpu_env);
5879 gen_helper_fldz_ST0(cpu_env);
5880 break;
5881 default:
5882 goto illegal_op;
5883 }
5884 }
5885 break;
5886 case 0x0e: /* grp d9/6 */
5887 switch(rm) {
5888 case 0: /* f2xm1 */
5889 gen_helper_f2xm1(cpu_env);
5890 break;
5891 case 1: /* fyl2x */
5892 gen_helper_fyl2x(cpu_env);
5893 break;
5894 case 2: /* fptan */
5895 gen_helper_fptan(cpu_env);
5896 break;
5897 case 3: /* fpatan */
5898 gen_helper_fpatan(cpu_env);
5899 break;
5900 case 4: /* fxtract */
5901 gen_helper_fxtract(cpu_env);
5902 break;
5903 case 5: /* fprem1 */
5904 gen_helper_fprem1(cpu_env);
5905 break;
5906 case 6: /* fdecstp */
5907 gen_helper_fdecstp(cpu_env);
5908 break;
5909 default:
5910 case 7: /* fincstp */
5911 gen_helper_fincstp(cpu_env);
5912 break;
5913 }
5914 break;
5915 case 0x0f: /* grp d9/7 */
5916 switch(rm) {
5917 case 0: /* fprem */
5918 gen_helper_fprem(cpu_env);
5919 break;
5920 case 1: /* fyl2xp1 */
5921 gen_helper_fyl2xp1(cpu_env);
5922 break;
5923 case 2: /* fsqrt */
5924 gen_helper_fsqrt(cpu_env);
5925 break;
5926 case 3: /* fsincos */
5927 gen_helper_fsincos(cpu_env);
5928 break;
5929 case 5: /* fscale */
5930 gen_helper_fscale(cpu_env);
5931 break;
5932 case 4: /* frndint */
5933 gen_helper_frndint(cpu_env);
5934 break;
5935 case 6: /* fsin */
5936 gen_helper_fsin(cpu_env);
5937 break;
5938 default:
5939 case 7: /* fcos */
5940 gen_helper_fcos(cpu_env);
5941 break;
5942 }
5943 break;
5944 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5945 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5946 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5947 {
5948 int op1;
5949
5950 op1 = op & 7;
5951 if (op >= 0x20) {
5952 gen_helper_fp_arith_STN_ST0(op1, opreg);
5953 if (op >= 0x30)
5954 gen_helper_fpop(cpu_env);
5955 } else {
5956 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5957 gen_helper_fp_arith_ST0_FT0(op1);
5958 }
5959 }
5960 break;
5961 case 0x02: /* fcom */
5962 case 0x22: /* fcom2, undocumented op */
5963 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5964 gen_helper_fcom_ST0_FT0(cpu_env);
5965 break;
5966 case 0x03: /* fcomp */
5967 case 0x23: /* fcomp3, undocumented op */
5968 case 0x32: /* fcomp5, undocumented op */
5969 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5970 gen_helper_fcom_ST0_FT0(cpu_env);
5971 gen_helper_fpop(cpu_env);
5972 break;
5973 case 0x15: /* da/5 */
5974 switch(rm) {
5975 case 1: /* fucompp */
5976 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
5977 gen_helper_fucom_ST0_FT0(cpu_env);
5978 gen_helper_fpop(cpu_env);
5979 gen_helper_fpop(cpu_env);
5980 break;
5981 default:
5982 goto illegal_op;
5983 }
5984 break;
5985 case 0x1c:
5986 switch(rm) {
5987 case 0: /* feni (287 only, just do nop here) */
5988 break;
5989 case 1: /* fdisi (287 only, just do nop here) */
5990 break;
5991 case 2: /* fclex */
5992 gen_helper_fclex(cpu_env);
5993 break;
5994 case 3: /* fninit */
5995 gen_helper_fninit(cpu_env);
5996 break;
5997 case 4: /* fsetpm (287 only, just do nop here) */
5998 break;
5999 default:
6000 goto illegal_op;
6001 }
6002 break;
6003 case 0x1d: /* fucomi */
6004 gen_update_cc_op(s);
6005 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6006 gen_helper_fucomi_ST0_FT0(cpu_env);
6007 set_cc_op(s, CC_OP_EFLAGS);
6008 break;
6009 case 0x1e: /* fcomi */
6010 gen_update_cc_op(s);
6011 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6012 gen_helper_fcomi_ST0_FT0(cpu_env);
6013 set_cc_op(s, CC_OP_EFLAGS);
6014 break;
6015 case 0x28: /* ffree sti */
6016 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6017 break;
6018 case 0x2a: /* fst sti */
6019 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6020 break;
6021 case 0x2b: /* fstp sti */
6022 case 0x0b: /* fstp1 sti, undocumented op */
6023 case 0x3a: /* fstp8 sti, undocumented op */
6024 case 0x3b: /* fstp9 sti, undocumented op */
6025 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6026 gen_helper_fpop(cpu_env);
6027 break;
6028 case 0x2c: /* fucom st(i) */
6029 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6030 gen_helper_fucom_ST0_FT0(cpu_env);
6031 break;
6032 case 0x2d: /* fucomp st(i) */
6033 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6034 gen_helper_fucom_ST0_FT0(cpu_env);
6035 gen_helper_fpop(cpu_env);
6036 break;
6037 case 0x33: /* de/3 */
6038 switch(rm) {
6039 case 1: /* fcompp */
6040 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6041 gen_helper_fcom_ST0_FT0(cpu_env);
6042 gen_helper_fpop(cpu_env);
6043 gen_helper_fpop(cpu_env);
6044 break;
6045 default:
6046 goto illegal_op;
6047 }
6048 break;
6049 case 0x38: /* ffreep sti, undocumented op */
6050 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6051 gen_helper_fpop(cpu_env);
6052 break;
6053 case 0x3c: /* df/4 */
6054 switch(rm) {
6055 case 0:
6056 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
6057 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
6058 gen_op_mov_reg_T0(OT_WORD, R_EAX);
6059 break;
6060 default:
6061 goto illegal_op;
6062 }
6063 break;
6064 case 0x3d: /* fucomip */
6065 gen_update_cc_op(s);
6066 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6067 gen_helper_fucomi_ST0_FT0(cpu_env);
6068 gen_helper_fpop(cpu_env);
6069 set_cc_op(s, CC_OP_EFLAGS);
6070 break;
6071 case 0x3e: /* fcomip */
6072 gen_update_cc_op(s);
6073 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6074 gen_helper_fcomi_ST0_FT0(cpu_env);
6075 gen_helper_fpop(cpu_env);
6076 set_cc_op(s, CC_OP_EFLAGS);
6077 break;
6078 case 0x10 ... 0x13: /* fcmovxx */
6079 case 0x18 ... 0x1b:
6080 {
6081 int op1, l1;
6082 static const uint8_t fcmov_cc[8] = {
6083 (JCC_B << 1),
6084 (JCC_Z << 1),
6085 (JCC_BE << 1),
6086 (JCC_P << 1),
6087 };
6088 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6089 l1 = gen_new_label();
6090 gen_jcc1(s, op1, l1);
6091 gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
6092 gen_set_label(l1);
6093 }
6094 break;
6095 default:
6096 goto illegal_op;
6097 }
6098 }
6099 break;
6100 /************************/
6101 /* string ops */
6102
6103 case 0xa4: /* movsS */
6104 case 0xa5:
6105 if ((b & 1) == 0)
6106 ot = OT_BYTE;
6107 else
6108 ot = dflag + OT_WORD;
6109
6110 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6111 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6112 } else {
6113 gen_movs(s, ot);
6114 }
6115 break;
6116
6117 case 0xaa: /* stosS */
6118 case 0xab:
6119 if ((b & 1) == 0)
6120 ot = OT_BYTE;
6121 else
6122 ot = dflag + OT_WORD;
6123
6124 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6125 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6126 } else {
6127 gen_stos(s, ot);
6128 }
6129 break;
6130 case 0xac: /* lodsS */
6131 case 0xad:
6132 if ((b & 1) == 0)
6133 ot = OT_BYTE;
6134 else
6135 ot = dflag + OT_WORD;
6136 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6137 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6138 } else {
6139 gen_lods(s, ot);
6140 }
6141 break;
6142 case 0xae: /* scasS */
6143 case 0xaf:
6144 if ((b & 1) == 0)
6145 ot = OT_BYTE;
6146 else
6147 ot = dflag + OT_WORD;
6148 if (prefixes & PREFIX_REPNZ) {
6149 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6150 } else if (prefixes & PREFIX_REPZ) {
6151 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6152 } else {
6153 gen_scas(s, ot);
6154 }
6155 break;
6156
6157 case 0xa6: /* cmpsS */
6158 case 0xa7:
6159 if ((b & 1) == 0)
6160 ot = OT_BYTE;
6161 else
6162 ot = dflag + OT_WORD;
6163 if (prefixes & PREFIX_REPNZ) {
6164 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6165 } else if (prefixes & PREFIX_REPZ) {
6166 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6167 } else {
6168 gen_cmps(s, ot);
6169 }
6170 break;
6171 case 0x6c: /* insS */
6172 case 0x6d:
6173 if ((b & 1) == 0)
6174 ot = OT_BYTE;
6175 else
6176 ot = dflag ? OT_LONG : OT_WORD;
6177 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6178 gen_op_andl_T0_ffff();
6179 gen_check_io(s, ot, pc_start - s->cs_base,
6180 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6181 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6182 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6183 } else {
6184 gen_ins(s, ot);
6185 if (use_icount) {
6186 gen_jmp(s, s->pc - s->cs_base);
6187 }
6188 }
6189 break;
6190 case 0x6e: /* outsS */
6191 case 0x6f:
6192 if ((b & 1) == 0)
6193 ot = OT_BYTE;
6194 else
6195 ot = dflag ? OT_LONG : OT_WORD;
6196 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6197 gen_op_andl_T0_ffff();
6198 gen_check_io(s, ot, pc_start - s->cs_base,
6199 svm_is_rep(prefixes) | 4);
6200 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6201 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6202 } else {
6203 gen_outs(s, ot);
6204 if (use_icount) {
6205 gen_jmp(s, s->pc - s->cs_base);
6206 }
6207 }
6208 break;
6209
6210 /************************/
6211 /* port I/O */
6212
6213 case 0xe4:
6214 case 0xe5:
6215 if ((b & 1) == 0)
6216 ot = OT_BYTE;
6217 else
6218 ot = dflag ? OT_LONG : OT_WORD;
6219 val = cpu_ldub_code(env, s->pc++);
6220 gen_op_movl_T0_im(val);
6221 gen_check_io(s, ot, pc_start - s->cs_base,
6222 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6223 if (use_icount)
6224 gen_io_start();
6225 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6226 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6227 gen_op_mov_reg_T1(ot, R_EAX);
6228 if (use_icount) {
6229 gen_io_end();
6230 gen_jmp(s, s->pc - s->cs_base);
6231 }
6232 break;
6233 case 0xe6:
6234 case 0xe7:
6235 if ((b & 1) == 0)
6236 ot = OT_BYTE;
6237 else
6238 ot = dflag ? OT_LONG : OT_WORD;
6239 val = cpu_ldub_code(env, s->pc++);
6240 gen_op_movl_T0_im(val);
6241 gen_check_io(s, ot, pc_start - s->cs_base,
6242 svm_is_rep(prefixes));
6243 gen_op_mov_TN_reg(ot, 1, R_EAX);
6244
6245 if (use_icount)
6246 gen_io_start();
6247 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6248 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6249 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6250 if (use_icount) {
6251 gen_io_end();
6252 gen_jmp(s, s->pc - s->cs_base);
6253 }
6254 break;
6255 case 0xec:
6256 case 0xed:
6257 if ((b & 1) == 0)
6258 ot = OT_BYTE;
6259 else
6260 ot = dflag ? OT_LONG : OT_WORD;
6261 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6262 gen_op_andl_T0_ffff();
6263 gen_check_io(s, ot, pc_start - s->cs_base,
6264 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6265 if (use_icount)
6266 gen_io_start();
6267 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6268 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6269 gen_op_mov_reg_T1(ot, R_EAX);
6270 if (use_icount) {
6271 gen_io_end();
6272 gen_jmp(s, s->pc - s->cs_base);
6273 }
6274 break;
6275 case 0xee:
6276 case 0xef:
6277 if ((b & 1) == 0)
6278 ot = OT_BYTE;
6279 else
6280 ot = dflag ? OT_LONG : OT_WORD;
6281 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6282 gen_op_andl_T0_ffff();
6283 gen_check_io(s, ot, pc_start - s->cs_base,
6284 svm_is_rep(prefixes));
6285 gen_op_mov_TN_reg(ot, 1, R_EAX);
6286
6287 if (use_icount)
6288 gen_io_start();
6289 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6290 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6291 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6292 if (use_icount) {
6293 gen_io_end();
6294 gen_jmp(s, s->pc - s->cs_base);
6295 }
6296 break;
6297
6298 /************************/
6299 /* control */
6300 case 0xc2: /* ret im */
6301 val = cpu_ldsw_code(env, s->pc);
6302 s->pc += 2;
6303 gen_pop_T0(s);
6304 if (CODE64(s) && s->dflag)
6305 s->dflag = 2;
6306 gen_stack_update(s, val + (2 << s->dflag));
6307 if (s->dflag == 0)
6308 gen_op_andl_T0_ffff();
6309 gen_op_jmp_T0();
6310 gen_eob(s);
6311 break;
6312 case 0xc3: /* ret */
6313 gen_pop_T0(s);
6314 gen_pop_update(s);
6315 if (s->dflag == 0)
6316 gen_op_andl_T0_ffff();
6317 gen_op_jmp_T0();
6318 gen_eob(s);
6319 break;
6320 case 0xca: /* lret im */
6321 val = cpu_ldsw_code(env, s->pc);
6322 s->pc += 2;
6323 do_lret:
6324 if (s->pe && !s->vm86) {
6325 gen_update_cc_op(s);
6326 gen_jmp_im(pc_start - s->cs_base);
6327 gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
6328 tcg_const_i32(val));
6329 } else {
6330 gen_stack_A0(s);
6331 /* pop offset */
6332 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6333 if (s->dflag == 0)
6334 gen_op_andl_T0_ffff();
6335 /* NOTE: keeping EIP updated is not a problem in case of
6336 exception */
6337 gen_op_jmp_T0();
6338 /* pop selector */
6339 gen_op_addl_A0_im(2 << s->dflag);
6340 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6341 gen_op_movl_seg_T0_vm(R_CS);
6342 /* add stack offset */
6343 gen_stack_update(s, val + (4 << s->dflag));
6344 }
6345 gen_eob(s);
6346 break;
6347 case 0xcb: /* lret */
6348 val = 0;
6349 goto do_lret;
6350 case 0xcf: /* iret */
6351 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6352 if (!s->pe) {
6353 /* real mode */
6354 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6355 set_cc_op(s, CC_OP_EFLAGS);
6356 } else if (s->vm86) {
6357 if (s->iopl != 3) {
6358 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6359 } else {
6360 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6361 set_cc_op(s, CC_OP_EFLAGS);
6362 }
6363 } else {
6364 gen_update_cc_op(s);
6365 gen_jmp_im(pc_start - s->cs_base);
6366 gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
6367 tcg_const_i32(s->pc - s->cs_base));
6368 set_cc_op(s, CC_OP_EFLAGS);
6369 }
6370 gen_eob(s);
6371 break;
6372 case 0xe8: /* call im */
6373 {
6374 if (dflag)
6375 tval = (int32_t)insn_get(env, s, OT_LONG);
6376 else
6377 tval = (int16_t)insn_get(env, s, OT_WORD);
6378 next_eip = s->pc - s->cs_base;
6379 tval += next_eip;
6380 if (s->dflag == 0)
6381 tval &= 0xffff;
6382 else if(!CODE64(s))
6383 tval &= 0xffffffff;
6384 gen_movtl_T0_im(next_eip);
6385 gen_push_T0(s);
6386 gen_jmp(s, tval);
6387 }
6388 break;
6389 case 0x9a: /* lcall im */
6390 {
6391 unsigned int selector, offset;
6392
6393 if (CODE64(s))
6394 goto illegal_op;
6395 ot = dflag ? OT_LONG : OT_WORD;
6396 offset = insn_get(env, s, ot);
6397 selector = insn_get(env, s, OT_WORD);
6398
6399 gen_op_movl_T0_im(selector);
6400 gen_op_movl_T1_imu(offset);
6401 }
6402 goto do_lcall;
6403 case 0xe9: /* jmp im */
6404 if (dflag)
6405 tval = (int32_t)insn_get(env, s, OT_LONG);
6406 else
6407 tval = (int16_t)insn_get(env, s, OT_WORD);
6408 tval += s->pc - s->cs_base;
6409 if (s->dflag == 0)
6410 tval &= 0xffff;
6411 else if(!CODE64(s))
6412 tval &= 0xffffffff;
6413 gen_jmp(s, tval);
6414 break;
6415 case 0xea: /* ljmp im */
6416 {
6417 unsigned int selector, offset;
6418
6419 if (CODE64(s))
6420 goto illegal_op;
6421 ot = dflag ? OT_LONG : OT_WORD;
6422 offset = insn_get(env, s, ot);
6423 selector = insn_get(env, s, OT_WORD);
6424
6425 gen_op_movl_T0_im(selector);
6426 gen_op_movl_T1_imu(offset);
6427 }
6428 goto do_ljmp;
6429 case 0xeb: /* jmp Jb */
6430 tval = (int8_t)insn_get(env, s, OT_BYTE);
6431 tval += s->pc - s->cs_base;
6432 if (s->dflag == 0)
6433 tval &= 0xffff;
6434 gen_jmp(s, tval);
6435 break;
6436 case 0x70 ... 0x7f: /* jcc Jb */
6437 tval = (int8_t)insn_get(env, s, OT_BYTE);
6438 goto do_jcc;
6439 case 0x180 ... 0x18f: /* jcc Jv */
6440 if (dflag) {
6441 tval = (int32_t)insn_get(env, s, OT_LONG);
6442 } else {
6443 tval = (int16_t)insn_get(env, s, OT_WORD);
6444 }
6445 do_jcc:
6446 next_eip = s->pc - s->cs_base;
6447 tval += next_eip;
6448 if (s->dflag == 0)
6449 tval &= 0xffff;
6450 gen_jcc(s, b, tval, next_eip);
6451 break;
6452
6453 case 0x190 ... 0x19f: /* setcc Gv */
6454 modrm = cpu_ldub_code(env, s->pc++);
6455 gen_setcc1(s, b, cpu_T[0]);
6456 gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1);
6457 break;
6458 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6459 ot = dflag + OT_WORD;
6460 modrm = cpu_ldub_code(env, s->pc++);
6461 reg = ((modrm >> 3) & 7) | rex_r;
6462 gen_cmovcc1(env, s, ot, b, modrm, reg);
6463 break;
6464
6465 /************************/
6466 /* flags */
6467 case 0x9c: /* pushf */
6468 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6469 if (s->vm86 && s->iopl != 3) {
6470 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6471 } else {
6472 gen_update_cc_op(s);
6473 gen_helper_read_eflags(cpu_T[0], cpu_env);
6474 gen_push_T0(s);
6475 }
6476 break;
6477 case 0x9d: /* popf */
6478 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6479 if (s->vm86 && s->iopl != 3) {
6480 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6481 } else {
6482 gen_pop_T0(s);
6483 if (s->cpl == 0) {
6484 if (s->dflag) {
6485 gen_helper_write_eflags(cpu_env, cpu_T[0],
6486 tcg_const_i32((TF_MASK | AC_MASK |
6487 ID_MASK | NT_MASK |
6488 IF_MASK |
6489 IOPL_MASK)));
6490 } else {
6491 gen_helper_write_eflags(cpu_env, cpu_T[0],
6492 tcg_const_i32((TF_MASK | AC_MASK |
6493 ID_MASK | NT_MASK |
6494 IF_MASK | IOPL_MASK)
6495 & 0xffff));
6496 }
6497 } else {
6498 if (s->cpl <= s->iopl) {
6499 if (s->dflag) {
6500 gen_helper_write_eflags(cpu_env, cpu_T[0],
6501 tcg_const_i32((TF_MASK |
6502 AC_MASK |
6503 ID_MASK |
6504 NT_MASK |
6505 IF_MASK)));
6506 } else {
6507 gen_helper_write_eflags(cpu_env, cpu_T[0],
6508 tcg_const_i32((TF_MASK |
6509 AC_MASK |
6510 ID_MASK |
6511 NT_MASK |
6512 IF_MASK)
6513 & 0xffff));
6514 }
6515 } else {
6516 if (s->dflag) {
6517 gen_helper_write_eflags(cpu_env, cpu_T[0],
6518 tcg_const_i32((TF_MASK | AC_MASK |
6519 ID_MASK | NT_MASK)));
6520 } else {
6521 gen_helper_write_eflags(cpu_env, cpu_T[0],
6522 tcg_const_i32((TF_MASK | AC_MASK |
6523 ID_MASK | NT_MASK)
6524 & 0xffff));
6525 }
6526 }
6527 }
6528 gen_pop_update(s);
6529 set_cc_op(s, CC_OP_EFLAGS);
6530 /* abort translation because TF/AC flag may change */
6531 gen_jmp_im(s->pc - s->cs_base);
6532 gen_eob(s);
6533 }
6534 break;
6535 case 0x9e: /* sahf */
6536 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6537 goto illegal_op;
6538 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6539 gen_compute_eflags(s);
6540 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6541 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6542 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6543 break;
6544 case 0x9f: /* lahf */
6545 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6546 goto illegal_op;
6547 gen_compute_eflags(s);
6548 /* Note: gen_compute_eflags() only gives the condition codes */
6549 tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
6550 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6551 break;
6552 case 0xf5: /* cmc */
6553 gen_compute_eflags(s);
6554 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6555 break;
6556 case 0xf8: /* clc */
6557 gen_compute_eflags(s);
6558 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6559 break;
6560 case 0xf9: /* stc */
6561 gen_compute_eflags(s);
6562 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6563 break;
6564 case 0xfc: /* cld */
6565 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6566 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6567 break;
6568 case 0xfd: /* std */
6569 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6570 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6571 break;
6572
6573 /************************/
6574 /* bit operations */
6575 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6576 ot = dflag + OT_WORD;
6577 modrm = cpu_ldub_code(env, s->pc++);
6578 op = (modrm >> 3) & 7;
6579 mod = (modrm >> 6) & 3;
6580 rm = (modrm & 7) | REX_B(s);
6581 if (mod != 3) {
6582 s->rip_offset = 1;
6583 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6584 gen_op_ld_T0_A0(ot + s->mem_index);
6585 } else {
6586 gen_op_mov_TN_reg(ot, 0, rm);
6587 }
6588 /* load shift */
6589 val = cpu_ldub_code(env, s->pc++);
6590 gen_op_movl_T1_im(val);
6591 if (op < 4)
6592 goto illegal_op;
6593 op -= 4;
6594 goto bt_op;
6595 case 0x1a3: /* bt Gv, Ev */
6596 op = 0;
6597 goto do_btx;
6598 case 0x1ab: /* bts */
6599 op = 1;
6600 goto do_btx;
6601 case 0x1b3: /* btr */
6602 op = 2;
6603 goto do_btx;
6604 case 0x1bb: /* btc */
6605 op = 3;
6606 do_btx:
6607 ot = dflag + OT_WORD;
6608 modrm = cpu_ldub_code(env, s->pc++);
6609 reg = ((modrm >> 3) & 7) | rex_r;
6610 mod = (modrm >> 6) & 3;
6611 rm = (modrm & 7) | REX_B(s);
6612 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6613 if (mod != 3) {
6614 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6615 /* specific case: we need to add a displacement */
6616 gen_exts(ot, cpu_T[1]);
6617 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6618 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6619 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6620 gen_op_ld_T0_A0(ot + s->mem_index);
6621 } else {
6622 gen_op_mov_TN_reg(ot, 0, rm);
6623 }
6624 bt_op:
6625 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6626 switch(op) {
6627 case 0:
6628 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6629 tcg_gen_movi_tl(cpu_cc_dst, 0);
6630 break;
6631 case 1:
6632 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6633 tcg_gen_movi_tl(cpu_tmp0, 1);
6634 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6635 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6636 break;
6637 case 2:
6638 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6639 tcg_gen_movi_tl(cpu_tmp0, 1);
6640 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6641 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6642 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6643 break;
6644 default:
6645 case 3:
6646 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6647 tcg_gen_movi_tl(cpu_tmp0, 1);
6648 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6649 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6650 break;
6651 }
6652 set_cc_op(s, CC_OP_SARB + ot);
6653 if (op != 0) {
6654 if (mod != 3)
6655 gen_op_st_T0_A0(ot + s->mem_index);
6656 else
6657 gen_op_mov_reg_T0(ot, rm);
6658 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6659 tcg_gen_movi_tl(cpu_cc_dst, 0);
6660 }
6661 break;
6662 case 0x1bc: /* bsf */
6663 case 0x1bd: /* bsr */
6664 {
6665 int label1;
6666 TCGv t0;
6667
6668 ot = dflag + OT_WORD;
6669 modrm = cpu_ldub_code(env, s->pc++);
6670 reg = ((modrm >> 3) & 7) | rex_r;
6671 gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0);
6672 gen_extu(ot, cpu_T[0]);
6673 t0 = tcg_temp_local_new();
6674 tcg_gen_mov_tl(t0, cpu_T[0]);
6675 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6676 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6677 switch(ot) {
6678 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6679 tcg_const_i32(16)); break;
6680 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6681 tcg_const_i32(32)); break;
6682 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6683 tcg_const_i32(64)); break;
6684 }
6685 gen_op_mov_reg_T0(ot, reg);
6686 } else {
6687 label1 = gen_new_label();
6688 tcg_gen_movi_tl(cpu_cc_dst, 0);
6689 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6690 if (b & 1) {
6691 gen_helper_bsr(cpu_T[0], t0);
6692 } else {
6693 gen_helper_bsf(cpu_T[0], t0);
6694 }
6695 gen_op_mov_reg_T0(ot, reg);
6696 tcg_gen_movi_tl(cpu_cc_dst, 1);
6697 gen_set_label(label1);
6698 set_cc_op(s, CC_OP_LOGICB + ot);
6699 }
6700 tcg_temp_free(t0);
6701 }
6702 break;
6703 /************************/
6704 /* bcd */
6705 case 0x27: /* daa */
6706 if (CODE64(s))
6707 goto illegal_op;
6708 gen_update_cc_op(s);
6709 gen_helper_daa(cpu_env);
6710 set_cc_op(s, CC_OP_EFLAGS);
6711 break;
6712 case 0x2f: /* das */
6713 if (CODE64(s))
6714 goto illegal_op;
6715 gen_update_cc_op(s);
6716 gen_helper_das(cpu_env);
6717 set_cc_op(s, CC_OP_EFLAGS);
6718 break;
6719 case 0x37: /* aaa */
6720 if (CODE64(s))
6721 goto illegal_op;
6722 gen_update_cc_op(s);
6723 gen_helper_aaa(cpu_env);
6724 set_cc_op(s, CC_OP_EFLAGS);
6725 break;
6726 case 0x3f: /* aas */
6727 if (CODE64(s))
6728 goto illegal_op;
6729 gen_update_cc_op(s);
6730 gen_helper_aas(cpu_env);
6731 set_cc_op(s, CC_OP_EFLAGS);
6732 break;
6733 case 0xd4: /* aam */
6734 if (CODE64(s))
6735 goto illegal_op;
6736 val = cpu_ldub_code(env, s->pc++);
6737 if (val == 0) {
6738 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6739 } else {
6740 gen_helper_aam(cpu_env, tcg_const_i32(val));
6741 set_cc_op(s, CC_OP_LOGICB);
6742 }
6743 break;
6744 case 0xd5: /* aad */
6745 if (CODE64(s))
6746 goto illegal_op;
6747 val = cpu_ldub_code(env, s->pc++);
6748 gen_helper_aad(cpu_env, tcg_const_i32(val));
6749 set_cc_op(s, CC_OP_LOGICB);
6750 break;
6751 /************************/
6752 /* misc */
6753 case 0x90: /* nop */
6754 /* XXX: correct lock test for all insn */
6755 if (prefixes & PREFIX_LOCK) {
6756 goto illegal_op;
6757 }
6758 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6759 if (REX_B(s)) {
6760 goto do_xchg_reg_eax;
6761 }
6762 if (prefixes & PREFIX_REPZ) {
6763 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6764 }
6765 break;
6766 case 0x9b: /* fwait */
6767 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6768 (HF_MP_MASK | HF_TS_MASK)) {
6769 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6770 } else {
6771 gen_update_cc_op(s);
6772 gen_jmp_im(pc_start - s->cs_base);
6773 gen_helper_fwait(cpu_env);
6774 }
6775 break;
6776 case 0xcc: /* int3 */
6777 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6778 break;
6779 case 0xcd: /* int N */
6780 val = cpu_ldub_code(env, s->pc++);
6781 if (s->vm86 && s->iopl != 3) {
6782 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6783 } else {
6784 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6785 }
6786 break;
6787 case 0xce: /* into */
6788 if (CODE64(s))
6789 goto illegal_op;
6790 gen_update_cc_op(s);
6791 gen_jmp_im(pc_start - s->cs_base);
6792 gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start));
6793 break;
6794 #ifdef WANT_ICEBP
6795 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6796 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6797 #if 1
6798 gen_debug(s, pc_start - s->cs_base);
6799 #else
6800 /* start debug */
6801 tb_flush(env);
6802 qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6803 #endif
6804 break;
6805 #endif
6806 case 0xfa: /* cli */
6807 if (!s->vm86) {
6808 if (s->cpl <= s->iopl) {
6809 gen_helper_cli(cpu_env);
6810 } else {
6811 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6812 }
6813 } else {
6814 if (s->iopl == 3) {
6815 gen_helper_cli(cpu_env);
6816 } else {
6817 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6818 }
6819 }
6820 break;
6821 case 0xfb: /* sti */
6822 if (!s->vm86) {
6823 if (s->cpl <= s->iopl) {
6824 gen_sti:
6825 gen_helper_sti(cpu_env);
6826 /* interruptions are enabled only the first insn after sti */
6827 /* If several instructions disable interrupts, only the
6828 _first_ does it */
6829 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6830 gen_helper_set_inhibit_irq(cpu_env);
6831 /* give a chance to handle pending irqs */
6832 gen_jmp_im(s->pc - s->cs_base);
6833 gen_eob(s);
6834 } else {
6835 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6836 }
6837 } else {
6838 if (s->iopl == 3) {
6839 goto gen_sti;
6840 } else {
6841 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6842 }
6843 }
6844 break;
6845 case 0x62: /* bound */
6846 if (CODE64(s))
6847 goto illegal_op;
6848 ot = dflag ? OT_LONG : OT_WORD;
6849 modrm = cpu_ldub_code(env, s->pc++);
6850 reg = (modrm >> 3) & 7;
6851 mod = (modrm >> 6) & 3;
6852 if (mod == 3)
6853 goto illegal_op;
6854 gen_op_mov_TN_reg(ot, 0, reg);
6855 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6856 gen_jmp_im(pc_start - s->cs_base);
6857 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6858 if (ot == OT_WORD) {
6859 gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
6860 } else {
6861 gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
6862 }
6863 break;
6864 case 0x1c8 ... 0x1cf: /* bswap reg */
6865 reg = (b & 7) | REX_B(s);
6866 #ifdef TARGET_X86_64
6867 if (dflag == 2) {
6868 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6869 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6870 gen_op_mov_reg_T0(OT_QUAD, reg);
6871 } else
6872 #endif
6873 {
6874 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6875 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6876 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6877 gen_op_mov_reg_T0(OT_LONG, reg);
6878 }
6879 break;
6880 case 0xd6: /* salc */
6881 if (CODE64(s))
6882 goto illegal_op;
6883 gen_compute_eflags_c(s, cpu_T[0]);
6884 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6885 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6886 break;
6887 case 0xe0: /* loopnz */
6888 case 0xe1: /* loopz */
6889 case 0xe2: /* loop */
6890 case 0xe3: /* jecxz */
6891 {
6892 int l1, l2, l3;
6893
6894 tval = (int8_t)insn_get(env, s, OT_BYTE);
6895 next_eip = s->pc - s->cs_base;
6896 tval += next_eip;
6897 if (s->dflag == 0)
6898 tval &= 0xffff;
6899
6900 l1 = gen_new_label();
6901 l2 = gen_new_label();
6902 l3 = gen_new_label();
6903 b &= 3;
6904 switch(b) {
6905 case 0: /* loopnz */
6906 case 1: /* loopz */
6907 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6908 gen_op_jz_ecx(s->aflag, l3);
6909 gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
6910 break;
6911 case 2: /* loop */
6912 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6913 gen_op_jnz_ecx(s->aflag, l1);
6914 break;
6915 default:
6916 case 3: /* jcxz */
6917 gen_op_jz_ecx(s->aflag, l1);
6918 break;
6919 }
6920
6921 gen_set_label(l3);
6922 gen_jmp_im(next_eip);
6923 tcg_gen_br(l2);
6924
6925 gen_set_label(l1);
6926 gen_jmp_im(tval);
6927 gen_set_label(l2);
6928 gen_eob(s);
6929 }
6930 break;
6931 case 0x130: /* wrmsr */
6932 case 0x132: /* rdmsr */
6933 if (s->cpl != 0) {
6934 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6935 } else {
6936 gen_update_cc_op(s);
6937 gen_jmp_im(pc_start - s->cs_base);
6938 if (b & 2) {
6939 gen_helper_rdmsr(cpu_env);
6940 } else {
6941 gen_helper_wrmsr(cpu_env);
6942 }
6943 }
6944 break;
6945 case 0x131: /* rdtsc */
6946 gen_update_cc_op(s);
6947 gen_jmp_im(pc_start - s->cs_base);
6948 if (use_icount)
6949 gen_io_start();
6950 gen_helper_rdtsc(cpu_env);
6951 if (use_icount) {
6952 gen_io_end();
6953 gen_jmp(s, s->pc - s->cs_base);
6954 }
6955 break;
6956 case 0x133: /* rdpmc */
6957 gen_update_cc_op(s);
6958 gen_jmp_im(pc_start - s->cs_base);
6959 gen_helper_rdpmc(cpu_env);
6960 break;
6961 case 0x134: /* sysenter */
6962 /* For Intel SYSENTER is valid on 64-bit */
6963 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6964 goto illegal_op;
6965 if (!s->pe) {
6966 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6967 } else {
6968 gen_update_cc_op(s);
6969 gen_jmp_im(pc_start - s->cs_base);
6970 gen_helper_sysenter(cpu_env);
6971 gen_eob(s);
6972 }
6973 break;
6974 case 0x135: /* sysexit */
6975 /* For Intel SYSEXIT is valid on 64-bit */
6976 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
6977 goto illegal_op;
6978 if (!s->pe) {
6979 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6980 } else {
6981 gen_update_cc_op(s);
6982 gen_jmp_im(pc_start - s->cs_base);
6983 gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
6984 gen_eob(s);
6985 }
6986 break;
6987 #ifdef TARGET_X86_64
6988 case 0x105: /* syscall */
6989 /* XXX: is it usable in real mode ? */
6990 gen_update_cc_op(s);
6991 gen_jmp_im(pc_start - s->cs_base);
6992 gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start));
6993 gen_eob(s);
6994 break;
6995 case 0x107: /* sysret */
6996 if (!s->pe) {
6997 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6998 } else {
6999 gen_update_cc_op(s);
7000 gen_jmp_im(pc_start - s->cs_base);
7001 gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
7002 /* condition codes are modified only in long mode */
7003 if (s->lma) {
7004 set_cc_op(s, CC_OP_EFLAGS);
7005 }
7006 gen_eob(s);
7007 }
7008 break;
7009 #endif
7010 case 0x1a2: /* cpuid */
7011 gen_update_cc_op(s);
7012 gen_jmp_im(pc_start - s->cs_base);
7013 gen_helper_cpuid(cpu_env);
7014 break;
7015 case 0xf4: /* hlt */
7016 if (s->cpl != 0) {
7017 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7018 } else {
7019 gen_update_cc_op(s);
7020 gen_jmp_im(pc_start - s->cs_base);
7021 gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));
7022 s->is_jmp = DISAS_TB_JUMP;
7023 }
7024 break;
7025 case 0x100:
7026 modrm = cpu_ldub_code(env, s->pc++);
7027 mod = (modrm >> 6) & 3;
7028 op = (modrm >> 3) & 7;
7029 switch(op) {
7030 case 0: /* sldt */
7031 if (!s->pe || s->vm86)
7032 goto illegal_op;
7033 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7034 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7035 ot = OT_WORD;
7036 if (mod == 3)
7037 ot += s->dflag;
7038 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7039 break;
7040 case 2: /* lldt */
7041 if (!s->pe || s->vm86)
7042 goto illegal_op;
7043 if (s->cpl != 0) {
7044 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7045 } else {
7046 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7047 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7048 gen_jmp_im(pc_start - s->cs_base);
7049 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7050 gen_helper_lldt(cpu_env, cpu_tmp2_i32);
7051 }
7052 break;
7053 case 1: /* str */
7054 if (!s->pe || s->vm86)
7055 goto illegal_op;
7056 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7057 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7058 ot = OT_WORD;
7059 if (mod == 3)
7060 ot += s->dflag;
7061 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7062 break;
7063 case 3: /* ltr */
7064 if (!s->pe || s->vm86)
7065 goto illegal_op;
7066 if (s->cpl != 0) {
7067 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7068 } else {
7069 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7070 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7071 gen_jmp_im(pc_start - s->cs_base);
7072 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7073 gen_helper_ltr(cpu_env, cpu_tmp2_i32);
7074 }
7075 break;
7076 case 4: /* verr */
7077 case 5: /* verw */
7078 if (!s->pe || s->vm86)
7079 goto illegal_op;
7080 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7081 gen_update_cc_op(s);
7082 if (op == 4) {
7083 gen_helper_verr(cpu_env, cpu_T[0]);
7084 } else {
7085 gen_helper_verw(cpu_env, cpu_T[0]);
7086 }
7087 set_cc_op(s, CC_OP_EFLAGS);
7088 break;
7089 default:
7090 goto illegal_op;
7091 }
7092 break;
7093 case 0x101:
7094 modrm = cpu_ldub_code(env, s->pc++);
7095 mod = (modrm >> 6) & 3;
7096 op = (modrm >> 3) & 7;
7097 rm = modrm & 7;
7098 switch(op) {
7099 case 0: /* sgdt */
7100 if (mod == 3)
7101 goto illegal_op;
7102 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7103 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7104 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7105 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7106 gen_add_A0_im(s, 2);
7107 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7108 if (!s->dflag)
7109 gen_op_andl_T0_im(0xffffff);
7110 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7111 break;
7112 case 1:
7113 if (mod == 3) {
7114 switch (rm) {
7115 case 0: /* monitor */
7116 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7117 s->cpl != 0)
7118 goto illegal_op;
7119 gen_update_cc_op(s);
7120 gen_jmp_im(pc_start - s->cs_base);
7121 #ifdef TARGET_X86_64
7122 if (s->aflag == 2) {
7123 gen_op_movq_A0_reg(R_EAX);
7124 } else
7125 #endif
7126 {
7127 gen_op_movl_A0_reg(R_EAX);
7128 if (s->aflag == 0)
7129 gen_op_andl_A0_ffff();
7130 }
7131 gen_add_A0_ds_seg(s);
7132 gen_helper_monitor(cpu_env, cpu_A0);
7133 break;
7134 case 1: /* mwait */
7135 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7136 s->cpl != 0)
7137 goto illegal_op;
7138 gen_update_cc_op(s);
7139 gen_jmp_im(pc_start - s->cs_base);
7140 gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start));
7141 gen_eob(s);
7142 break;
7143 case 2: /* clac */
7144 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7145 s->cpl != 0) {
7146 goto illegal_op;
7147 }
7148 gen_helper_clac(cpu_env);
7149 gen_jmp_im(s->pc - s->cs_base);
7150 gen_eob(s);
7151 break;
7152 case 3: /* stac */
7153 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7154 s->cpl != 0) {
7155 goto illegal_op;
7156 }
7157 gen_helper_stac(cpu_env);
7158 gen_jmp_im(s->pc - s->cs_base);
7159 gen_eob(s);
7160 break;
7161 default:
7162 goto illegal_op;
7163 }
7164 } else { /* sidt */
7165 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7166 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7167 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7168 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7169 gen_add_A0_im(s, 2);
7170 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7171 if (!s->dflag)
7172 gen_op_andl_T0_im(0xffffff);
7173 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7174 }
7175 break;
7176 case 2: /* lgdt */
7177 case 3: /* lidt */
7178 if (mod == 3) {
7179 gen_update_cc_op(s);
7180 gen_jmp_im(pc_start - s->cs_base);
7181 switch(rm) {
7182 case 0: /* VMRUN */
7183 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7184 goto illegal_op;
7185 if (s->cpl != 0) {
7186 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7187 break;
7188 } else {
7189 gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag),
7190 tcg_const_i32(s->pc - pc_start));
7191 tcg_gen_exit_tb(0);
7192 s->is_jmp = DISAS_TB_JUMP;
7193 }
7194 break;
7195 case 1: /* VMMCALL */
7196 if (!(s->flags & HF_SVME_MASK))
7197 goto illegal_op;
7198 gen_helper_vmmcall(cpu_env);
7199 break;
7200 case 2: /* VMLOAD */
7201 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7202 goto illegal_op;
7203 if (s->cpl != 0) {
7204 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7205 break;
7206 } else {
7207 gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag));
7208 }
7209 break;
7210 case 3: /* VMSAVE */
7211 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7212 goto illegal_op;
7213 if (s->cpl != 0) {
7214 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7215 break;
7216 } else {
7217 gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag));
7218 }
7219 break;
7220 case 4: /* STGI */
7221 if ((!(s->flags & HF_SVME_MASK) &&
7222 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7223 !s->pe)
7224 goto illegal_op;
7225 if (s->cpl != 0) {
7226 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7227 break;
7228 } else {
7229 gen_helper_stgi(cpu_env);
7230 }
7231 break;
7232 case 5: /* CLGI */
7233 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7234 goto illegal_op;
7235 if (s->cpl != 0) {
7236 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7237 break;
7238 } else {
7239 gen_helper_clgi(cpu_env);
7240 }
7241 break;
7242 case 6: /* SKINIT */
7243 if ((!(s->flags & HF_SVME_MASK) &&
7244 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7245 !s->pe)
7246 goto illegal_op;
7247 gen_helper_skinit(cpu_env);
7248 break;
7249 case 7: /* INVLPGA */
7250 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7251 goto illegal_op;
7252 if (s->cpl != 0) {
7253 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7254 break;
7255 } else {
7256 gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag));
7257 }
7258 break;
7259 default:
7260 goto illegal_op;
7261 }
7262 } else if (s->cpl != 0) {
7263 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7264 } else {
7265 gen_svm_check_intercept(s, pc_start,
7266 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7267 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7268 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7269 gen_add_A0_im(s, 2);
7270 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7271 if (!s->dflag)
7272 gen_op_andl_T0_im(0xffffff);
7273 if (op == 2) {
7274 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7275 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7276 } else {
7277 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7278 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7279 }
7280 }
7281 break;
7282 case 4: /* smsw */
7283 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7284 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7285 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7286 #else
7287 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7288 #endif
7289 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1);
7290 break;
7291 case 6: /* lmsw */
7292 if (s->cpl != 0) {
7293 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7294 } else {
7295 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7296 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7297 gen_helper_lmsw(cpu_env, cpu_T[0]);
7298 gen_jmp_im(s->pc - s->cs_base);
7299 gen_eob(s);
7300 }
7301 break;
7302 case 7:
7303 if (mod != 3) { /* invlpg */
7304 if (s->cpl != 0) {
7305 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7306 } else {
7307 gen_update_cc_op(s);
7308 gen_jmp_im(pc_start - s->cs_base);
7309 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7310 gen_helper_invlpg(cpu_env, cpu_A0);
7311 gen_jmp_im(s->pc - s->cs_base);
7312 gen_eob(s);
7313 }
7314 } else {
7315 switch (rm) {
7316 case 0: /* swapgs */
7317 #ifdef TARGET_X86_64
7318 if (CODE64(s)) {
7319 if (s->cpl != 0) {
7320 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7321 } else {
7322 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7323 offsetof(CPUX86State,segs[R_GS].base));
7324 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7325 offsetof(CPUX86State,kernelgsbase));
7326 tcg_gen_st_tl(cpu_T[1], cpu_env,
7327 offsetof(CPUX86State,segs[R_GS].base));
7328 tcg_gen_st_tl(cpu_T[0], cpu_env,
7329 offsetof(CPUX86State,kernelgsbase));
7330 }
7331 } else
7332 #endif
7333 {
7334 goto illegal_op;
7335 }
7336 break;
7337 case 1: /* rdtscp */
7338 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7339 goto illegal_op;
7340 gen_update_cc_op(s);
7341 gen_jmp_im(pc_start - s->cs_base);
7342 if (use_icount)
7343 gen_io_start();
7344 gen_helper_rdtscp(cpu_env);
7345 if (use_icount) {
7346 gen_io_end();
7347 gen_jmp(s, s->pc - s->cs_base);
7348 }
7349 break;
7350 default:
7351 goto illegal_op;
7352 }
7353 }
7354 break;
7355 default:
7356 goto illegal_op;
7357 }
7358 break;
7359 case 0x108: /* invd */
7360 case 0x109: /* wbinvd */
7361 if (s->cpl != 0) {
7362 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7363 } else {
7364 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7365 /* nothing to do */
7366 }
7367 break;
7368 case 0x63: /* arpl or movslS (x86_64) */
7369 #ifdef TARGET_X86_64
7370 if (CODE64(s)) {
7371 int d_ot;
7372 /* d_ot is the size of destination */
7373 d_ot = dflag + OT_WORD;
7374
7375 modrm = cpu_ldub_code(env, s->pc++);
7376 reg = ((modrm >> 3) & 7) | rex_r;
7377 mod = (modrm >> 6) & 3;
7378 rm = (modrm & 7) | REX_B(s);
7379
7380 if (mod == 3) {
7381 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7382 /* sign extend */
7383 if (d_ot == OT_QUAD)
7384 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7385 gen_op_mov_reg_T0(d_ot, reg);
7386 } else {
7387 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7388 if (d_ot == OT_QUAD) {
7389 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7390 } else {
7391 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7392 }
7393 gen_op_mov_reg_T0(d_ot, reg);
7394 }
7395 } else
7396 #endif
7397 {
7398 int label1;
7399 TCGv t0, t1, t2, a0;
7400
7401 if (!s->pe || s->vm86)
7402 goto illegal_op;
7403 t0 = tcg_temp_local_new();
7404 t1 = tcg_temp_local_new();
7405 t2 = tcg_temp_local_new();
7406 ot = OT_WORD;
7407 modrm = cpu_ldub_code(env, s->pc++);
7408 reg = (modrm >> 3) & 7;
7409 mod = (modrm >> 6) & 3;
7410 rm = modrm & 7;
7411 if (mod != 3) {
7412 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7413 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7414 a0 = tcg_temp_local_new();
7415 tcg_gen_mov_tl(a0, cpu_A0);
7416 } else {
7417 gen_op_mov_v_reg(ot, t0, rm);
7418 TCGV_UNUSED(a0);
7419 }
7420 gen_op_mov_v_reg(ot, t1, reg);
7421 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7422 tcg_gen_andi_tl(t1, t1, 3);
7423 tcg_gen_movi_tl(t2, 0);
7424 label1 = gen_new_label();
7425 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7426 tcg_gen_andi_tl(t0, t0, ~3);
7427 tcg_gen_or_tl(t0, t0, t1);
7428 tcg_gen_movi_tl(t2, CC_Z);
7429 gen_set_label(label1);
7430 if (mod != 3) {
7431 gen_op_st_v(ot + s->mem_index, t0, a0);
7432 tcg_temp_free(a0);
7433 } else {
7434 gen_op_mov_reg_v(ot, rm, t0);
7435 }
7436 gen_compute_eflags(s);
7437 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7438 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7439 tcg_temp_free(t0);
7440 tcg_temp_free(t1);
7441 tcg_temp_free(t2);
7442 }
7443 break;
7444 case 0x102: /* lar */
7445 case 0x103: /* lsl */
7446 {
7447 int label1;
7448 TCGv t0;
7449 if (!s->pe || s->vm86)
7450 goto illegal_op;
7451 ot = dflag ? OT_LONG : OT_WORD;
7452 modrm = cpu_ldub_code(env, s->pc++);
7453 reg = ((modrm >> 3) & 7) | rex_r;
7454 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7455 t0 = tcg_temp_local_new();
7456 gen_update_cc_op(s);
7457 if (b == 0x102) {
7458 gen_helper_lar(t0, cpu_env, cpu_T[0]);
7459 } else {
7460 gen_helper_lsl(t0, cpu_env, cpu_T[0]);
7461 }
7462 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7463 label1 = gen_new_label();
7464 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7465 gen_op_mov_reg_v(ot, reg, t0);
7466 gen_set_label(label1);
7467 set_cc_op(s, CC_OP_EFLAGS);
7468 tcg_temp_free(t0);
7469 }
7470 break;
7471 case 0x118:
7472 modrm = cpu_ldub_code(env, s->pc++);
7473 mod = (modrm >> 6) & 3;
7474 op = (modrm >> 3) & 7;
7475 switch(op) {
7476 case 0: /* prefetchnta */
7477 case 1: /* prefetchnt0 */
7478 case 2: /* prefetchnt0 */
7479 case 3: /* prefetchnt0 */
7480 if (mod == 3)
7481 goto illegal_op;
7482 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7483 /* nothing more to do */
7484 break;
7485 default: /* nop (multi byte) */
7486 gen_nop_modrm(env, s, modrm);
7487 break;
7488 }
7489 break;
7490 case 0x119 ... 0x11f: /* nop (multi byte) */
7491 modrm = cpu_ldub_code(env, s->pc++);
7492 gen_nop_modrm(env, s, modrm);
7493 break;
7494 case 0x120: /* mov reg, crN */
7495 case 0x122: /* mov crN, reg */
7496 if (s->cpl != 0) {
7497 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7498 } else {
7499 modrm = cpu_ldub_code(env, s->pc++);
7500 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7501 * AMD documentation (24594.pdf) and testing of
7502 * intel 386 and 486 processors all show that the mod bits
7503 * are assumed to be 1's, regardless of actual values.
7504 */
7505 rm = (modrm & 7) | REX_B(s);
7506 reg = ((modrm >> 3) & 7) | rex_r;
7507 if (CODE64(s))
7508 ot = OT_QUAD;
7509 else
7510 ot = OT_LONG;
7511 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7512 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7513 reg = 8;
7514 }
7515 switch(reg) {
7516 case 0:
7517 case 2:
7518 case 3:
7519 case 4:
7520 case 8:
7521 gen_update_cc_op(s);
7522 gen_jmp_im(pc_start - s->cs_base);
7523 if (b & 2) {
7524 gen_op_mov_TN_reg(ot, 0, rm);
7525 gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
7526 cpu_T[0]);
7527 gen_jmp_im(s->pc - s->cs_base);
7528 gen_eob(s);
7529 } else {
7530 gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
7531 gen_op_mov_reg_T0(ot, rm);
7532 }
7533 break;
7534 default:
7535 goto illegal_op;
7536 }
7537 }
7538 break;
7539 case 0x121: /* mov reg, drN */
7540 case 0x123: /* mov drN, reg */
7541 if (s->cpl != 0) {
7542 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7543 } else {
7544 modrm = cpu_ldub_code(env, s->pc++);
7545 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7546 * AMD documentation (24594.pdf) and testing of
7547 * intel 386 and 486 processors all show that the mod bits
7548 * are assumed to be 1's, regardless of actual values.
7549 */
7550 rm = (modrm & 7) | REX_B(s);
7551 reg = ((modrm >> 3) & 7) | rex_r;
7552 if (CODE64(s))
7553 ot = OT_QUAD;
7554 else
7555 ot = OT_LONG;
7556 /* XXX: do it dynamically with CR4.DE bit */
7557 if (reg == 4 || reg == 5 || reg >= 8)
7558 goto illegal_op;
7559 if (b & 2) {
7560 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7561 gen_op_mov_TN_reg(ot, 0, rm);
7562 gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
7563 gen_jmp_im(s->pc - s->cs_base);
7564 gen_eob(s);
7565 } else {
7566 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7567 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7568 gen_op_mov_reg_T0(ot, rm);
7569 }
7570 }
7571 break;
7572 case 0x106: /* clts */
7573 if (s->cpl != 0) {
7574 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7575 } else {
7576 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7577 gen_helper_clts(cpu_env);
7578 /* abort block because static cpu state changed */
7579 gen_jmp_im(s->pc - s->cs_base);
7580 gen_eob(s);
7581 }
7582 break;
7583 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7584 case 0x1c3: /* MOVNTI reg, mem */
7585 if (!(s->cpuid_features & CPUID_SSE2))
7586 goto illegal_op;
7587 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7588 modrm = cpu_ldub_code(env, s->pc++);
7589 mod = (modrm >> 6) & 3;
7590 if (mod == 3)
7591 goto illegal_op;
7592 reg = ((modrm >> 3) & 7) | rex_r;
7593 /* generate a generic store */
7594 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
7595 break;
7596 case 0x1ae:
7597 modrm = cpu_ldub_code(env, s->pc++);
7598 mod = (modrm >> 6) & 3;
7599 op = (modrm >> 3) & 7;
7600 switch(op) {
7601 case 0: /* fxsave */
7602 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7603 (s->prefix & PREFIX_LOCK))
7604 goto illegal_op;
7605 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7606 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7607 break;
7608 }
7609 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7610 gen_update_cc_op(s);
7611 gen_jmp_im(pc_start - s->cs_base);
7612 gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
7613 break;
7614 case 1: /* fxrstor */
7615 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7616 (s->prefix & PREFIX_LOCK))
7617 goto illegal_op;
7618 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7619 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7620 break;
7621 }
7622 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7623 gen_update_cc_op(s);
7624 gen_jmp_im(pc_start - s->cs_base);
7625 gen_helper_fxrstor(cpu_env, cpu_A0,
7626 tcg_const_i32((s->dflag == 2)));
7627 break;
7628 case 2: /* ldmxcsr */
7629 case 3: /* stmxcsr */
7630 if (s->flags & HF_TS_MASK) {
7631 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7632 break;
7633 }
7634 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7635 mod == 3)
7636 goto illegal_op;
7637 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7638 if (op == 2) {
7639 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7640 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7641 gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
7642 } else {
7643 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7644 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7645 }
7646 break;
7647 case 5: /* lfence */
7648 case 6: /* mfence */
7649 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7650 goto illegal_op;
7651 break;
7652 case 7: /* sfence / clflush */
7653 if ((modrm & 0xc7) == 0xc0) {
7654 /* sfence */
7655 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7656 if (!(s->cpuid_features & CPUID_SSE))
7657 goto illegal_op;
7658 } else {
7659 /* clflush */
7660 if (!(s->cpuid_features & CPUID_CLFLUSH))
7661 goto illegal_op;
7662 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7663 }
7664 break;
7665 default:
7666 goto illegal_op;
7667 }
7668 break;
7669 case 0x10d: /* 3DNow! prefetch(w) */
7670 modrm = cpu_ldub_code(env, s->pc++);
7671 mod = (modrm >> 6) & 3;
7672 if (mod == 3)
7673 goto illegal_op;
7674 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7675 /* ignore for now */
7676 break;
7677 case 0x1aa: /* rsm */
7678 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7679 if (!(s->flags & HF_SMM_MASK))
7680 goto illegal_op;
7681 gen_update_cc_op(s);
7682 gen_jmp_im(s->pc - s->cs_base);
7683 gen_helper_rsm(cpu_env);
7684 gen_eob(s);
7685 break;
7686 case 0x1b8: /* SSE4.2 popcnt */
7687 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7688 PREFIX_REPZ)
7689 goto illegal_op;
7690 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7691 goto illegal_op;
7692
7693 modrm = cpu_ldub_code(env, s->pc++);
7694 reg = ((modrm >> 3) & 7) | rex_r;
7695
7696 if (s->prefix & PREFIX_DATA)
7697 ot = OT_WORD;
7698 else if (s->dflag != 2)
7699 ot = OT_LONG;
7700 else
7701 ot = OT_QUAD;
7702
7703 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
7704 gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
7705 gen_op_mov_reg_T0(ot, reg);
7706
7707 set_cc_op(s, CC_OP_EFLAGS);
7708 break;
7709 case 0x10e ... 0x10f:
7710 /* 3DNow! instructions, ignore prefixes */
7711 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7712 case 0x110 ... 0x117:
7713 case 0x128 ... 0x12f:
7714 case 0x138 ... 0x13a:
7715 case 0x150 ... 0x179:
7716 case 0x17c ... 0x17f:
7717 case 0x1c2:
7718 case 0x1c4 ... 0x1c6:
7719 case 0x1d0 ... 0x1fe:
7720 gen_sse(env, s, b, pc_start, rex_r);
7721 break;
7722 default:
7723 goto illegal_op;
7724 }
7725 /* lock generation */
7726 if (s->prefix & PREFIX_LOCK)
7727 gen_helper_unlock();
7728 return s->pc;
7729 illegal_op:
7730 if (s->prefix & PREFIX_LOCK)
7731 gen_helper_unlock();
7732 /* XXX: ensure that no lock was generated */
7733 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7734 return s->pc;
7735 }
7736
7737 void optimize_flags_init(void)
7738 {
7739 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7740 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7741 offsetof(CPUX86State, cc_op), "cc_op");
7742 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7743 "cc_src");
7744 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7745 "cc_dst");
7746
7747 #ifdef TARGET_X86_64
7748 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7749 offsetof(CPUX86State, regs[R_EAX]), "rax");
7750 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7751 offsetof(CPUX86State, regs[R_ECX]), "rcx");
7752 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7753 offsetof(CPUX86State, regs[R_EDX]), "rdx");
7754 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7755 offsetof(CPUX86State, regs[R_EBX]), "rbx");
7756 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7757 offsetof(CPUX86State, regs[R_ESP]), "rsp");
7758 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7759 offsetof(CPUX86State, regs[R_EBP]), "rbp");
7760 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7761 offsetof(CPUX86State, regs[R_ESI]), "rsi");
7762 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7763 offsetof(CPUX86State, regs[R_EDI]), "rdi");
7764 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7765 offsetof(CPUX86State, regs[8]), "r8");
7766 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7767 offsetof(CPUX86State, regs[9]), "r9");
7768 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7769 offsetof(CPUX86State, regs[10]), "r10");
7770 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7771 offsetof(CPUX86State, regs[11]), "r11");
7772 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7773 offsetof(CPUX86State, regs[12]), "r12");
7774 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7775 offsetof(CPUX86State, regs[13]), "r13");
7776 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7777 offsetof(CPUX86State, regs[14]), "r14");
7778 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7779 offsetof(CPUX86State, regs[15]), "r15");
7780 #else
7781 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7782 offsetof(CPUX86State, regs[R_EAX]), "eax");
7783 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7784 offsetof(CPUX86State, regs[R_ECX]), "ecx");
7785 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7786 offsetof(CPUX86State, regs[R_EDX]), "edx");
7787 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7788 offsetof(CPUX86State, regs[R_EBX]), "ebx");
7789 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7790 offsetof(CPUX86State, regs[R_ESP]), "esp");
7791 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7792 offsetof(CPUX86State, regs[R_EBP]), "ebp");
7793 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7794 offsetof(CPUX86State, regs[R_ESI]), "esi");
7795 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7796 offsetof(CPUX86State, regs[R_EDI]), "edi");
7797 #endif
7798
7799 /* register helpers */
7800 #define GEN_HELPER 2
7801 #include "helper.h"
7802 }
7803
7804 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7805 basic block 'tb'. If search_pc is TRUE, also generate PC
7806 information for each intermediate instruction. */
7807 static inline void gen_intermediate_code_internal(CPUX86State *env,
7808 TranslationBlock *tb,
7809 int search_pc)
7810 {
7811 DisasContext dc1, *dc = &dc1;
7812 target_ulong pc_ptr;
7813 uint16_t *gen_opc_end;
7814 CPUBreakpoint *bp;
7815 int j, lj;
7816 uint64_t flags;
7817 target_ulong pc_start;
7818 target_ulong cs_base;
7819 int num_insns;
7820 int max_insns;
7821
7822 /* generate intermediate code */
7823 pc_start = tb->pc;
7824 cs_base = tb->cs_base;
7825 flags = tb->flags;
7826
7827 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7828 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7829 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7830 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7831 dc->f_st = 0;
7832 dc->vm86 = (flags >> VM_SHIFT) & 1;
7833 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7834 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7835 dc->tf = (flags >> TF_SHIFT) & 1;
7836 dc->singlestep_enabled = env->singlestep_enabled;
7837 dc->cc_op = CC_OP_DYNAMIC;
7838 dc->cc_op_dirty = false;
7839 dc->cs_base = cs_base;
7840 dc->tb = tb;
7841 dc->popl_esp_hack = 0;
7842 /* select memory access functions */
7843 dc->mem_index = 0;
7844 if (flags & HF_SOFTMMU_MASK) {
7845 dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
7846 }
7847 dc->cpuid_features = env->cpuid_features;
7848 dc->cpuid_ext_features = env->cpuid_ext_features;
7849 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7850 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7851 dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features;
7852 #ifdef TARGET_X86_64
7853 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7854 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7855 #endif
7856 dc->flags = flags;
7857 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7858 (flags & HF_INHIBIT_IRQ_MASK)
7859 #ifndef CONFIG_SOFTMMU
7860 || (flags & HF_SOFTMMU_MASK)
7861 #endif
7862 );
7863 #if 0
7864 /* check addseg logic */
7865 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7866 printf("ERROR addseg\n");
7867 #endif
7868
7869 cpu_T[0] = tcg_temp_new();
7870 cpu_T[1] = tcg_temp_new();
7871 cpu_A0 = tcg_temp_new();
7872 cpu_T3 = tcg_temp_new();
7873
7874 cpu_tmp0 = tcg_temp_new();
7875 cpu_tmp1_i64 = tcg_temp_new_i64();
7876 cpu_tmp2_i32 = tcg_temp_new_i32();
7877 cpu_tmp3_i32 = tcg_temp_new_i32();
7878 cpu_tmp4 = tcg_temp_new();
7879 cpu_tmp5 = tcg_temp_new();
7880 cpu_ptr0 = tcg_temp_new_ptr();
7881 cpu_ptr1 = tcg_temp_new_ptr();
7882
7883 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
7884
7885 dc->is_jmp = DISAS_NEXT;
7886 pc_ptr = pc_start;
7887 lj = -1;
7888 num_insns = 0;
7889 max_insns = tb->cflags & CF_COUNT_MASK;
7890 if (max_insns == 0)
7891 max_insns = CF_COUNT_MASK;
7892
7893 gen_icount_start();
7894 for(;;) {
7895 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7896 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7897 if (bp->pc == pc_ptr &&
7898 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7899 gen_debug(dc, pc_ptr - dc->cs_base);
7900 break;
7901 }
7902 }
7903 }
7904 if (search_pc) {
7905 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
7906 if (lj < j) {
7907 lj++;
7908 while (lj < j)
7909 tcg_ctx.gen_opc_instr_start[lj++] = 0;
7910 }
7911 tcg_ctx.gen_opc_pc[lj] = pc_ptr;
7912 gen_opc_cc_op[lj] = dc->cc_op;
7913 tcg_ctx.gen_opc_instr_start[lj] = 1;
7914 tcg_ctx.gen_opc_icount[lj] = num_insns;
7915 }
7916 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7917 gen_io_start();
7918
7919 pc_ptr = disas_insn(env, dc, pc_ptr);
7920 num_insns++;
7921 /* stop translation if indicated */
7922 if (dc->is_jmp)
7923 break;
7924 /* if single step mode, we generate only one instruction and
7925 generate an exception */
7926 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7927 the flag and abort the translation to give the irqs a
7928 change to be happen */
7929 if (dc->tf || dc->singlestep_enabled ||
7930 (flags & HF_INHIBIT_IRQ_MASK)) {
7931 gen_jmp_im(pc_ptr - dc->cs_base);
7932 gen_eob(dc);
7933 break;
7934 }
7935 /* if too long translation, stop generation too */
7936 if (tcg_ctx.gen_opc_ptr >= gen_opc_end ||
7937 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7938 num_insns >= max_insns) {
7939 gen_jmp_im(pc_ptr - dc->cs_base);
7940 gen_eob(dc);
7941 break;
7942 }
7943 if (singlestep) {
7944 gen_jmp_im(pc_ptr - dc->cs_base);
7945 gen_eob(dc);
7946 break;
7947 }
7948 }
7949 if (tb->cflags & CF_LAST_IO)
7950 gen_io_end();
7951 gen_icount_end(tb, num_insns);
7952 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
7953 /* we don't forget to fill the last values */
7954 if (search_pc) {
7955 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
7956 lj++;
7957 while (lj <= j)
7958 tcg_ctx.gen_opc_instr_start[lj++] = 0;
7959 }
7960
7961 #ifdef DEBUG_DISAS
7962 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
7963 int disas_flags;
7964 qemu_log("----------------\n");
7965 qemu_log("IN: %s\n", lookup_symbol(pc_start));
7966 #ifdef TARGET_X86_64
7967 if (dc->code64)
7968 disas_flags = 2;
7969 else
7970 #endif
7971 disas_flags = !dc->code32;
7972 log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags);
7973 qemu_log("\n");
7974 }
7975 #endif
7976
7977 if (!search_pc) {
7978 tb->size = pc_ptr - pc_start;
7979 tb->icount = num_insns;
7980 }
7981 }
7982
7983 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
7984 {
7985 gen_intermediate_code_internal(env, tb, 0);
7986 }
7987
7988 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
7989 {
7990 gen_intermediate_code_internal(env, tb, 1);
7991 }
7992
7993 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
7994 {
7995 int cc_op;
7996 #ifdef DEBUG_DISAS
7997 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
7998 int i;
7999 qemu_log("RESTORE:\n");
8000 for(i = 0;i <= pc_pos; i++) {
8001 if (tcg_ctx.gen_opc_instr_start[i]) {
8002 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i,
8003 tcg_ctx.gen_opc_pc[i]);
8004 }
8005 }
8006 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
8007 pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base,
8008 (uint32_t)tb->cs_base);
8009 }
8010 #endif
8011 env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base;
8012 cc_op = gen_opc_cc_op[pc_pos];
8013 if (cc_op != CC_OP_DYNAMIC)
8014 env->cc_op = cc_op;
8015 }
Qemu copy for testing