4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "disas/disas.h"
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
41 #define CODE64(s) ((s)->code64)
42 #define REX_X(s) ((s)->rex_x)
43 #define REX_B(s) ((s)->rex_b)
50 //#define MACRO_TEST 1
52 /* global register indexes */
53 static TCGv_ptr cpu_env
;
54 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
;
55 static TCGv_i32 cpu_cc_op
;
56 static TCGv cpu_regs
[CPU_NB_REGS
];
58 static TCGv cpu_T
[2], cpu_T3
;
59 /* local register indexes (only used inside old micro ops) */
60 static TCGv cpu_tmp0
, cpu_tmp4
;
61 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
62 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
63 static TCGv_i64 cpu_tmp1_i64
;
66 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
68 #include "exec/gen-icount.h"
71 static int x86_64_hregs
;
74 typedef struct DisasContext
{
75 /* current insn context */
76 int override
; /* -1 if no override */
79 target_ulong pc
; /* pc = eip + cs_base */
80 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base
; /* base of CS segment */
84 int pe
; /* protected mode */
85 int code32
; /* 32 bit code segment */
87 int lma
; /* long mode active */
88 int code64
; /* 64 bit code segment */
91 int ss32
; /* 32 bit stack segment */
92 CCOp cc_op
; /* current CC operation */
94 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
95 int f_st
; /* currently unused */
96 int vm86
; /* vm86 mode */
99 int tf
; /* TF cpu flag */
100 int singlestep_enabled
; /* "hardware" single step enabled */
101 int jmp_opt
; /* use direct block chaining for direct jumps */
102 int mem_index
; /* select memory access functions */
103 uint64_t flags
; /* all execution flags */
104 struct TranslationBlock
*tb
;
105 int popl_esp_hack
; /* for correct popl with esp base handling */
106 int rip_offset
; /* only used in x86_64, but left for simplicity */
108 int cpuid_ext_features
;
109 int cpuid_ext2_features
;
110 int cpuid_ext3_features
;
111 int cpuid_7_0_ebx_features
;
114 static void gen_eob(DisasContext
*s
);
115 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
116 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
118 /* i386 arith/logic operations */
138 OP_SHL1
, /* undocumented */
162 /* I386 int registers */
163 OR_EAX
, /* MUST be even numbered */
172 OR_TMP0
= 16, /* temporary operand register */
174 OR_A0
, /* temporary register used when doing address evaluation */
182 /* Bit set if the global variable is live after setting CC_OP to X. */
183 static const uint8_t cc_op_live
[CC_OP_NB
] = {
184 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
,
185 [CC_OP_EFLAGS
] = USES_CC_SRC
,
186 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
187 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
188 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
,
189 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
,
190 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
,
191 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
192 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
193 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
194 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
198 static void set_cc_op(DisasContext
*s
, CCOp op
)
202 if (s
->cc_op
== op
) {
206 /* Discard CC computation that will no longer be used. */
207 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
208 if (dead
& USES_CC_DST
) {
209 tcg_gen_discard_tl(cpu_cc_dst
);
211 if (dead
& USES_CC_SRC
) {
212 tcg_gen_discard_tl(cpu_cc_src
);
216 /* The DYNAMIC setting is translator only, and should never be
217 stored. Thus we always consider it clean. */
218 s
->cc_op_dirty
= (op
!= CC_OP_DYNAMIC
);
221 static void gen_update_cc_op(DisasContext
*s
)
223 if (s
->cc_op_dirty
) {
224 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
225 s
->cc_op_dirty
= false;
229 static inline void gen_op_movl_T0_0(void)
231 tcg_gen_movi_tl(cpu_T
[0], 0);
234 static inline void gen_op_movl_T0_im(int32_t val
)
236 tcg_gen_movi_tl(cpu_T
[0], val
);
239 static inline void gen_op_movl_T0_imu(uint32_t val
)
241 tcg_gen_movi_tl(cpu_T
[0], val
);
244 static inline void gen_op_movl_T1_im(int32_t val
)
246 tcg_gen_movi_tl(cpu_T
[1], val
);
249 static inline void gen_op_movl_T1_imu(uint32_t val
)
251 tcg_gen_movi_tl(cpu_T
[1], val
);
254 static inline void gen_op_movl_A0_im(uint32_t val
)
256 tcg_gen_movi_tl(cpu_A0
, val
);
260 static inline void gen_op_movq_A0_im(int64_t val
)
262 tcg_gen_movi_tl(cpu_A0
, val
);
266 static inline void gen_movtl_T0_im(target_ulong val
)
268 tcg_gen_movi_tl(cpu_T
[0], val
);
271 static inline void gen_movtl_T1_im(target_ulong val
)
273 tcg_gen_movi_tl(cpu_T
[1], val
);
276 static inline void gen_op_andl_T0_ffff(void)
278 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
281 static inline void gen_op_andl_T0_im(uint32_t val
)
283 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
286 static inline void gen_op_movl_T0_T1(void)
288 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
291 static inline void gen_op_andl_A0_ffff(void)
293 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
298 #define NB_OP_SIZES 4
300 #else /* !TARGET_X86_64 */
302 #define NB_OP_SIZES 3
304 #endif /* !TARGET_X86_64 */
306 #if defined(HOST_WORDS_BIGENDIAN)
307 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
308 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
309 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
310 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
311 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
313 #define REG_B_OFFSET 0
314 #define REG_H_OFFSET 1
315 #define REG_W_OFFSET 0
316 #define REG_L_OFFSET 0
317 #define REG_LH_OFFSET 4
320 /* In instruction encodings for byte register accesses the
321 * register number usually indicates "low 8 bits of register N";
322 * however there are some special cases where N 4..7 indicates
323 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
324 * true for this special case, false otherwise.
326 static inline bool byte_reg_is_xH(int reg
)
332 if (reg
>= 8 || x86_64_hregs
) {
339 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
343 if (!byte_reg_is_xH(reg
)) {
344 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
346 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
350 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
352 default: /* XXX this shouldn't be reached; abort? */
354 /* For x86_64, this sets the higher half of register to zero.
355 For i386, this is equivalent to a mov. */
356 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
360 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
366 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
368 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
371 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
373 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
376 static inline void gen_op_mov_reg_A0(int size
, int reg
)
380 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
382 default: /* XXX this shouldn't be reached; abort? */
384 /* For x86_64, this sets the higher half of register to zero.
385 For i386, this is equivalent to a mov. */
386 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
390 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
396 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
398 if (ot
== OT_BYTE
&& byte_reg_is_xH(reg
)) {
399 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
400 tcg_gen_ext8u_tl(t0
, t0
);
402 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
406 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
408 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
411 static inline void gen_op_movl_A0_reg(int reg
)
413 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
416 static inline void gen_op_addl_A0_im(int32_t val
)
418 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
420 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
425 static inline void gen_op_addq_A0_im(int64_t val
)
427 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
431 static void gen_add_A0_im(DisasContext
*s
, int val
)
435 gen_op_addq_A0_im(val
);
438 gen_op_addl_A0_im(val
);
441 static inline void gen_op_addl_T0_T1(void)
443 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
446 static inline void gen_op_jmp_T0(void)
448 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
451 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
455 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
456 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
459 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
460 /* For x86_64, this sets the higher half of register to zero.
461 For i386, this is equivalent to a nop. */
462 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
463 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
467 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
473 static inline void gen_op_add_reg_T0(int size
, int reg
)
477 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
478 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
481 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
482 /* For x86_64, this sets the higher half of register to zero.
483 For i386, this is equivalent to a nop. */
484 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
485 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
489 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
495 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
497 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
499 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
500 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
501 /* For x86_64, this sets the higher half of register to zero.
502 For i386, this is equivalent to a nop. */
503 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
506 static inline void gen_op_movl_A0_seg(int reg
)
508 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
511 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
513 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
516 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
517 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
519 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
520 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
523 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
528 static inline void gen_op_movq_A0_seg(int reg
)
530 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
533 static inline void gen_op_addq_A0_seg(int reg
)
535 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
536 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
539 static inline void gen_op_movq_A0_reg(int reg
)
541 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
544 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
546 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
548 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
549 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
553 static inline void gen_op_lds_T0_A0(int idx
)
555 int mem_index
= (idx
>> 2) - 1;
558 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
561 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
565 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
570 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
572 int mem_index
= (idx
>> 2) - 1;
575 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
578 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
581 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
585 /* Should never happen on 32-bit targets. */
587 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
593 /* XXX: always use ldu or lds */
594 static inline void gen_op_ld_T0_A0(int idx
)
596 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
599 static inline void gen_op_ldu_T0_A0(int idx
)
601 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
604 static inline void gen_op_ld_T1_A0(int idx
)
606 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
609 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
611 int mem_index
= (idx
>> 2) - 1;
614 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
617 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
620 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
624 /* Should never happen on 32-bit targets. */
626 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
632 static inline void gen_op_st_T0_A0(int idx
)
634 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
637 static inline void gen_op_st_T1_A0(int idx
)
639 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
642 static inline void gen_jmp_im(target_ulong pc
)
644 tcg_gen_movi_tl(cpu_tmp0
, pc
);
645 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
648 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
652 override
= s
->override
;
656 gen_op_movq_A0_seg(override
);
657 gen_op_addq_A0_reg_sN(0, R_ESI
);
659 gen_op_movq_A0_reg(R_ESI
);
665 if (s
->addseg
&& override
< 0)
668 gen_op_movl_A0_seg(override
);
669 gen_op_addl_A0_reg_sN(0, R_ESI
);
671 gen_op_movl_A0_reg(R_ESI
);
674 /* 16 address, always override */
677 gen_op_movl_A0_reg(R_ESI
);
678 gen_op_andl_A0_ffff();
679 gen_op_addl_A0_seg(s
, override
);
683 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
687 gen_op_movq_A0_reg(R_EDI
);
692 gen_op_movl_A0_seg(R_ES
);
693 gen_op_addl_A0_reg_sN(0, R_EDI
);
695 gen_op_movl_A0_reg(R_EDI
);
698 gen_op_movl_A0_reg(R_EDI
);
699 gen_op_andl_A0_ffff();
700 gen_op_addl_A0_seg(s
, R_ES
);
704 static inline void gen_op_movl_T0_Dshift(int ot
)
706 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
707 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
710 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
715 tcg_gen_ext8s_tl(dst
, src
);
717 tcg_gen_ext8u_tl(dst
, src
);
722 tcg_gen_ext16s_tl(dst
, src
);
724 tcg_gen_ext16u_tl(dst
, src
);
730 tcg_gen_ext32s_tl(dst
, src
);
732 tcg_gen_ext32u_tl(dst
, src
);
741 static void gen_extu(int ot
, TCGv reg
)
743 gen_ext_tl(reg
, reg
, ot
, false);
746 static void gen_exts(int ot
, TCGv reg
)
748 gen_ext_tl(reg
, reg
, ot
, true);
751 static inline void gen_op_jnz_ecx(int size
, int label1
)
753 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
754 gen_extu(size
+ 1, cpu_tmp0
);
755 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
758 static inline void gen_op_jz_ecx(int size
, int label1
)
760 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
761 gen_extu(size
+ 1, cpu_tmp0
);
762 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
765 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
769 gen_helper_inb(v
, n
);
772 gen_helper_inw(v
, n
);
775 gen_helper_inl(v
, n
);
780 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
784 gen_helper_outb(v
, n
);
787 gen_helper_outw(v
, n
);
790 gen_helper_outl(v
, n
);
795 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
799 target_ulong next_eip
;
802 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
806 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
809 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
812 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
815 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
819 if(s
->flags
& HF_SVMI_MASK
) {
824 svm_flags
|= (1 << (4 + ot
));
825 next_eip
= s
->pc
- s
->cs_base
;
826 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
827 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
828 tcg_const_i32(svm_flags
),
829 tcg_const_i32(next_eip
- cur_eip
));
833 static inline void gen_movs(DisasContext
*s
, int ot
)
835 gen_string_movl_A0_ESI(s
);
836 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
837 gen_string_movl_A0_EDI(s
);
838 gen_op_st_T0_A0(ot
+ s
->mem_index
);
839 gen_op_movl_T0_Dshift(ot
);
840 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
841 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
844 static void gen_op_update1_cc(void)
846 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
849 static void gen_op_update2_cc(void)
851 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
852 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
855 static inline void gen_op_cmpl_T0_T1_cc(void)
857 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
858 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
861 static inline void gen_op_testl_T0_T1_cc(void)
863 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
866 static void gen_op_update_neg_cc(void)
868 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
869 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
872 /* compute all eflags to cc_src */
873 static void gen_compute_eflags(DisasContext
*s
)
875 if (s
->cc_op
== CC_OP_EFLAGS
) {
879 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
880 set_cc_op(s
, CC_OP_EFLAGS
);
881 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
884 /* compute eflags.C to reg */
885 static void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
, bool inv
)
891 case CC_OP_SUBB
... CC_OP_SUBQ
:
892 /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
893 size
= s
->cc_op
- CC_OP_SUBB
;
894 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
895 /* If no temporary was used, be careful not to alias t1 and t0. */
896 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
897 tcg_gen_add_tl(t0
, cpu_cc_dst
, cpu_cc_src
);
901 case CC_OP_ADDB
... CC_OP_ADDQ
:
902 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
903 size
= s
->cc_op
- CC_OP_ADDB
;
904 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
905 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
907 tcg_gen_setcond_tl(inv
? TCG_COND_GEU
: TCG_COND_LTU
, reg
, t0
, t1
);
911 case CC_OP_SBBB
... CC_OP_SBBQ
:
912 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
913 size
= s
->cc_op
- CC_OP_SBBB
;
914 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
915 if (TCGV_EQUAL(t1
, reg
) && TCGV_EQUAL(reg
, cpu_cc_src
)) {
916 tcg_gen_mov_tl(cpu_tmp0
, cpu_cc_src
);
920 tcg_gen_add_tl(reg
, cpu_cc_dst
, cpu_cc_src
);
921 tcg_gen_addi_tl(reg
, reg
, 1);
926 case CC_OP_ADCB
... CC_OP_ADCQ
:
927 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
928 size
= s
->cc_op
- CC_OP_ADCB
;
929 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
930 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
932 tcg_gen_setcond_tl(inv
? TCG_COND_GTU
: TCG_COND_LEU
, reg
, t0
, t1
);
936 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
937 tcg_gen_movi_tl(reg
, 0);
940 case CC_OP_INCB
... CC_OP_INCQ
:
941 case CC_OP_DECB
... CC_OP_DECQ
:
943 tcg_gen_xori_tl(reg
, cpu_cc_src
, 1);
945 tcg_gen_mov_tl(reg
, cpu_cc_src
);
950 case CC_OP_SHLB
... CC_OP_SHLQ
:
951 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
952 size
= s
->cc_op
- CC_OP_SHLB
;
953 tcg_gen_shri_tl(reg
, cpu_cc_src
, (8 << size
) - 1);
954 tcg_gen_andi_tl(reg
, reg
, 1);
957 case CC_OP_MULB
... CC_OP_MULQ
:
958 tcg_gen_setcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
964 case CC_OP_SARB
... CC_OP_SARQ
:
966 tcg_gen_andi_tl(reg
, cpu_cc_src
, 1);
970 /* The need to compute only C from CC_OP_DYNAMIC is important
971 in efficiently implementing e.g. INC at the start of a TB. */
973 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
974 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
978 tcg_gen_xori_tl(reg
, reg
, 1);
982 /* compute eflags.P to reg */
983 static void gen_compute_eflags_p(DisasContext
*s
, TCGv reg
)
985 gen_compute_eflags(s
);
986 tcg_gen_shri_tl(reg
, cpu_cc_src
, 2);
987 tcg_gen_andi_tl(reg
, reg
, 1);
990 /* compute eflags.S to reg */
991 static void gen_compute_eflags_s(DisasContext
*s
, TCGv reg
, bool inv
)
995 gen_compute_eflags(s
);
998 tcg_gen_shri_tl(reg
, cpu_cc_src
, 7);
999 tcg_gen_andi_tl(reg
, reg
, 1);
1001 tcg_gen_xori_tl(reg
, reg
, 1);
1006 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1007 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
1008 tcg_gen_setcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, reg
, t0
, 0);
1014 /* compute eflags.O to reg */
1015 static void gen_compute_eflags_o(DisasContext
*s
, TCGv reg
)
1017 gen_compute_eflags(s
);
1018 tcg_gen_shri_tl(reg
, cpu_cc_src
, 11);
1019 tcg_gen_andi_tl(reg
, reg
, 1);
1022 /* compute eflags.Z to reg */
1023 static void gen_compute_eflags_z(DisasContext
*s
, TCGv reg
, bool inv
)
1027 gen_compute_eflags(s
);
1030 tcg_gen_shri_tl(reg
, cpu_cc_src
, 6);
1031 tcg_gen_andi_tl(reg
, reg
, 1);
1033 tcg_gen_xori_tl(reg
, reg
, 1);
1038 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1039 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1040 tcg_gen_setcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, reg
, t0
, 0);
1046 static void gen_setcc_slow(DisasContext
*s
, int jcc_op
, TCGv reg
, bool inv
)
1048 assert(!TCGV_EQUAL(reg
, cpu_cc_src
));
1051 gen_compute_eflags_o(s
, reg
);
1054 gen_compute_eflags_c(s
, reg
, inv
);
1058 gen_compute_eflags_z(s
, reg
, inv
);
1062 gen_compute_eflags(s
);
1063 tcg_gen_andi_tl(reg
, cpu_cc_src
, CC_Z
| CC_C
);
1064 tcg_gen_setcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, reg
, reg
, 0);
1067 gen_compute_eflags_s(s
, reg
, inv
);
1071 gen_compute_eflags_p(s
, reg
);
1074 gen_compute_eflags(s
);
1075 tcg_gen_shri_tl(reg
, cpu_cc_src
, 11); /* CC_O */
1076 tcg_gen_shri_tl(cpu_tmp0
, cpu_cc_src
, 7); /* CC_S */
1077 tcg_gen_xor_tl(reg
, reg
, cpu_tmp0
);
1078 tcg_gen_andi_tl(reg
, reg
, 1);
1082 gen_compute_eflags(s
);
1083 tcg_gen_shri_tl(reg
, cpu_cc_src
, 11); /* CC_O */
1084 tcg_gen_shri_tl(cpu_tmp4
, cpu_cc_src
, 7); /* CC_S */
1085 tcg_gen_shri_tl(cpu_tmp0
, cpu_cc_src
, 6); /* CC_Z */
1086 tcg_gen_xor_tl(reg
, reg
, cpu_tmp4
);
1087 tcg_gen_or_tl(reg
, reg
, cpu_tmp0
);
1088 tcg_gen_andi_tl(reg
, reg
, 1);
1092 tcg_gen_xori_tl(reg
, reg
, 1);
1096 /* return true if setcc_slow is not needed (WARNING: must be kept in
1097 sync with gen_jcc1) */
1098 static int is_fast_jcc_case(DisasContext
*s
, int b
)
1101 jcc_op
= (b
>> 1) & 7;
1103 /* we optimize the cmp/jcc case */
1108 if (jcc_op
== JCC_O
|| jcc_op
== JCC_P
)
1112 /* some jumps are easy to compute */
1137 if (jcc_op
!= JCC_Z
&& jcc_op
!= JCC_S
)
1147 /* generate a conditional jump to label 'l1' according to jump opcode
1148 value 'b'. In the fast case, T0 is guaranted not to be used. */
1149 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1151 int inv
, jcc_op
, size
, cond
;
1155 jcc_op
= (b
>> 1) & 7;
1158 /* we optimize the cmp/jcc case */
1164 size
= s
->cc_op
- CC_OP_SUBB
;
1168 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_dst
, size
, false);
1169 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
1173 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_dst
, size
, true);
1174 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, t0
, 0, l1
);
1178 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1181 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1183 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1184 gen_extu(size
, cpu_tmp4
);
1185 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1186 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1190 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1193 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1195 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1196 gen_exts(size
, cpu_tmp4
);
1197 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1198 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1206 /* some jumps are easy to compute */
1248 size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1251 size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1259 gen_setcc_slow(s
, jcc_op
, cpu_T
[0], false);
1260 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1266 /* XXX: does not work with gdbstub "ice" single step - not a
1268 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1272 l1
= gen_new_label();
1273 l2
= gen_new_label();
1274 gen_op_jnz_ecx(s
->aflag
, l1
);
1276 gen_jmp_tb(s
, next_eip
, 1);
1281 static inline void gen_stos(DisasContext
*s
, int ot
)
1283 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1284 gen_string_movl_A0_EDI(s
);
1285 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1286 gen_op_movl_T0_Dshift(ot
);
1287 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1290 static inline void gen_lods(DisasContext
*s
, int ot
)
1292 gen_string_movl_A0_ESI(s
);
1293 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1294 gen_op_mov_reg_T0(ot
, R_EAX
);
1295 gen_op_movl_T0_Dshift(ot
);
1296 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1299 static inline void gen_scas(DisasContext
*s
, int ot
)
1301 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1302 gen_string_movl_A0_EDI(s
);
1303 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1304 gen_op_cmpl_T0_T1_cc();
1305 gen_op_movl_T0_Dshift(ot
);
1306 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1307 set_cc_op(s
, CC_OP_SUBB
+ ot
);
1310 static inline void gen_cmps(DisasContext
*s
, int ot
)
1312 gen_string_movl_A0_ESI(s
);
1313 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1314 gen_string_movl_A0_EDI(s
);
1315 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1316 gen_op_cmpl_T0_T1_cc();
1317 gen_op_movl_T0_Dshift(ot
);
1318 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1319 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1320 set_cc_op(s
, CC_OP_SUBB
+ ot
);
1323 static inline void gen_ins(DisasContext
*s
, int ot
)
1327 gen_string_movl_A0_EDI(s
);
1328 /* Note: we must do this dummy write first to be restartable in
1329 case of page fault. */
1331 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1332 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1334 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1335 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1336 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1337 gen_op_movl_T0_Dshift(ot
);
1338 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1343 static inline void gen_outs(DisasContext
*s
, int ot
)
1347 gen_string_movl_A0_ESI(s
);
1348 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1350 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1351 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1352 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1353 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1354 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1356 gen_op_movl_T0_Dshift(ot
);
1357 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1362 /* same method as Valgrind : we generate jumps to current or next
1364 #define GEN_REPZ(op) \
1365 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1366 target_ulong cur_eip, target_ulong next_eip) \
1369 gen_update_cc_op(s); \
1370 l2 = gen_jz_ecx_string(s, next_eip); \
1371 gen_ ## op(s, ot); \
1372 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1373 /* a loop would cause two single step exceptions if ECX = 1 \
1374 before rep string_insn */ \
1376 gen_op_jz_ecx(s->aflag, l2); \
1377 gen_jmp(s, cur_eip); \
1380 #define GEN_REPZ2(op) \
1381 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1382 target_ulong cur_eip, \
1383 target_ulong next_eip, \
1387 gen_update_cc_op(s); \
1388 l2 = gen_jz_ecx_string(s, next_eip); \
1389 gen_ ## op(s, ot); \
1390 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1391 gen_update_cc_op(s); \
1392 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1394 gen_op_jz_ecx(s->aflag, l2); \
1395 gen_jmp(s, cur_eip); \
1396 set_cc_op(s, CC_OP_DYNAMIC); \
1407 static void gen_helper_fp_arith_ST0_FT0(int op
)
1411 gen_helper_fadd_ST0_FT0(cpu_env
);
1414 gen_helper_fmul_ST0_FT0(cpu_env
);
1417 gen_helper_fcom_ST0_FT0(cpu_env
);
1420 gen_helper_fcom_ST0_FT0(cpu_env
);
1423 gen_helper_fsub_ST0_FT0(cpu_env
);
1426 gen_helper_fsubr_ST0_FT0(cpu_env
);
1429 gen_helper_fdiv_ST0_FT0(cpu_env
);
1432 gen_helper_fdivr_ST0_FT0(cpu_env
);
1437 /* NOTE the exception in "r" op ordering */
1438 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1440 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1443 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1446 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1449 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1452 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1455 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1458 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1463 /* if d == OR_TMP0, it means memory operand (address in A0) */
1464 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1467 gen_op_mov_TN_reg(ot
, 0, d
);
1469 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1473 gen_compute_eflags_c(s1
, cpu_tmp4
, false);
1474 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1475 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1477 gen_op_mov_reg_T0(ot
, d
);
1479 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1480 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1481 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1482 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1483 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1484 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1485 set_cc_op(s1
, CC_OP_DYNAMIC
);
1488 gen_compute_eflags_c(s1
, cpu_tmp4
, false);
1489 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1490 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1492 gen_op_mov_reg_T0(ot
, d
);
1494 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1495 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1496 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1497 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1498 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1499 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1500 set_cc_op(s1
, CC_OP_DYNAMIC
);
1503 gen_op_addl_T0_T1();
1505 gen_op_mov_reg_T0(ot
, d
);
1507 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1508 gen_op_update2_cc();
1509 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1512 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1514 gen_op_mov_reg_T0(ot
, d
);
1516 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1517 gen_op_update2_cc();
1518 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1522 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1524 gen_op_mov_reg_T0(ot
, d
);
1526 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1527 gen_op_update1_cc();
1528 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1531 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1533 gen_op_mov_reg_T0(ot
, d
);
1535 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1536 gen_op_update1_cc();
1537 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1540 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1542 gen_op_mov_reg_T0(ot
, d
);
1544 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1545 gen_op_update1_cc();
1546 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1549 gen_op_cmpl_T0_T1_cc();
1550 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1555 /* if d == OR_TMP0, it means memory operand (address in A0) */
1556 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1559 gen_op_mov_TN_reg(ot
, 0, d
);
1561 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1562 gen_compute_eflags_c(s1
, cpu_cc_src
, false);
1564 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1565 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1567 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1568 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1571 gen_op_mov_reg_T0(ot
, d
);
1573 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1574 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1577 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1578 int is_right
, int is_arith
)
1584 if (ot
== OT_QUAD
) {
1591 if (op1
== OR_TMP0
) {
1592 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1594 gen_op_mov_TN_reg(ot
, 0, op1
);
1597 t0
= tcg_temp_local_new();
1598 t1
= tcg_temp_local_new();
1599 t2
= tcg_temp_local_new();
1601 tcg_gen_andi_tl(t2
, cpu_T
[1], mask
);
1605 gen_exts(ot
, cpu_T
[0]);
1606 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1607 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], t2
);
1609 gen_extu(ot
, cpu_T
[0]);
1610 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1611 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], t2
);
1614 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1615 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], t2
);
1619 if (op1
== OR_TMP0
) {
1620 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1622 gen_op_mov_reg_T0(ot
, op1
);
1626 gen_update_cc_op(s
);
1628 tcg_gen_mov_tl(t1
, cpu_T
[0]);
1630 shift_label
= gen_new_label();
1631 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, shift_label
);
1633 tcg_gen_addi_tl(t2
, t2
, -1);
1634 tcg_gen_mov_tl(cpu_cc_dst
, t1
);
1638 tcg_gen_sar_tl(cpu_cc_src
, t0
, t2
);
1640 tcg_gen_shr_tl(cpu_cc_src
, t0
, t2
);
1643 tcg_gen_shl_tl(cpu_cc_src
, t0
, t2
);
1647 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1649 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1652 gen_set_label(shift_label
);
1653 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
1660 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1661 int is_right
, int is_arith
)
1672 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1674 gen_op_mov_TN_reg(ot
, 0, op1
);
1680 gen_exts(ot
, cpu_T
[0]);
1681 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1682 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1684 gen_extu(ot
, cpu_T
[0]);
1685 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1686 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1689 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1690 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1696 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1698 gen_op_mov_reg_T0(ot
, op1
);
1700 /* update eflags if non zero shift */
1702 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1703 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1704 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1708 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1711 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1713 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1716 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1720 int label1
, label2
, data_bits
;
1721 TCGv t0
, t1
, t2
, a0
;
1723 /* XXX: inefficient, but we must use local temps */
1724 t0
= tcg_temp_local_new();
1725 t1
= tcg_temp_local_new();
1726 t2
= tcg_temp_local_new();
1727 a0
= tcg_temp_local_new();
1735 if (op1
== OR_TMP0
) {
1736 tcg_gen_mov_tl(a0
, cpu_A0
);
1737 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1739 gen_op_mov_v_reg(ot
, t0
, op1
);
1742 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1744 tcg_gen_andi_tl(t1
, t1
, mask
);
1746 /* Must test zero case to avoid using undefined behaviour in TCG
1748 label1
= gen_new_label();
1749 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1752 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1754 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1757 tcg_gen_mov_tl(t2
, t0
);
1759 data_bits
= 8 << ot
;
1760 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1761 fix TCG definition) */
1763 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1764 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1765 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1767 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1768 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1769 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1771 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1773 gen_set_label(label1
);
1775 if (op1
== OR_TMP0
) {
1776 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1778 gen_op_mov_reg_v(ot
, op1
, t0
);
1781 /* update eflags. It is needed anyway most of the time, do it always. */
1782 gen_compute_eflags(s
);
1783 assert(s
->cc_op
== CC_OP_EFLAGS
);
1785 label2
= gen_new_label();
1786 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1788 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1789 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1790 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1791 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1792 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1794 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1796 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1797 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1799 gen_set_label(label2
);
1807 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1814 /* XXX: inefficient, but we must use local temps */
1815 t0
= tcg_temp_local_new();
1816 t1
= tcg_temp_local_new();
1817 a0
= tcg_temp_local_new();
1825 if (op1
== OR_TMP0
) {
1826 tcg_gen_mov_tl(a0
, cpu_A0
);
1827 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1829 gen_op_mov_v_reg(ot
, t0
, op1
);
1833 tcg_gen_mov_tl(t1
, t0
);
1836 data_bits
= 8 << ot
;
1838 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1840 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1841 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1844 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1845 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1847 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1851 if (op1
== OR_TMP0
) {
1852 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1854 gen_op_mov_reg_v(ot
, op1
, t0
);
1859 gen_compute_eflags(s
);
1860 assert(s
->cc_op
== CC_OP_EFLAGS
);
1862 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1863 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1864 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1865 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1866 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1868 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1870 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1871 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1879 /* XXX: add faster immediate = 1 case */
1880 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1883 gen_compute_eflags(s
);
1884 assert(s
->cc_op
== CC_OP_EFLAGS
);
1888 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1890 gen_op_mov_TN_reg(ot
, 0, op1
);
1895 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1898 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1901 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1903 #ifdef TARGET_X86_64
1905 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1912 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1915 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1918 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1920 #ifdef TARGET_X86_64
1922 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1929 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1931 gen_op_mov_reg_T0(ot
, op1
);
1934 /* XXX: add faster immediate case */
1935 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1938 int label1
, label2
, data_bits
;
1940 TCGv t0
, t1
, t2
, a0
;
1942 t0
= tcg_temp_local_new();
1943 t1
= tcg_temp_local_new();
1944 t2
= tcg_temp_local_new();
1945 a0
= tcg_temp_local_new();
1953 if (op1
== OR_TMP0
) {
1954 tcg_gen_mov_tl(a0
, cpu_A0
);
1955 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1957 gen_op_mov_v_reg(ot
, t0
, op1
);
1960 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1962 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1963 tcg_gen_mov_tl(t2
, cpu_T3
);
1965 /* Must test zero case to avoid using undefined behaviour in TCG
1967 label1
= gen_new_label();
1968 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1970 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1971 if (ot
== OT_WORD
) {
1972 /* Note: we implement the Intel behaviour for shift count > 16 */
1974 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1975 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1976 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1977 tcg_gen_ext32u_tl(t0
, t0
);
1979 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1981 /* only needed if count > 16, but a test would complicate */
1982 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1983 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1985 tcg_gen_shr_tl(t0
, t0
, t2
);
1987 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1989 /* XXX: not optimal */
1990 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1991 tcg_gen_shli_tl(t1
, t1
, 16);
1992 tcg_gen_or_tl(t1
, t1
, t0
);
1993 tcg_gen_ext32u_tl(t1
, t1
);
1995 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1996 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1997 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1998 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
2000 tcg_gen_shl_tl(t0
, t0
, t2
);
2001 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
2002 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
2003 tcg_gen_or_tl(t0
, t0
, t1
);
2006 data_bits
= 8 << ot
;
2009 tcg_gen_ext32u_tl(t0
, t0
);
2011 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2013 tcg_gen_shr_tl(t0
, t0
, t2
);
2014 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
2015 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
2016 tcg_gen_or_tl(t0
, t0
, t1
);
2020 tcg_gen_ext32u_tl(t1
, t1
);
2022 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2024 tcg_gen_shl_tl(t0
, t0
, t2
);
2025 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
2026 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
2027 tcg_gen_or_tl(t0
, t0
, t1
);
2030 tcg_gen_mov_tl(t1
, cpu_tmp4
);
2032 gen_set_label(label1
);
2034 if (op1
== OR_TMP0
) {
2035 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
2037 gen_op_mov_reg_v(ot
, op1
, t0
);
2041 gen_update_cc_op(s
);
2043 label2
= gen_new_label();
2044 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
2046 tcg_gen_mov_tl(cpu_cc_src
, t1
);
2047 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
2049 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
2051 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
2053 gen_set_label(label2
);
2054 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
2062 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
2065 gen_op_mov_TN_reg(ot
, 1, s
);
2068 gen_rot_rm_T1(s1
, ot
, d
, 0);
2071 gen_rot_rm_T1(s1
, ot
, d
, 1);
2075 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
2078 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
2081 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
2084 gen_rotc_rm_T1(s1
, ot
, d
, 0);
2087 gen_rotc_rm_T1(s1
, ot
, d
, 1);
2092 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
2096 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
2099 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
2103 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
2106 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
2109 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
2112 /* currently not optimized */
2113 gen_op_movl_T1_im(c
);
2114 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
2119 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2120 int *reg_ptr
, int *offset_ptr
)
2128 int mod
, rm
, code
, override
, must_add_seg
;
2130 override
= s
->override
;
2131 must_add_seg
= s
->addseg
;
2134 mod
= (modrm
>> 6) & 3;
2146 code
= cpu_ldub_code(env
, s
->pc
++);
2147 scale
= (code
>> 6) & 3;
2148 index
= ((code
>> 3) & 7) | REX_X(s
);
2155 if ((base
& 7) == 5) {
2157 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2159 if (CODE64(s
) && !havesib
) {
2160 disp
+= s
->pc
+ s
->rip_offset
;
2167 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2171 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2177 /* for correct popl handling with esp */
2178 if (base
== 4 && s
->popl_esp_hack
)
2179 disp
+= s
->popl_esp_hack
;
2180 #ifdef TARGET_X86_64
2181 if (s
->aflag
== 2) {
2182 gen_op_movq_A0_reg(base
);
2184 gen_op_addq_A0_im(disp
);
2189 gen_op_movl_A0_reg(base
);
2191 gen_op_addl_A0_im(disp
);
2194 #ifdef TARGET_X86_64
2195 if (s
->aflag
== 2) {
2196 gen_op_movq_A0_im(disp
);
2200 gen_op_movl_A0_im(disp
);
2203 /* index == 4 means no index */
2204 if (havesib
&& (index
!= 4)) {
2205 #ifdef TARGET_X86_64
2206 if (s
->aflag
== 2) {
2207 gen_op_addq_A0_reg_sN(scale
, index
);
2211 gen_op_addl_A0_reg_sN(scale
, index
);
2216 if (base
== R_EBP
|| base
== R_ESP
)
2221 #ifdef TARGET_X86_64
2222 if (s
->aflag
== 2) {
2223 gen_op_addq_A0_seg(override
);
2227 gen_op_addl_A0_seg(s
, override
);
2234 disp
= cpu_lduw_code(env
, s
->pc
);
2236 gen_op_movl_A0_im(disp
);
2237 rm
= 0; /* avoid SS override */
2244 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2248 disp
= cpu_lduw_code(env
, s
->pc
);
2254 gen_op_movl_A0_reg(R_EBX
);
2255 gen_op_addl_A0_reg_sN(0, R_ESI
);
2258 gen_op_movl_A0_reg(R_EBX
);
2259 gen_op_addl_A0_reg_sN(0, R_EDI
);
2262 gen_op_movl_A0_reg(R_EBP
);
2263 gen_op_addl_A0_reg_sN(0, R_ESI
);
2266 gen_op_movl_A0_reg(R_EBP
);
2267 gen_op_addl_A0_reg_sN(0, R_EDI
);
2270 gen_op_movl_A0_reg(R_ESI
);
2273 gen_op_movl_A0_reg(R_EDI
);
2276 gen_op_movl_A0_reg(R_EBP
);
2280 gen_op_movl_A0_reg(R_EBX
);
2284 gen_op_addl_A0_im(disp
);
2285 gen_op_andl_A0_ffff();
2289 if (rm
== 2 || rm
== 3 || rm
== 6)
2294 gen_op_addl_A0_seg(s
, override
);
2304 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2306 int mod
, rm
, base
, code
;
2308 mod
= (modrm
>> 6) & 3;
2318 code
= cpu_ldub_code(env
, s
->pc
++);
2354 /* used for LEA and MOV AX, mem */
2355 static void gen_add_A0_ds_seg(DisasContext
*s
)
2357 int override
, must_add_seg
;
2358 must_add_seg
= s
->addseg
;
2360 if (s
->override
>= 0) {
2361 override
= s
->override
;
2365 #ifdef TARGET_X86_64
2367 gen_op_addq_A0_seg(override
);
2371 gen_op_addl_A0_seg(s
, override
);
2376 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2378 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2379 int ot
, int reg
, int is_store
)
2381 int mod
, rm
, opreg
, disp
;
2383 mod
= (modrm
>> 6) & 3;
2384 rm
= (modrm
& 7) | REX_B(s
);
2388 gen_op_mov_TN_reg(ot
, 0, reg
);
2389 gen_op_mov_reg_T0(ot
, rm
);
2391 gen_op_mov_TN_reg(ot
, 0, rm
);
2393 gen_op_mov_reg_T0(ot
, reg
);
2396 gen_lea_modrm(env
, s
, modrm
, &opreg
, &disp
);
2399 gen_op_mov_TN_reg(ot
, 0, reg
);
2400 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2402 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2404 gen_op_mov_reg_T0(ot
, reg
);
2409 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2415 ret
= cpu_ldub_code(env
, s
->pc
);
2419 ret
= cpu_lduw_code(env
, s
->pc
);
2424 ret
= cpu_ldl_code(env
, s
->pc
);
2431 static inline int insn_const_size(unsigned int ot
)
2439 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2441 TranslationBlock
*tb
;
2444 pc
= s
->cs_base
+ eip
;
2446 /* NOTE: we handle the case where the TB spans two pages here */
2447 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2448 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2449 /* jump to same page: we can use a direct jump */
2450 tcg_gen_goto_tb(tb_num
);
2452 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
2454 /* jump to another page: currently not optimized */
2460 static inline void gen_jcc(DisasContext
*s
, int b
,
2461 target_ulong val
, target_ulong next_eip
)
2466 gen_update_cc_op(s
);
2467 l1
= gen_new_label();
2469 set_cc_op(s
, CC_OP_DYNAMIC
);
2471 gen_goto_tb(s
, 0, next_eip
);
2474 gen_goto_tb(s
, 1, val
);
2475 s
->is_jmp
= DISAS_TB_JUMP
;
2477 l1
= gen_new_label();
2478 l2
= gen_new_label();
2481 gen_jmp_im(next_eip
);
2491 static void gen_setcc(DisasContext
*s
, int b
)
2493 int inv
, jcc_op
, l1
;
2496 if (is_fast_jcc_case(s
, b
)) {
2497 /* nominal case: we use a jump */
2498 /* XXX: make it faster by adding new instructions in TCG */
2499 t0
= tcg_temp_local_new();
2500 tcg_gen_movi_tl(t0
, 0);
2501 l1
= gen_new_label();
2502 gen_jcc1(s
, b
^ 1, l1
);
2503 tcg_gen_movi_tl(t0
, 1);
2505 tcg_gen_mov_tl(cpu_T
[0], t0
);
2508 /* slow case: it is more efficient not to generate a jump,
2509 although it is questionnable whether this optimization is
2512 jcc_op
= (b
>> 1) & 7;
2513 gen_setcc_slow(s
, jcc_op
, cpu_T
[0], inv
);
2517 static inline void gen_op_movl_T0_seg(int seg_reg
)
2519 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2520 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2523 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2525 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2526 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2527 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2528 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2529 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2530 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2533 /* move T0 to seg_reg and compute if the CPU state may change. Never
2534 call this function with seg_reg == R_CS */
2535 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2537 if (s
->pe
&& !s
->vm86
) {
2538 /* XXX: optimize by finding processor state dynamically */
2539 gen_update_cc_op(s
);
2540 gen_jmp_im(cur_eip
);
2541 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2542 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2543 /* abort translation because the addseg value may change or
2544 because ss32 may change. For R_SS, translation must always
2545 stop as a special handling must be done to disable hardware
2546 interrupts for the next instruction */
2547 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2548 s
->is_jmp
= DISAS_TB_JUMP
;
2550 gen_op_movl_seg_T0_vm(seg_reg
);
2551 if (seg_reg
== R_SS
)
2552 s
->is_jmp
= DISAS_TB_JUMP
;
2556 static inline int svm_is_rep(int prefixes
)
2558 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2562 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2563 uint32_t type
, uint64_t param
)
2565 /* no SVM activated; fast case */
2566 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2568 gen_update_cc_op(s
);
2569 gen_jmp_im(pc_start
- s
->cs_base
);
2570 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2571 tcg_const_i64(param
));
2575 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2577 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2580 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2582 #ifdef TARGET_X86_64
2584 gen_op_add_reg_im(2, R_ESP
, addend
);
2588 gen_op_add_reg_im(1, R_ESP
, addend
);
2590 gen_op_add_reg_im(0, R_ESP
, addend
);
2594 /* generate a push. It depends on ss32, addseg and dflag */
2595 static void gen_push_T0(DisasContext
*s
)
2597 #ifdef TARGET_X86_64
2599 gen_op_movq_A0_reg(R_ESP
);
2601 gen_op_addq_A0_im(-8);
2602 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2604 gen_op_addq_A0_im(-2);
2605 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2607 gen_op_mov_reg_A0(2, R_ESP
);
2611 gen_op_movl_A0_reg(R_ESP
);
2613 gen_op_addl_A0_im(-2);
2615 gen_op_addl_A0_im(-4);
2618 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2619 gen_op_addl_A0_seg(s
, R_SS
);
2622 gen_op_andl_A0_ffff();
2623 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2624 gen_op_addl_A0_seg(s
, R_SS
);
2626 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2627 if (s
->ss32
&& !s
->addseg
)
2628 gen_op_mov_reg_A0(1, R_ESP
);
2630 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2634 /* generate a push. It depends on ss32, addseg and dflag */
2635 /* slower version for T1, only used for call Ev */
2636 static void gen_push_T1(DisasContext
*s
)
2638 #ifdef TARGET_X86_64
2640 gen_op_movq_A0_reg(R_ESP
);
2642 gen_op_addq_A0_im(-8);
2643 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2645 gen_op_addq_A0_im(-2);
2646 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2648 gen_op_mov_reg_A0(2, R_ESP
);
2652 gen_op_movl_A0_reg(R_ESP
);
2654 gen_op_addl_A0_im(-2);
2656 gen_op_addl_A0_im(-4);
2659 gen_op_addl_A0_seg(s
, R_SS
);
2662 gen_op_andl_A0_ffff();
2663 gen_op_addl_A0_seg(s
, R_SS
);
2665 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2667 if (s
->ss32
&& !s
->addseg
)
2668 gen_op_mov_reg_A0(1, R_ESP
);
2670 gen_stack_update(s
, (-2) << s
->dflag
);
2674 /* two step pop is necessary for precise exceptions */
2675 static void gen_pop_T0(DisasContext
*s
)
2677 #ifdef TARGET_X86_64
2679 gen_op_movq_A0_reg(R_ESP
);
2680 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2684 gen_op_movl_A0_reg(R_ESP
);
2687 gen_op_addl_A0_seg(s
, R_SS
);
2689 gen_op_andl_A0_ffff();
2690 gen_op_addl_A0_seg(s
, R_SS
);
2692 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2696 static void gen_pop_update(DisasContext
*s
)
2698 #ifdef TARGET_X86_64
2699 if (CODE64(s
) && s
->dflag
) {
2700 gen_stack_update(s
, 8);
2704 gen_stack_update(s
, 2 << s
->dflag
);
2708 static void gen_stack_A0(DisasContext
*s
)
2710 gen_op_movl_A0_reg(R_ESP
);
2712 gen_op_andl_A0_ffff();
2713 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2715 gen_op_addl_A0_seg(s
, R_SS
);
2718 /* NOTE: wrap around in 16 bit not fully handled */
2719 static void gen_pusha(DisasContext
*s
)
2722 gen_op_movl_A0_reg(R_ESP
);
2723 gen_op_addl_A0_im(-16 << s
->dflag
);
2725 gen_op_andl_A0_ffff();
2726 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2728 gen_op_addl_A0_seg(s
, R_SS
);
2729 for(i
= 0;i
< 8; i
++) {
2730 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2731 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2732 gen_op_addl_A0_im(2 << s
->dflag
);
2734 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2737 /* NOTE: wrap around in 16 bit not fully handled */
2738 static void gen_popa(DisasContext
*s
)
2741 gen_op_movl_A0_reg(R_ESP
);
2743 gen_op_andl_A0_ffff();
2744 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2745 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2747 gen_op_addl_A0_seg(s
, R_SS
);
2748 for(i
= 0;i
< 8; i
++) {
2749 /* ESP is not reloaded */
2751 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2752 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2754 gen_op_addl_A0_im(2 << s
->dflag
);
2756 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2759 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2764 #ifdef TARGET_X86_64
2766 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2769 gen_op_movl_A0_reg(R_ESP
);
2770 gen_op_addq_A0_im(-opsize
);
2771 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2774 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2775 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2777 /* XXX: must save state */
2778 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2779 tcg_const_i32((ot
== OT_QUAD
)),
2782 gen_op_mov_reg_T1(ot
, R_EBP
);
2783 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2784 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2788 ot
= s
->dflag
+ OT_WORD
;
2789 opsize
= 2 << s
->dflag
;
2791 gen_op_movl_A0_reg(R_ESP
);
2792 gen_op_addl_A0_im(-opsize
);
2794 gen_op_andl_A0_ffff();
2795 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2797 gen_op_addl_A0_seg(s
, R_SS
);
2799 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2800 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2802 /* XXX: must save state */
2803 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2804 tcg_const_i32(s
->dflag
),
2807 gen_op_mov_reg_T1(ot
, R_EBP
);
2808 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2809 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2813 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2815 gen_update_cc_op(s
);
2816 gen_jmp_im(cur_eip
);
2817 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2818 s
->is_jmp
= DISAS_TB_JUMP
;
2821 /* an interrupt is different from an exception because of the
2823 static void gen_interrupt(DisasContext
*s
, int intno
,
2824 target_ulong cur_eip
, target_ulong next_eip
)
2826 gen_update_cc_op(s
);
2827 gen_jmp_im(cur_eip
);
2828 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2829 tcg_const_i32(next_eip
- cur_eip
));
2830 s
->is_jmp
= DISAS_TB_JUMP
;
2833 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2835 gen_update_cc_op(s
);
2836 gen_jmp_im(cur_eip
);
2837 gen_helper_debug(cpu_env
);
2838 s
->is_jmp
= DISAS_TB_JUMP
;
2841 /* generate a generic end of block. Trace exception is also generated
2843 static void gen_eob(DisasContext
*s
)
2845 gen_update_cc_op(s
);
2846 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2847 gen_helper_reset_inhibit_irq(cpu_env
);
2849 if (s
->tb
->flags
& HF_RF_MASK
) {
2850 gen_helper_reset_rf(cpu_env
);
2852 if (s
->singlestep_enabled
) {
2853 gen_helper_debug(cpu_env
);
2855 gen_helper_single_step(cpu_env
);
2859 s
->is_jmp
= DISAS_TB_JUMP
;
2862 /* generate a jump to eip. No segment change must happen before as a
2863 direct call to the next block may occur */
2864 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2867 gen_update_cc_op(s
);
2868 gen_goto_tb(s
, tb_num
, eip
);
2869 s
->is_jmp
= DISAS_TB_JUMP
;
2876 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2878 gen_jmp_tb(s
, eip
, 0);
2881 static inline void gen_ldq_env_A0(int idx
, int offset
)
2883 int mem_index
= (idx
>> 2) - 1;
2884 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2885 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2888 static inline void gen_stq_env_A0(int idx
, int offset
)
2890 int mem_index
= (idx
>> 2) - 1;
2891 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2892 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2895 static inline void gen_ldo_env_A0(int idx
, int offset
)
2897 int mem_index
= (idx
>> 2) - 1;
2898 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2899 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2900 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2901 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2902 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2905 static inline void gen_sto_env_A0(int idx
, int offset
)
2907 int mem_index
= (idx
>> 2) - 1;
2908 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2909 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2910 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2911 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2912 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2915 static inline void gen_op_movo(int d_offset
, int s_offset
)
2917 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2918 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2919 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2920 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2923 static inline void gen_op_movq(int d_offset
, int s_offset
)
2925 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2926 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2929 static inline void gen_op_movl(int d_offset
, int s_offset
)
2931 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2932 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2935 static inline void gen_op_movq_env_0(int d_offset
)
2937 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2938 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2941 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2942 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2943 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2944 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2945 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2946 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2948 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2949 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2952 #define SSE_SPECIAL ((void *)1)
2953 #define SSE_DUMMY ((void *)2)
2955 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2956 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2957 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2959 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2960 /* 3DNow! extensions */
2961 [0x0e] = { SSE_DUMMY
}, /* femms */
2962 [0x0f] = { SSE_DUMMY
}, /* pf... */
2963 /* pure SSE operations */
2964 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2965 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2966 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2967 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2968 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2969 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2970 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2971 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2973 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2974 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2975 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2976 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2977 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2978 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2979 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2980 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2981 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2982 [0x51] = SSE_FOP(sqrt
),
2983 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2984 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2985 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2986 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2987 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2988 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2989 [0x58] = SSE_FOP(add
),
2990 [0x59] = SSE_FOP(mul
),
2991 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2992 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2993 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2994 [0x5c] = SSE_FOP(sub
),
2995 [0x5d] = SSE_FOP(min
),
2996 [0x5e] = SSE_FOP(div
),
2997 [0x5f] = SSE_FOP(max
),
2999 [0xc2] = SSE_FOP(cmpeq
),
3000 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
3001 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
3003 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
3004 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
3006 /* MMX ops and their SSE extensions */
3007 [0x60] = MMX_OP2(punpcklbw
),
3008 [0x61] = MMX_OP2(punpcklwd
),
3009 [0x62] = MMX_OP2(punpckldq
),
3010 [0x63] = MMX_OP2(packsswb
),
3011 [0x64] = MMX_OP2(pcmpgtb
),
3012 [0x65] = MMX_OP2(pcmpgtw
),
3013 [0x66] = MMX_OP2(pcmpgtl
),
3014 [0x67] = MMX_OP2(packuswb
),
3015 [0x68] = MMX_OP2(punpckhbw
),
3016 [0x69] = MMX_OP2(punpckhwd
),
3017 [0x6a] = MMX_OP2(punpckhdq
),
3018 [0x6b] = MMX_OP2(packssdw
),
3019 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
3020 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
3021 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
3022 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
3023 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
3024 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
3025 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
3026 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
3027 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
3028 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
3029 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
3030 [0x74] = MMX_OP2(pcmpeqb
),
3031 [0x75] = MMX_OP2(pcmpeqw
),
3032 [0x76] = MMX_OP2(pcmpeql
),
3033 [0x77] = { SSE_DUMMY
}, /* emms */
3034 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
3035 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
3036 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
3037 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
3038 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
3039 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
3040 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
3041 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
3042 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
3043 [0xd1] = MMX_OP2(psrlw
),
3044 [0xd2] = MMX_OP2(psrld
),
3045 [0xd3] = MMX_OP2(psrlq
),
3046 [0xd4] = MMX_OP2(paddq
),
3047 [0xd5] = MMX_OP2(pmullw
),
3048 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
3049 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
3050 [0xd8] = MMX_OP2(psubusb
),
3051 [0xd9] = MMX_OP2(psubusw
),
3052 [0xda] = MMX_OP2(pminub
),
3053 [0xdb] = MMX_OP2(pand
),
3054 [0xdc] = MMX_OP2(paddusb
),
3055 [0xdd] = MMX_OP2(paddusw
),
3056 [0xde] = MMX_OP2(pmaxub
),
3057 [0xdf] = MMX_OP2(pandn
),
3058 [0xe0] = MMX_OP2(pavgb
),
3059 [0xe1] = MMX_OP2(psraw
),
3060 [0xe2] = MMX_OP2(psrad
),
3061 [0xe3] = MMX_OP2(pavgw
),
3062 [0xe4] = MMX_OP2(pmulhuw
),
3063 [0xe5] = MMX_OP2(pmulhw
),
3064 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
3065 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
3066 [0xe8] = MMX_OP2(psubsb
),
3067 [0xe9] = MMX_OP2(psubsw
),
3068 [0xea] = MMX_OP2(pminsw
),
3069 [0xeb] = MMX_OP2(por
),
3070 [0xec] = MMX_OP2(paddsb
),
3071 [0xed] = MMX_OP2(paddsw
),
3072 [0xee] = MMX_OP2(pmaxsw
),
3073 [0xef] = MMX_OP2(pxor
),
3074 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
3075 [0xf1] = MMX_OP2(psllw
),
3076 [0xf2] = MMX_OP2(pslld
),
3077 [0xf3] = MMX_OP2(psllq
),
3078 [0xf4] = MMX_OP2(pmuludq
),
3079 [0xf5] = MMX_OP2(pmaddwd
),
3080 [0xf6] = MMX_OP2(psadbw
),
3081 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
3082 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
3083 [0xf8] = MMX_OP2(psubb
),
3084 [0xf9] = MMX_OP2(psubw
),
3085 [0xfa] = MMX_OP2(psubl
),
3086 [0xfb] = MMX_OP2(psubq
),
3087 [0xfc] = MMX_OP2(paddb
),
3088 [0xfd] = MMX_OP2(paddw
),
3089 [0xfe] = MMX_OP2(paddl
),
3092 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
3093 [0 + 2] = MMX_OP2(psrlw
),
3094 [0 + 4] = MMX_OP2(psraw
),
3095 [0 + 6] = MMX_OP2(psllw
),
3096 [8 + 2] = MMX_OP2(psrld
),
3097 [8 + 4] = MMX_OP2(psrad
),
3098 [8 + 6] = MMX_OP2(pslld
),
3099 [16 + 2] = MMX_OP2(psrlq
),
3100 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
3101 [16 + 6] = MMX_OP2(psllq
),
3102 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
3105 static const SSEFunc_0_epi sse_op_table3ai
[] = {
3106 gen_helper_cvtsi2ss
,
3110 #ifdef TARGET_X86_64
3111 static const SSEFunc_0_epl sse_op_table3aq
[] = {
3112 gen_helper_cvtsq2ss
,
3117 static const SSEFunc_i_ep sse_op_table3bi
[] = {
3118 gen_helper_cvttss2si
,
3119 gen_helper_cvtss2si
,
3120 gen_helper_cvttsd2si
,
3124 #ifdef TARGET_X86_64
3125 static const SSEFunc_l_ep sse_op_table3bq
[] = {
3126 gen_helper_cvttss2sq
,
3127 gen_helper_cvtss2sq
,
3128 gen_helper_cvttsd2sq
,
3133 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
3144 static const SSEFunc_0_epp sse_op_table5
[256] = {
3145 [0x0c] = gen_helper_pi2fw
,
3146 [0x0d] = gen_helper_pi2fd
,
3147 [0x1c] = gen_helper_pf2iw
,
3148 [0x1d] = gen_helper_pf2id
,
3149 [0x8a] = gen_helper_pfnacc
,
3150 [0x8e] = gen_helper_pfpnacc
,
3151 [0x90] = gen_helper_pfcmpge
,
3152 [0x94] = gen_helper_pfmin
,
3153 [0x96] = gen_helper_pfrcp
,
3154 [0x97] = gen_helper_pfrsqrt
,
3155 [0x9a] = gen_helper_pfsub
,
3156 [0x9e] = gen_helper_pfadd
,
3157 [0xa0] = gen_helper_pfcmpgt
,
3158 [0xa4] = gen_helper_pfmax
,
3159 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
3160 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
3161 [0xaa] = gen_helper_pfsubr
,
3162 [0xae] = gen_helper_pfacc
,
3163 [0xb0] = gen_helper_pfcmpeq
,
3164 [0xb4] = gen_helper_pfmul
,
3165 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3166 [0xb7] = gen_helper_pmulhrw_mmx
,
3167 [0xbb] = gen_helper_pswapd
,
3168 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3171 struct SSEOpHelper_epp
{
3172 SSEFunc_0_epp op
[2];
3176 struct SSEOpHelper_eppi
{
3177 SSEFunc_0_eppi op
[2];
3181 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3182 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3183 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3184 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3186 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3187 [0x00] = SSSE3_OP(pshufb
),
3188 [0x01] = SSSE3_OP(phaddw
),
3189 [0x02] = SSSE3_OP(phaddd
),
3190 [0x03] = SSSE3_OP(phaddsw
),
3191 [0x04] = SSSE3_OP(pmaddubsw
),
3192 [0x05] = SSSE3_OP(phsubw
),
3193 [0x06] = SSSE3_OP(phsubd
),
3194 [0x07] = SSSE3_OP(phsubsw
),
3195 [0x08] = SSSE3_OP(psignb
),
3196 [0x09] = SSSE3_OP(psignw
),
3197 [0x0a] = SSSE3_OP(psignd
),
3198 [0x0b] = SSSE3_OP(pmulhrsw
),
3199 [0x10] = SSE41_OP(pblendvb
),
3200 [0x14] = SSE41_OP(blendvps
),
3201 [0x15] = SSE41_OP(blendvpd
),
3202 [0x17] = SSE41_OP(ptest
),
3203 [0x1c] = SSSE3_OP(pabsb
),
3204 [0x1d] = SSSE3_OP(pabsw
),
3205 [0x1e] = SSSE3_OP(pabsd
),
3206 [0x20] = SSE41_OP(pmovsxbw
),
3207 [0x21] = SSE41_OP(pmovsxbd
),
3208 [0x22] = SSE41_OP(pmovsxbq
),
3209 [0x23] = SSE41_OP(pmovsxwd
),
3210 [0x24] = SSE41_OP(pmovsxwq
),
3211 [0x25] = SSE41_OP(pmovsxdq
),
3212 [0x28] = SSE41_OP(pmuldq
),
3213 [0x29] = SSE41_OP(pcmpeqq
),
3214 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3215 [0x2b] = SSE41_OP(packusdw
),
3216 [0x30] = SSE41_OP(pmovzxbw
),
3217 [0x31] = SSE41_OP(pmovzxbd
),
3218 [0x32] = SSE41_OP(pmovzxbq
),
3219 [0x33] = SSE41_OP(pmovzxwd
),
3220 [0x34] = SSE41_OP(pmovzxwq
),
3221 [0x35] = SSE41_OP(pmovzxdq
),
3222 [0x37] = SSE42_OP(pcmpgtq
),
3223 [0x38] = SSE41_OP(pminsb
),
3224 [0x39] = SSE41_OP(pminsd
),
3225 [0x3a] = SSE41_OP(pminuw
),
3226 [0x3b] = SSE41_OP(pminud
),
3227 [0x3c] = SSE41_OP(pmaxsb
),
3228 [0x3d] = SSE41_OP(pmaxsd
),
3229 [0x3e] = SSE41_OP(pmaxuw
),
3230 [0x3f] = SSE41_OP(pmaxud
),
3231 [0x40] = SSE41_OP(pmulld
),
3232 [0x41] = SSE41_OP(phminposuw
),
3235 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3236 [0x08] = SSE41_OP(roundps
),
3237 [0x09] = SSE41_OP(roundpd
),
3238 [0x0a] = SSE41_OP(roundss
),
3239 [0x0b] = SSE41_OP(roundsd
),
3240 [0x0c] = SSE41_OP(blendps
),
3241 [0x0d] = SSE41_OP(blendpd
),
3242 [0x0e] = SSE41_OP(pblendw
),
3243 [0x0f] = SSSE3_OP(palignr
),
3244 [0x14] = SSE41_SPECIAL
, /* pextrb */
3245 [0x15] = SSE41_SPECIAL
, /* pextrw */
3246 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3247 [0x17] = SSE41_SPECIAL
, /* extractps */
3248 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3249 [0x21] = SSE41_SPECIAL
, /* insertps */
3250 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3251 [0x40] = SSE41_OP(dpps
),
3252 [0x41] = SSE41_OP(dppd
),
3253 [0x42] = SSE41_OP(mpsadbw
),
3254 [0x60] = SSE42_OP(pcmpestrm
),
3255 [0x61] = SSE42_OP(pcmpestri
),
3256 [0x62] = SSE42_OP(pcmpistrm
),
3257 [0x63] = SSE42_OP(pcmpistri
),
3260 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3261 target_ulong pc_start
, int rex_r
)
3263 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3264 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3265 SSEFunc_0_epp sse_fn_epp
;
3266 SSEFunc_0_eppi sse_fn_eppi
;
3267 SSEFunc_0_ppi sse_fn_ppi
;
3268 SSEFunc_0_eppt sse_fn_eppt
;
3271 if (s
->prefix
& PREFIX_DATA
)
3273 else if (s
->prefix
& PREFIX_REPZ
)
3275 else if (s
->prefix
& PREFIX_REPNZ
)
3279 sse_fn_epp
= sse_op_table1
[b
][b1
];
3283 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3293 /* simple MMX/SSE operation */
3294 if (s
->flags
& HF_TS_MASK
) {
3295 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3298 if (s
->flags
& HF_EM_MASK
) {
3300 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3303 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3304 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3307 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3310 gen_helper_emms(cpu_env
);
3315 gen_helper_emms(cpu_env
);
3318 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3319 the static cpu state) */
3321 gen_helper_enter_mmx(cpu_env
);
3324 modrm
= cpu_ldub_code(env
, s
->pc
++);
3325 reg
= ((modrm
>> 3) & 7);
3328 mod
= (modrm
>> 6) & 3;
3329 if (sse_fn_epp
== SSE_SPECIAL
) {
3332 case 0x0e7: /* movntq */
3335 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3336 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3338 case 0x1e7: /* movntdq */
3339 case 0x02b: /* movntps */
3340 case 0x12b: /* movntps */
3343 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3344 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3346 case 0x3f0: /* lddqu */
3349 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3350 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3352 case 0x22b: /* movntss */
3353 case 0x32b: /* movntsd */
3356 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3358 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3361 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3362 xmm_regs
[reg
].XMM_L(0)));
3363 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3366 case 0x6e: /* movd mm, ea */
3367 #ifdef TARGET_X86_64
3368 if (s
->dflag
== 2) {
3369 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3370 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3374 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3375 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3376 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3377 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3378 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3381 case 0x16e: /* movd xmm, ea */
3382 #ifdef TARGET_X86_64
3383 if (s
->dflag
== 2) {
3384 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3385 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3386 offsetof(CPUX86State
,xmm_regs
[reg
]));
3387 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3391 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3392 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3393 offsetof(CPUX86State
,xmm_regs
[reg
]));
3394 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3395 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3398 case 0x6f: /* movq mm, ea */
3400 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3401 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3404 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3405 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3406 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3407 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3410 case 0x010: /* movups */
3411 case 0x110: /* movupd */
3412 case 0x028: /* movaps */
3413 case 0x128: /* movapd */
3414 case 0x16f: /* movdqa xmm, ea */
3415 case 0x26f: /* movdqu xmm, ea */
3417 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3418 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3420 rm
= (modrm
& 7) | REX_B(s
);
3421 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3422 offsetof(CPUX86State
,xmm_regs
[rm
]));
3425 case 0x210: /* movss xmm, ea */
3427 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3428 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3429 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3431 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3432 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3433 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3435 rm
= (modrm
& 7) | REX_B(s
);
3436 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3437 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3440 case 0x310: /* movsd xmm, ea */
3442 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3443 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3445 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3446 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3448 rm
= (modrm
& 7) | REX_B(s
);
3449 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3450 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3453 case 0x012: /* movlps */
3454 case 0x112: /* movlpd */
3456 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3457 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3460 rm
= (modrm
& 7) | REX_B(s
);
3461 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3462 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3465 case 0x212: /* movsldup */
3467 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3468 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3470 rm
= (modrm
& 7) | REX_B(s
);
3471 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3472 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3473 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3474 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3476 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3477 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3478 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3479 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3481 case 0x312: /* movddup */
3483 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3484 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3486 rm
= (modrm
& 7) | REX_B(s
);
3487 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3488 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3490 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3491 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3493 case 0x016: /* movhps */
3494 case 0x116: /* movhpd */
3496 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3497 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3500 rm
= (modrm
& 7) | REX_B(s
);
3501 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3502 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3505 case 0x216: /* movshdup */
3507 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3508 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3510 rm
= (modrm
& 7) | REX_B(s
);
3511 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3512 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3513 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3514 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3516 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3517 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3518 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3519 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3524 int bit_index
, field_length
;
3526 if (b1
== 1 && reg
!= 0)
3528 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3529 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3530 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3531 offsetof(CPUX86State
,xmm_regs
[reg
]));
3533 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3534 tcg_const_i32(bit_index
),
3535 tcg_const_i32(field_length
));
3537 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3538 tcg_const_i32(bit_index
),
3539 tcg_const_i32(field_length
));
3542 case 0x7e: /* movd ea, mm */
3543 #ifdef TARGET_X86_64
3544 if (s
->dflag
== 2) {
3545 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3546 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3547 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3551 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3552 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3553 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3556 case 0x17e: /* movd ea, xmm */
3557 #ifdef TARGET_X86_64
3558 if (s
->dflag
== 2) {
3559 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3560 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3561 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3565 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3566 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3567 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3570 case 0x27e: /* movq xmm, ea */
3572 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3573 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3575 rm
= (modrm
& 7) | REX_B(s
);
3576 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3577 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3579 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3581 case 0x7f: /* movq ea, mm */
3583 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3584 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3587 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3588 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3591 case 0x011: /* movups */
3592 case 0x111: /* movupd */
3593 case 0x029: /* movaps */
3594 case 0x129: /* movapd */
3595 case 0x17f: /* movdqa ea, xmm */
3596 case 0x27f: /* movdqu ea, xmm */
3598 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3599 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3601 rm
= (modrm
& 7) | REX_B(s
);
3602 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3603 offsetof(CPUX86State
,xmm_regs
[reg
]));
3606 case 0x211: /* movss ea, xmm */
3608 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3609 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3610 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3612 rm
= (modrm
& 7) | REX_B(s
);
3613 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3614 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3617 case 0x311: /* movsd ea, xmm */
3619 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3620 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3622 rm
= (modrm
& 7) | REX_B(s
);
3623 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3624 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3627 case 0x013: /* movlps */
3628 case 0x113: /* movlpd */
3630 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3631 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3636 case 0x017: /* movhps */
3637 case 0x117: /* movhpd */
3639 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3640 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3645 case 0x71: /* shift mm, im */
3648 case 0x171: /* shift xmm, im */
3654 val
= cpu_ldub_code(env
, s
->pc
++);
3656 gen_op_movl_T0_im(val
);
3657 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3659 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3660 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3662 gen_op_movl_T0_im(val
);
3663 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3665 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3666 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3668 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3669 (((modrm
>> 3)) & 7)][b1
];
3674 rm
= (modrm
& 7) | REX_B(s
);
3675 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3678 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3680 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3681 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3682 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3684 case 0x050: /* movmskps */
3685 rm
= (modrm
& 7) | REX_B(s
);
3686 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3687 offsetof(CPUX86State
,xmm_regs
[rm
]));
3688 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3689 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3690 gen_op_mov_reg_T0(OT_LONG
, reg
);
3692 case 0x150: /* movmskpd */
3693 rm
= (modrm
& 7) | REX_B(s
);
3694 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3695 offsetof(CPUX86State
,xmm_regs
[rm
]));
3696 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3697 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3698 gen_op_mov_reg_T0(OT_LONG
, reg
);
3700 case 0x02a: /* cvtpi2ps */
3701 case 0x12a: /* cvtpi2pd */
3702 gen_helper_enter_mmx(cpu_env
);
3704 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3705 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3706 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3709 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3711 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3712 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3713 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3716 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3720 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3724 case 0x22a: /* cvtsi2ss */
3725 case 0x32a: /* cvtsi2sd */
3726 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3727 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3728 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3729 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3730 if (ot
== OT_LONG
) {
3731 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3732 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3733 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3735 #ifdef TARGET_X86_64
3736 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3737 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3743 case 0x02c: /* cvttps2pi */
3744 case 0x12c: /* cvttpd2pi */
3745 case 0x02d: /* cvtps2pi */
3746 case 0x12d: /* cvtpd2pi */
3747 gen_helper_enter_mmx(cpu_env
);
3749 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3750 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3751 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3753 rm
= (modrm
& 7) | REX_B(s
);
3754 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3756 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3757 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3758 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3761 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3764 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3767 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3770 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3774 case 0x22c: /* cvttss2si */
3775 case 0x32c: /* cvttsd2si */
3776 case 0x22d: /* cvtss2si */
3777 case 0x32d: /* cvtsd2si */
3778 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3780 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3782 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3784 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3785 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3787 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3789 rm
= (modrm
& 7) | REX_B(s
);
3790 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3792 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3793 if (ot
== OT_LONG
) {
3794 SSEFunc_i_ep sse_fn_i_ep
=
3795 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3796 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3797 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3799 #ifdef TARGET_X86_64
3800 SSEFunc_l_ep sse_fn_l_ep
=
3801 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3802 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3807 gen_op_mov_reg_T0(ot
, reg
);
3809 case 0xc4: /* pinsrw */
3812 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3813 val
= cpu_ldub_code(env
, s
->pc
++);
3816 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3817 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3820 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3821 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3824 case 0xc5: /* pextrw */
3828 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3829 val
= cpu_ldub_code(env
, s
->pc
++);
3832 rm
= (modrm
& 7) | REX_B(s
);
3833 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3834 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3838 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3839 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3841 reg
= ((modrm
>> 3) & 7) | rex_r
;
3842 gen_op_mov_reg_T0(ot
, reg
);
3844 case 0x1d6: /* movq ea, xmm */
3846 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3847 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3849 rm
= (modrm
& 7) | REX_B(s
);
3850 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3851 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3852 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3855 case 0x2d6: /* movq2dq */
3856 gen_helper_enter_mmx(cpu_env
);
3858 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3859 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3860 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3862 case 0x3d6: /* movdq2q */
3863 gen_helper_enter_mmx(cpu_env
);
3864 rm
= (modrm
& 7) | REX_B(s
);
3865 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3866 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3868 case 0xd7: /* pmovmskb */
3873 rm
= (modrm
& 7) | REX_B(s
);
3874 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3875 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3878 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3879 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3881 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3882 reg
= ((modrm
>> 3) & 7) | rex_r
;
3883 gen_op_mov_reg_T0(OT_LONG
, reg
);
3886 if (s
->prefix
& PREFIX_REPNZ
)
3890 modrm
= cpu_ldub_code(env
, s
->pc
++);
3892 reg
= ((modrm
>> 3) & 7) | rex_r
;
3893 mod
= (modrm
>> 6) & 3;
3898 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3902 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3906 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3908 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3910 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3911 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3913 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3914 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3915 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3916 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3917 offsetof(XMMReg
, XMM_Q(0)));
3919 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3920 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3921 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3922 (s
->mem_index
>> 2) - 1);
3923 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3924 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3925 offsetof(XMMReg
, XMM_L(0)));
3927 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3928 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3929 (s
->mem_index
>> 2) - 1);
3930 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3931 offsetof(XMMReg
, XMM_W(0)));
3933 case 0x2a: /* movntqda */
3934 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3937 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3941 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3943 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3945 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3946 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3947 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3950 if (sse_fn_epp
== SSE_SPECIAL
) {
3954 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3955 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3956 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3959 set_cc_op(s
, CC_OP_EFLAGS
);
3962 case 0x338: /* crc32 */
3965 modrm
= cpu_ldub_code(env
, s
->pc
++);
3966 reg
= ((modrm
>> 3) & 7) | rex_r
;
3968 if (b
!= 0xf0 && b
!= 0xf1)
3970 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3975 else if (b
== 0xf1 && s
->dflag
!= 2)
3976 if (s
->prefix
& PREFIX_DATA
)
3983 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3984 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3985 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3986 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3987 cpu_T
[0], tcg_const_i32(8 << ot
));
3989 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3990 gen_op_mov_reg_T0(ot
, reg
);
3995 modrm
= cpu_ldub_code(env
, s
->pc
++);
3997 reg
= ((modrm
>> 3) & 7) | rex_r
;
3998 mod
= (modrm
>> 6) & 3;
4003 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4007 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4010 if (sse_fn_eppi
== SSE_SPECIAL
) {
4011 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
4012 rm
= (modrm
& 7) | REX_B(s
);
4014 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4015 reg
= ((modrm
>> 3) & 7) | rex_r
;
4016 val
= cpu_ldub_code(env
, s
->pc
++);
4018 case 0x14: /* pextrb */
4019 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4020 xmm_regs
[reg
].XMM_B(val
& 15)));
4022 gen_op_mov_reg_T0(ot
, rm
);
4024 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
4025 (s
->mem_index
>> 2) - 1);
4027 case 0x15: /* pextrw */
4028 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4029 xmm_regs
[reg
].XMM_W(val
& 7)));
4031 gen_op_mov_reg_T0(ot
, rm
);
4033 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
4034 (s
->mem_index
>> 2) - 1);
4037 if (ot
== OT_LONG
) { /* pextrd */
4038 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4039 offsetof(CPUX86State
,
4040 xmm_regs
[reg
].XMM_L(val
& 3)));
4041 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4043 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4045 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4046 (s
->mem_index
>> 2) - 1);
4047 } else { /* pextrq */
4048 #ifdef TARGET_X86_64
4049 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4050 offsetof(CPUX86State
,
4051 xmm_regs
[reg
].XMM_Q(val
& 1)));
4053 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
4055 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
4056 (s
->mem_index
>> 2) - 1);
4062 case 0x17: /* extractps */
4063 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4064 xmm_regs
[reg
].XMM_L(val
& 3)));
4066 gen_op_mov_reg_T0(ot
, rm
);
4068 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4069 (s
->mem_index
>> 2) - 1);
4071 case 0x20: /* pinsrb */
4073 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
4075 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
4076 (s
->mem_index
>> 2) - 1);
4077 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
4078 xmm_regs
[reg
].XMM_B(val
& 15)));
4080 case 0x21: /* insertps */
4082 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4083 offsetof(CPUX86State
,xmm_regs
[rm
]
4084 .XMM_L((val
>> 6) & 3)));
4086 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4087 (s
->mem_index
>> 2) - 1);
4088 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4090 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4091 offsetof(CPUX86State
,xmm_regs
[reg
]
4092 .XMM_L((val
>> 4) & 3)));
4094 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4095 cpu_env
, offsetof(CPUX86State
,
4096 xmm_regs
[reg
].XMM_L(0)));
4098 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4099 cpu_env
, offsetof(CPUX86State
,
4100 xmm_regs
[reg
].XMM_L(1)));
4102 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4103 cpu_env
, offsetof(CPUX86State
,
4104 xmm_regs
[reg
].XMM_L(2)));
4106 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4107 cpu_env
, offsetof(CPUX86State
,
4108 xmm_regs
[reg
].XMM_L(3)));
4111 if (ot
== OT_LONG
) { /* pinsrd */
4113 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4115 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4116 (s
->mem_index
>> 2) - 1);
4117 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4118 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4119 offsetof(CPUX86State
,
4120 xmm_regs
[reg
].XMM_L(val
& 3)));
4121 } else { /* pinsrq */
4122 #ifdef TARGET_X86_64
4124 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4126 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
4127 (s
->mem_index
>> 2) - 1);
4128 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4129 offsetof(CPUX86State
,
4130 xmm_regs
[reg
].XMM_Q(val
& 1)));
4141 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4143 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4145 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4146 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4147 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4150 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4152 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4154 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4155 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4156 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4159 val
= cpu_ldub_code(env
, s
->pc
++);
4161 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4162 set_cc_op(s
, CC_OP_EFLAGS
);
4165 /* The helper must use entire 64-bit gp registers */
4169 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4170 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4171 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4177 /* generic MMX or SSE operation */
4179 case 0x70: /* pshufx insn */
4180 case 0xc6: /* pshufx insn */
4181 case 0xc2: /* compare insns */
4188 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4190 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4191 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4192 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4194 /* specific case for SSE single instructions */
4197 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
4198 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4201 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4204 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4207 rm
= (modrm
& 7) | REX_B(s
);
4208 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4211 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4213 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4214 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4215 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4218 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4222 case 0x0f: /* 3DNow! data insns */
4223 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4225 val
= cpu_ldub_code(env
, s
->pc
++);
4226 sse_fn_epp
= sse_op_table5
[val
];
4230 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4231 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4232 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4234 case 0x70: /* pshufx insn */
4235 case 0xc6: /* pshufx insn */
4236 val
= cpu_ldub_code(env
, s
->pc
++);
4237 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4238 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4239 /* XXX: introduce a new table? */
4240 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4241 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4245 val
= cpu_ldub_code(env
, s
->pc
++);
4248 sse_fn_epp
= sse_op_table4
[val
][b1
];
4250 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4251 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4252 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4255 /* maskmov : we must prepare A0 */
4258 #ifdef TARGET_X86_64
4259 if (s
->aflag
== 2) {
4260 gen_op_movq_A0_reg(R_EDI
);
4264 gen_op_movl_A0_reg(R_EDI
);
4266 gen_op_andl_A0_ffff();
4268 gen_add_A0_ds_seg(s
);
4270 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4271 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4272 /* XXX: introduce a new table? */
4273 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4274 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4277 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4278 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4279 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4282 if (b
== 0x2e || b
== 0x2f) {
4283 set_cc_op(s
, CC_OP_EFLAGS
);
4288 /* convert one instruction. s->is_jmp is set if the translation must
4289 be stopped. Return the next pc value */
4290 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4291 target_ulong pc_start
)
4293 int b
, prefixes
, aflag
, dflag
;
4295 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4296 target_ulong next_eip
, tval
;
4299 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4300 tcg_gen_debug_insn_start(pc_start
);
4309 #ifdef TARGET_X86_64
4314 s
->rip_offset
= 0; /* for relative ip address */
4316 b
= cpu_ldub_code(env
, s
->pc
);
4318 /* check prefixes */
4319 #ifdef TARGET_X86_64
4323 prefixes
|= PREFIX_REPZ
;
4326 prefixes
|= PREFIX_REPNZ
;
4329 prefixes
|= PREFIX_LOCK
;
4350 prefixes
|= PREFIX_DATA
;
4353 prefixes
|= PREFIX_ADR
;
4357 rex_w
= (b
>> 3) & 1;
4358 rex_r
= (b
& 0x4) << 1;
4359 s
->rex_x
= (b
& 0x2) << 2;
4360 REX_B(s
) = (b
& 0x1) << 3;
4361 x86_64_hregs
= 1; /* select uniform byte register addressing */
4365 /* 0x66 is ignored if rex.w is set */
4368 if (prefixes
& PREFIX_DATA
)
4371 if (!(prefixes
& PREFIX_ADR
))
4378 prefixes
|= PREFIX_REPZ
;
4381 prefixes
|= PREFIX_REPNZ
;
4384 prefixes
|= PREFIX_LOCK
;
4405 prefixes
|= PREFIX_DATA
;
4408 prefixes
|= PREFIX_ADR
;
4411 if (prefixes
& PREFIX_DATA
)
4413 if (prefixes
& PREFIX_ADR
)
4417 s
->prefix
= prefixes
;
4421 /* lock generation */
4422 if (prefixes
& PREFIX_LOCK
)
4425 /* now check op code */
4429 /**************************/
4430 /* extended op code */
4431 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4434 /**************************/
4452 ot
= dflag
+ OT_WORD
;
4455 case 0: /* OP Ev, Gv */
4456 modrm
= cpu_ldub_code(env
, s
->pc
++);
4457 reg
= ((modrm
>> 3) & 7) | rex_r
;
4458 mod
= (modrm
>> 6) & 3;
4459 rm
= (modrm
& 7) | REX_B(s
);
4461 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4463 } else if (op
== OP_XORL
&& rm
== reg
) {
4465 /* xor reg, reg optimisation */
4467 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4468 gen_op_mov_reg_T0(ot
, reg
);
4469 gen_op_update1_cc();
4474 gen_op_mov_TN_reg(ot
, 1, reg
);
4475 gen_op(s
, op
, ot
, opreg
);
4477 case 1: /* OP Gv, Ev */
4478 modrm
= cpu_ldub_code(env
, s
->pc
++);
4479 mod
= (modrm
>> 6) & 3;
4480 reg
= ((modrm
>> 3) & 7) | rex_r
;
4481 rm
= (modrm
& 7) | REX_B(s
);
4483 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4484 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4485 } else if (op
== OP_XORL
&& rm
== reg
) {
4488 gen_op_mov_TN_reg(ot
, 1, rm
);
4490 gen_op(s
, op
, ot
, reg
);
4492 case 2: /* OP A, Iv */
4493 val
= insn_get(env
, s
, ot
);
4494 gen_op_movl_T1_im(val
);
4495 gen_op(s
, op
, ot
, OR_EAX
);
4504 case 0x80: /* GRP1 */
4513 ot
= dflag
+ OT_WORD
;
4515 modrm
= cpu_ldub_code(env
, s
->pc
++);
4516 mod
= (modrm
>> 6) & 3;
4517 rm
= (modrm
& 7) | REX_B(s
);
4518 op
= (modrm
>> 3) & 7;
4524 s
->rip_offset
= insn_const_size(ot
);
4525 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4536 val
= insn_get(env
, s
, ot
);
4539 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4542 gen_op_movl_T1_im(val
);
4543 gen_op(s
, op
, ot
, opreg
);
4547 /**************************/
4548 /* inc, dec, and other misc arith */
4549 case 0x40 ... 0x47: /* inc Gv */
4550 ot
= dflag
? OT_LONG
: OT_WORD
;
4551 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4553 case 0x48 ... 0x4f: /* dec Gv */
4554 ot
= dflag
? OT_LONG
: OT_WORD
;
4555 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4557 case 0xf6: /* GRP3 */
4562 ot
= dflag
+ OT_WORD
;
4564 modrm
= cpu_ldub_code(env
, s
->pc
++);
4565 mod
= (modrm
>> 6) & 3;
4566 rm
= (modrm
& 7) | REX_B(s
);
4567 op
= (modrm
>> 3) & 7;
4570 s
->rip_offset
= insn_const_size(ot
);
4571 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4572 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4574 gen_op_mov_TN_reg(ot
, 0, rm
);
4579 val
= insn_get(env
, s
, ot
);
4580 gen_op_movl_T1_im(val
);
4581 gen_op_testl_T0_T1_cc();
4582 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4585 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4587 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4589 gen_op_mov_reg_T0(ot
, rm
);
4593 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4595 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4597 gen_op_mov_reg_T0(ot
, rm
);
4599 gen_op_update_neg_cc();
4600 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4605 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4606 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4607 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4608 /* XXX: use 32 bit mul which could be faster */
4609 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4610 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4611 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4612 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4613 set_cc_op(s
, CC_OP_MULB
);
4616 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4617 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4618 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4619 /* XXX: use 32 bit mul which could be faster */
4620 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4621 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4622 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4623 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4624 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4625 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4626 set_cc_op(s
, CC_OP_MULW
);
4630 #ifdef TARGET_X86_64
4631 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4632 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4633 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4634 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4635 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4636 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4637 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4638 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4639 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4643 t0
= tcg_temp_new_i64();
4644 t1
= tcg_temp_new_i64();
4645 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4646 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4647 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4648 tcg_gen_mul_i64(t0
, t0
, t1
);
4649 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4650 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4651 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4652 tcg_gen_shri_i64(t0
, t0
, 32);
4653 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4654 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4655 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4658 set_cc_op(s
, CC_OP_MULL
);
4660 #ifdef TARGET_X86_64
4662 gen_helper_mulq_EAX_T0(cpu_env
, cpu_T
[0]);
4663 set_cc_op(s
, CC_OP_MULQ
);
4671 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4672 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4673 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4674 /* XXX: use 32 bit mul which could be faster */
4675 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4676 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4677 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4678 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4679 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4680 set_cc_op(s
, CC_OP_MULB
);
4683 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4684 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4685 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4686 /* XXX: use 32 bit mul which could be faster */
4687 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4688 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4689 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4690 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4691 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4692 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4693 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4694 set_cc_op(s
, CC_OP_MULW
);
4698 #ifdef TARGET_X86_64
4699 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4700 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4701 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4702 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4703 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4704 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4705 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4706 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4707 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4708 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4712 t0
= tcg_temp_new_i64();
4713 t1
= tcg_temp_new_i64();
4714 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4715 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4716 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4717 tcg_gen_mul_i64(t0
, t0
, t1
);
4718 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4719 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4720 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4721 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4722 tcg_gen_shri_i64(t0
, t0
, 32);
4723 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4724 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4725 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4728 set_cc_op(s
, CC_OP_MULL
);
4730 #ifdef TARGET_X86_64
4732 gen_helper_imulq_EAX_T0(cpu_env
, cpu_T
[0]);
4733 set_cc_op(s
, CC_OP_MULQ
);
4741 gen_jmp_im(pc_start
- s
->cs_base
);
4742 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4745 gen_jmp_im(pc_start
- s
->cs_base
);
4746 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4750 gen_jmp_im(pc_start
- s
->cs_base
);
4751 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4753 #ifdef TARGET_X86_64
4755 gen_jmp_im(pc_start
- s
->cs_base
);
4756 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4764 gen_jmp_im(pc_start
- s
->cs_base
);
4765 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4768 gen_jmp_im(pc_start
- s
->cs_base
);
4769 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4773 gen_jmp_im(pc_start
- s
->cs_base
);
4774 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4776 #ifdef TARGET_X86_64
4778 gen_jmp_im(pc_start
- s
->cs_base
);
4779 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4789 case 0xfe: /* GRP4 */
4790 case 0xff: /* GRP5 */
4794 ot
= dflag
+ OT_WORD
;
4796 modrm
= cpu_ldub_code(env
, s
->pc
++);
4797 mod
= (modrm
>> 6) & 3;
4798 rm
= (modrm
& 7) | REX_B(s
);
4799 op
= (modrm
>> 3) & 7;
4800 if (op
>= 2 && b
== 0xfe) {
4804 if (op
== 2 || op
== 4) {
4805 /* operand size for jumps is 64 bit */
4807 } else if (op
== 3 || op
== 5) {
4808 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4809 } else if (op
== 6) {
4810 /* default push size is 64 bit */
4811 ot
= dflag
? OT_QUAD
: OT_WORD
;
4815 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4816 if (op
>= 2 && op
!= 3 && op
!= 5)
4817 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4819 gen_op_mov_TN_reg(ot
, 0, rm
);
4823 case 0: /* inc Ev */
4828 gen_inc(s
, ot
, opreg
, 1);
4830 case 1: /* dec Ev */
4835 gen_inc(s
, ot
, opreg
, -1);
4837 case 2: /* call Ev */
4838 /* XXX: optimize if memory (no 'and' is necessary) */
4840 gen_op_andl_T0_ffff();
4841 next_eip
= s
->pc
- s
->cs_base
;
4842 gen_movtl_T1_im(next_eip
);
4847 case 3: /* lcall Ev */
4848 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4849 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4850 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4852 if (s
->pe
&& !s
->vm86
) {
4853 gen_update_cc_op(s
);
4854 gen_jmp_im(pc_start
- s
->cs_base
);
4855 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4856 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4857 tcg_const_i32(dflag
),
4858 tcg_const_i32(s
->pc
- pc_start
));
4860 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4861 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4862 tcg_const_i32(dflag
),
4863 tcg_const_i32(s
->pc
- s
->cs_base
));
4867 case 4: /* jmp Ev */
4869 gen_op_andl_T0_ffff();
4873 case 5: /* ljmp Ev */
4874 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4875 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4876 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4878 if (s
->pe
&& !s
->vm86
) {
4879 gen_update_cc_op(s
);
4880 gen_jmp_im(pc_start
- s
->cs_base
);
4881 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4882 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4883 tcg_const_i32(s
->pc
- pc_start
));
4885 gen_op_movl_seg_T0_vm(R_CS
);
4886 gen_op_movl_T0_T1();
4891 case 6: /* push Ev */
4899 case 0x84: /* test Ev, Gv */
4904 ot
= dflag
+ OT_WORD
;
4906 modrm
= cpu_ldub_code(env
, s
->pc
++);
4907 reg
= ((modrm
>> 3) & 7) | rex_r
;
4909 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4910 gen_op_mov_TN_reg(ot
, 1, reg
);
4911 gen_op_testl_T0_T1_cc();
4912 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4915 case 0xa8: /* test eAX, Iv */
4920 ot
= dflag
+ OT_WORD
;
4921 val
= insn_get(env
, s
, ot
);
4923 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4924 gen_op_movl_T1_im(val
);
4925 gen_op_testl_T0_T1_cc();
4926 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4929 case 0x98: /* CWDE/CBW */
4930 #ifdef TARGET_X86_64
4932 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4933 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4934 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4938 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4939 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4940 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4942 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4943 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4944 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4947 case 0x99: /* CDQ/CWD */
4948 #ifdef TARGET_X86_64
4950 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4951 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4952 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4956 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4957 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4958 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4959 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4961 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4962 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4963 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4964 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4967 case 0x1af: /* imul Gv, Ev */
4968 case 0x69: /* imul Gv, Ev, I */
4970 ot
= dflag
+ OT_WORD
;
4971 modrm
= cpu_ldub_code(env
, s
->pc
++);
4972 reg
= ((modrm
>> 3) & 7) | rex_r
;
4974 s
->rip_offset
= insn_const_size(ot
);
4977 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4979 val
= insn_get(env
, s
, ot
);
4980 gen_op_movl_T1_im(val
);
4981 } else if (b
== 0x6b) {
4982 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4983 gen_op_movl_T1_im(val
);
4985 gen_op_mov_TN_reg(ot
, 1, reg
);
4988 #ifdef TARGET_X86_64
4989 if (ot
== OT_QUAD
) {
4990 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
4993 if (ot
== OT_LONG
) {
4994 #ifdef TARGET_X86_64
4995 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4996 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4997 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4998 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4999 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
5000 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5004 t0
= tcg_temp_new_i64();
5005 t1
= tcg_temp_new_i64();
5006 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
5007 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
5008 tcg_gen_mul_i64(t0
, t0
, t1
);
5009 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
5010 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5011 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
5012 tcg_gen_shri_i64(t0
, t0
, 32);
5013 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
5014 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
5018 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5019 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5020 /* XXX: use 32 bit mul which could be faster */
5021 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5022 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5023 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5024 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5026 gen_op_mov_reg_T0(ot
, reg
);
5027 set_cc_op(s
, CC_OP_MULB
+ ot
);
5030 case 0x1c1: /* xadd Ev, Gv */
5034 ot
= dflag
+ OT_WORD
;
5035 modrm
= cpu_ldub_code(env
, s
->pc
++);
5036 reg
= ((modrm
>> 3) & 7) | rex_r
;
5037 mod
= (modrm
>> 6) & 3;
5039 rm
= (modrm
& 7) | REX_B(s
);
5040 gen_op_mov_TN_reg(ot
, 0, reg
);
5041 gen_op_mov_TN_reg(ot
, 1, rm
);
5042 gen_op_addl_T0_T1();
5043 gen_op_mov_reg_T1(ot
, reg
);
5044 gen_op_mov_reg_T0(ot
, rm
);
5046 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5047 gen_op_mov_TN_reg(ot
, 0, reg
);
5048 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5049 gen_op_addl_T0_T1();
5050 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5051 gen_op_mov_reg_T1(ot
, reg
);
5053 gen_op_update2_cc();
5054 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5057 case 0x1b1: /* cmpxchg Ev, Gv */
5060 TCGv t0
, t1
, t2
, a0
;
5065 ot
= dflag
+ OT_WORD
;
5066 modrm
= cpu_ldub_code(env
, s
->pc
++);
5067 reg
= ((modrm
>> 3) & 7) | rex_r
;
5068 mod
= (modrm
>> 6) & 3;
5069 t0
= tcg_temp_local_new();
5070 t1
= tcg_temp_local_new();
5071 t2
= tcg_temp_local_new();
5072 a0
= tcg_temp_local_new();
5073 gen_op_mov_v_reg(ot
, t1
, reg
);
5075 rm
= (modrm
& 7) | REX_B(s
);
5076 gen_op_mov_v_reg(ot
, t0
, rm
);
5078 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5079 tcg_gen_mov_tl(a0
, cpu_A0
);
5080 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
5081 rm
= 0; /* avoid warning */
5083 label1
= gen_new_label();
5084 tcg_gen_sub_tl(t2
, cpu_regs
[R_EAX
], t0
);
5086 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
5087 label2
= gen_new_label();
5089 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5091 gen_set_label(label1
);
5092 gen_op_mov_reg_v(ot
, rm
, t1
);
5094 /* perform no-op store cycle like physical cpu; must be
5095 before changing accumulator to ensure idempotency if
5096 the store faults and the instruction is restarted */
5097 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
5098 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5100 gen_set_label(label1
);
5101 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
5103 gen_set_label(label2
);
5104 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5105 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
5106 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5113 case 0x1c7: /* cmpxchg8b */
5114 modrm
= cpu_ldub_code(env
, s
->pc
++);
5115 mod
= (modrm
>> 6) & 3;
5116 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5118 #ifdef TARGET_X86_64
5120 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5122 gen_jmp_im(pc_start
- s
->cs_base
);
5123 gen_update_cc_op(s
);
5124 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5125 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5129 if (!(s
->cpuid_features
& CPUID_CX8
))
5131 gen_jmp_im(pc_start
- s
->cs_base
);
5132 gen_update_cc_op(s
);
5133 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5134 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5136 set_cc_op(s
, CC_OP_EFLAGS
);
5139 /**************************/
5141 case 0x50 ... 0x57: /* push */
5142 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
5145 case 0x58 ... 0x5f: /* pop */
5147 ot
= dflag
? OT_QUAD
: OT_WORD
;
5149 ot
= dflag
+ OT_WORD
;
5152 /* NOTE: order is important for pop %sp */
5154 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5156 case 0x60: /* pusha */
5161 case 0x61: /* popa */
5166 case 0x68: /* push Iv */
5169 ot
= dflag
? OT_QUAD
: OT_WORD
;
5171 ot
= dflag
+ OT_WORD
;
5174 val
= insn_get(env
, s
, ot
);
5176 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
5177 gen_op_movl_T0_im(val
);
5180 case 0x8f: /* pop Ev */
5182 ot
= dflag
? OT_QUAD
: OT_WORD
;
5184 ot
= dflag
+ OT_WORD
;
5186 modrm
= cpu_ldub_code(env
, s
->pc
++);
5187 mod
= (modrm
>> 6) & 3;
5190 /* NOTE: order is important for pop %sp */
5192 rm
= (modrm
& 7) | REX_B(s
);
5193 gen_op_mov_reg_T0(ot
, rm
);
5195 /* NOTE: order is important too for MMU exceptions */
5196 s
->popl_esp_hack
= 1 << ot
;
5197 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5198 s
->popl_esp_hack
= 0;
5202 case 0xc8: /* enter */
5205 val
= cpu_lduw_code(env
, s
->pc
);
5207 level
= cpu_ldub_code(env
, s
->pc
++);
5208 gen_enter(s
, val
, level
);
5211 case 0xc9: /* leave */
5212 /* XXX: exception not precise (ESP is updated before potential exception) */
5214 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5215 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5216 } else if (s
->ss32
) {
5217 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5218 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5220 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5221 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5225 ot
= dflag
? OT_QUAD
: OT_WORD
;
5227 ot
= dflag
+ OT_WORD
;
5229 gen_op_mov_reg_T0(ot
, R_EBP
);
5232 case 0x06: /* push es */
5233 case 0x0e: /* push cs */
5234 case 0x16: /* push ss */
5235 case 0x1e: /* push ds */
5238 gen_op_movl_T0_seg(b
>> 3);
5241 case 0x1a0: /* push fs */
5242 case 0x1a8: /* push gs */
5243 gen_op_movl_T0_seg((b
>> 3) & 7);
5246 case 0x07: /* pop es */
5247 case 0x17: /* pop ss */
5248 case 0x1f: /* pop ds */
5253 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5256 /* if reg == SS, inhibit interrupts/trace. */
5257 /* If several instructions disable interrupts, only the
5259 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5260 gen_helper_set_inhibit_irq(cpu_env
);
5264 gen_jmp_im(s
->pc
- s
->cs_base
);
5268 case 0x1a1: /* pop fs */
5269 case 0x1a9: /* pop gs */
5271 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5274 gen_jmp_im(s
->pc
- s
->cs_base
);
5279 /**************************/
5282 case 0x89: /* mov Gv, Ev */
5286 ot
= dflag
+ OT_WORD
;
5287 modrm
= cpu_ldub_code(env
, s
->pc
++);
5288 reg
= ((modrm
>> 3) & 7) | rex_r
;
5290 /* generate a generic store */
5291 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5294 case 0xc7: /* mov Ev, Iv */
5298 ot
= dflag
+ OT_WORD
;
5299 modrm
= cpu_ldub_code(env
, s
->pc
++);
5300 mod
= (modrm
>> 6) & 3;
5302 s
->rip_offset
= insn_const_size(ot
);
5303 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5305 val
= insn_get(env
, s
, ot
);
5306 gen_op_movl_T0_im(val
);
5308 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5310 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5313 case 0x8b: /* mov Ev, Gv */
5317 ot
= OT_WORD
+ dflag
;
5318 modrm
= cpu_ldub_code(env
, s
->pc
++);
5319 reg
= ((modrm
>> 3) & 7) | rex_r
;
5321 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5322 gen_op_mov_reg_T0(ot
, reg
);
5324 case 0x8e: /* mov seg, Gv */
5325 modrm
= cpu_ldub_code(env
, s
->pc
++);
5326 reg
= (modrm
>> 3) & 7;
5327 if (reg
>= 6 || reg
== R_CS
)
5329 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5330 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5332 /* if reg == SS, inhibit interrupts/trace */
5333 /* If several instructions disable interrupts, only the
5335 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5336 gen_helper_set_inhibit_irq(cpu_env
);
5340 gen_jmp_im(s
->pc
- s
->cs_base
);
5344 case 0x8c: /* mov Gv, seg */
5345 modrm
= cpu_ldub_code(env
, s
->pc
++);
5346 reg
= (modrm
>> 3) & 7;
5347 mod
= (modrm
>> 6) & 3;
5350 gen_op_movl_T0_seg(reg
);
5352 ot
= OT_WORD
+ dflag
;
5355 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5358 case 0x1b6: /* movzbS Gv, Eb */
5359 case 0x1b7: /* movzwS Gv, Eb */
5360 case 0x1be: /* movsbS Gv, Eb */
5361 case 0x1bf: /* movswS Gv, Eb */
5364 /* d_ot is the size of destination */
5365 d_ot
= dflag
+ OT_WORD
;
5366 /* ot is the size of source */
5367 ot
= (b
& 1) + OT_BYTE
;
5368 modrm
= cpu_ldub_code(env
, s
->pc
++);
5369 reg
= ((modrm
>> 3) & 7) | rex_r
;
5370 mod
= (modrm
>> 6) & 3;
5371 rm
= (modrm
& 7) | REX_B(s
);
5374 gen_op_mov_TN_reg(ot
, 0, rm
);
5375 switch(ot
| (b
& 8)) {
5377 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5380 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5383 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5387 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5390 gen_op_mov_reg_T0(d_ot
, reg
);
5392 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5394 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5396 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5398 gen_op_mov_reg_T0(d_ot
, reg
);
5403 case 0x8d: /* lea */
5404 ot
= dflag
+ OT_WORD
;
5405 modrm
= cpu_ldub_code(env
, s
->pc
++);
5406 mod
= (modrm
>> 6) & 3;
5409 reg
= ((modrm
>> 3) & 7) | rex_r
;
5410 /* we must ensure that no segment is added */
5414 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5416 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5419 case 0xa0: /* mov EAX, Ov */
5421 case 0xa2: /* mov Ov, EAX */
5424 target_ulong offset_addr
;
5429 ot
= dflag
+ OT_WORD
;
5430 #ifdef TARGET_X86_64
5431 if (s
->aflag
== 2) {
5432 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5434 gen_op_movq_A0_im(offset_addr
);
5439 offset_addr
= insn_get(env
, s
, OT_LONG
);
5441 offset_addr
= insn_get(env
, s
, OT_WORD
);
5443 gen_op_movl_A0_im(offset_addr
);
5445 gen_add_A0_ds_seg(s
);
5447 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5448 gen_op_mov_reg_T0(ot
, R_EAX
);
5450 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5451 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5455 case 0xd7: /* xlat */
5456 #ifdef TARGET_X86_64
5457 if (s
->aflag
== 2) {
5458 gen_op_movq_A0_reg(R_EBX
);
5459 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5460 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5461 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5465 gen_op_movl_A0_reg(R_EBX
);
5466 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5467 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5468 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5470 gen_op_andl_A0_ffff();
5472 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5474 gen_add_A0_ds_seg(s
);
5475 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5476 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5478 case 0xb0 ... 0xb7: /* mov R, Ib */
5479 val
= insn_get(env
, s
, OT_BYTE
);
5480 gen_op_movl_T0_im(val
);
5481 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5483 case 0xb8 ... 0xbf: /* mov R, Iv */
5484 #ifdef TARGET_X86_64
5488 tmp
= cpu_ldq_code(env
, s
->pc
);
5490 reg
= (b
& 7) | REX_B(s
);
5491 gen_movtl_T0_im(tmp
);
5492 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5496 ot
= dflag
? OT_LONG
: OT_WORD
;
5497 val
= insn_get(env
, s
, ot
);
5498 reg
= (b
& 7) | REX_B(s
);
5499 gen_op_movl_T0_im(val
);
5500 gen_op_mov_reg_T0(ot
, reg
);
5504 case 0x91 ... 0x97: /* xchg R, EAX */
5506 ot
= dflag
+ OT_WORD
;
5507 reg
= (b
& 7) | REX_B(s
);
5511 case 0x87: /* xchg Ev, Gv */
5515 ot
= dflag
+ OT_WORD
;
5516 modrm
= cpu_ldub_code(env
, s
->pc
++);
5517 reg
= ((modrm
>> 3) & 7) | rex_r
;
5518 mod
= (modrm
>> 6) & 3;
5520 rm
= (modrm
& 7) | REX_B(s
);
5522 gen_op_mov_TN_reg(ot
, 0, reg
);
5523 gen_op_mov_TN_reg(ot
, 1, rm
);
5524 gen_op_mov_reg_T0(ot
, rm
);
5525 gen_op_mov_reg_T1(ot
, reg
);
5527 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5528 gen_op_mov_TN_reg(ot
, 0, reg
);
5529 /* for xchg, lock is implicit */
5530 if (!(prefixes
& PREFIX_LOCK
))
5532 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5533 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5534 if (!(prefixes
& PREFIX_LOCK
))
5535 gen_helper_unlock();
5536 gen_op_mov_reg_T1(ot
, reg
);
5539 case 0xc4: /* les Gv */
5544 case 0xc5: /* lds Gv */
5549 case 0x1b2: /* lss Gv */
5552 case 0x1b4: /* lfs Gv */
5555 case 0x1b5: /* lgs Gv */
5558 ot
= dflag
? OT_LONG
: OT_WORD
;
5559 modrm
= cpu_ldub_code(env
, s
->pc
++);
5560 reg
= ((modrm
>> 3) & 7) | rex_r
;
5561 mod
= (modrm
>> 6) & 3;
5564 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5565 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5566 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5567 /* load the segment first to handle exceptions properly */
5568 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5569 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5570 /* then put the data */
5571 gen_op_mov_reg_T1(ot
, reg
);
5573 gen_jmp_im(s
->pc
- s
->cs_base
);
5578 /************************/
5589 ot
= dflag
+ OT_WORD
;
5591 modrm
= cpu_ldub_code(env
, s
->pc
++);
5592 mod
= (modrm
>> 6) & 3;
5593 op
= (modrm
>> 3) & 7;
5599 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5602 opreg
= (modrm
& 7) | REX_B(s
);
5607 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5610 shift
= cpu_ldub_code(env
, s
->pc
++);
5612 gen_shifti(s
, op
, ot
, opreg
, shift
);
5627 case 0x1a4: /* shld imm */
5631 case 0x1a5: /* shld cl */
5635 case 0x1ac: /* shrd imm */
5639 case 0x1ad: /* shrd cl */
5643 ot
= dflag
+ OT_WORD
;
5644 modrm
= cpu_ldub_code(env
, s
->pc
++);
5645 mod
= (modrm
>> 6) & 3;
5646 rm
= (modrm
& 7) | REX_B(s
);
5647 reg
= ((modrm
>> 3) & 7) | rex_r
;
5649 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5654 gen_op_mov_TN_reg(ot
, 1, reg
);
5657 val
= cpu_ldub_code(env
, s
->pc
++);
5658 tcg_gen_movi_tl(cpu_T3
, val
);
5660 tcg_gen_mov_tl(cpu_T3
, cpu_regs
[R_ECX
]);
5662 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
5665 /************************/
5668 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5669 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5670 /* XXX: what to do if illegal op ? */
5671 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5674 modrm
= cpu_ldub_code(env
, s
->pc
++);
5675 mod
= (modrm
>> 6) & 3;
5677 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5680 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5682 case 0x00 ... 0x07: /* fxxxs */
5683 case 0x10 ... 0x17: /* fixxxl */
5684 case 0x20 ... 0x27: /* fxxxl */
5685 case 0x30 ... 0x37: /* fixxx */
5692 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5693 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5694 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5697 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5698 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5699 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5702 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5703 (s
->mem_index
>> 2) - 1);
5704 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5708 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5709 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5710 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5714 gen_helper_fp_arith_ST0_FT0(op1
);
5716 /* fcomp needs pop */
5717 gen_helper_fpop(cpu_env
);
5721 case 0x08: /* flds */
5722 case 0x0a: /* fsts */
5723 case 0x0b: /* fstps */
5724 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5725 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5726 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5731 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5732 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5733 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5736 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5737 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5738 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5741 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5742 (s
->mem_index
>> 2) - 1);
5743 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5747 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5748 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5749 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5754 /* XXX: the corresponding CPUID bit must be tested ! */
5757 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5758 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5759 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5762 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5763 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5764 (s
->mem_index
>> 2) - 1);
5768 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5769 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5770 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5773 gen_helper_fpop(cpu_env
);
5778 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5779 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5780 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5783 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5784 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5785 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5788 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5789 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5790 (s
->mem_index
>> 2) - 1);
5794 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5795 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5796 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5800 gen_helper_fpop(cpu_env
);
5804 case 0x0c: /* fldenv mem */
5805 gen_update_cc_op(s
);
5806 gen_jmp_im(pc_start
- s
->cs_base
);
5807 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5809 case 0x0d: /* fldcw mem */
5810 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5811 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5812 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5814 case 0x0e: /* fnstenv mem */
5815 gen_update_cc_op(s
);
5816 gen_jmp_im(pc_start
- s
->cs_base
);
5817 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5819 case 0x0f: /* fnstcw mem */
5820 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5821 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5822 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5824 case 0x1d: /* fldt mem */
5825 gen_update_cc_op(s
);
5826 gen_jmp_im(pc_start
- s
->cs_base
);
5827 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5829 case 0x1f: /* fstpt mem */
5830 gen_update_cc_op(s
);
5831 gen_jmp_im(pc_start
- s
->cs_base
);
5832 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5833 gen_helper_fpop(cpu_env
);
5835 case 0x2c: /* frstor mem */
5836 gen_update_cc_op(s
);
5837 gen_jmp_im(pc_start
- s
->cs_base
);
5838 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5840 case 0x2e: /* fnsave mem */
5841 gen_update_cc_op(s
);
5842 gen_jmp_im(pc_start
- s
->cs_base
);
5843 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5845 case 0x2f: /* fnstsw mem */
5846 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5847 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5848 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5850 case 0x3c: /* fbld */
5851 gen_update_cc_op(s
);
5852 gen_jmp_im(pc_start
- s
->cs_base
);
5853 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5855 case 0x3e: /* fbstp */
5856 gen_update_cc_op(s
);
5857 gen_jmp_im(pc_start
- s
->cs_base
);
5858 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5859 gen_helper_fpop(cpu_env
);
5861 case 0x3d: /* fildll */
5862 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5863 (s
->mem_index
>> 2) - 1);
5864 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5866 case 0x3f: /* fistpll */
5867 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5868 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5869 (s
->mem_index
>> 2) - 1);
5870 gen_helper_fpop(cpu_env
);
5876 /* register float ops */
5880 case 0x08: /* fld sti */
5881 gen_helper_fpush(cpu_env
);
5882 gen_helper_fmov_ST0_STN(cpu_env
,
5883 tcg_const_i32((opreg
+ 1) & 7));
5885 case 0x09: /* fxchg sti */
5886 case 0x29: /* fxchg4 sti, undocumented op */
5887 case 0x39: /* fxchg7 sti, undocumented op */
5888 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5890 case 0x0a: /* grp d9/2 */
5893 /* check exceptions (FreeBSD FPU probe) */
5894 gen_update_cc_op(s
);
5895 gen_jmp_im(pc_start
- s
->cs_base
);
5896 gen_helper_fwait(cpu_env
);
5902 case 0x0c: /* grp d9/4 */
5905 gen_helper_fchs_ST0(cpu_env
);
5908 gen_helper_fabs_ST0(cpu_env
);
5911 gen_helper_fldz_FT0(cpu_env
);
5912 gen_helper_fcom_ST0_FT0(cpu_env
);
5915 gen_helper_fxam_ST0(cpu_env
);
5921 case 0x0d: /* grp d9/5 */
5925 gen_helper_fpush(cpu_env
);
5926 gen_helper_fld1_ST0(cpu_env
);
5929 gen_helper_fpush(cpu_env
);
5930 gen_helper_fldl2t_ST0(cpu_env
);
5933 gen_helper_fpush(cpu_env
);
5934 gen_helper_fldl2e_ST0(cpu_env
);
5937 gen_helper_fpush(cpu_env
);
5938 gen_helper_fldpi_ST0(cpu_env
);
5941 gen_helper_fpush(cpu_env
);
5942 gen_helper_fldlg2_ST0(cpu_env
);
5945 gen_helper_fpush(cpu_env
);
5946 gen_helper_fldln2_ST0(cpu_env
);
5949 gen_helper_fpush(cpu_env
);
5950 gen_helper_fldz_ST0(cpu_env
);
5957 case 0x0e: /* grp d9/6 */
5960 gen_helper_f2xm1(cpu_env
);
5963 gen_helper_fyl2x(cpu_env
);
5966 gen_helper_fptan(cpu_env
);
5968 case 3: /* fpatan */
5969 gen_helper_fpatan(cpu_env
);
5971 case 4: /* fxtract */
5972 gen_helper_fxtract(cpu_env
);
5974 case 5: /* fprem1 */
5975 gen_helper_fprem1(cpu_env
);
5977 case 6: /* fdecstp */
5978 gen_helper_fdecstp(cpu_env
);
5981 case 7: /* fincstp */
5982 gen_helper_fincstp(cpu_env
);
5986 case 0x0f: /* grp d9/7 */
5989 gen_helper_fprem(cpu_env
);
5991 case 1: /* fyl2xp1 */
5992 gen_helper_fyl2xp1(cpu_env
);
5995 gen_helper_fsqrt(cpu_env
);
5997 case 3: /* fsincos */
5998 gen_helper_fsincos(cpu_env
);
6000 case 5: /* fscale */
6001 gen_helper_fscale(cpu_env
);
6003 case 4: /* frndint */
6004 gen_helper_frndint(cpu_env
);
6007 gen_helper_fsin(cpu_env
);
6011 gen_helper_fcos(cpu_env
);
6015 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6016 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6017 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6023 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6025 gen_helper_fpop(cpu_env
);
6027 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6028 gen_helper_fp_arith_ST0_FT0(op1
);
6032 case 0x02: /* fcom */
6033 case 0x22: /* fcom2, undocumented op */
6034 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6035 gen_helper_fcom_ST0_FT0(cpu_env
);
6037 case 0x03: /* fcomp */
6038 case 0x23: /* fcomp3, undocumented op */
6039 case 0x32: /* fcomp5, undocumented op */
6040 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6041 gen_helper_fcom_ST0_FT0(cpu_env
);
6042 gen_helper_fpop(cpu_env
);
6044 case 0x15: /* da/5 */
6046 case 1: /* fucompp */
6047 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6048 gen_helper_fucom_ST0_FT0(cpu_env
);
6049 gen_helper_fpop(cpu_env
);
6050 gen_helper_fpop(cpu_env
);
6058 case 0: /* feni (287 only, just do nop here) */
6060 case 1: /* fdisi (287 only, just do nop here) */
6063 gen_helper_fclex(cpu_env
);
6065 case 3: /* fninit */
6066 gen_helper_fninit(cpu_env
);
6068 case 4: /* fsetpm (287 only, just do nop here) */
6074 case 0x1d: /* fucomi */
6075 gen_update_cc_op(s
);
6076 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6077 gen_helper_fucomi_ST0_FT0(cpu_env
);
6078 set_cc_op(s
, CC_OP_EFLAGS
);
6080 case 0x1e: /* fcomi */
6081 gen_update_cc_op(s
);
6082 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6083 gen_helper_fcomi_ST0_FT0(cpu_env
);
6084 set_cc_op(s
, CC_OP_EFLAGS
);
6086 case 0x28: /* ffree sti */
6087 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6089 case 0x2a: /* fst sti */
6090 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6092 case 0x2b: /* fstp sti */
6093 case 0x0b: /* fstp1 sti, undocumented op */
6094 case 0x3a: /* fstp8 sti, undocumented op */
6095 case 0x3b: /* fstp9 sti, undocumented op */
6096 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6097 gen_helper_fpop(cpu_env
);
6099 case 0x2c: /* fucom st(i) */
6100 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6101 gen_helper_fucom_ST0_FT0(cpu_env
);
6103 case 0x2d: /* fucomp st(i) */
6104 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6105 gen_helper_fucom_ST0_FT0(cpu_env
);
6106 gen_helper_fpop(cpu_env
);
6108 case 0x33: /* de/3 */
6110 case 1: /* fcompp */
6111 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6112 gen_helper_fcom_ST0_FT0(cpu_env
);
6113 gen_helper_fpop(cpu_env
);
6114 gen_helper_fpop(cpu_env
);
6120 case 0x38: /* ffreep sti, undocumented op */
6121 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6122 gen_helper_fpop(cpu_env
);
6124 case 0x3c: /* df/4 */
6127 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6128 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6129 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
6135 case 0x3d: /* fucomip */
6136 gen_update_cc_op(s
);
6137 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6138 gen_helper_fucomi_ST0_FT0(cpu_env
);
6139 gen_helper_fpop(cpu_env
);
6140 set_cc_op(s
, CC_OP_EFLAGS
);
6142 case 0x3e: /* fcomip */
6143 gen_update_cc_op(s
);
6144 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6145 gen_helper_fcomi_ST0_FT0(cpu_env
);
6146 gen_helper_fpop(cpu_env
);
6147 set_cc_op(s
, CC_OP_EFLAGS
);
6149 case 0x10 ... 0x13: /* fcmovxx */
6153 static const uint8_t fcmov_cc
[8] = {
6159 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6160 l1
= gen_new_label();
6161 gen_jcc1(s
, op1
, l1
);
6162 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6171 /************************/
6174 case 0xa4: /* movsS */
6179 ot
= dflag
+ OT_WORD
;
6181 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6182 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6188 case 0xaa: /* stosS */
6193 ot
= dflag
+ OT_WORD
;
6195 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6196 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6201 case 0xac: /* lodsS */
6206 ot
= dflag
+ OT_WORD
;
6207 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6208 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6213 case 0xae: /* scasS */
6218 ot
= dflag
+ OT_WORD
;
6219 if (prefixes
& PREFIX_REPNZ
) {
6220 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6221 } else if (prefixes
& PREFIX_REPZ
) {
6222 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6228 case 0xa6: /* cmpsS */
6233 ot
= dflag
+ OT_WORD
;
6234 if (prefixes
& PREFIX_REPNZ
) {
6235 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6236 } else if (prefixes
& PREFIX_REPZ
) {
6237 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6242 case 0x6c: /* insS */
6247 ot
= dflag
? OT_LONG
: OT_WORD
;
6248 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6249 gen_op_andl_T0_ffff();
6250 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6251 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6252 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6253 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6257 gen_jmp(s
, s
->pc
- s
->cs_base
);
6261 case 0x6e: /* outsS */
6266 ot
= dflag
? OT_LONG
: OT_WORD
;
6267 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6268 gen_op_andl_T0_ffff();
6269 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6270 svm_is_rep(prefixes
) | 4);
6271 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6272 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6276 gen_jmp(s
, s
->pc
- s
->cs_base
);
6281 /************************/
6289 ot
= dflag
? OT_LONG
: OT_WORD
;
6290 val
= cpu_ldub_code(env
, s
->pc
++);
6291 gen_op_movl_T0_im(val
);
6292 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6293 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6296 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6297 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6298 gen_op_mov_reg_T1(ot
, R_EAX
);
6301 gen_jmp(s
, s
->pc
- s
->cs_base
);
6309 ot
= dflag
? OT_LONG
: OT_WORD
;
6310 val
= cpu_ldub_code(env
, s
->pc
++);
6311 gen_op_movl_T0_im(val
);
6312 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6313 svm_is_rep(prefixes
));
6314 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6318 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6319 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6320 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6323 gen_jmp(s
, s
->pc
- s
->cs_base
);
6331 ot
= dflag
? OT_LONG
: OT_WORD
;
6332 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6333 gen_op_andl_T0_ffff();
6334 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6335 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6338 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6339 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6340 gen_op_mov_reg_T1(ot
, R_EAX
);
6343 gen_jmp(s
, s
->pc
- s
->cs_base
);
6351 ot
= dflag
? OT_LONG
: OT_WORD
;
6352 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6353 gen_op_andl_T0_ffff();
6354 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6355 svm_is_rep(prefixes
));
6356 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6360 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6361 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6362 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6365 gen_jmp(s
, s
->pc
- s
->cs_base
);
6369 /************************/
6371 case 0xc2: /* ret im */
6372 val
= cpu_ldsw_code(env
, s
->pc
);
6375 if (CODE64(s
) && s
->dflag
)
6377 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6379 gen_op_andl_T0_ffff();
6383 case 0xc3: /* ret */
6387 gen_op_andl_T0_ffff();
6391 case 0xca: /* lret im */
6392 val
= cpu_ldsw_code(env
, s
->pc
);
6395 if (s
->pe
&& !s
->vm86
) {
6396 gen_update_cc_op(s
);
6397 gen_jmp_im(pc_start
- s
->cs_base
);
6398 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6399 tcg_const_i32(val
));
6403 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6405 gen_op_andl_T0_ffff();
6406 /* NOTE: keeping EIP updated is not a problem in case of
6410 gen_op_addl_A0_im(2 << s
->dflag
);
6411 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6412 gen_op_movl_seg_T0_vm(R_CS
);
6413 /* add stack offset */
6414 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6418 case 0xcb: /* lret */
6421 case 0xcf: /* iret */
6422 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6425 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6426 set_cc_op(s
, CC_OP_EFLAGS
);
6427 } else if (s
->vm86
) {
6429 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6431 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6432 set_cc_op(s
, CC_OP_EFLAGS
);
6435 gen_update_cc_op(s
);
6436 gen_jmp_im(pc_start
- s
->cs_base
);
6437 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6438 tcg_const_i32(s
->pc
- s
->cs_base
));
6439 set_cc_op(s
, CC_OP_EFLAGS
);
6443 case 0xe8: /* call im */
6446 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6448 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6449 next_eip
= s
->pc
- s
->cs_base
;
6455 gen_movtl_T0_im(next_eip
);
6460 case 0x9a: /* lcall im */
6462 unsigned int selector
, offset
;
6466 ot
= dflag
? OT_LONG
: OT_WORD
;
6467 offset
= insn_get(env
, s
, ot
);
6468 selector
= insn_get(env
, s
, OT_WORD
);
6470 gen_op_movl_T0_im(selector
);
6471 gen_op_movl_T1_imu(offset
);
6474 case 0xe9: /* jmp im */
6476 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6478 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6479 tval
+= s
->pc
- s
->cs_base
;
6486 case 0xea: /* ljmp im */
6488 unsigned int selector
, offset
;
6492 ot
= dflag
? OT_LONG
: OT_WORD
;
6493 offset
= insn_get(env
, s
, ot
);
6494 selector
= insn_get(env
, s
, OT_WORD
);
6496 gen_op_movl_T0_im(selector
);
6497 gen_op_movl_T1_imu(offset
);
6500 case 0xeb: /* jmp Jb */
6501 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6502 tval
+= s
->pc
- s
->cs_base
;
6507 case 0x70 ... 0x7f: /* jcc Jb */
6508 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6510 case 0x180 ... 0x18f: /* jcc Jv */
6512 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6514 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6517 next_eip
= s
->pc
- s
->cs_base
;
6521 gen_jcc(s
, b
, tval
, next_eip
);
6524 case 0x190 ... 0x19f: /* setcc Gv */
6525 modrm
= cpu_ldub_code(env
, s
->pc
++);
6527 gen_ldst_modrm(env
, s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6529 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6534 ot
= dflag
+ OT_WORD
;
6535 modrm
= cpu_ldub_code(env
, s
->pc
++);
6536 reg
= ((modrm
>> 3) & 7) | rex_r
;
6537 mod
= (modrm
>> 6) & 3;
6538 t0
= tcg_temp_local_new();
6540 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6541 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6543 rm
= (modrm
& 7) | REX_B(s
);
6544 gen_op_mov_v_reg(ot
, t0
, rm
);
6546 #ifdef TARGET_X86_64
6547 if (ot
== OT_LONG
) {
6548 /* XXX: specific Intel behaviour ? */
6549 l1
= gen_new_label();
6550 gen_jcc1(s
, b
^ 1, l1
);
6551 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
6553 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_regs
[reg
]);
6557 l1
= gen_new_label();
6558 gen_jcc1(s
, b
^ 1, l1
);
6559 gen_op_mov_reg_v(ot
, reg
, t0
);
6566 /************************/
6568 case 0x9c: /* pushf */
6569 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6570 if (s
->vm86
&& s
->iopl
!= 3) {
6571 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6573 gen_update_cc_op(s
);
6574 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6578 case 0x9d: /* popf */
6579 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6580 if (s
->vm86
&& s
->iopl
!= 3) {
6581 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6586 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6587 tcg_const_i32((TF_MASK
| AC_MASK
|
6592 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6593 tcg_const_i32((TF_MASK
| AC_MASK
|
6595 IF_MASK
| IOPL_MASK
)
6599 if (s
->cpl
<= s
->iopl
) {
6601 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6602 tcg_const_i32((TF_MASK
|
6608 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6609 tcg_const_i32((TF_MASK
|
6618 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6619 tcg_const_i32((TF_MASK
| AC_MASK
|
6620 ID_MASK
| NT_MASK
)));
6622 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6623 tcg_const_i32((TF_MASK
| AC_MASK
|
6630 set_cc_op(s
, CC_OP_EFLAGS
);
6631 /* abort translation because TF/AC flag may change */
6632 gen_jmp_im(s
->pc
- s
->cs_base
);
6636 case 0x9e: /* sahf */
6637 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6639 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6640 gen_compute_eflags(s
);
6641 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6642 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6643 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6645 case 0x9f: /* lahf */
6646 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6648 gen_compute_eflags(s
);
6649 /* Note: gen_compute_eflags() only gives the condition codes */
6650 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6651 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6653 case 0xf5: /* cmc */
6654 gen_compute_eflags(s
);
6655 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6657 case 0xf8: /* clc */
6658 gen_compute_eflags(s
);
6659 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6661 case 0xf9: /* stc */
6662 gen_compute_eflags(s
);
6663 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6665 case 0xfc: /* cld */
6666 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6667 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6669 case 0xfd: /* std */
6670 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6671 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6674 /************************/
6675 /* bit operations */
6676 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6677 ot
= dflag
+ OT_WORD
;
6678 modrm
= cpu_ldub_code(env
, s
->pc
++);
6679 op
= (modrm
>> 3) & 7;
6680 mod
= (modrm
>> 6) & 3;
6681 rm
= (modrm
& 7) | REX_B(s
);
6684 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6685 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6687 gen_op_mov_TN_reg(ot
, 0, rm
);
6690 val
= cpu_ldub_code(env
, s
->pc
++);
6691 gen_op_movl_T1_im(val
);
6696 case 0x1a3: /* bt Gv, Ev */
6699 case 0x1ab: /* bts */
6702 case 0x1b3: /* btr */
6705 case 0x1bb: /* btc */
6708 ot
= dflag
+ OT_WORD
;
6709 modrm
= cpu_ldub_code(env
, s
->pc
++);
6710 reg
= ((modrm
>> 3) & 7) | rex_r
;
6711 mod
= (modrm
>> 6) & 3;
6712 rm
= (modrm
& 7) | REX_B(s
);
6713 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6715 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6716 /* specific case: we need to add a displacement */
6717 gen_exts(ot
, cpu_T
[1]);
6718 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6719 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6720 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6721 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6723 gen_op_mov_TN_reg(ot
, 0, rm
);
6726 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6729 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6730 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6733 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6734 tcg_gen_movi_tl(cpu_tmp0
, 1);
6735 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6736 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6739 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6740 tcg_gen_movi_tl(cpu_tmp0
, 1);
6741 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6742 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6743 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6747 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6748 tcg_gen_movi_tl(cpu_tmp0
, 1);
6749 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6750 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6753 set_cc_op(s
, CC_OP_SARB
+ ot
);
6756 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6758 gen_op_mov_reg_T0(ot
, rm
);
6759 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6760 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6763 case 0x1bc: /* bsf */
6764 case 0x1bd: /* bsr */
6769 ot
= dflag
+ OT_WORD
;
6770 modrm
= cpu_ldub_code(env
, s
->pc
++);
6771 reg
= ((modrm
>> 3) & 7) | rex_r
;
6772 gen_ldst_modrm(env
, s
,modrm
, ot
, OR_TMP0
, 0);
6773 gen_extu(ot
, cpu_T
[0]);
6774 t0
= tcg_temp_local_new();
6775 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6776 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6777 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6779 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6780 tcg_const_i32(16)); break;
6781 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6782 tcg_const_i32(32)); break;
6783 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6784 tcg_const_i32(64)); break;
6786 gen_op_mov_reg_T0(ot
, reg
);
6788 label1
= gen_new_label();
6789 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6790 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6792 gen_helper_bsr(cpu_T
[0], t0
);
6794 gen_helper_bsf(cpu_T
[0], t0
);
6796 gen_op_mov_reg_T0(ot
, reg
);
6797 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6798 gen_set_label(label1
);
6799 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6804 /************************/
6806 case 0x27: /* daa */
6809 gen_update_cc_op(s
);
6810 gen_helper_daa(cpu_env
);
6811 set_cc_op(s
, CC_OP_EFLAGS
);
6813 case 0x2f: /* das */
6816 gen_update_cc_op(s
);
6817 gen_helper_das(cpu_env
);
6818 set_cc_op(s
, CC_OP_EFLAGS
);
6820 case 0x37: /* aaa */
6823 gen_update_cc_op(s
);
6824 gen_helper_aaa(cpu_env
);
6825 set_cc_op(s
, CC_OP_EFLAGS
);
6827 case 0x3f: /* aas */
6830 gen_update_cc_op(s
);
6831 gen_helper_aas(cpu_env
);
6832 set_cc_op(s
, CC_OP_EFLAGS
);
6834 case 0xd4: /* aam */
6837 val
= cpu_ldub_code(env
, s
->pc
++);
6839 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6841 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6842 set_cc_op(s
, CC_OP_LOGICB
);
6845 case 0xd5: /* aad */
6848 val
= cpu_ldub_code(env
, s
->pc
++);
6849 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6850 set_cc_op(s
, CC_OP_LOGICB
);
6852 /************************/
6854 case 0x90: /* nop */
6855 /* XXX: correct lock test for all insn */
6856 if (prefixes
& PREFIX_LOCK
) {
6859 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6861 goto do_xchg_reg_eax
;
6863 if (prefixes
& PREFIX_REPZ
) {
6864 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6867 case 0x9b: /* fwait */
6868 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6869 (HF_MP_MASK
| HF_TS_MASK
)) {
6870 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6872 gen_update_cc_op(s
);
6873 gen_jmp_im(pc_start
- s
->cs_base
);
6874 gen_helper_fwait(cpu_env
);
6877 case 0xcc: /* int3 */
6878 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6880 case 0xcd: /* int N */
6881 val
= cpu_ldub_code(env
, s
->pc
++);
6882 if (s
->vm86
&& s
->iopl
!= 3) {
6883 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6885 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6888 case 0xce: /* into */
6891 gen_update_cc_op(s
);
6892 gen_jmp_im(pc_start
- s
->cs_base
);
6893 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6896 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6897 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6899 gen_debug(s
, pc_start
- s
->cs_base
);
6903 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6907 case 0xfa: /* cli */
6909 if (s
->cpl
<= s
->iopl
) {
6910 gen_helper_cli(cpu_env
);
6912 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6916 gen_helper_cli(cpu_env
);
6918 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6922 case 0xfb: /* sti */
6924 if (s
->cpl
<= s
->iopl
) {
6926 gen_helper_sti(cpu_env
);
6927 /* interruptions are enabled only the first insn after sti */
6928 /* If several instructions disable interrupts, only the
6930 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6931 gen_helper_set_inhibit_irq(cpu_env
);
6932 /* give a chance to handle pending irqs */
6933 gen_jmp_im(s
->pc
- s
->cs_base
);
6936 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6942 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6946 case 0x62: /* bound */
6949 ot
= dflag
? OT_LONG
: OT_WORD
;
6950 modrm
= cpu_ldub_code(env
, s
->pc
++);
6951 reg
= (modrm
>> 3) & 7;
6952 mod
= (modrm
>> 6) & 3;
6955 gen_op_mov_TN_reg(ot
, 0, reg
);
6956 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6957 gen_jmp_im(pc_start
- s
->cs_base
);
6958 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6959 if (ot
== OT_WORD
) {
6960 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6962 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6965 case 0x1c8 ... 0x1cf: /* bswap reg */
6966 reg
= (b
& 7) | REX_B(s
);
6967 #ifdef TARGET_X86_64
6969 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6970 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6971 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6975 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6976 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6977 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6978 gen_op_mov_reg_T0(OT_LONG
, reg
);
6981 case 0xd6: /* salc */
6984 gen_compute_eflags_c(s
, cpu_T
[0], false);
6985 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6986 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6988 case 0xe0: /* loopnz */
6989 case 0xe1: /* loopz */
6990 case 0xe2: /* loop */
6991 case 0xe3: /* jecxz */
6995 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6996 next_eip
= s
->pc
- s
->cs_base
;
7001 l1
= gen_new_label();
7002 l2
= gen_new_label();
7003 l3
= gen_new_label();
7006 case 0: /* loopnz */
7008 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7009 gen_op_jz_ecx(s
->aflag
, l3
);
7010 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7013 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7014 gen_op_jnz_ecx(s
->aflag
, l1
);
7018 gen_op_jz_ecx(s
->aflag
, l1
);
7023 gen_jmp_im(next_eip
);
7032 case 0x130: /* wrmsr */
7033 case 0x132: /* rdmsr */
7035 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7037 gen_update_cc_op(s
);
7038 gen_jmp_im(pc_start
- s
->cs_base
);
7040 gen_helper_rdmsr(cpu_env
);
7042 gen_helper_wrmsr(cpu_env
);
7046 case 0x131: /* rdtsc */
7047 gen_update_cc_op(s
);
7048 gen_jmp_im(pc_start
- s
->cs_base
);
7051 gen_helper_rdtsc(cpu_env
);
7054 gen_jmp(s
, s
->pc
- s
->cs_base
);
7057 case 0x133: /* rdpmc */
7058 gen_update_cc_op(s
);
7059 gen_jmp_im(pc_start
- s
->cs_base
);
7060 gen_helper_rdpmc(cpu_env
);
7062 case 0x134: /* sysenter */
7063 /* For Intel SYSENTER is valid on 64-bit */
7064 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7067 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7069 gen_update_cc_op(s
);
7070 gen_jmp_im(pc_start
- s
->cs_base
);
7071 gen_helper_sysenter(cpu_env
);
7075 case 0x135: /* sysexit */
7076 /* For Intel SYSEXIT is valid on 64-bit */
7077 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7080 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7082 gen_update_cc_op(s
);
7083 gen_jmp_im(pc_start
- s
->cs_base
);
7084 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7088 #ifdef TARGET_X86_64
7089 case 0x105: /* syscall */
7090 /* XXX: is it usable in real mode ? */
7091 gen_update_cc_op(s
);
7092 gen_jmp_im(pc_start
- s
->cs_base
);
7093 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7096 case 0x107: /* sysret */
7098 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7100 gen_update_cc_op(s
);
7101 gen_jmp_im(pc_start
- s
->cs_base
);
7102 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7103 /* condition codes are modified only in long mode */
7105 set_cc_op(s
, CC_OP_EFLAGS
);
7111 case 0x1a2: /* cpuid */
7112 gen_update_cc_op(s
);
7113 gen_jmp_im(pc_start
- s
->cs_base
);
7114 gen_helper_cpuid(cpu_env
);
7116 case 0xf4: /* hlt */
7118 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7120 gen_update_cc_op(s
);
7121 gen_jmp_im(pc_start
- s
->cs_base
);
7122 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7123 s
->is_jmp
= DISAS_TB_JUMP
;
7127 modrm
= cpu_ldub_code(env
, s
->pc
++);
7128 mod
= (modrm
>> 6) & 3;
7129 op
= (modrm
>> 3) & 7;
7132 if (!s
->pe
|| s
->vm86
)
7134 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7135 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7139 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7142 if (!s
->pe
|| s
->vm86
)
7145 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7147 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7148 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7149 gen_jmp_im(pc_start
- s
->cs_base
);
7150 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7151 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7155 if (!s
->pe
|| s
->vm86
)
7157 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7158 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7162 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7165 if (!s
->pe
|| s
->vm86
)
7168 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7170 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7171 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7172 gen_jmp_im(pc_start
- s
->cs_base
);
7173 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7174 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7179 if (!s
->pe
|| s
->vm86
)
7181 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7182 gen_update_cc_op(s
);
7184 gen_helper_verr(cpu_env
, cpu_T
[0]);
7186 gen_helper_verw(cpu_env
, cpu_T
[0]);
7188 set_cc_op(s
, CC_OP_EFLAGS
);
7195 modrm
= cpu_ldub_code(env
, s
->pc
++);
7196 mod
= (modrm
>> 6) & 3;
7197 op
= (modrm
>> 3) & 7;
7203 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7204 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7205 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7206 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7207 gen_add_A0_im(s
, 2);
7208 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7210 gen_op_andl_T0_im(0xffffff);
7211 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7216 case 0: /* monitor */
7217 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7220 gen_update_cc_op(s
);
7221 gen_jmp_im(pc_start
- s
->cs_base
);
7222 #ifdef TARGET_X86_64
7223 if (s
->aflag
== 2) {
7224 gen_op_movq_A0_reg(R_EAX
);
7228 gen_op_movl_A0_reg(R_EAX
);
7230 gen_op_andl_A0_ffff();
7232 gen_add_A0_ds_seg(s
);
7233 gen_helper_monitor(cpu_env
, cpu_A0
);
7236 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7239 gen_update_cc_op(s
);
7240 gen_jmp_im(pc_start
- s
->cs_base
);
7241 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7245 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7249 gen_helper_clac(cpu_env
);
7250 gen_jmp_im(s
->pc
- s
->cs_base
);
7254 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7258 gen_helper_stac(cpu_env
);
7259 gen_jmp_im(s
->pc
- s
->cs_base
);
7266 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7267 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7268 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7269 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7270 gen_add_A0_im(s
, 2);
7271 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7273 gen_op_andl_T0_im(0xffffff);
7274 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7280 gen_update_cc_op(s
);
7281 gen_jmp_im(pc_start
- s
->cs_base
);
7284 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7287 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7290 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7291 tcg_const_i32(s
->pc
- pc_start
));
7293 s
->is_jmp
= DISAS_TB_JUMP
;
7296 case 1: /* VMMCALL */
7297 if (!(s
->flags
& HF_SVME_MASK
))
7299 gen_helper_vmmcall(cpu_env
);
7301 case 2: /* VMLOAD */
7302 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7305 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7308 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7311 case 3: /* VMSAVE */
7312 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7315 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7318 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7322 if ((!(s
->flags
& HF_SVME_MASK
) &&
7323 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7327 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7330 gen_helper_stgi(cpu_env
);
7334 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7337 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7340 gen_helper_clgi(cpu_env
);
7343 case 6: /* SKINIT */
7344 if ((!(s
->flags
& HF_SVME_MASK
) &&
7345 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7348 gen_helper_skinit(cpu_env
);
7350 case 7: /* INVLPGA */
7351 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7354 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7357 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7363 } else if (s
->cpl
!= 0) {
7364 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7366 gen_svm_check_intercept(s
, pc_start
,
7367 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7368 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7369 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7370 gen_add_A0_im(s
, 2);
7371 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7373 gen_op_andl_T0_im(0xffffff);
7375 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7376 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7378 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7379 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7384 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7385 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7386 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7388 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7390 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7394 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7396 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7397 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7398 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7399 gen_jmp_im(s
->pc
- s
->cs_base
);
7404 if (mod
!= 3) { /* invlpg */
7406 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7408 gen_update_cc_op(s
);
7409 gen_jmp_im(pc_start
- s
->cs_base
);
7410 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7411 gen_helper_invlpg(cpu_env
, cpu_A0
);
7412 gen_jmp_im(s
->pc
- s
->cs_base
);
7417 case 0: /* swapgs */
7418 #ifdef TARGET_X86_64
7421 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7423 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7424 offsetof(CPUX86State
,segs
[R_GS
].base
));
7425 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7426 offsetof(CPUX86State
,kernelgsbase
));
7427 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7428 offsetof(CPUX86State
,segs
[R_GS
].base
));
7429 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7430 offsetof(CPUX86State
,kernelgsbase
));
7438 case 1: /* rdtscp */
7439 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7441 gen_update_cc_op(s
);
7442 gen_jmp_im(pc_start
- s
->cs_base
);
7445 gen_helper_rdtscp(cpu_env
);
7448 gen_jmp(s
, s
->pc
- s
->cs_base
);
7460 case 0x108: /* invd */
7461 case 0x109: /* wbinvd */
7463 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7465 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7469 case 0x63: /* arpl or movslS (x86_64) */
7470 #ifdef TARGET_X86_64
7473 /* d_ot is the size of destination */
7474 d_ot
= dflag
+ OT_WORD
;
7476 modrm
= cpu_ldub_code(env
, s
->pc
++);
7477 reg
= ((modrm
>> 3) & 7) | rex_r
;
7478 mod
= (modrm
>> 6) & 3;
7479 rm
= (modrm
& 7) | REX_B(s
);
7482 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7484 if (d_ot
== OT_QUAD
)
7485 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7486 gen_op_mov_reg_T0(d_ot
, reg
);
7488 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7489 if (d_ot
== OT_QUAD
) {
7490 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7492 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7494 gen_op_mov_reg_T0(d_ot
, reg
);
7500 TCGv t0
, t1
, t2
, a0
;
7502 if (!s
->pe
|| s
->vm86
)
7504 t0
= tcg_temp_local_new();
7505 t1
= tcg_temp_local_new();
7506 t2
= tcg_temp_local_new();
7508 modrm
= cpu_ldub_code(env
, s
->pc
++);
7509 reg
= (modrm
>> 3) & 7;
7510 mod
= (modrm
>> 6) & 3;
7513 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7514 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7515 a0
= tcg_temp_local_new();
7516 tcg_gen_mov_tl(a0
, cpu_A0
);
7518 gen_op_mov_v_reg(ot
, t0
, rm
);
7521 gen_op_mov_v_reg(ot
, t1
, reg
);
7522 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7523 tcg_gen_andi_tl(t1
, t1
, 3);
7524 tcg_gen_movi_tl(t2
, 0);
7525 label1
= gen_new_label();
7526 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7527 tcg_gen_andi_tl(t0
, t0
, ~3);
7528 tcg_gen_or_tl(t0
, t0
, t1
);
7529 tcg_gen_movi_tl(t2
, CC_Z
);
7530 gen_set_label(label1
);
7532 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7535 gen_op_mov_reg_v(ot
, rm
, t0
);
7537 gen_compute_eflags(s
);
7538 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7539 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7545 case 0x102: /* lar */
7546 case 0x103: /* lsl */
7550 if (!s
->pe
|| s
->vm86
)
7552 ot
= dflag
? OT_LONG
: OT_WORD
;
7553 modrm
= cpu_ldub_code(env
, s
->pc
++);
7554 reg
= ((modrm
>> 3) & 7) | rex_r
;
7555 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7556 t0
= tcg_temp_local_new();
7557 gen_update_cc_op(s
);
7559 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7561 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7563 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7564 label1
= gen_new_label();
7565 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7566 gen_op_mov_reg_v(ot
, reg
, t0
);
7567 gen_set_label(label1
);
7568 set_cc_op(s
, CC_OP_EFLAGS
);
7573 modrm
= cpu_ldub_code(env
, s
->pc
++);
7574 mod
= (modrm
>> 6) & 3;
7575 op
= (modrm
>> 3) & 7;
7577 case 0: /* prefetchnta */
7578 case 1: /* prefetchnt0 */
7579 case 2: /* prefetchnt0 */
7580 case 3: /* prefetchnt0 */
7583 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7584 /* nothing more to do */
7586 default: /* nop (multi byte) */
7587 gen_nop_modrm(env
, s
, modrm
);
7591 case 0x119 ... 0x11f: /* nop (multi byte) */
7592 modrm
= cpu_ldub_code(env
, s
->pc
++);
7593 gen_nop_modrm(env
, s
, modrm
);
7595 case 0x120: /* mov reg, crN */
7596 case 0x122: /* mov crN, reg */
7598 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7600 modrm
= cpu_ldub_code(env
, s
->pc
++);
7601 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7602 * AMD documentation (24594.pdf) and testing of
7603 * intel 386 and 486 processors all show that the mod bits
7604 * are assumed to be 1's, regardless of actual values.
7606 rm
= (modrm
& 7) | REX_B(s
);
7607 reg
= ((modrm
>> 3) & 7) | rex_r
;
7612 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7613 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7622 gen_update_cc_op(s
);
7623 gen_jmp_im(pc_start
- s
->cs_base
);
7625 gen_op_mov_TN_reg(ot
, 0, rm
);
7626 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7628 gen_jmp_im(s
->pc
- s
->cs_base
);
7631 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7632 gen_op_mov_reg_T0(ot
, rm
);
7640 case 0x121: /* mov reg, drN */
7641 case 0x123: /* mov drN, reg */
7643 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7645 modrm
= cpu_ldub_code(env
, s
->pc
++);
7646 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7647 * AMD documentation (24594.pdf) and testing of
7648 * intel 386 and 486 processors all show that the mod bits
7649 * are assumed to be 1's, regardless of actual values.
7651 rm
= (modrm
& 7) | REX_B(s
);
7652 reg
= ((modrm
>> 3) & 7) | rex_r
;
7657 /* XXX: do it dynamically with CR4.DE bit */
7658 if (reg
== 4 || reg
== 5 || reg
>= 8)
7661 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7662 gen_op_mov_TN_reg(ot
, 0, rm
);
7663 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7664 gen_jmp_im(s
->pc
- s
->cs_base
);
7667 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7668 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7669 gen_op_mov_reg_T0(ot
, rm
);
7673 case 0x106: /* clts */
7675 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7677 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7678 gen_helper_clts(cpu_env
);
7679 /* abort block because static cpu state changed */
7680 gen_jmp_im(s
->pc
- s
->cs_base
);
7684 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7685 case 0x1c3: /* MOVNTI reg, mem */
7686 if (!(s
->cpuid_features
& CPUID_SSE2
))
7688 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7689 modrm
= cpu_ldub_code(env
, s
->pc
++);
7690 mod
= (modrm
>> 6) & 3;
7693 reg
= ((modrm
>> 3) & 7) | rex_r
;
7694 /* generate a generic store */
7695 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7698 modrm
= cpu_ldub_code(env
, s
->pc
++);
7699 mod
= (modrm
>> 6) & 3;
7700 op
= (modrm
>> 3) & 7;
7702 case 0: /* fxsave */
7703 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7704 (s
->prefix
& PREFIX_LOCK
))
7706 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7707 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7710 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7711 gen_update_cc_op(s
);
7712 gen_jmp_im(pc_start
- s
->cs_base
);
7713 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7715 case 1: /* fxrstor */
7716 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7717 (s
->prefix
& PREFIX_LOCK
))
7719 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7720 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7723 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7724 gen_update_cc_op(s
);
7725 gen_jmp_im(pc_start
- s
->cs_base
);
7726 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7727 tcg_const_i32((s
->dflag
== 2)));
7729 case 2: /* ldmxcsr */
7730 case 3: /* stmxcsr */
7731 if (s
->flags
& HF_TS_MASK
) {
7732 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7735 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7738 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7740 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7741 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7742 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7744 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7745 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7748 case 5: /* lfence */
7749 case 6: /* mfence */
7750 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7753 case 7: /* sfence / clflush */
7754 if ((modrm
& 0xc7) == 0xc0) {
7756 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7757 if (!(s
->cpuid_features
& CPUID_SSE
))
7761 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7763 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7770 case 0x10d: /* 3DNow! prefetch(w) */
7771 modrm
= cpu_ldub_code(env
, s
->pc
++);
7772 mod
= (modrm
>> 6) & 3;
7775 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7776 /* ignore for now */
7778 case 0x1aa: /* rsm */
7779 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7780 if (!(s
->flags
& HF_SMM_MASK
))
7782 gen_update_cc_op(s
);
7783 gen_jmp_im(s
->pc
- s
->cs_base
);
7784 gen_helper_rsm(cpu_env
);
7787 case 0x1b8: /* SSE4.2 popcnt */
7788 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7791 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7794 modrm
= cpu_ldub_code(env
, s
->pc
++);
7795 reg
= ((modrm
>> 3) & 7) | rex_r
;
7797 if (s
->prefix
& PREFIX_DATA
)
7799 else if (s
->dflag
!= 2)
7804 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7805 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7806 gen_op_mov_reg_T0(ot
, reg
);
7808 set_cc_op(s
, CC_OP_EFLAGS
);
7810 case 0x10e ... 0x10f:
7811 /* 3DNow! instructions, ignore prefixes */
7812 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7813 case 0x110 ... 0x117:
7814 case 0x128 ... 0x12f:
7815 case 0x138 ... 0x13a:
7816 case 0x150 ... 0x179:
7817 case 0x17c ... 0x17f:
7819 case 0x1c4 ... 0x1c6:
7820 case 0x1d0 ... 0x1fe:
7821 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7826 /* lock generation */
7827 if (s
->prefix
& PREFIX_LOCK
)
7828 gen_helper_unlock();
7831 if (s
->prefix
& PREFIX_LOCK
)
7832 gen_helper_unlock();
7833 /* XXX: ensure that no lock was generated */
7834 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7838 void optimize_flags_init(void)
7840 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7841 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7842 offsetof(CPUX86State
, cc_op
), "cc_op");
7843 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7845 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7848 #ifdef TARGET_X86_64
7849 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7850 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7851 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7852 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7853 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7854 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7855 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7856 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7857 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7858 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7859 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7860 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7861 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7862 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7863 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7864 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7865 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7866 offsetof(CPUX86State
, regs
[8]), "r8");
7867 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7868 offsetof(CPUX86State
, regs
[9]), "r9");
7869 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7870 offsetof(CPUX86State
, regs
[10]), "r10");
7871 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7872 offsetof(CPUX86State
, regs
[11]), "r11");
7873 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7874 offsetof(CPUX86State
, regs
[12]), "r12");
7875 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7876 offsetof(CPUX86State
, regs
[13]), "r13");
7877 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7878 offsetof(CPUX86State
, regs
[14]), "r14");
7879 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7880 offsetof(CPUX86State
, regs
[15]), "r15");
7882 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7883 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7884 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7885 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7886 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7887 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7888 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7889 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7890 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7891 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7892 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7893 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7894 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7895 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7896 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7897 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7900 /* register helpers */
7901 #define GEN_HELPER 2
7905 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7906 basic block 'tb'. If search_pc is TRUE, also generate PC
7907 information for each intermediate instruction. */
7908 static inline void gen_intermediate_code_internal(CPUX86State
*env
,
7909 TranslationBlock
*tb
,
7912 DisasContext dc1
, *dc
= &dc1
;
7913 target_ulong pc_ptr
;
7914 uint16_t *gen_opc_end
;
7918 target_ulong pc_start
;
7919 target_ulong cs_base
;
7923 /* generate intermediate code */
7925 cs_base
= tb
->cs_base
;
7928 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7929 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7930 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7931 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7933 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7934 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7935 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7936 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7937 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7938 dc
->cc_op
= CC_OP_DYNAMIC
;
7939 dc
->cc_op_dirty
= false;
7940 dc
->cs_base
= cs_base
;
7942 dc
->popl_esp_hack
= 0;
7943 /* select memory access functions */
7945 if (flags
& HF_SOFTMMU_MASK
) {
7946 dc
->mem_index
= (cpu_mmu_index(env
) + 1) << 2;
7948 dc
->cpuid_features
= env
->cpuid_features
;
7949 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7950 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7951 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7952 dc
->cpuid_7_0_ebx_features
= env
->cpuid_7_0_ebx_features
;
7953 #ifdef TARGET_X86_64
7954 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7955 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7958 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7959 (flags
& HF_INHIBIT_IRQ_MASK
)
7960 #ifndef CONFIG_SOFTMMU
7961 || (flags
& HF_SOFTMMU_MASK
)
7965 /* check addseg logic */
7966 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7967 printf("ERROR addseg\n");
7970 cpu_T
[0] = tcg_temp_new();
7971 cpu_T
[1] = tcg_temp_new();
7972 cpu_A0
= tcg_temp_new();
7973 cpu_T3
= tcg_temp_new();
7975 cpu_tmp0
= tcg_temp_new();
7976 cpu_tmp1_i64
= tcg_temp_new_i64();
7977 cpu_tmp2_i32
= tcg_temp_new_i32();
7978 cpu_tmp3_i32
= tcg_temp_new_i32();
7979 cpu_tmp4
= tcg_temp_new();
7980 cpu_tmp5
= tcg_temp_new();
7981 cpu_ptr0
= tcg_temp_new_ptr();
7982 cpu_ptr1
= tcg_temp_new_ptr();
7984 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7986 dc
->is_jmp
= DISAS_NEXT
;
7990 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7992 max_insns
= CF_COUNT_MASK
;
7996 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7997 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7998 if (bp
->pc
== pc_ptr
&&
7999 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8000 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8006 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8010 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8012 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8013 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8014 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8015 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8017 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8020 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8022 /* stop translation if indicated */
8025 /* if single step mode, we generate only one instruction and
8026 generate an exception */
8027 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8028 the flag and abort the translation to give the irqs a
8029 change to be happen */
8030 if (dc
->tf
|| dc
->singlestep_enabled
||
8031 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8032 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8036 /* if too long translation, stop generation too */
8037 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8038 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8039 num_insns
>= max_insns
) {
8040 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8045 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8050 if (tb
->cflags
& CF_LAST_IO
)
8052 gen_icount_end(tb
, num_insns
);
8053 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8054 /* we don't forget to fill the last values */
8056 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8059 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8063 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8065 qemu_log("----------------\n");
8066 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8067 #ifdef TARGET_X86_64
8072 disas_flags
= !dc
->code32
;
8073 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8079 tb
->size
= pc_ptr
- pc_start
;
8080 tb
->icount
= num_insns
;
8084 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8086 gen_intermediate_code_internal(env
, tb
, 0);
8089 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8091 gen_intermediate_code_internal(env
, tb
, 1);
8094 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8098 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8100 qemu_log("RESTORE:\n");
8101 for(i
= 0;i
<= pc_pos
; i
++) {
8102 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8103 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8104 tcg_ctx
.gen_opc_pc
[i
]);
8107 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8108 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8109 (uint32_t)tb
->cs_base
);
8112 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8113 cc_op
= gen_opc_cc_op
[pc_pos
];
8114 if (cc_op
!= CC_OP_DYNAMIC
)