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1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "disas/disas.h"
28 #include "tcg-op.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define CODE64(s) ((s)->code64)
42 #define REX_X(s) ((s)->rex_x)
43 #define REX_B(s) ((s)->rex_b)
44 #else
45 #define CODE64(s) 0
46 #define REX_X(s) 0
47 #define REX_B(s) 0
48 #endif
49
50 //#define MACRO_TEST 1
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst;
55 static TCGv_i32 cpu_cc_op;
56 static TCGv cpu_regs[CPU_NB_REGS];
57 /* local temps */
58 static TCGv cpu_T[2], cpu_T3;
59 /* local register indexes (only used inside old micro ops) */
60 static TCGv cpu_tmp0, cpu_tmp4;
61 static TCGv_ptr cpu_ptr0, cpu_ptr1;
62 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
63 static TCGv_i64 cpu_tmp1_i64;
64 static TCGv cpu_tmp5;
65
66 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
67
68 #include "exec/gen-icount.h"
69
70 #ifdef TARGET_X86_64
71 static int x86_64_hregs;
72 #endif
73
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
77 int prefix;
78 int aflag, dflag;
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
86 #ifdef TARGET_X86_64
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
89 int rex_x, rex_b;
90 #endif
91 int ss32; /* 32 bit stack segment */
92 CCOp cc_op; /* current CC operation */
93 bool cc_op_dirty;
94 int addseg; /* non zero if either DS/ES/SS have a non zero base */
95 int f_st; /* currently unused */
96 int vm86; /* vm86 mode */
97 int cpl;
98 int iopl;
99 int tf; /* TF cpu flag */
100 int singlestep_enabled; /* "hardware" single step enabled */
101 int jmp_opt; /* use direct block chaining for direct jumps */
102 int mem_index; /* select memory access functions */
103 uint64_t flags; /* all execution flags */
104 struct TranslationBlock *tb;
105 int popl_esp_hack; /* for correct popl with esp base handling */
106 int rip_offset; /* only used in x86_64, but left for simplicity */
107 int cpuid_features;
108 int cpuid_ext_features;
109 int cpuid_ext2_features;
110 int cpuid_ext3_features;
111 int cpuid_7_0_ebx_features;
112 } DisasContext;
113
114 static void gen_eob(DisasContext *s);
115 static void gen_jmp(DisasContext *s, target_ulong eip);
116 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
117
118 /* i386 arith/logic operations */
119 enum {
120 OP_ADDL,
121 OP_ORL,
122 OP_ADCL,
123 OP_SBBL,
124 OP_ANDL,
125 OP_SUBL,
126 OP_XORL,
127 OP_CMPL,
128 };
129
130 /* i386 shift ops */
131 enum {
132 OP_ROL,
133 OP_ROR,
134 OP_RCL,
135 OP_RCR,
136 OP_SHL,
137 OP_SHR,
138 OP_SHL1, /* undocumented */
139 OP_SAR = 7,
140 };
141
142 enum {
143 JCC_O,
144 JCC_B,
145 JCC_Z,
146 JCC_BE,
147 JCC_S,
148 JCC_P,
149 JCC_L,
150 JCC_LE,
151 };
152
153 /* operand size */
154 enum {
155 OT_BYTE = 0,
156 OT_WORD,
157 OT_LONG,
158 OT_QUAD,
159 };
160
161 enum {
162 /* I386 int registers */
163 OR_EAX, /* MUST be even numbered */
164 OR_ECX,
165 OR_EDX,
166 OR_EBX,
167 OR_ESP,
168 OR_EBP,
169 OR_ESI,
170 OR_EDI,
171
172 OR_TMP0 = 16, /* temporary operand register */
173 OR_TMP1,
174 OR_A0, /* temporary register used when doing address evaluation */
175 };
176
177 enum {
178 USES_CC_DST = 1,
179 USES_CC_SRC = 2,
180 };
181
182 /* Bit set if the global variable is live after setting CC_OP to X. */
183 static const uint8_t cc_op_live[CC_OP_NB] = {
184 [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC,
185 [CC_OP_EFLAGS] = USES_CC_SRC,
186 [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC,
187 [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC,
188 [CC_OP_ADCB ... CC_OP_ADCQ] = USES_CC_DST | USES_CC_SRC,
189 [CC_OP_SUBB ... CC_OP_SUBQ] = USES_CC_DST | USES_CC_SRC,
190 [CC_OP_SBBB ... CC_OP_SBBQ] = USES_CC_DST | USES_CC_SRC,
191 [CC_OP_LOGICB ... CC_OP_LOGICQ] = USES_CC_DST,
192 [CC_OP_INCB ... CC_OP_INCQ] = USES_CC_DST | USES_CC_SRC,
193 [CC_OP_DECB ... CC_OP_DECQ] = USES_CC_DST | USES_CC_SRC,
194 [CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
195 [CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
196 };
197
198 static void set_cc_op(DisasContext *s, CCOp op)
199 {
200 int dead;
201
202 if (s->cc_op == op) {
203 return;
204 }
205
206 /* Discard CC computation that will no longer be used. */
207 dead = cc_op_live[s->cc_op] & ~cc_op_live[op];
208 if (dead & USES_CC_DST) {
209 tcg_gen_discard_tl(cpu_cc_dst);
210 }
211 if (dead & USES_CC_SRC) {
212 tcg_gen_discard_tl(cpu_cc_src);
213 }
214
215 s->cc_op = op;
216 /* The DYNAMIC setting is translator only, and should never be
217 stored. Thus we always consider it clean. */
218 s->cc_op_dirty = (op != CC_OP_DYNAMIC);
219 }
220
221 static void gen_update_cc_op(DisasContext *s)
222 {
223 if (s->cc_op_dirty) {
224 tcg_gen_movi_i32(cpu_cc_op, s->cc_op);
225 s->cc_op_dirty = false;
226 }
227 }
228
229 static inline void gen_op_movl_T0_0(void)
230 {
231 tcg_gen_movi_tl(cpu_T[0], 0);
232 }
233
234 static inline void gen_op_movl_T0_im(int32_t val)
235 {
236 tcg_gen_movi_tl(cpu_T[0], val);
237 }
238
239 static inline void gen_op_movl_T0_imu(uint32_t val)
240 {
241 tcg_gen_movi_tl(cpu_T[0], val);
242 }
243
244 static inline void gen_op_movl_T1_im(int32_t val)
245 {
246 tcg_gen_movi_tl(cpu_T[1], val);
247 }
248
249 static inline void gen_op_movl_T1_imu(uint32_t val)
250 {
251 tcg_gen_movi_tl(cpu_T[1], val);
252 }
253
254 static inline void gen_op_movl_A0_im(uint32_t val)
255 {
256 tcg_gen_movi_tl(cpu_A0, val);
257 }
258
259 #ifdef TARGET_X86_64
260 static inline void gen_op_movq_A0_im(int64_t val)
261 {
262 tcg_gen_movi_tl(cpu_A0, val);
263 }
264 #endif
265
266 static inline void gen_movtl_T0_im(target_ulong val)
267 {
268 tcg_gen_movi_tl(cpu_T[0], val);
269 }
270
271 static inline void gen_movtl_T1_im(target_ulong val)
272 {
273 tcg_gen_movi_tl(cpu_T[1], val);
274 }
275
276 static inline void gen_op_andl_T0_ffff(void)
277 {
278 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
279 }
280
281 static inline void gen_op_andl_T0_im(uint32_t val)
282 {
283 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
284 }
285
286 static inline void gen_op_movl_T0_T1(void)
287 {
288 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
289 }
290
291 static inline void gen_op_andl_A0_ffff(void)
292 {
293 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
294 }
295
296 #ifdef TARGET_X86_64
297
298 #define NB_OP_SIZES 4
299
300 #else /* !TARGET_X86_64 */
301
302 #define NB_OP_SIZES 3
303
304 #endif /* !TARGET_X86_64 */
305
306 #if defined(HOST_WORDS_BIGENDIAN)
307 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
308 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
309 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
310 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
311 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
312 #else
313 #define REG_B_OFFSET 0
314 #define REG_H_OFFSET 1
315 #define REG_W_OFFSET 0
316 #define REG_L_OFFSET 0
317 #define REG_LH_OFFSET 4
318 #endif
319
320 /* In instruction encodings for byte register accesses the
321 * register number usually indicates "low 8 bits of register N";
322 * however there are some special cases where N 4..7 indicates
323 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
324 * true for this special case, false otherwise.
325 */
326 static inline bool byte_reg_is_xH(int reg)
327 {
328 if (reg < 4) {
329 return false;
330 }
331 #ifdef TARGET_X86_64
332 if (reg >= 8 || x86_64_hregs) {
333 return false;
334 }
335 #endif
336 return true;
337 }
338
339 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
340 {
341 switch(ot) {
342 case OT_BYTE:
343 if (!byte_reg_is_xH(reg)) {
344 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
345 } else {
346 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
347 }
348 break;
349 case OT_WORD:
350 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
351 break;
352 default: /* XXX this shouldn't be reached; abort? */
353 case OT_LONG:
354 /* For x86_64, this sets the higher half of register to zero.
355 For i386, this is equivalent to a mov. */
356 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
357 break;
358 #ifdef TARGET_X86_64
359 case OT_QUAD:
360 tcg_gen_mov_tl(cpu_regs[reg], t0);
361 break;
362 #endif
363 }
364 }
365
366 static inline void gen_op_mov_reg_T0(int ot, int reg)
367 {
368 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
369 }
370
371 static inline void gen_op_mov_reg_T1(int ot, int reg)
372 {
373 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
374 }
375
376 static inline void gen_op_mov_reg_A0(int size, int reg)
377 {
378 switch(size) {
379 case OT_BYTE:
380 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
381 break;
382 default: /* XXX this shouldn't be reached; abort? */
383 case OT_WORD:
384 /* For x86_64, this sets the higher half of register to zero.
385 For i386, this is equivalent to a mov. */
386 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
387 break;
388 #ifdef TARGET_X86_64
389 case OT_LONG:
390 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
391 break;
392 #endif
393 }
394 }
395
396 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
397 {
398 if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
399 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
400 tcg_gen_ext8u_tl(t0, t0);
401 } else {
402 tcg_gen_mov_tl(t0, cpu_regs[reg]);
403 }
404 }
405
406 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
407 {
408 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
409 }
410
411 static inline void gen_op_movl_A0_reg(int reg)
412 {
413 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
414 }
415
416 static inline void gen_op_addl_A0_im(int32_t val)
417 {
418 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
419 #ifdef TARGET_X86_64
420 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
421 #endif
422 }
423
424 #ifdef TARGET_X86_64
425 static inline void gen_op_addq_A0_im(int64_t val)
426 {
427 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
428 }
429 #endif
430
431 static void gen_add_A0_im(DisasContext *s, int val)
432 {
433 #ifdef TARGET_X86_64
434 if (CODE64(s))
435 gen_op_addq_A0_im(val);
436 else
437 #endif
438 gen_op_addl_A0_im(val);
439 }
440
441 static inline void gen_op_addl_T0_T1(void)
442 {
443 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
444 }
445
446 static inline void gen_op_jmp_T0(void)
447 {
448 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
449 }
450
451 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
452 {
453 switch(size) {
454 case OT_BYTE:
455 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
456 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
457 break;
458 case OT_WORD:
459 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
460 /* For x86_64, this sets the higher half of register to zero.
461 For i386, this is equivalent to a nop. */
462 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
463 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
464 break;
465 #ifdef TARGET_X86_64
466 case OT_LONG:
467 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
468 break;
469 #endif
470 }
471 }
472
473 static inline void gen_op_add_reg_T0(int size, int reg)
474 {
475 switch(size) {
476 case OT_BYTE:
477 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
478 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
479 break;
480 case OT_WORD:
481 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
482 /* For x86_64, this sets the higher half of register to zero.
483 For i386, this is equivalent to a nop. */
484 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
485 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
486 break;
487 #ifdef TARGET_X86_64
488 case OT_LONG:
489 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
490 break;
491 #endif
492 }
493 }
494
495 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
496 {
497 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
498 if (shift != 0)
499 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
500 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
501 /* For x86_64, this sets the higher half of register to zero.
502 For i386, this is equivalent to a nop. */
503 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
504 }
505
506 static inline void gen_op_movl_A0_seg(int reg)
507 {
508 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
509 }
510
511 static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
512 {
513 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
514 #ifdef TARGET_X86_64
515 if (CODE64(s)) {
516 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
517 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
518 } else {
519 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
520 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
521 }
522 #else
523 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
524 #endif
525 }
526
527 #ifdef TARGET_X86_64
528 static inline void gen_op_movq_A0_seg(int reg)
529 {
530 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
531 }
532
533 static inline void gen_op_addq_A0_seg(int reg)
534 {
535 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
536 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
537 }
538
539 static inline void gen_op_movq_A0_reg(int reg)
540 {
541 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
542 }
543
544 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
545 {
546 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
547 if (shift != 0)
548 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
549 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
550 }
551 #endif
552
553 static inline void gen_op_lds_T0_A0(int idx)
554 {
555 int mem_index = (idx >> 2) - 1;
556 switch(idx & 3) {
557 case OT_BYTE:
558 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
559 break;
560 case OT_WORD:
561 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
562 break;
563 default:
564 case OT_LONG:
565 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
566 break;
567 }
568 }
569
570 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
571 {
572 int mem_index = (idx >> 2) - 1;
573 switch(idx & 3) {
574 case OT_BYTE:
575 tcg_gen_qemu_ld8u(t0, a0, mem_index);
576 break;
577 case OT_WORD:
578 tcg_gen_qemu_ld16u(t0, a0, mem_index);
579 break;
580 case OT_LONG:
581 tcg_gen_qemu_ld32u(t0, a0, mem_index);
582 break;
583 default:
584 case OT_QUAD:
585 /* Should never happen on 32-bit targets. */
586 #ifdef TARGET_X86_64
587 tcg_gen_qemu_ld64(t0, a0, mem_index);
588 #endif
589 break;
590 }
591 }
592
593 /* XXX: always use ldu or lds */
594 static inline void gen_op_ld_T0_A0(int idx)
595 {
596 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
597 }
598
599 static inline void gen_op_ldu_T0_A0(int idx)
600 {
601 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
602 }
603
604 static inline void gen_op_ld_T1_A0(int idx)
605 {
606 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
607 }
608
609 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
610 {
611 int mem_index = (idx >> 2) - 1;
612 switch(idx & 3) {
613 case OT_BYTE:
614 tcg_gen_qemu_st8(t0, a0, mem_index);
615 break;
616 case OT_WORD:
617 tcg_gen_qemu_st16(t0, a0, mem_index);
618 break;
619 case OT_LONG:
620 tcg_gen_qemu_st32(t0, a0, mem_index);
621 break;
622 default:
623 case OT_QUAD:
624 /* Should never happen on 32-bit targets. */
625 #ifdef TARGET_X86_64
626 tcg_gen_qemu_st64(t0, a0, mem_index);
627 #endif
628 break;
629 }
630 }
631
632 static inline void gen_op_st_T0_A0(int idx)
633 {
634 gen_op_st_v(idx, cpu_T[0], cpu_A0);
635 }
636
637 static inline void gen_op_st_T1_A0(int idx)
638 {
639 gen_op_st_v(idx, cpu_T[1], cpu_A0);
640 }
641
642 static inline void gen_jmp_im(target_ulong pc)
643 {
644 tcg_gen_movi_tl(cpu_tmp0, pc);
645 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
646 }
647
648 static inline void gen_string_movl_A0_ESI(DisasContext *s)
649 {
650 int override;
651
652 override = s->override;
653 #ifdef TARGET_X86_64
654 if (s->aflag == 2) {
655 if (override >= 0) {
656 gen_op_movq_A0_seg(override);
657 gen_op_addq_A0_reg_sN(0, R_ESI);
658 } else {
659 gen_op_movq_A0_reg(R_ESI);
660 }
661 } else
662 #endif
663 if (s->aflag) {
664 /* 32 bit address */
665 if (s->addseg && override < 0)
666 override = R_DS;
667 if (override >= 0) {
668 gen_op_movl_A0_seg(override);
669 gen_op_addl_A0_reg_sN(0, R_ESI);
670 } else {
671 gen_op_movl_A0_reg(R_ESI);
672 }
673 } else {
674 /* 16 address, always override */
675 if (override < 0)
676 override = R_DS;
677 gen_op_movl_A0_reg(R_ESI);
678 gen_op_andl_A0_ffff();
679 gen_op_addl_A0_seg(s, override);
680 }
681 }
682
683 static inline void gen_string_movl_A0_EDI(DisasContext *s)
684 {
685 #ifdef TARGET_X86_64
686 if (s->aflag == 2) {
687 gen_op_movq_A0_reg(R_EDI);
688 } else
689 #endif
690 if (s->aflag) {
691 if (s->addseg) {
692 gen_op_movl_A0_seg(R_ES);
693 gen_op_addl_A0_reg_sN(0, R_EDI);
694 } else {
695 gen_op_movl_A0_reg(R_EDI);
696 }
697 } else {
698 gen_op_movl_A0_reg(R_EDI);
699 gen_op_andl_A0_ffff();
700 gen_op_addl_A0_seg(s, R_ES);
701 }
702 }
703
704 static inline void gen_op_movl_T0_Dshift(int ot)
705 {
706 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
707 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
708 };
709
710 static TCGv gen_ext_tl(TCGv dst, TCGv src, int size, bool sign)
711 {
712 switch (size) {
713 case OT_BYTE:
714 if (sign) {
715 tcg_gen_ext8s_tl(dst, src);
716 } else {
717 tcg_gen_ext8u_tl(dst, src);
718 }
719 return dst;
720 case OT_WORD:
721 if (sign) {
722 tcg_gen_ext16s_tl(dst, src);
723 } else {
724 tcg_gen_ext16u_tl(dst, src);
725 }
726 return dst;
727 #ifdef TARGET_X86_64
728 case OT_LONG:
729 if (sign) {
730 tcg_gen_ext32s_tl(dst, src);
731 } else {
732 tcg_gen_ext32u_tl(dst, src);
733 }
734 return dst;
735 #endif
736 default:
737 return src;
738 }
739 }
740
741 static void gen_extu(int ot, TCGv reg)
742 {
743 gen_ext_tl(reg, reg, ot, false);
744 }
745
746 static void gen_exts(int ot, TCGv reg)
747 {
748 gen_ext_tl(reg, reg, ot, true);
749 }
750
751 static inline void gen_op_jnz_ecx(int size, int label1)
752 {
753 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
754 gen_extu(size + 1, cpu_tmp0);
755 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
756 }
757
758 static inline void gen_op_jz_ecx(int size, int label1)
759 {
760 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
761 gen_extu(size + 1, cpu_tmp0);
762 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
763 }
764
765 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
766 {
767 switch (ot) {
768 case OT_BYTE:
769 gen_helper_inb(v, n);
770 break;
771 case OT_WORD:
772 gen_helper_inw(v, n);
773 break;
774 case OT_LONG:
775 gen_helper_inl(v, n);
776 break;
777 }
778 }
779
780 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
781 {
782 switch (ot) {
783 case OT_BYTE:
784 gen_helper_outb(v, n);
785 break;
786 case OT_WORD:
787 gen_helper_outw(v, n);
788 break;
789 case OT_LONG:
790 gen_helper_outl(v, n);
791 break;
792 }
793 }
794
795 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
796 uint32_t svm_flags)
797 {
798 int state_saved;
799 target_ulong next_eip;
800
801 state_saved = 0;
802 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
803 gen_update_cc_op(s);
804 gen_jmp_im(cur_eip);
805 state_saved = 1;
806 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
807 switch (ot) {
808 case OT_BYTE:
809 gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
810 break;
811 case OT_WORD:
812 gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
813 break;
814 case OT_LONG:
815 gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
816 break;
817 }
818 }
819 if(s->flags & HF_SVMI_MASK) {
820 if (!state_saved) {
821 gen_update_cc_op(s);
822 gen_jmp_im(cur_eip);
823 }
824 svm_flags |= (1 << (4 + ot));
825 next_eip = s->pc - s->cs_base;
826 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
827 gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32,
828 tcg_const_i32(svm_flags),
829 tcg_const_i32(next_eip - cur_eip));
830 }
831 }
832
833 static inline void gen_movs(DisasContext *s, int ot)
834 {
835 gen_string_movl_A0_ESI(s);
836 gen_op_ld_T0_A0(ot + s->mem_index);
837 gen_string_movl_A0_EDI(s);
838 gen_op_st_T0_A0(ot + s->mem_index);
839 gen_op_movl_T0_Dshift(ot);
840 gen_op_add_reg_T0(s->aflag, R_ESI);
841 gen_op_add_reg_T0(s->aflag, R_EDI);
842 }
843
844 static void gen_op_update1_cc(void)
845 {
846 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
847 }
848
849 static void gen_op_update2_cc(void)
850 {
851 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
852 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
853 }
854
855 static inline void gen_op_cmpl_T0_T1_cc(void)
856 {
857 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
858 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
859 }
860
861 static inline void gen_op_testl_T0_T1_cc(void)
862 {
863 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
864 }
865
866 static void gen_op_update_neg_cc(void)
867 {
868 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
869 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
870 }
871
872 /* compute all eflags to cc_src */
873 static void gen_compute_eflags(DisasContext *s)
874 {
875 if (s->cc_op == CC_OP_EFLAGS) {
876 return;
877 }
878 gen_update_cc_op(s);
879 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op);
880 set_cc_op(s, CC_OP_EFLAGS);
881 tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
882 }
883
884 /* compute eflags.C to reg */
885 static void gen_compute_eflags_c(DisasContext *s, TCGv reg, bool inv)
886 {
887 TCGv t0, t1;
888 int size;
889
890 switch (s->cc_op) {
891 case CC_OP_SUBB ... CC_OP_SUBQ:
892 /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
893 size = s->cc_op - CC_OP_SUBB;
894 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
895 /* If no temporary was used, be careful not to alias t1 and t0. */
896 t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
897 tcg_gen_add_tl(t0, cpu_cc_dst, cpu_cc_src);
898 gen_extu(size, t0);
899 goto add_sub;
900
901 case CC_OP_ADDB ... CC_OP_ADDQ:
902 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
903 size = s->cc_op - CC_OP_ADDB;
904 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
905 t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
906 add_sub:
907 tcg_gen_setcond_tl(inv ? TCG_COND_GEU : TCG_COND_LTU, reg, t0, t1);
908 inv = false;
909 break;
910
911 case CC_OP_SBBB ... CC_OP_SBBQ:
912 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
913 size = s->cc_op - CC_OP_SBBB;
914 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
915 if (TCGV_EQUAL(t1, reg) && TCGV_EQUAL(reg, cpu_cc_src)) {
916 tcg_gen_mov_tl(cpu_tmp0, cpu_cc_src);
917 t1 = cpu_tmp0;
918 }
919
920 tcg_gen_add_tl(reg, cpu_cc_dst, cpu_cc_src);
921 tcg_gen_addi_tl(reg, reg, 1);
922 gen_extu(size, reg);
923 t0 = reg;
924 goto adc_sbb;
925
926 case CC_OP_ADCB ... CC_OP_ADCQ:
927 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
928 size = s->cc_op - CC_OP_ADCB;
929 t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
930 t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
931 adc_sbb:
932 tcg_gen_setcond_tl(inv ? TCG_COND_GTU : TCG_COND_LEU, reg, t0, t1);
933 inv = false;
934 break;
935
936 case CC_OP_LOGICB ... CC_OP_LOGICQ:
937 tcg_gen_movi_tl(reg, 0);
938 break;
939
940 case CC_OP_INCB ... CC_OP_INCQ:
941 case CC_OP_DECB ... CC_OP_DECQ:
942 if (inv) {
943 tcg_gen_xori_tl(reg, cpu_cc_src, 1);
944 } else {
945 tcg_gen_mov_tl(reg, cpu_cc_src);
946 }
947 inv = false;
948 break;
949
950 case CC_OP_SHLB ... CC_OP_SHLQ:
951 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
952 size = s->cc_op - CC_OP_SHLB;
953 tcg_gen_shri_tl(reg, cpu_cc_src, (8 << size) - 1);
954 tcg_gen_andi_tl(reg, reg, 1);
955 break;
956
957 case CC_OP_MULB ... CC_OP_MULQ:
958 tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
959 reg, cpu_cc_src, 0);
960 inv = false;
961 break;
962
963 case CC_OP_EFLAGS:
964 case CC_OP_SARB ... CC_OP_SARQ:
965 /* CC_SRC & 1 */
966 tcg_gen_andi_tl(reg, cpu_cc_src, 1);
967 break;
968
969 default:
970 /* The need to compute only C from CC_OP_DYNAMIC is important
971 in efficiently implementing e.g. INC at the start of a TB. */
972 gen_update_cc_op(s);
973 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
974 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
975 break;
976 }
977 if (inv) {
978 tcg_gen_xori_tl(reg, reg, 1);
979 }
980 }
981
982 /* compute eflags.P to reg */
983 static void gen_compute_eflags_p(DisasContext *s, TCGv reg)
984 {
985 gen_compute_eflags(s);
986 tcg_gen_shri_tl(reg, cpu_cc_src, 2);
987 tcg_gen_andi_tl(reg, reg, 1);
988 }
989
990 /* compute eflags.S to reg */
991 static void gen_compute_eflags_s(DisasContext *s, TCGv reg, bool inv)
992 {
993 switch (s->cc_op) {
994 case CC_OP_DYNAMIC:
995 gen_compute_eflags(s);
996 /* FALLTHRU */
997 case CC_OP_EFLAGS:
998 tcg_gen_shri_tl(reg, cpu_cc_src, 7);
999 tcg_gen_andi_tl(reg, reg, 1);
1000 if (inv) {
1001 tcg_gen_xori_tl(reg, reg, 1);
1002 }
1003 break;
1004 default:
1005 {
1006 int size = (s->cc_op - CC_OP_ADDB) & 3;
1007 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, true);
1008 tcg_gen_setcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, reg, t0, 0);
1009 }
1010 break;
1011 }
1012 }
1013
1014 /* compute eflags.O to reg */
1015 static void gen_compute_eflags_o(DisasContext *s, TCGv reg)
1016 {
1017 gen_compute_eflags(s);
1018 tcg_gen_shri_tl(reg, cpu_cc_src, 11);
1019 tcg_gen_andi_tl(reg, reg, 1);
1020 }
1021
1022 /* compute eflags.Z to reg */
1023 static void gen_compute_eflags_z(DisasContext *s, TCGv reg, bool inv)
1024 {
1025 switch (s->cc_op) {
1026 case CC_OP_DYNAMIC:
1027 gen_compute_eflags(s);
1028 /* FALLTHRU */
1029 case CC_OP_EFLAGS:
1030 tcg_gen_shri_tl(reg, cpu_cc_src, 6);
1031 tcg_gen_andi_tl(reg, reg, 1);
1032 if (inv) {
1033 tcg_gen_xori_tl(reg, reg, 1);
1034 }
1035 break;
1036 default:
1037 {
1038 int size = (s->cc_op - CC_OP_ADDB) & 3;
1039 TCGv t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
1040 tcg_gen_setcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, reg, t0, 0);
1041 }
1042 break;
1043 }
1044 }
1045
1046 static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv)
1047 {
1048 assert(!TCGV_EQUAL(reg, cpu_cc_src));
1049 switch(jcc_op) {
1050 case JCC_O:
1051 gen_compute_eflags_o(s, reg);
1052 break;
1053 case JCC_B:
1054 gen_compute_eflags_c(s, reg, inv);
1055 inv = false;
1056 break;
1057 case JCC_Z:
1058 gen_compute_eflags_z(s, reg, inv);
1059 inv = false;
1060 break;
1061 case JCC_BE:
1062 gen_compute_eflags(s);
1063 tcg_gen_andi_tl(reg, cpu_cc_src, CC_Z | CC_C);
1064 tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, reg, reg, 0);
1065 return;
1066 case JCC_S:
1067 gen_compute_eflags_s(s, reg, inv);
1068 inv = false;
1069 break;
1070 case JCC_P:
1071 gen_compute_eflags_p(s, reg);
1072 break;
1073 case JCC_L:
1074 gen_compute_eflags(s);
1075 tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */
1076 tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 7); /* CC_S */
1077 tcg_gen_xor_tl(reg, reg, cpu_tmp0);
1078 tcg_gen_andi_tl(reg, reg, 1);
1079 break;
1080 default:
1081 case JCC_LE:
1082 gen_compute_eflags(s);
1083 tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */
1084 tcg_gen_shri_tl(cpu_tmp4, cpu_cc_src, 7); /* CC_S */
1085 tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 6); /* CC_Z */
1086 tcg_gen_xor_tl(reg, reg, cpu_tmp4);
1087 tcg_gen_or_tl(reg, reg, cpu_tmp0);
1088 tcg_gen_andi_tl(reg, reg, 1);
1089 break;
1090 }
1091 if (inv) {
1092 tcg_gen_xori_tl(reg, reg, 1);
1093 }
1094 }
1095
1096 /* return true if setcc_slow is not needed (WARNING: must be kept in
1097 sync with gen_jcc1) */
1098 static int is_fast_jcc_case(DisasContext *s, int b)
1099 {
1100 int jcc_op;
1101 jcc_op = (b >> 1) & 7;
1102 switch(s->cc_op) {
1103 /* we optimize the cmp/jcc case */
1104 case CC_OP_SUBB:
1105 case CC_OP_SUBW:
1106 case CC_OP_SUBL:
1107 case CC_OP_SUBQ:
1108 if (jcc_op == JCC_O || jcc_op == JCC_P)
1109 goto slow_jcc;
1110 break;
1111
1112 /* some jumps are easy to compute */
1113 case CC_OP_ADDB:
1114 case CC_OP_ADDW:
1115 case CC_OP_ADDL:
1116 case CC_OP_ADDQ:
1117
1118 case CC_OP_LOGICB:
1119 case CC_OP_LOGICW:
1120 case CC_OP_LOGICL:
1121 case CC_OP_LOGICQ:
1122
1123 case CC_OP_INCB:
1124 case CC_OP_INCW:
1125 case CC_OP_INCL:
1126 case CC_OP_INCQ:
1127
1128 case CC_OP_DECB:
1129 case CC_OP_DECW:
1130 case CC_OP_DECL:
1131 case CC_OP_DECQ:
1132
1133 case CC_OP_SHLB:
1134 case CC_OP_SHLW:
1135 case CC_OP_SHLL:
1136 case CC_OP_SHLQ:
1137 if (jcc_op != JCC_Z && jcc_op != JCC_S)
1138 goto slow_jcc;
1139 break;
1140 default:
1141 slow_jcc:
1142 return 0;
1143 }
1144 return 1;
1145 }
1146
1147 /* generate a conditional jump to label 'l1' according to jump opcode
1148 value 'b'. In the fast case, T0 is guaranted not to be used. */
1149 static inline void gen_jcc1(DisasContext *s, int b, int l1)
1150 {
1151 int inv, jcc_op, size, cond;
1152 TCGv t0;
1153
1154 inv = b & 1;
1155 jcc_op = (b >> 1) & 7;
1156
1157 switch (s->cc_op) {
1158 /* we optimize the cmp/jcc case */
1159 case CC_OP_SUBB:
1160 case CC_OP_SUBW:
1161 case CC_OP_SUBL:
1162 case CC_OP_SUBQ:
1163
1164 size = s->cc_op - CC_OP_SUBB;
1165 switch(jcc_op) {
1166 case JCC_Z:
1167 fast_jcc_z:
1168 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, false);
1169 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
1170 break;
1171 case JCC_S:
1172 fast_jcc_s:
1173 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_dst, size, true);
1174 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, t0, 0, l1);
1175 break;
1176
1177 case JCC_B:
1178 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1179 goto fast_jcc_b;
1180 case JCC_BE:
1181 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1182 fast_jcc_b:
1183 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1184 gen_extu(size, cpu_tmp4);
1185 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
1186 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1187 break;
1188
1189 case JCC_L:
1190 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1191 goto fast_jcc_l;
1192 case JCC_LE:
1193 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1194 fast_jcc_l:
1195 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1196 gen_exts(size, cpu_tmp4);
1197 t0 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, true);
1198 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1199 break;
1200
1201 default:
1202 goto slow_jcc;
1203 }
1204 break;
1205
1206 /* some jumps are easy to compute */
1207 case CC_OP_ADDB:
1208 case CC_OP_ADDW:
1209 case CC_OP_ADDL:
1210 case CC_OP_ADDQ:
1211
1212 case CC_OP_ADCB:
1213 case CC_OP_ADCW:
1214 case CC_OP_ADCL:
1215 case CC_OP_ADCQ:
1216
1217 case CC_OP_SBBB:
1218 case CC_OP_SBBW:
1219 case CC_OP_SBBL:
1220 case CC_OP_SBBQ:
1221
1222 case CC_OP_LOGICB:
1223 case CC_OP_LOGICW:
1224 case CC_OP_LOGICL:
1225 case CC_OP_LOGICQ:
1226
1227 case CC_OP_INCB:
1228 case CC_OP_INCW:
1229 case CC_OP_INCL:
1230 case CC_OP_INCQ:
1231
1232 case CC_OP_DECB:
1233 case CC_OP_DECW:
1234 case CC_OP_DECL:
1235 case CC_OP_DECQ:
1236
1237 case CC_OP_SHLB:
1238 case CC_OP_SHLW:
1239 case CC_OP_SHLL:
1240 case CC_OP_SHLQ:
1241
1242 case CC_OP_SARB:
1243 case CC_OP_SARW:
1244 case CC_OP_SARL:
1245 case CC_OP_SARQ:
1246 switch(jcc_op) {
1247 case JCC_Z:
1248 size = (s->cc_op - CC_OP_ADDB) & 3;
1249 goto fast_jcc_z;
1250 case JCC_S:
1251 size = (s->cc_op - CC_OP_ADDB) & 3;
1252 goto fast_jcc_s;
1253 default:
1254 goto slow_jcc;
1255 }
1256 break;
1257 default:
1258 slow_jcc:
1259 gen_setcc_slow(s, jcc_op, cpu_T[0], false);
1260 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1261 cpu_T[0], 0, l1);
1262 break;
1263 }
1264 }
1265
1266 /* XXX: does not work with gdbstub "ice" single step - not a
1267 serious problem */
1268 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1269 {
1270 int l1, l2;
1271
1272 l1 = gen_new_label();
1273 l2 = gen_new_label();
1274 gen_op_jnz_ecx(s->aflag, l1);
1275 gen_set_label(l2);
1276 gen_jmp_tb(s, next_eip, 1);
1277 gen_set_label(l1);
1278 return l2;
1279 }
1280
1281 static inline void gen_stos(DisasContext *s, int ot)
1282 {
1283 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1284 gen_string_movl_A0_EDI(s);
1285 gen_op_st_T0_A0(ot + s->mem_index);
1286 gen_op_movl_T0_Dshift(ot);
1287 gen_op_add_reg_T0(s->aflag, R_EDI);
1288 }
1289
1290 static inline void gen_lods(DisasContext *s, int ot)
1291 {
1292 gen_string_movl_A0_ESI(s);
1293 gen_op_ld_T0_A0(ot + s->mem_index);
1294 gen_op_mov_reg_T0(ot, R_EAX);
1295 gen_op_movl_T0_Dshift(ot);
1296 gen_op_add_reg_T0(s->aflag, R_ESI);
1297 }
1298
1299 static inline void gen_scas(DisasContext *s, int ot)
1300 {
1301 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1302 gen_string_movl_A0_EDI(s);
1303 gen_op_ld_T1_A0(ot + s->mem_index);
1304 gen_op_cmpl_T0_T1_cc();
1305 gen_op_movl_T0_Dshift(ot);
1306 gen_op_add_reg_T0(s->aflag, R_EDI);
1307 set_cc_op(s, CC_OP_SUBB + ot);
1308 }
1309
1310 static inline void gen_cmps(DisasContext *s, int ot)
1311 {
1312 gen_string_movl_A0_ESI(s);
1313 gen_op_ld_T0_A0(ot + s->mem_index);
1314 gen_string_movl_A0_EDI(s);
1315 gen_op_ld_T1_A0(ot + s->mem_index);
1316 gen_op_cmpl_T0_T1_cc();
1317 gen_op_movl_T0_Dshift(ot);
1318 gen_op_add_reg_T0(s->aflag, R_ESI);
1319 gen_op_add_reg_T0(s->aflag, R_EDI);
1320 set_cc_op(s, CC_OP_SUBB + ot);
1321 }
1322
1323 static inline void gen_ins(DisasContext *s, int ot)
1324 {
1325 if (use_icount)
1326 gen_io_start();
1327 gen_string_movl_A0_EDI(s);
1328 /* Note: we must do this dummy write first to be restartable in
1329 case of page fault. */
1330 gen_op_movl_T0_0();
1331 gen_op_st_T0_A0(ot + s->mem_index);
1332 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1334 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1335 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1336 gen_op_st_T0_A0(ot + s->mem_index);
1337 gen_op_movl_T0_Dshift(ot);
1338 gen_op_add_reg_T0(s->aflag, R_EDI);
1339 if (use_icount)
1340 gen_io_end();
1341 }
1342
1343 static inline void gen_outs(DisasContext *s, int ot)
1344 {
1345 if (use_icount)
1346 gen_io_start();
1347 gen_string_movl_A0_ESI(s);
1348 gen_op_ld_T0_A0(ot + s->mem_index);
1349
1350 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1351 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1352 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1353 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1354 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1355
1356 gen_op_movl_T0_Dshift(ot);
1357 gen_op_add_reg_T0(s->aflag, R_ESI);
1358 if (use_icount)
1359 gen_io_end();
1360 }
1361
1362 /* same method as Valgrind : we generate jumps to current or next
1363 instruction */
1364 #define GEN_REPZ(op) \
1365 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1366 target_ulong cur_eip, target_ulong next_eip) \
1367 { \
1368 int l2;\
1369 gen_update_cc_op(s); \
1370 l2 = gen_jz_ecx_string(s, next_eip); \
1371 gen_ ## op(s, ot); \
1372 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1373 /* a loop would cause two single step exceptions if ECX = 1 \
1374 before rep string_insn */ \
1375 if (!s->jmp_opt) \
1376 gen_op_jz_ecx(s->aflag, l2); \
1377 gen_jmp(s, cur_eip); \
1378 }
1379
1380 #define GEN_REPZ2(op) \
1381 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1382 target_ulong cur_eip, \
1383 target_ulong next_eip, \
1384 int nz) \
1385 { \
1386 int l2;\
1387 gen_update_cc_op(s); \
1388 l2 = gen_jz_ecx_string(s, next_eip); \
1389 gen_ ## op(s, ot); \
1390 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1391 gen_update_cc_op(s); \
1392 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1393 if (!s->jmp_opt) \
1394 gen_op_jz_ecx(s->aflag, l2); \
1395 gen_jmp(s, cur_eip); \
1396 set_cc_op(s, CC_OP_DYNAMIC); \
1397 }
1398
1399 GEN_REPZ(movs)
1400 GEN_REPZ(stos)
1401 GEN_REPZ(lods)
1402 GEN_REPZ(ins)
1403 GEN_REPZ(outs)
1404 GEN_REPZ2(scas)
1405 GEN_REPZ2(cmps)
1406
1407 static void gen_helper_fp_arith_ST0_FT0(int op)
1408 {
1409 switch (op) {
1410 case 0:
1411 gen_helper_fadd_ST0_FT0(cpu_env);
1412 break;
1413 case 1:
1414 gen_helper_fmul_ST0_FT0(cpu_env);
1415 break;
1416 case 2:
1417 gen_helper_fcom_ST0_FT0(cpu_env);
1418 break;
1419 case 3:
1420 gen_helper_fcom_ST0_FT0(cpu_env);
1421 break;
1422 case 4:
1423 gen_helper_fsub_ST0_FT0(cpu_env);
1424 break;
1425 case 5:
1426 gen_helper_fsubr_ST0_FT0(cpu_env);
1427 break;
1428 case 6:
1429 gen_helper_fdiv_ST0_FT0(cpu_env);
1430 break;
1431 case 7:
1432 gen_helper_fdivr_ST0_FT0(cpu_env);
1433 break;
1434 }
1435 }
1436
1437 /* NOTE the exception in "r" op ordering */
1438 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1439 {
1440 TCGv_i32 tmp = tcg_const_i32(opreg);
1441 switch (op) {
1442 case 0:
1443 gen_helper_fadd_STN_ST0(cpu_env, tmp);
1444 break;
1445 case 1:
1446 gen_helper_fmul_STN_ST0(cpu_env, tmp);
1447 break;
1448 case 4:
1449 gen_helper_fsubr_STN_ST0(cpu_env, tmp);
1450 break;
1451 case 5:
1452 gen_helper_fsub_STN_ST0(cpu_env, tmp);
1453 break;
1454 case 6:
1455 gen_helper_fdivr_STN_ST0(cpu_env, tmp);
1456 break;
1457 case 7:
1458 gen_helper_fdiv_STN_ST0(cpu_env, tmp);
1459 break;
1460 }
1461 }
1462
1463 /* if d == OR_TMP0, it means memory operand (address in A0) */
1464 static void gen_op(DisasContext *s1, int op, int ot, int d)
1465 {
1466 if (d != OR_TMP0) {
1467 gen_op_mov_TN_reg(ot, 0, d);
1468 } else {
1469 gen_op_ld_T0_A0(ot + s1->mem_index);
1470 }
1471 switch(op) {
1472 case OP_ADCL:
1473 gen_compute_eflags_c(s1, cpu_tmp4, false);
1474 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1475 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1476 if (d != OR_TMP0)
1477 gen_op_mov_reg_T0(ot, d);
1478 else
1479 gen_op_st_T0_A0(ot + s1->mem_index);
1480 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1481 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1482 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1483 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1484 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1485 set_cc_op(s1, CC_OP_DYNAMIC);
1486 break;
1487 case OP_SBBL:
1488 gen_compute_eflags_c(s1, cpu_tmp4, false);
1489 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1490 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1491 if (d != OR_TMP0)
1492 gen_op_mov_reg_T0(ot, d);
1493 else
1494 gen_op_st_T0_A0(ot + s1->mem_index);
1495 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1496 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1497 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1498 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1499 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1500 set_cc_op(s1, CC_OP_DYNAMIC);
1501 break;
1502 case OP_ADDL:
1503 gen_op_addl_T0_T1();
1504 if (d != OR_TMP0)
1505 gen_op_mov_reg_T0(ot, d);
1506 else
1507 gen_op_st_T0_A0(ot + s1->mem_index);
1508 gen_op_update2_cc();
1509 set_cc_op(s1, CC_OP_ADDB + ot);
1510 break;
1511 case OP_SUBL:
1512 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1513 if (d != OR_TMP0)
1514 gen_op_mov_reg_T0(ot, d);
1515 else
1516 gen_op_st_T0_A0(ot + s1->mem_index);
1517 gen_op_update2_cc();
1518 set_cc_op(s1, CC_OP_SUBB + ot);
1519 break;
1520 default:
1521 case OP_ANDL:
1522 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1523 if (d != OR_TMP0)
1524 gen_op_mov_reg_T0(ot, d);
1525 else
1526 gen_op_st_T0_A0(ot + s1->mem_index);
1527 gen_op_update1_cc();
1528 set_cc_op(s1, CC_OP_LOGICB + ot);
1529 break;
1530 case OP_ORL:
1531 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1532 if (d != OR_TMP0)
1533 gen_op_mov_reg_T0(ot, d);
1534 else
1535 gen_op_st_T0_A0(ot + s1->mem_index);
1536 gen_op_update1_cc();
1537 set_cc_op(s1, CC_OP_LOGICB + ot);
1538 break;
1539 case OP_XORL:
1540 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1541 if (d != OR_TMP0)
1542 gen_op_mov_reg_T0(ot, d);
1543 else
1544 gen_op_st_T0_A0(ot + s1->mem_index);
1545 gen_op_update1_cc();
1546 set_cc_op(s1, CC_OP_LOGICB + ot);
1547 break;
1548 case OP_CMPL:
1549 gen_op_cmpl_T0_T1_cc();
1550 set_cc_op(s1, CC_OP_SUBB + ot);
1551 break;
1552 }
1553 }
1554
1555 /* if d == OR_TMP0, it means memory operand (address in A0) */
1556 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1557 {
1558 if (d != OR_TMP0)
1559 gen_op_mov_TN_reg(ot, 0, d);
1560 else
1561 gen_op_ld_T0_A0(ot + s1->mem_index);
1562 gen_compute_eflags_c(s1, cpu_cc_src, false);
1563 if (c > 0) {
1564 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1565 set_cc_op(s1, CC_OP_INCB + ot);
1566 } else {
1567 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1568 set_cc_op(s1, CC_OP_DECB + ot);
1569 }
1570 if (d != OR_TMP0)
1571 gen_op_mov_reg_T0(ot, d);
1572 else
1573 gen_op_st_T0_A0(ot + s1->mem_index);
1574 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1575 }
1576
1577 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1578 int is_right, int is_arith)
1579 {
1580 target_ulong mask;
1581 int shift_label;
1582 TCGv t0, t1, t2;
1583
1584 if (ot == OT_QUAD) {
1585 mask = 0x3f;
1586 } else {
1587 mask = 0x1f;
1588 }
1589
1590 /* load */
1591 if (op1 == OR_TMP0) {
1592 gen_op_ld_T0_A0(ot + s->mem_index);
1593 } else {
1594 gen_op_mov_TN_reg(ot, 0, op1);
1595 }
1596
1597 t0 = tcg_temp_local_new();
1598 t1 = tcg_temp_local_new();
1599 t2 = tcg_temp_local_new();
1600
1601 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1602
1603 if (is_right) {
1604 if (is_arith) {
1605 gen_exts(ot, cpu_T[0]);
1606 tcg_gen_mov_tl(t0, cpu_T[0]);
1607 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1608 } else {
1609 gen_extu(ot, cpu_T[0]);
1610 tcg_gen_mov_tl(t0, cpu_T[0]);
1611 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1612 }
1613 } else {
1614 tcg_gen_mov_tl(t0, cpu_T[0]);
1615 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1616 }
1617
1618 /* store */
1619 if (op1 == OR_TMP0) {
1620 gen_op_st_T0_A0(ot + s->mem_index);
1621 } else {
1622 gen_op_mov_reg_T0(ot, op1);
1623 }
1624
1625 /* update eflags */
1626 gen_update_cc_op(s);
1627
1628 tcg_gen_mov_tl(t1, cpu_T[0]);
1629
1630 shift_label = gen_new_label();
1631 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1632
1633 tcg_gen_addi_tl(t2, t2, -1);
1634 tcg_gen_mov_tl(cpu_cc_dst, t1);
1635
1636 if (is_right) {
1637 if (is_arith) {
1638 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1639 } else {
1640 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1641 }
1642 } else {
1643 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1644 }
1645
1646 if (is_right) {
1647 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1648 } else {
1649 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1650 }
1651
1652 gen_set_label(shift_label);
1653 set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */
1654
1655 tcg_temp_free(t0);
1656 tcg_temp_free(t1);
1657 tcg_temp_free(t2);
1658 }
1659
1660 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1661 int is_right, int is_arith)
1662 {
1663 int mask;
1664
1665 if (ot == OT_QUAD)
1666 mask = 0x3f;
1667 else
1668 mask = 0x1f;
1669
1670 /* load */
1671 if (op1 == OR_TMP0)
1672 gen_op_ld_T0_A0(ot + s->mem_index);
1673 else
1674 gen_op_mov_TN_reg(ot, 0, op1);
1675
1676 op2 &= mask;
1677 if (op2 != 0) {
1678 if (is_right) {
1679 if (is_arith) {
1680 gen_exts(ot, cpu_T[0]);
1681 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1682 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1683 } else {
1684 gen_extu(ot, cpu_T[0]);
1685 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1686 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1687 }
1688 } else {
1689 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1690 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1691 }
1692 }
1693
1694 /* store */
1695 if (op1 == OR_TMP0)
1696 gen_op_st_T0_A0(ot + s->mem_index);
1697 else
1698 gen_op_mov_reg_T0(ot, op1);
1699
1700 /* update eflags if non zero shift */
1701 if (op2 != 0) {
1702 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1703 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1704 set_cc_op(s, (is_right ? CC_OP_SARB : CC_OP_SHLB) + ot);
1705 }
1706 }
1707
1708 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1709 {
1710 if (arg2 >= 0)
1711 tcg_gen_shli_tl(ret, arg1, arg2);
1712 else
1713 tcg_gen_shri_tl(ret, arg1, -arg2);
1714 }
1715
1716 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1717 int is_right)
1718 {
1719 target_ulong mask;
1720 int label1, label2, data_bits;
1721 TCGv t0, t1, t2, a0;
1722
1723 /* XXX: inefficient, but we must use local temps */
1724 t0 = tcg_temp_local_new();
1725 t1 = tcg_temp_local_new();
1726 t2 = tcg_temp_local_new();
1727 a0 = tcg_temp_local_new();
1728
1729 if (ot == OT_QUAD)
1730 mask = 0x3f;
1731 else
1732 mask = 0x1f;
1733
1734 /* load */
1735 if (op1 == OR_TMP0) {
1736 tcg_gen_mov_tl(a0, cpu_A0);
1737 gen_op_ld_v(ot + s->mem_index, t0, a0);
1738 } else {
1739 gen_op_mov_v_reg(ot, t0, op1);
1740 }
1741
1742 tcg_gen_mov_tl(t1, cpu_T[1]);
1743
1744 tcg_gen_andi_tl(t1, t1, mask);
1745
1746 /* Must test zero case to avoid using undefined behaviour in TCG
1747 shifts. */
1748 label1 = gen_new_label();
1749 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1750
1751 if (ot <= OT_WORD)
1752 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1753 else
1754 tcg_gen_mov_tl(cpu_tmp0, t1);
1755
1756 gen_extu(ot, t0);
1757 tcg_gen_mov_tl(t2, t0);
1758
1759 data_bits = 8 << ot;
1760 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1761 fix TCG definition) */
1762 if (is_right) {
1763 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1764 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1765 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1766 } else {
1767 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1768 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1769 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1770 }
1771 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1772
1773 gen_set_label(label1);
1774 /* store */
1775 if (op1 == OR_TMP0) {
1776 gen_op_st_v(ot + s->mem_index, t0, a0);
1777 } else {
1778 gen_op_mov_reg_v(ot, op1, t0);
1779 }
1780
1781 /* update eflags. It is needed anyway most of the time, do it always. */
1782 gen_compute_eflags(s);
1783 assert(s->cc_op == CC_OP_EFLAGS);
1784
1785 label2 = gen_new_label();
1786 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1787
1788 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1789 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1790 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1791 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1792 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1793 if (is_right) {
1794 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1795 }
1796 tcg_gen_andi_tl(t0, t0, CC_C);
1797 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1798
1799 gen_set_label(label2);
1800
1801 tcg_temp_free(t0);
1802 tcg_temp_free(t1);
1803 tcg_temp_free(t2);
1804 tcg_temp_free(a0);
1805 }
1806
1807 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1808 int is_right)
1809 {
1810 int mask;
1811 int data_bits;
1812 TCGv t0, t1, a0;
1813
1814 /* XXX: inefficient, but we must use local temps */
1815 t0 = tcg_temp_local_new();
1816 t1 = tcg_temp_local_new();
1817 a0 = tcg_temp_local_new();
1818
1819 if (ot == OT_QUAD)
1820 mask = 0x3f;
1821 else
1822 mask = 0x1f;
1823
1824 /* load */
1825 if (op1 == OR_TMP0) {
1826 tcg_gen_mov_tl(a0, cpu_A0);
1827 gen_op_ld_v(ot + s->mem_index, t0, a0);
1828 } else {
1829 gen_op_mov_v_reg(ot, t0, op1);
1830 }
1831
1832 gen_extu(ot, t0);
1833 tcg_gen_mov_tl(t1, t0);
1834
1835 op2 &= mask;
1836 data_bits = 8 << ot;
1837 if (op2 != 0) {
1838 int shift = op2 & ((1 << (3 + ot)) - 1);
1839 if (is_right) {
1840 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1841 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1842 }
1843 else {
1844 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1845 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1846 }
1847 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1848 }
1849
1850 /* store */
1851 if (op1 == OR_TMP0) {
1852 gen_op_st_v(ot + s->mem_index, t0, a0);
1853 } else {
1854 gen_op_mov_reg_v(ot, op1, t0);
1855 }
1856
1857 if (op2 != 0) {
1858 /* update eflags */
1859 gen_compute_eflags(s);
1860 assert(s->cc_op == CC_OP_EFLAGS);
1861
1862 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1863 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1864 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1865 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1866 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1867 if (is_right) {
1868 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1869 }
1870 tcg_gen_andi_tl(t0, t0, CC_C);
1871 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1872 }
1873
1874 tcg_temp_free(t0);
1875 tcg_temp_free(t1);
1876 tcg_temp_free(a0);
1877 }
1878
1879 /* XXX: add faster immediate = 1 case */
1880 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1881 int is_right)
1882 {
1883 gen_compute_eflags(s);
1884 assert(s->cc_op == CC_OP_EFLAGS);
1885
1886 /* load */
1887 if (op1 == OR_TMP0)
1888 gen_op_ld_T0_A0(ot + s->mem_index);
1889 else
1890 gen_op_mov_TN_reg(ot, 0, op1);
1891
1892 if (is_right) {
1893 switch (ot) {
1894 case OT_BYTE:
1895 gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1896 break;
1897 case OT_WORD:
1898 gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1899 break;
1900 case OT_LONG:
1901 gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1902 break;
1903 #ifdef TARGET_X86_64
1904 case OT_QUAD:
1905 gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1906 break;
1907 #endif
1908 }
1909 } else {
1910 switch (ot) {
1911 case OT_BYTE:
1912 gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1913 break;
1914 case OT_WORD:
1915 gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1916 break;
1917 case OT_LONG:
1918 gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1919 break;
1920 #ifdef TARGET_X86_64
1921 case OT_QUAD:
1922 gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1923 break;
1924 #endif
1925 }
1926 }
1927 /* store */
1928 if (op1 == OR_TMP0)
1929 gen_op_st_T0_A0(ot + s->mem_index);
1930 else
1931 gen_op_mov_reg_T0(ot, op1);
1932 }
1933
1934 /* XXX: add faster immediate case */
1935 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1936 int is_right)
1937 {
1938 int label1, label2, data_bits;
1939 target_ulong mask;
1940 TCGv t0, t1, t2, a0;
1941
1942 t0 = tcg_temp_local_new();
1943 t1 = tcg_temp_local_new();
1944 t2 = tcg_temp_local_new();
1945 a0 = tcg_temp_local_new();
1946
1947 if (ot == OT_QUAD)
1948 mask = 0x3f;
1949 else
1950 mask = 0x1f;
1951
1952 /* load */
1953 if (op1 == OR_TMP0) {
1954 tcg_gen_mov_tl(a0, cpu_A0);
1955 gen_op_ld_v(ot + s->mem_index, t0, a0);
1956 } else {
1957 gen_op_mov_v_reg(ot, t0, op1);
1958 }
1959
1960 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1961
1962 tcg_gen_mov_tl(t1, cpu_T[1]);
1963 tcg_gen_mov_tl(t2, cpu_T3);
1964
1965 /* Must test zero case to avoid using undefined behaviour in TCG
1966 shifts. */
1967 label1 = gen_new_label();
1968 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1969
1970 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1971 if (ot == OT_WORD) {
1972 /* Note: we implement the Intel behaviour for shift count > 16 */
1973 if (is_right) {
1974 tcg_gen_andi_tl(t0, t0, 0xffff);
1975 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1976 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1977 tcg_gen_ext32u_tl(t0, t0);
1978
1979 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1980
1981 /* only needed if count > 16, but a test would complicate */
1982 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1983 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1984
1985 tcg_gen_shr_tl(t0, t0, t2);
1986
1987 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1988 } else {
1989 /* XXX: not optimal */
1990 tcg_gen_andi_tl(t0, t0, 0xffff);
1991 tcg_gen_shli_tl(t1, t1, 16);
1992 tcg_gen_or_tl(t1, t1, t0);
1993 tcg_gen_ext32u_tl(t1, t1);
1994
1995 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1996 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1997 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1998 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1999
2000 tcg_gen_shl_tl(t0, t0, t2);
2001 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
2002 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
2003 tcg_gen_or_tl(t0, t0, t1);
2004 }
2005 } else {
2006 data_bits = 8 << ot;
2007 if (is_right) {
2008 if (ot == OT_LONG)
2009 tcg_gen_ext32u_tl(t0, t0);
2010
2011 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
2012
2013 tcg_gen_shr_tl(t0, t0, t2);
2014 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
2015 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
2016 tcg_gen_or_tl(t0, t0, t1);
2017
2018 } else {
2019 if (ot == OT_LONG)
2020 tcg_gen_ext32u_tl(t1, t1);
2021
2022 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
2023
2024 tcg_gen_shl_tl(t0, t0, t2);
2025 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
2026 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
2027 tcg_gen_or_tl(t0, t0, t1);
2028 }
2029 }
2030 tcg_gen_mov_tl(t1, cpu_tmp4);
2031
2032 gen_set_label(label1);
2033 /* store */
2034 if (op1 == OR_TMP0) {
2035 gen_op_st_v(ot + s->mem_index, t0, a0);
2036 } else {
2037 gen_op_mov_reg_v(ot, op1, t0);
2038 }
2039
2040 /* update eflags */
2041 gen_update_cc_op(s);
2042
2043 label2 = gen_new_label();
2044 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
2045
2046 tcg_gen_mov_tl(cpu_cc_src, t1);
2047 tcg_gen_mov_tl(cpu_cc_dst, t0);
2048 if (is_right) {
2049 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
2050 } else {
2051 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
2052 }
2053 gen_set_label(label2);
2054 set_cc_op(s, CC_OP_DYNAMIC); /* cannot predict flags after */
2055
2056 tcg_temp_free(t0);
2057 tcg_temp_free(t1);
2058 tcg_temp_free(t2);
2059 tcg_temp_free(a0);
2060 }
2061
2062 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
2063 {
2064 if (s != OR_TMP1)
2065 gen_op_mov_TN_reg(ot, 1, s);
2066 switch(op) {
2067 case OP_ROL:
2068 gen_rot_rm_T1(s1, ot, d, 0);
2069 break;
2070 case OP_ROR:
2071 gen_rot_rm_T1(s1, ot, d, 1);
2072 break;
2073 case OP_SHL:
2074 case OP_SHL1:
2075 gen_shift_rm_T1(s1, ot, d, 0, 0);
2076 break;
2077 case OP_SHR:
2078 gen_shift_rm_T1(s1, ot, d, 1, 0);
2079 break;
2080 case OP_SAR:
2081 gen_shift_rm_T1(s1, ot, d, 1, 1);
2082 break;
2083 case OP_RCL:
2084 gen_rotc_rm_T1(s1, ot, d, 0);
2085 break;
2086 case OP_RCR:
2087 gen_rotc_rm_T1(s1, ot, d, 1);
2088 break;
2089 }
2090 }
2091
2092 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
2093 {
2094 switch(op) {
2095 case OP_ROL:
2096 gen_rot_rm_im(s1, ot, d, c, 0);
2097 break;
2098 case OP_ROR:
2099 gen_rot_rm_im(s1, ot, d, c, 1);
2100 break;
2101 case OP_SHL:
2102 case OP_SHL1:
2103 gen_shift_rm_im(s1, ot, d, c, 0, 0);
2104 break;
2105 case OP_SHR:
2106 gen_shift_rm_im(s1, ot, d, c, 1, 0);
2107 break;
2108 case OP_SAR:
2109 gen_shift_rm_im(s1, ot, d, c, 1, 1);
2110 break;
2111 default:
2112 /* currently not optimized */
2113 gen_op_movl_T1_im(c);
2114 gen_shift(s1, op, ot, d, OR_TMP1);
2115 break;
2116 }
2117 }
2118
2119 static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
2120 int *reg_ptr, int *offset_ptr)
2121 {
2122 target_long disp;
2123 int havesib;
2124 int base;
2125 int index;
2126 int scale;
2127 int opreg;
2128 int mod, rm, code, override, must_add_seg;
2129
2130 override = s->override;
2131 must_add_seg = s->addseg;
2132 if (override >= 0)
2133 must_add_seg = 1;
2134 mod = (modrm >> 6) & 3;
2135 rm = modrm & 7;
2136
2137 if (s->aflag) {
2138
2139 havesib = 0;
2140 base = rm;
2141 index = 0;
2142 scale = 0;
2143
2144 if (base == 4) {
2145 havesib = 1;
2146 code = cpu_ldub_code(env, s->pc++);
2147 scale = (code >> 6) & 3;
2148 index = ((code >> 3) & 7) | REX_X(s);
2149 base = (code & 7);
2150 }
2151 base |= REX_B(s);
2152
2153 switch (mod) {
2154 case 0:
2155 if ((base & 7) == 5) {
2156 base = -1;
2157 disp = (int32_t)cpu_ldl_code(env, s->pc);
2158 s->pc += 4;
2159 if (CODE64(s) && !havesib) {
2160 disp += s->pc + s->rip_offset;
2161 }
2162 } else {
2163 disp = 0;
2164 }
2165 break;
2166 case 1:
2167 disp = (int8_t)cpu_ldub_code(env, s->pc++);
2168 break;
2169 default:
2170 case 2:
2171 disp = (int32_t)cpu_ldl_code(env, s->pc);
2172 s->pc += 4;
2173 break;
2174 }
2175
2176 if (base >= 0) {
2177 /* for correct popl handling with esp */
2178 if (base == 4 && s->popl_esp_hack)
2179 disp += s->popl_esp_hack;
2180 #ifdef TARGET_X86_64
2181 if (s->aflag == 2) {
2182 gen_op_movq_A0_reg(base);
2183 if (disp != 0) {
2184 gen_op_addq_A0_im(disp);
2185 }
2186 } else
2187 #endif
2188 {
2189 gen_op_movl_A0_reg(base);
2190 if (disp != 0)
2191 gen_op_addl_A0_im(disp);
2192 }
2193 } else {
2194 #ifdef TARGET_X86_64
2195 if (s->aflag == 2) {
2196 gen_op_movq_A0_im(disp);
2197 } else
2198 #endif
2199 {
2200 gen_op_movl_A0_im(disp);
2201 }
2202 }
2203 /* index == 4 means no index */
2204 if (havesib && (index != 4)) {
2205 #ifdef TARGET_X86_64
2206 if (s->aflag == 2) {
2207 gen_op_addq_A0_reg_sN(scale, index);
2208 } else
2209 #endif
2210 {
2211 gen_op_addl_A0_reg_sN(scale, index);
2212 }
2213 }
2214 if (must_add_seg) {
2215 if (override < 0) {
2216 if (base == R_EBP || base == R_ESP)
2217 override = R_SS;
2218 else
2219 override = R_DS;
2220 }
2221 #ifdef TARGET_X86_64
2222 if (s->aflag == 2) {
2223 gen_op_addq_A0_seg(override);
2224 } else
2225 #endif
2226 {
2227 gen_op_addl_A0_seg(s, override);
2228 }
2229 }
2230 } else {
2231 switch (mod) {
2232 case 0:
2233 if (rm == 6) {
2234 disp = cpu_lduw_code(env, s->pc);
2235 s->pc += 2;
2236 gen_op_movl_A0_im(disp);
2237 rm = 0; /* avoid SS override */
2238 goto no_rm;
2239 } else {
2240 disp = 0;
2241 }
2242 break;
2243 case 1:
2244 disp = (int8_t)cpu_ldub_code(env, s->pc++);
2245 break;
2246 default:
2247 case 2:
2248 disp = cpu_lduw_code(env, s->pc);
2249 s->pc += 2;
2250 break;
2251 }
2252 switch(rm) {
2253 case 0:
2254 gen_op_movl_A0_reg(R_EBX);
2255 gen_op_addl_A0_reg_sN(0, R_ESI);
2256 break;
2257 case 1:
2258 gen_op_movl_A0_reg(R_EBX);
2259 gen_op_addl_A0_reg_sN(0, R_EDI);
2260 break;
2261 case 2:
2262 gen_op_movl_A0_reg(R_EBP);
2263 gen_op_addl_A0_reg_sN(0, R_ESI);
2264 break;
2265 case 3:
2266 gen_op_movl_A0_reg(R_EBP);
2267 gen_op_addl_A0_reg_sN(0, R_EDI);
2268 break;
2269 case 4:
2270 gen_op_movl_A0_reg(R_ESI);
2271 break;
2272 case 5:
2273 gen_op_movl_A0_reg(R_EDI);
2274 break;
2275 case 6:
2276 gen_op_movl_A0_reg(R_EBP);
2277 break;
2278 default:
2279 case 7:
2280 gen_op_movl_A0_reg(R_EBX);
2281 break;
2282 }
2283 if (disp != 0)
2284 gen_op_addl_A0_im(disp);
2285 gen_op_andl_A0_ffff();
2286 no_rm:
2287 if (must_add_seg) {
2288 if (override < 0) {
2289 if (rm == 2 || rm == 3 || rm == 6)
2290 override = R_SS;
2291 else
2292 override = R_DS;
2293 }
2294 gen_op_addl_A0_seg(s, override);
2295 }
2296 }
2297
2298 opreg = OR_A0;
2299 disp = 0;
2300 *reg_ptr = opreg;
2301 *offset_ptr = disp;
2302 }
2303
2304 static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
2305 {
2306 int mod, rm, base, code;
2307
2308 mod = (modrm >> 6) & 3;
2309 if (mod == 3)
2310 return;
2311 rm = modrm & 7;
2312
2313 if (s->aflag) {
2314
2315 base = rm;
2316
2317 if (base == 4) {
2318 code = cpu_ldub_code(env, s->pc++);
2319 base = (code & 7);
2320 }
2321
2322 switch (mod) {
2323 case 0:
2324 if (base == 5) {
2325 s->pc += 4;
2326 }
2327 break;
2328 case 1:
2329 s->pc++;
2330 break;
2331 default:
2332 case 2:
2333 s->pc += 4;
2334 break;
2335 }
2336 } else {
2337 switch (mod) {
2338 case 0:
2339 if (rm == 6) {
2340 s->pc += 2;
2341 }
2342 break;
2343 case 1:
2344 s->pc++;
2345 break;
2346 default:
2347 case 2:
2348 s->pc += 2;
2349 break;
2350 }
2351 }
2352 }
2353
2354 /* used for LEA and MOV AX, mem */
2355 static void gen_add_A0_ds_seg(DisasContext *s)
2356 {
2357 int override, must_add_seg;
2358 must_add_seg = s->addseg;
2359 override = R_DS;
2360 if (s->override >= 0) {
2361 override = s->override;
2362 must_add_seg = 1;
2363 }
2364 if (must_add_seg) {
2365 #ifdef TARGET_X86_64
2366 if (CODE64(s)) {
2367 gen_op_addq_A0_seg(override);
2368 } else
2369 #endif
2370 {
2371 gen_op_addl_A0_seg(s, override);
2372 }
2373 }
2374 }
2375
2376 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2377 OR_TMP0 */
2378 static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
2379 int ot, int reg, int is_store)
2380 {
2381 int mod, rm, opreg, disp;
2382
2383 mod = (modrm >> 6) & 3;
2384 rm = (modrm & 7) | REX_B(s);
2385 if (mod == 3) {
2386 if (is_store) {
2387 if (reg != OR_TMP0)
2388 gen_op_mov_TN_reg(ot, 0, reg);
2389 gen_op_mov_reg_T0(ot, rm);
2390 } else {
2391 gen_op_mov_TN_reg(ot, 0, rm);
2392 if (reg != OR_TMP0)
2393 gen_op_mov_reg_T0(ot, reg);
2394 }
2395 } else {
2396 gen_lea_modrm(env, s, modrm, &opreg, &disp);
2397 if (is_store) {
2398 if (reg != OR_TMP0)
2399 gen_op_mov_TN_reg(ot, 0, reg);
2400 gen_op_st_T0_A0(ot + s->mem_index);
2401 } else {
2402 gen_op_ld_T0_A0(ot + s->mem_index);
2403 if (reg != OR_TMP0)
2404 gen_op_mov_reg_T0(ot, reg);
2405 }
2406 }
2407 }
2408
2409 static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
2410 {
2411 uint32_t ret;
2412
2413 switch(ot) {
2414 case OT_BYTE:
2415 ret = cpu_ldub_code(env, s->pc);
2416 s->pc++;
2417 break;
2418 case OT_WORD:
2419 ret = cpu_lduw_code(env, s->pc);
2420 s->pc += 2;
2421 break;
2422 default:
2423 case OT_LONG:
2424 ret = cpu_ldl_code(env, s->pc);
2425 s->pc += 4;
2426 break;
2427 }
2428 return ret;
2429 }
2430
2431 static inline int insn_const_size(unsigned int ot)
2432 {
2433 if (ot <= OT_LONG)
2434 return 1 << ot;
2435 else
2436 return 4;
2437 }
2438
2439 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2440 {
2441 TranslationBlock *tb;
2442 target_ulong pc;
2443
2444 pc = s->cs_base + eip;
2445 tb = s->tb;
2446 /* NOTE: we handle the case where the TB spans two pages here */
2447 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2448 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2449 /* jump to same page: we can use a direct jump */
2450 tcg_gen_goto_tb(tb_num);
2451 gen_jmp_im(eip);
2452 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2453 } else {
2454 /* jump to another page: currently not optimized */
2455 gen_jmp_im(eip);
2456 gen_eob(s);
2457 }
2458 }
2459
2460 static inline void gen_jcc(DisasContext *s, int b,
2461 target_ulong val, target_ulong next_eip)
2462 {
2463 int l1, l2;
2464
2465 if (s->jmp_opt) {
2466 gen_update_cc_op(s);
2467 l1 = gen_new_label();
2468 gen_jcc1(s, b, l1);
2469 set_cc_op(s, CC_OP_DYNAMIC);
2470
2471 gen_goto_tb(s, 0, next_eip);
2472
2473 gen_set_label(l1);
2474 gen_goto_tb(s, 1, val);
2475 s->is_jmp = DISAS_TB_JUMP;
2476 } else {
2477 l1 = gen_new_label();
2478 l2 = gen_new_label();
2479 gen_jcc1(s, b, l1);
2480
2481 gen_jmp_im(next_eip);
2482 tcg_gen_br(l2);
2483
2484 gen_set_label(l1);
2485 gen_jmp_im(val);
2486 gen_set_label(l2);
2487 gen_eob(s);
2488 }
2489 }
2490
2491 static void gen_setcc(DisasContext *s, int b)
2492 {
2493 int inv, jcc_op, l1;
2494 TCGv t0;
2495
2496 if (is_fast_jcc_case(s, b)) {
2497 /* nominal case: we use a jump */
2498 /* XXX: make it faster by adding new instructions in TCG */
2499 t0 = tcg_temp_local_new();
2500 tcg_gen_movi_tl(t0, 0);
2501 l1 = gen_new_label();
2502 gen_jcc1(s, b ^ 1, l1);
2503 tcg_gen_movi_tl(t0, 1);
2504 gen_set_label(l1);
2505 tcg_gen_mov_tl(cpu_T[0], t0);
2506 tcg_temp_free(t0);
2507 } else {
2508 /* slow case: it is more efficient not to generate a jump,
2509 although it is questionnable whether this optimization is
2510 worth to */
2511 inv = b & 1;
2512 jcc_op = (b >> 1) & 7;
2513 gen_setcc_slow(s, jcc_op, cpu_T[0], inv);
2514 }
2515 }
2516
2517 static inline void gen_op_movl_T0_seg(int seg_reg)
2518 {
2519 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2520 offsetof(CPUX86State,segs[seg_reg].selector));
2521 }
2522
2523 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2524 {
2525 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2526 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2527 offsetof(CPUX86State,segs[seg_reg].selector));
2528 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2529 tcg_gen_st_tl(cpu_T[0], cpu_env,
2530 offsetof(CPUX86State,segs[seg_reg].base));
2531 }
2532
2533 /* move T0 to seg_reg and compute if the CPU state may change. Never
2534 call this function with seg_reg == R_CS */
2535 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2536 {
2537 if (s->pe && !s->vm86) {
2538 /* XXX: optimize by finding processor state dynamically */
2539 gen_update_cc_op(s);
2540 gen_jmp_im(cur_eip);
2541 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2542 gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2543 /* abort translation because the addseg value may change or
2544 because ss32 may change. For R_SS, translation must always
2545 stop as a special handling must be done to disable hardware
2546 interrupts for the next instruction */
2547 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2548 s->is_jmp = DISAS_TB_JUMP;
2549 } else {
2550 gen_op_movl_seg_T0_vm(seg_reg);
2551 if (seg_reg == R_SS)
2552 s->is_jmp = DISAS_TB_JUMP;
2553 }
2554 }
2555
2556 static inline int svm_is_rep(int prefixes)
2557 {
2558 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2559 }
2560
2561 static inline void
2562 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2563 uint32_t type, uint64_t param)
2564 {
2565 /* no SVM activated; fast case */
2566 if (likely(!(s->flags & HF_SVMI_MASK)))
2567 return;
2568 gen_update_cc_op(s);
2569 gen_jmp_im(pc_start - s->cs_base);
2570 gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type),
2571 tcg_const_i64(param));
2572 }
2573
2574 static inline void
2575 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2576 {
2577 gen_svm_check_intercept_param(s, pc_start, type, 0);
2578 }
2579
2580 static inline void gen_stack_update(DisasContext *s, int addend)
2581 {
2582 #ifdef TARGET_X86_64
2583 if (CODE64(s)) {
2584 gen_op_add_reg_im(2, R_ESP, addend);
2585 } else
2586 #endif
2587 if (s->ss32) {
2588 gen_op_add_reg_im(1, R_ESP, addend);
2589 } else {
2590 gen_op_add_reg_im(0, R_ESP, addend);
2591 }
2592 }
2593
2594 /* generate a push. It depends on ss32, addseg and dflag */
2595 static void gen_push_T0(DisasContext *s)
2596 {
2597 #ifdef TARGET_X86_64
2598 if (CODE64(s)) {
2599 gen_op_movq_A0_reg(R_ESP);
2600 if (s->dflag) {
2601 gen_op_addq_A0_im(-8);
2602 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2603 } else {
2604 gen_op_addq_A0_im(-2);
2605 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2606 }
2607 gen_op_mov_reg_A0(2, R_ESP);
2608 } else
2609 #endif
2610 {
2611 gen_op_movl_A0_reg(R_ESP);
2612 if (!s->dflag)
2613 gen_op_addl_A0_im(-2);
2614 else
2615 gen_op_addl_A0_im(-4);
2616 if (s->ss32) {
2617 if (s->addseg) {
2618 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2619 gen_op_addl_A0_seg(s, R_SS);
2620 }
2621 } else {
2622 gen_op_andl_A0_ffff();
2623 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2624 gen_op_addl_A0_seg(s, R_SS);
2625 }
2626 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2627 if (s->ss32 && !s->addseg)
2628 gen_op_mov_reg_A0(1, R_ESP);
2629 else
2630 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2631 }
2632 }
2633
2634 /* generate a push. It depends on ss32, addseg and dflag */
2635 /* slower version for T1, only used for call Ev */
2636 static void gen_push_T1(DisasContext *s)
2637 {
2638 #ifdef TARGET_X86_64
2639 if (CODE64(s)) {
2640 gen_op_movq_A0_reg(R_ESP);
2641 if (s->dflag) {
2642 gen_op_addq_A0_im(-8);
2643 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2644 } else {
2645 gen_op_addq_A0_im(-2);
2646 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2647 }
2648 gen_op_mov_reg_A0(2, R_ESP);
2649 } else
2650 #endif
2651 {
2652 gen_op_movl_A0_reg(R_ESP);
2653 if (!s->dflag)
2654 gen_op_addl_A0_im(-2);
2655 else
2656 gen_op_addl_A0_im(-4);
2657 if (s->ss32) {
2658 if (s->addseg) {
2659 gen_op_addl_A0_seg(s, R_SS);
2660 }
2661 } else {
2662 gen_op_andl_A0_ffff();
2663 gen_op_addl_A0_seg(s, R_SS);
2664 }
2665 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2666
2667 if (s->ss32 && !s->addseg)
2668 gen_op_mov_reg_A0(1, R_ESP);
2669 else
2670 gen_stack_update(s, (-2) << s->dflag);
2671 }
2672 }
2673
2674 /* two step pop is necessary for precise exceptions */
2675 static void gen_pop_T0(DisasContext *s)
2676 {
2677 #ifdef TARGET_X86_64
2678 if (CODE64(s)) {
2679 gen_op_movq_A0_reg(R_ESP);
2680 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2681 } else
2682 #endif
2683 {
2684 gen_op_movl_A0_reg(R_ESP);
2685 if (s->ss32) {
2686 if (s->addseg)
2687 gen_op_addl_A0_seg(s, R_SS);
2688 } else {
2689 gen_op_andl_A0_ffff();
2690 gen_op_addl_A0_seg(s, R_SS);
2691 }
2692 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2693 }
2694 }
2695
2696 static void gen_pop_update(DisasContext *s)
2697 {
2698 #ifdef TARGET_X86_64
2699 if (CODE64(s) && s->dflag) {
2700 gen_stack_update(s, 8);
2701 } else
2702 #endif
2703 {
2704 gen_stack_update(s, 2 << s->dflag);
2705 }
2706 }
2707
2708 static void gen_stack_A0(DisasContext *s)
2709 {
2710 gen_op_movl_A0_reg(R_ESP);
2711 if (!s->ss32)
2712 gen_op_andl_A0_ffff();
2713 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2714 if (s->addseg)
2715 gen_op_addl_A0_seg(s, R_SS);
2716 }
2717
2718 /* NOTE: wrap around in 16 bit not fully handled */
2719 static void gen_pusha(DisasContext *s)
2720 {
2721 int i;
2722 gen_op_movl_A0_reg(R_ESP);
2723 gen_op_addl_A0_im(-16 << s->dflag);
2724 if (!s->ss32)
2725 gen_op_andl_A0_ffff();
2726 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2727 if (s->addseg)
2728 gen_op_addl_A0_seg(s, R_SS);
2729 for(i = 0;i < 8; i++) {
2730 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2731 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2732 gen_op_addl_A0_im(2 << s->dflag);
2733 }
2734 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2735 }
2736
2737 /* NOTE: wrap around in 16 bit not fully handled */
2738 static void gen_popa(DisasContext *s)
2739 {
2740 int i;
2741 gen_op_movl_A0_reg(R_ESP);
2742 if (!s->ss32)
2743 gen_op_andl_A0_ffff();
2744 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2745 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2746 if (s->addseg)
2747 gen_op_addl_A0_seg(s, R_SS);
2748 for(i = 0;i < 8; i++) {
2749 /* ESP is not reloaded */
2750 if (i != 3) {
2751 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2752 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2753 }
2754 gen_op_addl_A0_im(2 << s->dflag);
2755 }
2756 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2757 }
2758
2759 static void gen_enter(DisasContext *s, int esp_addend, int level)
2760 {
2761 int ot, opsize;
2762
2763 level &= 0x1f;
2764 #ifdef TARGET_X86_64
2765 if (CODE64(s)) {
2766 ot = s->dflag ? OT_QUAD : OT_WORD;
2767 opsize = 1 << ot;
2768
2769 gen_op_movl_A0_reg(R_ESP);
2770 gen_op_addq_A0_im(-opsize);
2771 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2772
2773 /* push bp */
2774 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2775 gen_op_st_T0_A0(ot + s->mem_index);
2776 if (level) {
2777 /* XXX: must save state */
2778 gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
2779 tcg_const_i32((ot == OT_QUAD)),
2780 cpu_T[1]);
2781 }
2782 gen_op_mov_reg_T1(ot, R_EBP);
2783 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2784 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2785 } else
2786 #endif
2787 {
2788 ot = s->dflag + OT_WORD;
2789 opsize = 2 << s->dflag;
2790
2791 gen_op_movl_A0_reg(R_ESP);
2792 gen_op_addl_A0_im(-opsize);
2793 if (!s->ss32)
2794 gen_op_andl_A0_ffff();
2795 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2796 if (s->addseg)
2797 gen_op_addl_A0_seg(s, R_SS);
2798 /* push bp */
2799 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2800 gen_op_st_T0_A0(ot + s->mem_index);
2801 if (level) {
2802 /* XXX: must save state */
2803 gen_helper_enter_level(cpu_env, tcg_const_i32(level),
2804 tcg_const_i32(s->dflag),
2805 cpu_T[1]);
2806 }
2807 gen_op_mov_reg_T1(ot, R_EBP);
2808 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2809 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2810 }
2811 }
2812
2813 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2814 {
2815 gen_update_cc_op(s);
2816 gen_jmp_im(cur_eip);
2817 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2818 s->is_jmp = DISAS_TB_JUMP;
2819 }
2820
2821 /* an interrupt is different from an exception because of the
2822 privilege checks */
2823 static void gen_interrupt(DisasContext *s, int intno,
2824 target_ulong cur_eip, target_ulong next_eip)
2825 {
2826 gen_update_cc_op(s);
2827 gen_jmp_im(cur_eip);
2828 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2829 tcg_const_i32(next_eip - cur_eip));
2830 s->is_jmp = DISAS_TB_JUMP;
2831 }
2832
2833 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2834 {
2835 gen_update_cc_op(s);
2836 gen_jmp_im(cur_eip);
2837 gen_helper_debug(cpu_env);
2838 s->is_jmp = DISAS_TB_JUMP;
2839 }
2840
2841 /* generate a generic end of block. Trace exception is also generated
2842 if needed */
2843 static void gen_eob(DisasContext *s)
2844 {
2845 gen_update_cc_op(s);
2846 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2847 gen_helper_reset_inhibit_irq(cpu_env);
2848 }
2849 if (s->tb->flags & HF_RF_MASK) {
2850 gen_helper_reset_rf(cpu_env);
2851 }
2852 if (s->singlestep_enabled) {
2853 gen_helper_debug(cpu_env);
2854 } else if (s->tf) {
2855 gen_helper_single_step(cpu_env);
2856 } else {
2857 tcg_gen_exit_tb(0);
2858 }
2859 s->is_jmp = DISAS_TB_JUMP;
2860 }
2861
2862 /* generate a jump to eip. No segment change must happen before as a
2863 direct call to the next block may occur */
2864 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2865 {
2866 if (s->jmp_opt) {
2867 gen_update_cc_op(s);
2868 gen_goto_tb(s, tb_num, eip);
2869 s->is_jmp = DISAS_TB_JUMP;
2870 } else {
2871 gen_jmp_im(eip);
2872 gen_eob(s);
2873 }
2874 }
2875
2876 static void gen_jmp(DisasContext *s, target_ulong eip)
2877 {
2878 gen_jmp_tb(s, eip, 0);
2879 }
2880
2881 static inline void gen_ldq_env_A0(int idx, int offset)
2882 {
2883 int mem_index = (idx >> 2) - 1;
2884 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2885 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2886 }
2887
2888 static inline void gen_stq_env_A0(int idx, int offset)
2889 {
2890 int mem_index = (idx >> 2) - 1;
2891 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2892 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2893 }
2894
2895 static inline void gen_ldo_env_A0(int idx, int offset)
2896 {
2897 int mem_index = (idx >> 2) - 1;
2898 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2899 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2900 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2901 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2902 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2903 }
2904
2905 static inline void gen_sto_env_A0(int idx, int offset)
2906 {
2907 int mem_index = (idx >> 2) - 1;
2908 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2909 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2910 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2911 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2912 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2913 }
2914
2915 static inline void gen_op_movo(int d_offset, int s_offset)
2916 {
2917 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2918 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2919 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2920 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2921 }
2922
2923 static inline void gen_op_movq(int d_offset, int s_offset)
2924 {
2925 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2926 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2927 }
2928
2929 static inline void gen_op_movl(int d_offset, int s_offset)
2930 {
2931 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2932 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2933 }
2934
2935 static inline void gen_op_movq_env_0(int d_offset)
2936 {
2937 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2938 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2939 }
2940
2941 typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
2942 typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
2943 typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val);
2944 typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
2945 typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
2946 typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2947 TCGv_i32 val);
2948 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2949 typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2950 TCGv val);
2951
2952 #define SSE_SPECIAL ((void *)1)
2953 #define SSE_DUMMY ((void *)2)
2954
2955 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2956 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2957 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2958
2959 static const SSEFunc_0_epp sse_op_table1[256][4] = {
2960 /* 3DNow! extensions */
2961 [0x0e] = { SSE_DUMMY }, /* femms */
2962 [0x0f] = { SSE_DUMMY }, /* pf... */
2963 /* pure SSE operations */
2964 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2965 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2966 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2967 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2968 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2969 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2970 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2971 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2972
2973 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2974 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2975 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2976 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2977 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2978 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2979 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2980 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2981 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2982 [0x51] = SSE_FOP(sqrt),
2983 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2984 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2985 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2986 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2987 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2988 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2989 [0x58] = SSE_FOP(add),
2990 [0x59] = SSE_FOP(mul),
2991 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2992 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2993 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2994 [0x5c] = SSE_FOP(sub),
2995 [0x5d] = SSE_FOP(min),
2996 [0x5e] = SSE_FOP(div),
2997 [0x5f] = SSE_FOP(max),
2998
2999 [0xc2] = SSE_FOP(cmpeq),
3000 [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
3001 (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
3002
3003 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
3004 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
3005
3006 /* MMX ops and their SSE extensions */
3007 [0x60] = MMX_OP2(punpcklbw),
3008 [0x61] = MMX_OP2(punpcklwd),
3009 [0x62] = MMX_OP2(punpckldq),
3010 [0x63] = MMX_OP2(packsswb),
3011 [0x64] = MMX_OP2(pcmpgtb),
3012 [0x65] = MMX_OP2(pcmpgtw),
3013 [0x66] = MMX_OP2(pcmpgtl),
3014 [0x67] = MMX_OP2(packuswb),
3015 [0x68] = MMX_OP2(punpckhbw),
3016 [0x69] = MMX_OP2(punpckhwd),
3017 [0x6a] = MMX_OP2(punpckhdq),
3018 [0x6b] = MMX_OP2(packssdw),
3019 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
3020 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
3021 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
3022 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
3023 [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx,
3024 (SSEFunc_0_epp)gen_helper_pshufd_xmm,
3025 (SSEFunc_0_epp)gen_helper_pshufhw_xmm,
3026 (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */
3027 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
3028 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
3029 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
3030 [0x74] = MMX_OP2(pcmpeqb),
3031 [0x75] = MMX_OP2(pcmpeqw),
3032 [0x76] = MMX_OP2(pcmpeql),
3033 [0x77] = { SSE_DUMMY }, /* emms */
3034 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
3035 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
3036 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
3037 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
3038 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
3039 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
3040 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
3041 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
3042 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
3043 [0xd1] = MMX_OP2(psrlw),
3044 [0xd2] = MMX_OP2(psrld),
3045 [0xd3] = MMX_OP2(psrlq),
3046 [0xd4] = MMX_OP2(paddq),
3047 [0xd5] = MMX_OP2(pmullw),
3048 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
3049 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
3050 [0xd8] = MMX_OP2(psubusb),
3051 [0xd9] = MMX_OP2(psubusw),
3052 [0xda] = MMX_OP2(pminub),
3053 [0xdb] = MMX_OP2(pand),
3054 [0xdc] = MMX_OP2(paddusb),
3055 [0xdd] = MMX_OP2(paddusw),
3056 [0xde] = MMX_OP2(pmaxub),
3057 [0xdf] = MMX_OP2(pandn),
3058 [0xe0] = MMX_OP2(pavgb),
3059 [0xe1] = MMX_OP2(psraw),
3060 [0xe2] = MMX_OP2(psrad),
3061 [0xe3] = MMX_OP2(pavgw),
3062 [0xe4] = MMX_OP2(pmulhuw),
3063 [0xe5] = MMX_OP2(pmulhw),
3064 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
3065 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
3066 [0xe8] = MMX_OP2(psubsb),
3067 [0xe9] = MMX_OP2(psubsw),
3068 [0xea] = MMX_OP2(pminsw),
3069 [0xeb] = MMX_OP2(por),
3070 [0xec] = MMX_OP2(paddsb),
3071 [0xed] = MMX_OP2(paddsw),
3072 [0xee] = MMX_OP2(pmaxsw),
3073 [0xef] = MMX_OP2(pxor),
3074 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
3075 [0xf1] = MMX_OP2(psllw),
3076 [0xf2] = MMX_OP2(pslld),
3077 [0xf3] = MMX_OP2(psllq),
3078 [0xf4] = MMX_OP2(pmuludq),
3079 [0xf5] = MMX_OP2(pmaddwd),
3080 [0xf6] = MMX_OP2(psadbw),
3081 [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx,
3082 (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */
3083 [0xf8] = MMX_OP2(psubb),
3084 [0xf9] = MMX_OP2(psubw),
3085 [0xfa] = MMX_OP2(psubl),
3086 [0xfb] = MMX_OP2(psubq),
3087 [0xfc] = MMX_OP2(paddb),
3088 [0xfd] = MMX_OP2(paddw),
3089 [0xfe] = MMX_OP2(paddl),
3090 };
3091
3092 static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
3093 [0 + 2] = MMX_OP2(psrlw),
3094 [0 + 4] = MMX_OP2(psraw),
3095 [0 + 6] = MMX_OP2(psllw),
3096 [8 + 2] = MMX_OP2(psrld),
3097 [8 + 4] = MMX_OP2(psrad),
3098 [8 + 6] = MMX_OP2(pslld),
3099 [16 + 2] = MMX_OP2(psrlq),
3100 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
3101 [16 + 6] = MMX_OP2(psllq),
3102 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
3103 };
3104
3105 static const SSEFunc_0_epi sse_op_table3ai[] = {
3106 gen_helper_cvtsi2ss,
3107 gen_helper_cvtsi2sd
3108 };
3109
3110 #ifdef TARGET_X86_64
3111 static const SSEFunc_0_epl sse_op_table3aq[] = {
3112 gen_helper_cvtsq2ss,
3113 gen_helper_cvtsq2sd
3114 };
3115 #endif
3116
3117 static const SSEFunc_i_ep sse_op_table3bi[] = {
3118 gen_helper_cvttss2si,
3119 gen_helper_cvtss2si,
3120 gen_helper_cvttsd2si,
3121 gen_helper_cvtsd2si
3122 };
3123
3124 #ifdef TARGET_X86_64
3125 static const SSEFunc_l_ep sse_op_table3bq[] = {
3126 gen_helper_cvttss2sq,
3127 gen_helper_cvtss2sq,
3128 gen_helper_cvttsd2sq,
3129 gen_helper_cvtsd2sq
3130 };
3131 #endif
3132
3133 static const SSEFunc_0_epp sse_op_table4[8][4] = {
3134 SSE_FOP(cmpeq),
3135 SSE_FOP(cmplt),
3136 SSE_FOP(cmple),
3137 SSE_FOP(cmpunord),
3138 SSE_FOP(cmpneq),
3139 SSE_FOP(cmpnlt),
3140 SSE_FOP(cmpnle),
3141 SSE_FOP(cmpord),
3142 };
3143
3144 static const SSEFunc_0_epp sse_op_table5[256] = {
3145 [0x0c] = gen_helper_pi2fw,
3146 [0x0d] = gen_helper_pi2fd,
3147 [0x1c] = gen_helper_pf2iw,
3148 [0x1d] = gen_helper_pf2id,
3149 [0x8a] = gen_helper_pfnacc,
3150 [0x8e] = gen_helper_pfpnacc,
3151 [0x90] = gen_helper_pfcmpge,
3152 [0x94] = gen_helper_pfmin,
3153 [0x96] = gen_helper_pfrcp,
3154 [0x97] = gen_helper_pfrsqrt,
3155 [0x9a] = gen_helper_pfsub,
3156 [0x9e] = gen_helper_pfadd,
3157 [0xa0] = gen_helper_pfcmpgt,
3158 [0xa4] = gen_helper_pfmax,
3159 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3160 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3161 [0xaa] = gen_helper_pfsubr,
3162 [0xae] = gen_helper_pfacc,
3163 [0xb0] = gen_helper_pfcmpeq,
3164 [0xb4] = gen_helper_pfmul,
3165 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3166 [0xb7] = gen_helper_pmulhrw_mmx,
3167 [0xbb] = gen_helper_pswapd,
3168 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3169 };
3170
3171 struct SSEOpHelper_epp {
3172 SSEFunc_0_epp op[2];
3173 uint32_t ext_mask;
3174 };
3175
3176 struct SSEOpHelper_eppi {
3177 SSEFunc_0_eppi op[2];
3178 uint32_t ext_mask;
3179 };
3180
3181 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3182 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3183 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3184 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3185
3186 static const struct SSEOpHelper_epp sse_op_table6[256] = {
3187 [0x00] = SSSE3_OP(pshufb),
3188 [0x01] = SSSE3_OP(phaddw),
3189 [0x02] = SSSE3_OP(phaddd),
3190 [0x03] = SSSE3_OP(phaddsw),
3191 [0x04] = SSSE3_OP(pmaddubsw),
3192 [0x05] = SSSE3_OP(phsubw),
3193 [0x06] = SSSE3_OP(phsubd),
3194 [0x07] = SSSE3_OP(phsubsw),
3195 [0x08] = SSSE3_OP(psignb),
3196 [0x09] = SSSE3_OP(psignw),
3197 [0x0a] = SSSE3_OP(psignd),
3198 [0x0b] = SSSE3_OP(pmulhrsw),
3199 [0x10] = SSE41_OP(pblendvb),
3200 [0x14] = SSE41_OP(blendvps),
3201 [0x15] = SSE41_OP(blendvpd),
3202 [0x17] = SSE41_OP(ptest),
3203 [0x1c] = SSSE3_OP(pabsb),
3204 [0x1d] = SSSE3_OP(pabsw),
3205 [0x1e] = SSSE3_OP(pabsd),
3206 [0x20] = SSE41_OP(pmovsxbw),
3207 [0x21] = SSE41_OP(pmovsxbd),
3208 [0x22] = SSE41_OP(pmovsxbq),
3209 [0x23] = SSE41_OP(pmovsxwd),
3210 [0x24] = SSE41_OP(pmovsxwq),
3211 [0x25] = SSE41_OP(pmovsxdq),
3212 [0x28] = SSE41_OP(pmuldq),
3213 [0x29] = SSE41_OP(pcmpeqq),
3214 [0x2a] = SSE41_SPECIAL, /* movntqda */
3215 [0x2b] = SSE41_OP(packusdw),
3216 [0x30] = SSE41_OP(pmovzxbw),
3217 [0x31] = SSE41_OP(pmovzxbd),
3218 [0x32] = SSE41_OP(pmovzxbq),
3219 [0x33] = SSE41_OP(pmovzxwd),
3220 [0x34] = SSE41_OP(pmovzxwq),
3221 [0x35] = SSE41_OP(pmovzxdq),
3222 [0x37] = SSE42_OP(pcmpgtq),
3223 [0x38] = SSE41_OP(pminsb),
3224 [0x39] = SSE41_OP(pminsd),
3225 [0x3a] = SSE41_OP(pminuw),
3226 [0x3b] = SSE41_OP(pminud),
3227 [0x3c] = SSE41_OP(pmaxsb),
3228 [0x3d] = SSE41_OP(pmaxsd),
3229 [0x3e] = SSE41_OP(pmaxuw),
3230 [0x3f] = SSE41_OP(pmaxud),
3231 [0x40] = SSE41_OP(pmulld),
3232 [0x41] = SSE41_OP(phminposuw),
3233 };
3234
3235 static const struct SSEOpHelper_eppi sse_op_table7[256] = {
3236 [0x08] = SSE41_OP(roundps),
3237 [0x09] = SSE41_OP(roundpd),
3238 [0x0a] = SSE41_OP(roundss),
3239 [0x0b] = SSE41_OP(roundsd),
3240 [0x0c] = SSE41_OP(blendps),
3241 [0x0d] = SSE41_OP(blendpd),
3242 [0x0e] = SSE41_OP(pblendw),
3243 [0x0f] = SSSE3_OP(palignr),
3244 [0x14] = SSE41_SPECIAL, /* pextrb */
3245 [0x15] = SSE41_SPECIAL, /* pextrw */
3246 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3247 [0x17] = SSE41_SPECIAL, /* extractps */
3248 [0x20] = SSE41_SPECIAL, /* pinsrb */
3249 [0x21] = SSE41_SPECIAL, /* insertps */
3250 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3251 [0x40] = SSE41_OP(dpps),
3252 [0x41] = SSE41_OP(dppd),
3253 [0x42] = SSE41_OP(mpsadbw),
3254 [0x60] = SSE42_OP(pcmpestrm),
3255 [0x61] = SSE42_OP(pcmpestri),
3256 [0x62] = SSE42_OP(pcmpistrm),
3257 [0x63] = SSE42_OP(pcmpistri),
3258 };
3259
3260 static void gen_sse(CPUX86State *env, DisasContext *s, int b,
3261 target_ulong pc_start, int rex_r)
3262 {
3263 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3264 int modrm, mod, rm, reg, reg_addr, offset_addr;
3265 SSEFunc_0_epp sse_fn_epp;
3266 SSEFunc_0_eppi sse_fn_eppi;
3267 SSEFunc_0_ppi sse_fn_ppi;
3268 SSEFunc_0_eppt sse_fn_eppt;
3269
3270 b &= 0xff;
3271 if (s->prefix & PREFIX_DATA)
3272 b1 = 1;
3273 else if (s->prefix & PREFIX_REPZ)
3274 b1 = 2;
3275 else if (s->prefix & PREFIX_REPNZ)
3276 b1 = 3;
3277 else
3278 b1 = 0;
3279 sse_fn_epp = sse_op_table1[b][b1];
3280 if (!sse_fn_epp) {
3281 goto illegal_op;
3282 }
3283 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3284 is_xmm = 1;
3285 } else {
3286 if (b1 == 0) {
3287 /* MMX case */
3288 is_xmm = 0;
3289 } else {
3290 is_xmm = 1;
3291 }
3292 }
3293 /* simple MMX/SSE operation */
3294 if (s->flags & HF_TS_MASK) {
3295 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3296 return;
3297 }
3298 if (s->flags & HF_EM_MASK) {
3299 illegal_op:
3300 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3301 return;
3302 }
3303 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3304 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3305 goto illegal_op;
3306 if (b == 0x0e) {
3307 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3308 goto illegal_op;
3309 /* femms */
3310 gen_helper_emms(cpu_env);
3311 return;
3312 }
3313 if (b == 0x77) {
3314 /* emms */
3315 gen_helper_emms(cpu_env);
3316 return;
3317 }
3318 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3319 the static cpu state) */
3320 if (!is_xmm) {
3321 gen_helper_enter_mmx(cpu_env);
3322 }
3323
3324 modrm = cpu_ldub_code(env, s->pc++);
3325 reg = ((modrm >> 3) & 7);
3326 if (is_xmm)
3327 reg |= rex_r;
3328 mod = (modrm >> 6) & 3;
3329 if (sse_fn_epp == SSE_SPECIAL) {
3330 b |= (b1 << 8);
3331 switch(b) {
3332 case 0x0e7: /* movntq */
3333 if (mod == 3)
3334 goto illegal_op;
3335 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3336 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3337 break;
3338 case 0x1e7: /* movntdq */
3339 case 0x02b: /* movntps */
3340 case 0x12b: /* movntps */
3341 if (mod == 3)
3342 goto illegal_op;
3343 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3344 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3345 break;
3346 case 0x3f0: /* lddqu */
3347 if (mod == 3)
3348 goto illegal_op;
3349 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3350 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3351 break;
3352 case 0x22b: /* movntss */
3353 case 0x32b: /* movntsd */
3354 if (mod == 3)
3355 goto illegal_op;
3356 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3357 if (b1 & 1) {
3358 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3359 xmm_regs[reg]));
3360 } else {
3361 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3362 xmm_regs[reg].XMM_L(0)));
3363 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3364 }
3365 break;
3366 case 0x6e: /* movd mm, ea */
3367 #ifdef TARGET_X86_64
3368 if (s->dflag == 2) {
3369 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
3370 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3371 } else
3372 #endif
3373 {
3374 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
3375 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3376 offsetof(CPUX86State,fpregs[reg].mmx));
3377 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3378 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3379 }
3380 break;
3381 case 0x16e: /* movd xmm, ea */
3382 #ifdef TARGET_X86_64
3383 if (s->dflag == 2) {
3384 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
3385 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3386 offsetof(CPUX86State,xmm_regs[reg]));
3387 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3388 } else
3389 #endif
3390 {
3391 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
3392 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3393 offsetof(CPUX86State,xmm_regs[reg]));
3394 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3395 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3396 }
3397 break;
3398 case 0x6f: /* movq mm, ea */
3399 if (mod != 3) {
3400 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3401 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3402 } else {
3403 rm = (modrm & 7);
3404 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3405 offsetof(CPUX86State,fpregs[rm].mmx));
3406 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3407 offsetof(CPUX86State,fpregs[reg].mmx));
3408 }
3409 break;
3410 case 0x010: /* movups */
3411 case 0x110: /* movupd */
3412 case 0x028: /* movaps */
3413 case 0x128: /* movapd */
3414 case 0x16f: /* movdqa xmm, ea */
3415 case 0x26f: /* movdqu xmm, ea */
3416 if (mod != 3) {
3417 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3418 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3419 } else {
3420 rm = (modrm & 7) | REX_B(s);
3421 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3422 offsetof(CPUX86State,xmm_regs[rm]));
3423 }
3424 break;
3425 case 0x210: /* movss xmm, ea */
3426 if (mod != 3) {
3427 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3428 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3429 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3430 gen_op_movl_T0_0();
3431 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3432 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3433 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3434 } else {
3435 rm = (modrm & 7) | REX_B(s);
3436 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3437 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3438 }
3439 break;
3440 case 0x310: /* movsd xmm, ea */
3441 if (mod != 3) {
3442 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3443 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3444 gen_op_movl_T0_0();
3445 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3446 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3447 } else {
3448 rm = (modrm & 7) | REX_B(s);
3449 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3450 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3451 }
3452 break;
3453 case 0x012: /* movlps */
3454 case 0x112: /* movlpd */
3455 if (mod != 3) {
3456 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3457 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3458 } else {
3459 /* movhlps */
3460 rm = (modrm & 7) | REX_B(s);
3461 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3462 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3463 }
3464 break;
3465 case 0x212: /* movsldup */
3466 if (mod != 3) {
3467 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3468 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3469 } else {
3470 rm = (modrm & 7) | REX_B(s);
3471 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3472 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3473 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3474 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3475 }
3476 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3477 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3478 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3479 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3480 break;
3481 case 0x312: /* movddup */
3482 if (mod != 3) {
3483 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3484 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3485 } else {
3486 rm = (modrm & 7) | REX_B(s);
3487 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3488 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3489 }
3490 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3491 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3492 break;
3493 case 0x016: /* movhps */
3494 case 0x116: /* movhpd */
3495 if (mod != 3) {
3496 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3497 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3498 } else {
3499 /* movlhps */
3500 rm = (modrm & 7) | REX_B(s);
3501 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3502 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3503 }
3504 break;
3505 case 0x216: /* movshdup */
3506 if (mod != 3) {
3507 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3508 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3509 } else {
3510 rm = (modrm & 7) | REX_B(s);
3511 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3512 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3513 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3514 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3515 }
3516 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3517 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3518 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3519 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3520 break;
3521 case 0x178:
3522 case 0x378:
3523 {
3524 int bit_index, field_length;
3525
3526 if (b1 == 1 && reg != 0)
3527 goto illegal_op;
3528 field_length = cpu_ldub_code(env, s->pc++) & 0x3F;
3529 bit_index = cpu_ldub_code(env, s->pc++) & 0x3F;
3530 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3531 offsetof(CPUX86State,xmm_regs[reg]));
3532 if (b1 == 1)
3533 gen_helper_extrq_i(cpu_env, cpu_ptr0,
3534 tcg_const_i32(bit_index),
3535 tcg_const_i32(field_length));
3536 else
3537 gen_helper_insertq_i(cpu_env, cpu_ptr0,
3538 tcg_const_i32(bit_index),
3539 tcg_const_i32(field_length));
3540 }
3541 break;
3542 case 0x7e: /* movd ea, mm */
3543 #ifdef TARGET_X86_64
3544 if (s->dflag == 2) {
3545 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3546 offsetof(CPUX86State,fpregs[reg].mmx));
3547 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
3548 } else
3549 #endif
3550 {
3551 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3552 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3553 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
3554 }
3555 break;
3556 case 0x17e: /* movd ea, xmm */
3557 #ifdef TARGET_X86_64
3558 if (s->dflag == 2) {
3559 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3560 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3561 gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
3562 } else
3563 #endif
3564 {
3565 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3566 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3567 gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
3568 }
3569 break;
3570 case 0x27e: /* movq xmm, ea */
3571 if (mod != 3) {
3572 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3573 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3574 } else {
3575 rm = (modrm & 7) | REX_B(s);
3576 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3577 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3578 }
3579 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3580 break;
3581 case 0x7f: /* movq ea, mm */
3582 if (mod != 3) {
3583 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3584 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3585 } else {
3586 rm = (modrm & 7);
3587 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3588 offsetof(CPUX86State,fpregs[reg].mmx));
3589 }
3590 break;
3591 case 0x011: /* movups */
3592 case 0x111: /* movupd */
3593 case 0x029: /* movaps */
3594 case 0x129: /* movapd */
3595 case 0x17f: /* movdqa ea, xmm */
3596 case 0x27f: /* movdqu ea, xmm */
3597 if (mod != 3) {
3598 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3599 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3600 } else {
3601 rm = (modrm & 7) | REX_B(s);
3602 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3603 offsetof(CPUX86State,xmm_regs[reg]));
3604 }
3605 break;
3606 case 0x211: /* movss ea, xmm */
3607 if (mod != 3) {
3608 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3609 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3610 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3611 } else {
3612 rm = (modrm & 7) | REX_B(s);
3613 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3614 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3615 }
3616 break;
3617 case 0x311: /* movsd ea, xmm */
3618 if (mod != 3) {
3619 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3620 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3621 } else {
3622 rm = (modrm & 7) | REX_B(s);
3623 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3624 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3625 }
3626 break;
3627 case 0x013: /* movlps */
3628 case 0x113: /* movlpd */
3629 if (mod != 3) {
3630 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3631 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3632 } else {
3633 goto illegal_op;
3634 }
3635 break;
3636 case 0x017: /* movhps */
3637 case 0x117: /* movhpd */
3638 if (mod != 3) {
3639 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3640 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3641 } else {
3642 goto illegal_op;
3643 }
3644 break;
3645 case 0x71: /* shift mm, im */
3646 case 0x72:
3647 case 0x73:
3648 case 0x171: /* shift xmm, im */
3649 case 0x172:
3650 case 0x173:
3651 if (b1 >= 2) {
3652 goto illegal_op;
3653 }
3654 val = cpu_ldub_code(env, s->pc++);
3655 if (is_xmm) {
3656 gen_op_movl_T0_im(val);
3657 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3658 gen_op_movl_T0_0();
3659 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3660 op1_offset = offsetof(CPUX86State,xmm_t0);
3661 } else {
3662 gen_op_movl_T0_im(val);
3663 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3664 gen_op_movl_T0_0();
3665 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3666 op1_offset = offsetof(CPUX86State,mmx_t0);
3667 }
3668 sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
3669 (((modrm >> 3)) & 7)][b1];
3670 if (!sse_fn_epp) {
3671 goto illegal_op;
3672 }
3673 if (is_xmm) {
3674 rm = (modrm & 7) | REX_B(s);
3675 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3676 } else {
3677 rm = (modrm & 7);
3678 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3679 }
3680 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3681 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3682 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3683 break;
3684 case 0x050: /* movmskps */
3685 rm = (modrm & 7) | REX_B(s);
3686 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3687 offsetof(CPUX86State,xmm_regs[rm]));
3688 gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3689 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3690 gen_op_mov_reg_T0(OT_LONG, reg);
3691 break;
3692 case 0x150: /* movmskpd */
3693 rm = (modrm & 7) | REX_B(s);
3694 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3695 offsetof(CPUX86State,xmm_regs[rm]));
3696 gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3697 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3698 gen_op_mov_reg_T0(OT_LONG, reg);
3699 break;
3700 case 0x02a: /* cvtpi2ps */
3701 case 0x12a: /* cvtpi2pd */
3702 gen_helper_enter_mmx(cpu_env);
3703 if (mod != 3) {
3704 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3705 op2_offset = offsetof(CPUX86State,mmx_t0);
3706 gen_ldq_env_A0(s->mem_index, op2_offset);
3707 } else {
3708 rm = (modrm & 7);
3709 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3710 }
3711 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3712 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3713 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3714 switch(b >> 8) {
3715 case 0x0:
3716 gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1);
3717 break;
3718 default:
3719 case 0x1:
3720 gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1);
3721 break;
3722 }
3723 break;
3724 case 0x22a: /* cvtsi2ss */
3725 case 0x32a: /* cvtsi2sd */
3726 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3727 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3728 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3729 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3730 if (ot == OT_LONG) {
3731 SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
3732 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3733 sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
3734 } else {
3735 #ifdef TARGET_X86_64
3736 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
3737 sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
3738 #else
3739 goto illegal_op;
3740 #endif
3741 }
3742 break;
3743 case 0x02c: /* cvttps2pi */
3744 case 0x12c: /* cvttpd2pi */
3745 case 0x02d: /* cvtps2pi */
3746 case 0x12d: /* cvtpd2pi */
3747 gen_helper_enter_mmx(cpu_env);
3748 if (mod != 3) {
3749 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3750 op2_offset = offsetof(CPUX86State,xmm_t0);
3751 gen_ldo_env_A0(s->mem_index, op2_offset);
3752 } else {
3753 rm = (modrm & 7) | REX_B(s);
3754 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3755 }
3756 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3757 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3758 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3759 switch(b) {
3760 case 0x02c:
3761 gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3762 break;
3763 case 0x12c:
3764 gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3765 break;
3766 case 0x02d:
3767 gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3768 break;
3769 case 0x12d:
3770 gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3771 break;
3772 }
3773 break;
3774 case 0x22c: /* cvttss2si */
3775 case 0x32c: /* cvttsd2si */
3776 case 0x22d: /* cvtss2si */
3777 case 0x32d: /* cvtsd2si */
3778 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3779 if (mod != 3) {
3780 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3781 if ((b >> 8) & 1) {
3782 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3783 } else {
3784 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3785 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3786 }
3787 op2_offset = offsetof(CPUX86State,xmm_t0);
3788 } else {
3789 rm = (modrm & 7) | REX_B(s);
3790 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3791 }
3792 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3793 if (ot == OT_LONG) {
3794 SSEFunc_i_ep sse_fn_i_ep =
3795 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3796 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3797 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3798 } else {
3799 #ifdef TARGET_X86_64
3800 SSEFunc_l_ep sse_fn_l_ep =
3801 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3802 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3803 #else
3804 goto illegal_op;
3805 #endif
3806 }
3807 gen_op_mov_reg_T0(ot, reg);
3808 break;
3809 case 0xc4: /* pinsrw */
3810 case 0x1c4:
3811 s->rip_offset = 1;
3812 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
3813 val = cpu_ldub_code(env, s->pc++);
3814 if (b1) {
3815 val &= 7;
3816 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3817 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3818 } else {
3819 val &= 3;
3820 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3821 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3822 }
3823 break;
3824 case 0xc5: /* pextrw */
3825 case 0x1c5:
3826 if (mod != 3)
3827 goto illegal_op;
3828 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3829 val = cpu_ldub_code(env, s->pc++);
3830 if (b1) {
3831 val &= 7;
3832 rm = (modrm & 7) | REX_B(s);
3833 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3834 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3835 } else {
3836 val &= 3;
3837 rm = (modrm & 7);
3838 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3839 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3840 }
3841 reg = ((modrm >> 3) & 7) | rex_r;
3842 gen_op_mov_reg_T0(ot, reg);
3843 break;
3844 case 0x1d6: /* movq ea, xmm */
3845 if (mod != 3) {
3846 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3847 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3848 } else {
3849 rm = (modrm & 7) | REX_B(s);
3850 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3851 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3852 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3853 }
3854 break;
3855 case 0x2d6: /* movq2dq */
3856 gen_helper_enter_mmx(cpu_env);
3857 rm = (modrm & 7);
3858 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3859 offsetof(CPUX86State,fpregs[rm].mmx));
3860 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3861 break;
3862 case 0x3d6: /* movdq2q */
3863 gen_helper_enter_mmx(cpu_env);
3864 rm = (modrm & 7) | REX_B(s);
3865 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3866 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3867 break;
3868 case 0xd7: /* pmovmskb */
3869 case 0x1d7:
3870 if (mod != 3)
3871 goto illegal_op;
3872 if (b1) {
3873 rm = (modrm & 7) | REX_B(s);
3874 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3875 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3876 } else {
3877 rm = (modrm & 7);
3878 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3879 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3880 }
3881 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3882 reg = ((modrm >> 3) & 7) | rex_r;
3883 gen_op_mov_reg_T0(OT_LONG, reg);
3884 break;
3885 case 0x138:
3886 if (s->prefix & PREFIX_REPNZ)
3887 goto crc32;
3888 case 0x038:
3889 b = modrm;
3890 modrm = cpu_ldub_code(env, s->pc++);
3891 rm = modrm & 7;
3892 reg = ((modrm >> 3) & 7) | rex_r;
3893 mod = (modrm >> 6) & 3;
3894 if (b1 >= 2) {
3895 goto illegal_op;
3896 }
3897
3898 sse_fn_epp = sse_op_table6[b].op[b1];
3899 if (!sse_fn_epp) {
3900 goto illegal_op;
3901 }
3902 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3903 goto illegal_op;
3904
3905 if (b1) {
3906 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3907 if (mod == 3) {
3908 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3909 } else {
3910 op2_offset = offsetof(CPUX86State,xmm_t0);
3911 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3912 switch (b) {
3913 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3914 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3915 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3916 gen_ldq_env_A0(s->mem_index, op2_offset +
3917 offsetof(XMMReg, XMM_Q(0)));
3918 break;
3919 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3920 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3921 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3922 (s->mem_index >> 2) - 1);
3923 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3924 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3925 offsetof(XMMReg, XMM_L(0)));
3926 break;
3927 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3928 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3929 (s->mem_index >> 2) - 1);
3930 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3931 offsetof(XMMReg, XMM_W(0)));
3932 break;
3933 case 0x2a: /* movntqda */
3934 gen_ldo_env_A0(s->mem_index, op1_offset);
3935 return;
3936 default:
3937 gen_ldo_env_A0(s->mem_index, op2_offset);
3938 }
3939 }
3940 } else {
3941 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3942 if (mod == 3) {
3943 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3944 } else {
3945 op2_offset = offsetof(CPUX86State,mmx_t0);
3946 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
3947 gen_ldq_env_A0(s->mem_index, op2_offset);
3948 }
3949 }
3950 if (sse_fn_epp == SSE_SPECIAL) {
3951 goto illegal_op;
3952 }
3953
3954 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3955 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3956 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3957
3958 if (b == 0x17) {
3959 set_cc_op(s, CC_OP_EFLAGS);
3960 }
3961 break;
3962 case 0x338: /* crc32 */
3963 crc32:
3964 b = modrm;
3965 modrm = cpu_ldub_code(env, s->pc++);
3966 reg = ((modrm >> 3) & 7) | rex_r;
3967
3968 if (b != 0xf0 && b != 0xf1)
3969 goto illegal_op;
3970 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3971 goto illegal_op;
3972
3973 if (b == 0xf0)
3974 ot = OT_BYTE;
3975 else if (b == 0xf1 && s->dflag != 2)
3976 if (s->prefix & PREFIX_DATA)
3977 ot = OT_WORD;
3978 else
3979 ot = OT_LONG;
3980 else
3981 ot = OT_QUAD;
3982
3983 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3984 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3985 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
3986 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3987 cpu_T[0], tcg_const_i32(8 << ot));
3988
3989 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3990 gen_op_mov_reg_T0(ot, reg);
3991 break;
3992 case 0x03a:
3993 case 0x13a:
3994 b = modrm;
3995 modrm = cpu_ldub_code(env, s->pc++);
3996 rm = modrm & 7;
3997 reg = ((modrm >> 3) & 7) | rex_r;
3998 mod = (modrm >> 6) & 3;
3999 if (b1 >= 2) {
4000 goto illegal_op;
4001 }
4002
4003 sse_fn_eppi = sse_op_table7[b].op[b1];
4004 if (!sse_fn_eppi) {
4005 goto illegal_op;
4006 }
4007 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
4008 goto illegal_op;
4009
4010 if (sse_fn_eppi == SSE_SPECIAL) {
4011 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
4012 rm = (modrm & 7) | REX_B(s);
4013 if (mod != 3)
4014 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4015 reg = ((modrm >> 3) & 7) | rex_r;
4016 val = cpu_ldub_code(env, s->pc++);
4017 switch (b) {
4018 case 0x14: /* pextrb */
4019 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4020 xmm_regs[reg].XMM_B(val & 15)));
4021 if (mod == 3)
4022 gen_op_mov_reg_T0(ot, rm);
4023 else
4024 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
4025 (s->mem_index >> 2) - 1);
4026 break;
4027 case 0x15: /* pextrw */
4028 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4029 xmm_regs[reg].XMM_W(val & 7)));
4030 if (mod == 3)
4031 gen_op_mov_reg_T0(ot, rm);
4032 else
4033 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
4034 (s->mem_index >> 2) - 1);
4035 break;
4036 case 0x16:
4037 if (ot == OT_LONG) { /* pextrd */
4038 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4039 offsetof(CPUX86State,
4040 xmm_regs[reg].XMM_L(val & 3)));
4041 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
4042 if (mod == 3)
4043 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
4044 else
4045 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
4046 (s->mem_index >> 2) - 1);
4047 } else { /* pextrq */
4048 #ifdef TARGET_X86_64
4049 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
4050 offsetof(CPUX86State,
4051 xmm_regs[reg].XMM_Q(val & 1)));
4052 if (mod == 3)
4053 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
4054 else
4055 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
4056 (s->mem_index >> 2) - 1);
4057 #else
4058 goto illegal_op;
4059 #endif
4060 }
4061 break;
4062 case 0x17: /* extractps */
4063 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
4064 xmm_regs[reg].XMM_L(val & 3)));
4065 if (mod == 3)
4066 gen_op_mov_reg_T0(ot, rm);
4067 else
4068 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
4069 (s->mem_index >> 2) - 1);
4070 break;
4071 case 0x20: /* pinsrb */
4072 if (mod == 3)
4073 gen_op_mov_TN_reg(OT_LONG, 0, rm);
4074 else
4075 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
4076 (s->mem_index >> 2) - 1);
4077 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
4078 xmm_regs[reg].XMM_B(val & 15)));
4079 break;
4080 case 0x21: /* insertps */
4081 if (mod == 3) {
4082 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
4083 offsetof(CPUX86State,xmm_regs[rm]
4084 .XMM_L((val >> 6) & 3)));
4085 } else {
4086 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4087 (s->mem_index >> 2) - 1);
4088 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4089 }
4090 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4091 offsetof(CPUX86State,xmm_regs[reg]
4092 .XMM_L((val >> 4) & 3)));
4093 if ((val >> 0) & 1)
4094 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4095 cpu_env, offsetof(CPUX86State,
4096 xmm_regs[reg].XMM_L(0)));
4097 if ((val >> 1) & 1)
4098 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4099 cpu_env, offsetof(CPUX86State,
4100 xmm_regs[reg].XMM_L(1)));
4101 if ((val >> 2) & 1)
4102 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4103 cpu_env, offsetof(CPUX86State,
4104 xmm_regs[reg].XMM_L(2)));
4105 if ((val >> 3) & 1)
4106 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4107 cpu_env, offsetof(CPUX86State,
4108 xmm_regs[reg].XMM_L(3)));
4109 break;
4110 case 0x22:
4111 if (ot == OT_LONG) { /* pinsrd */
4112 if (mod == 3)
4113 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
4114 else
4115 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4116 (s->mem_index >> 2) - 1);
4117 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4118 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4119 offsetof(CPUX86State,
4120 xmm_regs[reg].XMM_L(val & 3)));
4121 } else { /* pinsrq */
4122 #ifdef TARGET_X86_64
4123 if (mod == 3)
4124 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
4125 else
4126 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4127 (s->mem_index >> 2) - 1);
4128 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4129 offsetof(CPUX86State,
4130 xmm_regs[reg].XMM_Q(val & 1)));
4131 #else
4132 goto illegal_op;
4133 #endif
4134 }
4135 break;
4136 }
4137 return;
4138 }
4139
4140 if (b1) {
4141 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4142 if (mod == 3) {
4143 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
4144 } else {
4145 op2_offset = offsetof(CPUX86State,xmm_t0);
4146 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4147 gen_ldo_env_A0(s->mem_index, op2_offset);
4148 }
4149 } else {
4150 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4151 if (mod == 3) {
4152 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4153 } else {
4154 op2_offset = offsetof(CPUX86State,mmx_t0);
4155 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4156 gen_ldq_env_A0(s->mem_index, op2_offset);
4157 }
4158 }
4159 val = cpu_ldub_code(env, s->pc++);
4160
4161 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4162 set_cc_op(s, CC_OP_EFLAGS);
4163
4164 if (s->dflag == 2)
4165 /* The helper must use entire 64-bit gp registers */
4166 val |= 1 << 8;
4167 }
4168
4169 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4170 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4171 sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4172 break;
4173 default:
4174 goto illegal_op;
4175 }
4176 } else {
4177 /* generic MMX or SSE operation */
4178 switch(b) {
4179 case 0x70: /* pshufx insn */
4180 case 0xc6: /* pshufx insn */
4181 case 0xc2: /* compare insns */
4182 s->rip_offset = 1;
4183 break;
4184 default:
4185 break;
4186 }
4187 if (is_xmm) {
4188 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4189 if (mod != 3) {
4190 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4191 op2_offset = offsetof(CPUX86State,xmm_t0);
4192 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4193 b == 0xc2)) {
4194 /* specific case for SSE single instructions */
4195 if (b1 == 2) {
4196 /* 32 bit access */
4197 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4198 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4199 } else {
4200 /* 64 bit access */
4201 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4202 }
4203 } else {
4204 gen_ldo_env_A0(s->mem_index, op2_offset);
4205 }
4206 } else {
4207 rm = (modrm & 7) | REX_B(s);
4208 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4209 }
4210 } else {
4211 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4212 if (mod != 3) {
4213 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4214 op2_offset = offsetof(CPUX86State,mmx_t0);
4215 gen_ldq_env_A0(s->mem_index, op2_offset);
4216 } else {
4217 rm = (modrm & 7);
4218 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4219 }
4220 }
4221 switch(b) {
4222 case 0x0f: /* 3DNow! data insns */
4223 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4224 goto illegal_op;
4225 val = cpu_ldub_code(env, s->pc++);
4226 sse_fn_epp = sse_op_table5[val];
4227 if (!sse_fn_epp) {
4228 goto illegal_op;
4229 }
4230 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4231 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4232 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4233 break;
4234 case 0x70: /* pshufx insn */
4235 case 0xc6: /* pshufx insn */
4236 val = cpu_ldub_code(env, s->pc++);
4237 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4238 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4239 /* XXX: introduce a new table? */
4240 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
4241 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4242 break;
4243 case 0xc2:
4244 /* compare insns */
4245 val = cpu_ldub_code(env, s->pc++);
4246 if (val >= 8)
4247 goto illegal_op;
4248 sse_fn_epp = sse_op_table4[val][b1];
4249
4250 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4251 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4252 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4253 break;
4254 case 0xf7:
4255 /* maskmov : we must prepare A0 */
4256 if (mod != 3)
4257 goto illegal_op;
4258 #ifdef TARGET_X86_64
4259 if (s->aflag == 2) {
4260 gen_op_movq_A0_reg(R_EDI);
4261 } else
4262 #endif
4263 {
4264 gen_op_movl_A0_reg(R_EDI);
4265 if (s->aflag == 0)
4266 gen_op_andl_A0_ffff();
4267 }
4268 gen_add_A0_ds_seg(s);
4269
4270 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4271 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4272 /* XXX: introduce a new table? */
4273 sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
4274 sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0);
4275 break;
4276 default:
4277 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4278 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4279 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4280 break;
4281 }
4282 if (b == 0x2e || b == 0x2f) {
4283 set_cc_op(s, CC_OP_EFLAGS);
4284 }
4285 }
4286 }
4287
4288 /* convert one instruction. s->is_jmp is set if the translation must
4289 be stopped. Return the next pc value */
4290 static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
4291 target_ulong pc_start)
4292 {
4293 int b, prefixes, aflag, dflag;
4294 int shift, ot;
4295 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4296 target_ulong next_eip, tval;
4297 int rex_w, rex_r;
4298
4299 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
4300 tcg_gen_debug_insn_start(pc_start);
4301 }
4302 s->pc = pc_start;
4303 prefixes = 0;
4304 aflag = s->code32;
4305 dflag = s->code32;
4306 s->override = -1;
4307 rex_w = -1;
4308 rex_r = 0;
4309 #ifdef TARGET_X86_64
4310 s->rex_x = 0;
4311 s->rex_b = 0;
4312 x86_64_hregs = 0;
4313 #endif
4314 s->rip_offset = 0; /* for relative ip address */
4315 next_byte:
4316 b = cpu_ldub_code(env, s->pc);
4317 s->pc++;
4318 /* check prefixes */
4319 #ifdef TARGET_X86_64
4320 if (CODE64(s)) {
4321 switch (b) {
4322 case 0xf3:
4323 prefixes |= PREFIX_REPZ;
4324 goto next_byte;
4325 case 0xf2:
4326 prefixes |= PREFIX_REPNZ;
4327 goto next_byte;
4328 case 0xf0:
4329 prefixes |= PREFIX_LOCK;
4330 goto next_byte;
4331 case 0x2e:
4332 s->override = R_CS;
4333 goto next_byte;
4334 case 0x36:
4335 s->override = R_SS;
4336 goto next_byte;
4337 case 0x3e:
4338 s->override = R_DS;
4339 goto next_byte;
4340 case 0x26:
4341 s->override = R_ES;
4342 goto next_byte;
4343 case 0x64:
4344 s->override = R_FS;
4345 goto next_byte;
4346 case 0x65:
4347 s->override = R_GS;
4348 goto next_byte;
4349 case 0x66:
4350 prefixes |= PREFIX_DATA;
4351 goto next_byte;
4352 case 0x67:
4353 prefixes |= PREFIX_ADR;
4354 goto next_byte;
4355 case 0x40 ... 0x4f:
4356 /* REX prefix */
4357 rex_w = (b >> 3) & 1;
4358 rex_r = (b & 0x4) << 1;
4359 s->rex_x = (b & 0x2) << 2;
4360 REX_B(s) = (b & 0x1) << 3;
4361 x86_64_hregs = 1; /* select uniform byte register addressing */
4362 goto next_byte;
4363 }
4364 if (rex_w == 1) {
4365 /* 0x66 is ignored if rex.w is set */
4366 dflag = 2;
4367 } else {
4368 if (prefixes & PREFIX_DATA)
4369 dflag ^= 1;
4370 }
4371 if (!(prefixes & PREFIX_ADR))
4372 aflag = 2;
4373 } else
4374 #endif
4375 {
4376 switch (b) {
4377 case 0xf3:
4378 prefixes |= PREFIX_REPZ;
4379 goto next_byte;
4380 case 0xf2:
4381 prefixes |= PREFIX_REPNZ;
4382 goto next_byte;
4383 case 0xf0:
4384 prefixes |= PREFIX_LOCK;
4385 goto next_byte;
4386 case 0x2e:
4387 s->override = R_CS;
4388 goto next_byte;
4389 case 0x36:
4390 s->override = R_SS;
4391 goto next_byte;
4392 case 0x3e:
4393 s->override = R_DS;
4394 goto next_byte;
4395 case 0x26:
4396 s->override = R_ES;
4397 goto next_byte;
4398 case 0x64:
4399 s->override = R_FS;
4400 goto next_byte;
4401 case 0x65:
4402 s->override = R_GS;
4403 goto next_byte;
4404 case 0x66:
4405 prefixes |= PREFIX_DATA;
4406 goto next_byte;
4407 case 0x67:
4408 prefixes |= PREFIX_ADR;
4409 goto next_byte;
4410 }
4411 if (prefixes & PREFIX_DATA)
4412 dflag ^= 1;
4413 if (prefixes & PREFIX_ADR)
4414 aflag ^= 1;
4415 }
4416
4417 s->prefix = prefixes;
4418 s->aflag = aflag;
4419 s->dflag = dflag;
4420
4421 /* lock generation */
4422 if (prefixes & PREFIX_LOCK)
4423 gen_helper_lock();
4424
4425 /* now check op code */
4426 reswitch:
4427 switch(b) {
4428 case 0x0f:
4429 /**************************/
4430 /* extended op code */
4431 b = cpu_ldub_code(env, s->pc++) | 0x100;
4432 goto reswitch;
4433
4434 /**************************/
4435 /* arith & logic */
4436 case 0x00 ... 0x05:
4437 case 0x08 ... 0x0d:
4438 case 0x10 ... 0x15:
4439 case 0x18 ... 0x1d:
4440 case 0x20 ... 0x25:
4441 case 0x28 ... 0x2d:
4442 case 0x30 ... 0x35:
4443 case 0x38 ... 0x3d:
4444 {
4445 int op, f, val;
4446 op = (b >> 3) & 7;
4447 f = (b >> 1) & 3;
4448
4449 if ((b & 1) == 0)
4450 ot = OT_BYTE;
4451 else
4452 ot = dflag + OT_WORD;
4453
4454 switch(f) {
4455 case 0: /* OP Ev, Gv */
4456 modrm = cpu_ldub_code(env, s->pc++);
4457 reg = ((modrm >> 3) & 7) | rex_r;
4458 mod = (modrm >> 6) & 3;
4459 rm = (modrm & 7) | REX_B(s);
4460 if (mod != 3) {
4461 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4462 opreg = OR_TMP0;
4463 } else if (op == OP_XORL && rm == reg) {
4464 xor_zero:
4465 /* xor reg, reg optimisation */
4466 gen_op_movl_T0_0();
4467 set_cc_op(s, CC_OP_LOGICB + ot);
4468 gen_op_mov_reg_T0(ot, reg);
4469 gen_op_update1_cc();
4470 break;
4471 } else {
4472 opreg = rm;
4473 }
4474 gen_op_mov_TN_reg(ot, 1, reg);
4475 gen_op(s, op, ot, opreg);
4476 break;
4477 case 1: /* OP Gv, Ev */
4478 modrm = cpu_ldub_code(env, s->pc++);
4479 mod = (modrm >> 6) & 3;
4480 reg = ((modrm >> 3) & 7) | rex_r;
4481 rm = (modrm & 7) | REX_B(s);
4482 if (mod != 3) {
4483 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4484 gen_op_ld_T1_A0(ot + s->mem_index);
4485 } else if (op == OP_XORL && rm == reg) {
4486 goto xor_zero;
4487 } else {
4488 gen_op_mov_TN_reg(ot, 1, rm);
4489 }
4490 gen_op(s, op, ot, reg);
4491 break;
4492 case 2: /* OP A, Iv */
4493 val = insn_get(env, s, ot);
4494 gen_op_movl_T1_im(val);
4495 gen_op(s, op, ot, OR_EAX);
4496 break;
4497 }
4498 }
4499 break;
4500
4501 case 0x82:
4502 if (CODE64(s))
4503 goto illegal_op;
4504 case 0x80: /* GRP1 */
4505 case 0x81:
4506 case 0x83:
4507 {
4508 int val;
4509
4510 if ((b & 1) == 0)
4511 ot = OT_BYTE;
4512 else
4513 ot = dflag + OT_WORD;
4514
4515 modrm = cpu_ldub_code(env, s->pc++);
4516 mod = (modrm >> 6) & 3;
4517 rm = (modrm & 7) | REX_B(s);
4518 op = (modrm >> 3) & 7;
4519
4520 if (mod != 3) {
4521 if (b == 0x83)
4522 s->rip_offset = 1;
4523 else
4524 s->rip_offset = insn_const_size(ot);
4525 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4526 opreg = OR_TMP0;
4527 } else {
4528 opreg = rm;
4529 }
4530
4531 switch(b) {
4532 default:
4533 case 0x80:
4534 case 0x81:
4535 case 0x82:
4536 val = insn_get(env, s, ot);
4537 break;
4538 case 0x83:
4539 val = (int8_t)insn_get(env, s, OT_BYTE);
4540 break;
4541 }
4542 gen_op_movl_T1_im(val);
4543 gen_op(s, op, ot, opreg);
4544 }
4545 break;
4546
4547 /**************************/
4548 /* inc, dec, and other misc arith */
4549 case 0x40 ... 0x47: /* inc Gv */
4550 ot = dflag ? OT_LONG : OT_WORD;
4551 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4552 break;
4553 case 0x48 ... 0x4f: /* dec Gv */
4554 ot = dflag ? OT_LONG : OT_WORD;
4555 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4556 break;
4557 case 0xf6: /* GRP3 */
4558 case 0xf7:
4559 if ((b & 1) == 0)
4560 ot = OT_BYTE;
4561 else
4562 ot = dflag + OT_WORD;
4563
4564 modrm = cpu_ldub_code(env, s->pc++);
4565 mod = (modrm >> 6) & 3;
4566 rm = (modrm & 7) | REX_B(s);
4567 op = (modrm >> 3) & 7;
4568 if (mod != 3) {
4569 if (op == 0)
4570 s->rip_offset = insn_const_size(ot);
4571 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4572 gen_op_ld_T0_A0(ot + s->mem_index);
4573 } else {
4574 gen_op_mov_TN_reg(ot, 0, rm);
4575 }
4576
4577 switch(op) {
4578 case 0: /* test */
4579 val = insn_get(env, s, ot);
4580 gen_op_movl_T1_im(val);
4581 gen_op_testl_T0_T1_cc();
4582 set_cc_op(s, CC_OP_LOGICB + ot);
4583 break;
4584 case 2: /* not */
4585 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4586 if (mod != 3) {
4587 gen_op_st_T0_A0(ot + s->mem_index);
4588 } else {
4589 gen_op_mov_reg_T0(ot, rm);
4590 }
4591 break;
4592 case 3: /* neg */
4593 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4594 if (mod != 3) {
4595 gen_op_st_T0_A0(ot + s->mem_index);
4596 } else {
4597 gen_op_mov_reg_T0(ot, rm);
4598 }
4599 gen_op_update_neg_cc();
4600 set_cc_op(s, CC_OP_SUBB + ot);
4601 break;
4602 case 4: /* mul */
4603 switch(ot) {
4604 case OT_BYTE:
4605 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4606 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4607 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4608 /* XXX: use 32 bit mul which could be faster */
4609 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4610 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4611 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4612 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4613 set_cc_op(s, CC_OP_MULB);
4614 break;
4615 case OT_WORD:
4616 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4617 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4618 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4619 /* XXX: use 32 bit mul which could be faster */
4620 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4621 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4622 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4623 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4624 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4625 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4626 set_cc_op(s, CC_OP_MULW);
4627 break;
4628 default:
4629 case OT_LONG:
4630 #ifdef TARGET_X86_64
4631 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4632 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4633 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4634 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4635 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4636 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4637 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4638 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4639 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4640 #else
4641 {
4642 TCGv_i64 t0, t1;
4643 t0 = tcg_temp_new_i64();
4644 t1 = tcg_temp_new_i64();
4645 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4646 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4647 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4648 tcg_gen_mul_i64(t0, t0, t1);
4649 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4650 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4651 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4652 tcg_gen_shri_i64(t0, t0, 32);
4653 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4654 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4655 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4656 }
4657 #endif
4658 set_cc_op(s, CC_OP_MULL);
4659 break;
4660 #ifdef TARGET_X86_64
4661 case OT_QUAD:
4662 gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]);
4663 set_cc_op(s, CC_OP_MULQ);
4664 break;
4665 #endif
4666 }
4667 break;
4668 case 5: /* imul */
4669 switch(ot) {
4670 case OT_BYTE:
4671 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4672 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4673 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4674 /* XXX: use 32 bit mul which could be faster */
4675 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4676 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4677 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4678 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4679 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4680 set_cc_op(s, CC_OP_MULB);
4681 break;
4682 case OT_WORD:
4683 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4684 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4685 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4686 /* XXX: use 32 bit mul which could be faster */
4687 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4688 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4689 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4690 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4691 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4692 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4693 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4694 set_cc_op(s, CC_OP_MULW);
4695 break;
4696 default:
4697 case OT_LONG:
4698 #ifdef TARGET_X86_64
4699 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4700 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4701 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4702 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4703 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4704 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4705 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4706 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4707 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4708 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4709 #else
4710 {
4711 TCGv_i64 t0, t1;
4712 t0 = tcg_temp_new_i64();
4713 t1 = tcg_temp_new_i64();
4714 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4715 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4716 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4717 tcg_gen_mul_i64(t0, t0, t1);
4718 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4719 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4720 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4721 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4722 tcg_gen_shri_i64(t0, t0, 32);
4723 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4724 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4725 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4726 }
4727 #endif
4728 set_cc_op(s, CC_OP_MULL);
4729 break;
4730 #ifdef TARGET_X86_64
4731 case OT_QUAD:
4732 gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]);
4733 set_cc_op(s, CC_OP_MULQ);
4734 break;
4735 #endif
4736 }
4737 break;
4738 case 6: /* div */
4739 switch(ot) {
4740 case OT_BYTE:
4741 gen_jmp_im(pc_start - s->cs_base);
4742 gen_helper_divb_AL(cpu_env, cpu_T[0]);
4743 break;
4744 case OT_WORD:
4745 gen_jmp_im(pc_start - s->cs_base);
4746 gen_helper_divw_AX(cpu_env, cpu_T[0]);
4747 break;
4748 default:
4749 case OT_LONG:
4750 gen_jmp_im(pc_start - s->cs_base);
4751 gen_helper_divl_EAX(cpu_env, cpu_T[0]);
4752 break;
4753 #ifdef TARGET_X86_64
4754 case OT_QUAD:
4755 gen_jmp_im(pc_start - s->cs_base);
4756 gen_helper_divq_EAX(cpu_env, cpu_T[0]);
4757 break;
4758 #endif
4759 }
4760 break;
4761 case 7: /* idiv */
4762 switch(ot) {
4763 case OT_BYTE:
4764 gen_jmp_im(pc_start - s->cs_base);
4765 gen_helper_idivb_AL(cpu_env, cpu_T[0]);
4766 break;
4767 case OT_WORD:
4768 gen_jmp_im(pc_start - s->cs_base);
4769 gen_helper_idivw_AX(cpu_env, cpu_T[0]);
4770 break;
4771 default:
4772 case OT_LONG:
4773 gen_jmp_im(pc_start - s->cs_base);
4774 gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
4775 break;
4776 #ifdef TARGET_X86_64
4777 case OT_QUAD:
4778 gen_jmp_im(pc_start - s->cs_base);
4779 gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
4780 break;
4781 #endif
4782 }
4783 break;
4784 default:
4785 goto illegal_op;
4786 }
4787 break;
4788
4789 case 0xfe: /* GRP4 */
4790 case 0xff: /* GRP5 */
4791 if ((b & 1) == 0)
4792 ot = OT_BYTE;
4793 else
4794 ot = dflag + OT_WORD;
4795
4796 modrm = cpu_ldub_code(env, s->pc++);
4797 mod = (modrm >> 6) & 3;
4798 rm = (modrm & 7) | REX_B(s);
4799 op = (modrm >> 3) & 7;
4800 if (op >= 2 && b == 0xfe) {
4801 goto illegal_op;
4802 }
4803 if (CODE64(s)) {
4804 if (op == 2 || op == 4) {
4805 /* operand size for jumps is 64 bit */
4806 ot = OT_QUAD;
4807 } else if (op == 3 || op == 5) {
4808 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4809 } else if (op == 6) {
4810 /* default push size is 64 bit */
4811 ot = dflag ? OT_QUAD : OT_WORD;
4812 }
4813 }
4814 if (mod != 3) {
4815 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
4816 if (op >= 2 && op != 3 && op != 5)
4817 gen_op_ld_T0_A0(ot + s->mem_index);
4818 } else {
4819 gen_op_mov_TN_reg(ot, 0, rm);
4820 }
4821
4822 switch(op) {
4823 case 0: /* inc Ev */
4824 if (mod != 3)
4825 opreg = OR_TMP0;
4826 else
4827 opreg = rm;
4828 gen_inc(s, ot, opreg, 1);
4829 break;
4830 case 1: /* dec Ev */
4831 if (mod != 3)
4832 opreg = OR_TMP0;
4833 else
4834 opreg = rm;
4835 gen_inc(s, ot, opreg, -1);
4836 break;
4837 case 2: /* call Ev */
4838 /* XXX: optimize if memory (no 'and' is necessary) */
4839 if (s->dflag == 0)
4840 gen_op_andl_T0_ffff();
4841 next_eip = s->pc - s->cs_base;
4842 gen_movtl_T1_im(next_eip);
4843 gen_push_T1(s);
4844 gen_op_jmp_T0();
4845 gen_eob(s);
4846 break;
4847 case 3: /* lcall Ev */
4848 gen_op_ld_T1_A0(ot + s->mem_index);
4849 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4850 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4851 do_lcall:
4852 if (s->pe && !s->vm86) {
4853 gen_update_cc_op(s);
4854 gen_jmp_im(pc_start - s->cs_base);
4855 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4856 gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4857 tcg_const_i32(dflag),
4858 tcg_const_i32(s->pc - pc_start));
4859 } else {
4860 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4861 gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
4862 tcg_const_i32(dflag),
4863 tcg_const_i32(s->pc - s->cs_base));
4864 }
4865 gen_eob(s);
4866 break;
4867 case 4: /* jmp Ev */
4868 if (s->dflag == 0)
4869 gen_op_andl_T0_ffff();
4870 gen_op_jmp_T0();
4871 gen_eob(s);
4872 break;
4873 case 5: /* ljmp Ev */
4874 gen_op_ld_T1_A0(ot + s->mem_index);
4875 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4876 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4877 do_ljmp:
4878 if (s->pe && !s->vm86) {
4879 gen_update_cc_op(s);
4880 gen_jmp_im(pc_start - s->cs_base);
4881 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4882 gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4883 tcg_const_i32(s->pc - pc_start));
4884 } else {
4885 gen_op_movl_seg_T0_vm(R_CS);
4886 gen_op_movl_T0_T1();
4887 gen_op_jmp_T0();
4888 }
4889 gen_eob(s);
4890 break;
4891 case 6: /* push Ev */
4892 gen_push_T0(s);
4893 break;
4894 default:
4895 goto illegal_op;
4896 }
4897 break;
4898
4899 case 0x84: /* test Ev, Gv */
4900 case 0x85:
4901 if ((b & 1) == 0)
4902 ot = OT_BYTE;
4903 else
4904 ot = dflag + OT_WORD;
4905
4906 modrm = cpu_ldub_code(env, s->pc++);
4907 reg = ((modrm >> 3) & 7) | rex_r;
4908
4909 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4910 gen_op_mov_TN_reg(ot, 1, reg);
4911 gen_op_testl_T0_T1_cc();
4912 set_cc_op(s, CC_OP_LOGICB + ot);
4913 break;
4914
4915 case 0xa8: /* test eAX, Iv */
4916 case 0xa9:
4917 if ((b & 1) == 0)
4918 ot = OT_BYTE;
4919 else
4920 ot = dflag + OT_WORD;
4921 val = insn_get(env, s, ot);
4922
4923 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4924 gen_op_movl_T1_im(val);
4925 gen_op_testl_T0_T1_cc();
4926 set_cc_op(s, CC_OP_LOGICB + ot);
4927 break;
4928
4929 case 0x98: /* CWDE/CBW */
4930 #ifdef TARGET_X86_64
4931 if (dflag == 2) {
4932 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4933 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4934 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4935 } else
4936 #endif
4937 if (dflag == 1) {
4938 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4939 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4940 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4941 } else {
4942 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4943 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4944 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4945 }
4946 break;
4947 case 0x99: /* CDQ/CWD */
4948 #ifdef TARGET_X86_64
4949 if (dflag == 2) {
4950 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4951 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4952 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4953 } else
4954 #endif
4955 if (dflag == 1) {
4956 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4957 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4958 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4959 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4960 } else {
4961 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4962 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4963 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4964 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4965 }
4966 break;
4967 case 0x1af: /* imul Gv, Ev */
4968 case 0x69: /* imul Gv, Ev, I */
4969 case 0x6b:
4970 ot = dflag + OT_WORD;
4971 modrm = cpu_ldub_code(env, s->pc++);
4972 reg = ((modrm >> 3) & 7) | rex_r;
4973 if (b == 0x69)
4974 s->rip_offset = insn_const_size(ot);
4975 else if (b == 0x6b)
4976 s->rip_offset = 1;
4977 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
4978 if (b == 0x69) {
4979 val = insn_get(env, s, ot);
4980 gen_op_movl_T1_im(val);
4981 } else if (b == 0x6b) {
4982 val = (int8_t)insn_get(env, s, OT_BYTE);
4983 gen_op_movl_T1_im(val);
4984 } else {
4985 gen_op_mov_TN_reg(ot, 1, reg);
4986 }
4987
4988 #ifdef TARGET_X86_64
4989 if (ot == OT_QUAD) {
4990 gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
4991 } else
4992 #endif
4993 if (ot == OT_LONG) {
4994 #ifdef TARGET_X86_64
4995 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4996 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4997 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4998 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4999 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
5000 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
5001 #else
5002 {
5003 TCGv_i64 t0, t1;
5004 t0 = tcg_temp_new_i64();
5005 t1 = tcg_temp_new_i64();
5006 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
5007 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
5008 tcg_gen_mul_i64(t0, t0, t1);
5009 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
5010 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
5011 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
5012 tcg_gen_shri_i64(t0, t0, 32);
5013 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
5014 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
5015 }
5016 #endif
5017 } else {
5018 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5019 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
5020 /* XXX: use 32 bit mul which could be faster */
5021 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
5022 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
5023 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
5024 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
5025 }
5026 gen_op_mov_reg_T0(ot, reg);
5027 set_cc_op(s, CC_OP_MULB + ot);
5028 break;
5029 case 0x1c0:
5030 case 0x1c1: /* xadd Ev, Gv */
5031 if ((b & 1) == 0)
5032 ot = OT_BYTE;
5033 else
5034 ot = dflag + OT_WORD;
5035 modrm = cpu_ldub_code(env, s->pc++);
5036 reg = ((modrm >> 3) & 7) | rex_r;
5037 mod = (modrm >> 6) & 3;
5038 if (mod == 3) {
5039 rm = (modrm & 7) | REX_B(s);
5040 gen_op_mov_TN_reg(ot, 0, reg);
5041 gen_op_mov_TN_reg(ot, 1, rm);
5042 gen_op_addl_T0_T1();
5043 gen_op_mov_reg_T1(ot, reg);
5044 gen_op_mov_reg_T0(ot, rm);
5045 } else {
5046 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5047 gen_op_mov_TN_reg(ot, 0, reg);
5048 gen_op_ld_T1_A0(ot + s->mem_index);
5049 gen_op_addl_T0_T1();
5050 gen_op_st_T0_A0(ot + s->mem_index);
5051 gen_op_mov_reg_T1(ot, reg);
5052 }
5053 gen_op_update2_cc();
5054 set_cc_op(s, CC_OP_ADDB + ot);
5055 break;
5056 case 0x1b0:
5057 case 0x1b1: /* cmpxchg Ev, Gv */
5058 {
5059 int label1, label2;
5060 TCGv t0, t1, t2, a0;
5061
5062 if ((b & 1) == 0)
5063 ot = OT_BYTE;
5064 else
5065 ot = dflag + OT_WORD;
5066 modrm = cpu_ldub_code(env, s->pc++);
5067 reg = ((modrm >> 3) & 7) | rex_r;
5068 mod = (modrm >> 6) & 3;
5069 t0 = tcg_temp_local_new();
5070 t1 = tcg_temp_local_new();
5071 t2 = tcg_temp_local_new();
5072 a0 = tcg_temp_local_new();
5073 gen_op_mov_v_reg(ot, t1, reg);
5074 if (mod == 3) {
5075 rm = (modrm & 7) | REX_B(s);
5076 gen_op_mov_v_reg(ot, t0, rm);
5077 } else {
5078 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5079 tcg_gen_mov_tl(a0, cpu_A0);
5080 gen_op_ld_v(ot + s->mem_index, t0, a0);
5081 rm = 0; /* avoid warning */
5082 }
5083 label1 = gen_new_label();
5084 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
5085 gen_extu(ot, t2);
5086 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
5087 label2 = gen_new_label();
5088 if (mod == 3) {
5089 gen_op_mov_reg_v(ot, R_EAX, t0);
5090 tcg_gen_br(label2);
5091 gen_set_label(label1);
5092 gen_op_mov_reg_v(ot, rm, t1);
5093 } else {
5094 /* perform no-op store cycle like physical cpu; must be
5095 before changing accumulator to ensure idempotency if
5096 the store faults and the instruction is restarted */
5097 gen_op_st_v(ot + s->mem_index, t0, a0);
5098 gen_op_mov_reg_v(ot, R_EAX, t0);
5099 tcg_gen_br(label2);
5100 gen_set_label(label1);
5101 gen_op_st_v(ot + s->mem_index, t1, a0);
5102 }
5103 gen_set_label(label2);
5104 tcg_gen_mov_tl(cpu_cc_src, t0);
5105 tcg_gen_mov_tl(cpu_cc_dst, t2);
5106 set_cc_op(s, CC_OP_SUBB + ot);
5107 tcg_temp_free(t0);
5108 tcg_temp_free(t1);
5109 tcg_temp_free(t2);
5110 tcg_temp_free(a0);
5111 }
5112 break;
5113 case 0x1c7: /* cmpxchg8b */
5114 modrm = cpu_ldub_code(env, s->pc++);
5115 mod = (modrm >> 6) & 3;
5116 if ((mod == 3) || ((modrm & 0x38) != 0x8))
5117 goto illegal_op;
5118 #ifdef TARGET_X86_64
5119 if (dflag == 2) {
5120 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
5121 goto illegal_op;
5122 gen_jmp_im(pc_start - s->cs_base);
5123 gen_update_cc_op(s);
5124 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5125 gen_helper_cmpxchg16b(cpu_env, cpu_A0);
5126 } else
5127 #endif
5128 {
5129 if (!(s->cpuid_features & CPUID_CX8))
5130 goto illegal_op;
5131 gen_jmp_im(pc_start - s->cs_base);
5132 gen_update_cc_op(s);
5133 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5134 gen_helper_cmpxchg8b(cpu_env, cpu_A0);
5135 }
5136 set_cc_op(s, CC_OP_EFLAGS);
5137 break;
5138
5139 /**************************/
5140 /* push/pop */
5141 case 0x50 ... 0x57: /* push */
5142 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
5143 gen_push_T0(s);
5144 break;
5145 case 0x58 ... 0x5f: /* pop */
5146 if (CODE64(s)) {
5147 ot = dflag ? OT_QUAD : OT_WORD;
5148 } else {
5149 ot = dflag + OT_WORD;
5150 }
5151 gen_pop_T0(s);
5152 /* NOTE: order is important for pop %sp */
5153 gen_pop_update(s);
5154 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
5155 break;
5156 case 0x60: /* pusha */
5157 if (CODE64(s))
5158 goto illegal_op;
5159 gen_pusha(s);
5160 break;
5161 case 0x61: /* popa */
5162 if (CODE64(s))
5163 goto illegal_op;
5164 gen_popa(s);
5165 break;
5166 case 0x68: /* push Iv */
5167 case 0x6a:
5168 if (CODE64(s)) {
5169 ot = dflag ? OT_QUAD : OT_WORD;
5170 } else {
5171 ot = dflag + OT_WORD;
5172 }
5173 if (b == 0x68)
5174 val = insn_get(env, s, ot);
5175 else
5176 val = (int8_t)insn_get(env, s, OT_BYTE);
5177 gen_op_movl_T0_im(val);
5178 gen_push_T0(s);
5179 break;
5180 case 0x8f: /* pop Ev */
5181 if (CODE64(s)) {
5182 ot = dflag ? OT_QUAD : OT_WORD;
5183 } else {
5184 ot = dflag + OT_WORD;
5185 }
5186 modrm = cpu_ldub_code(env, s->pc++);
5187 mod = (modrm >> 6) & 3;
5188 gen_pop_T0(s);
5189 if (mod == 3) {
5190 /* NOTE: order is important for pop %sp */
5191 gen_pop_update(s);
5192 rm = (modrm & 7) | REX_B(s);
5193 gen_op_mov_reg_T0(ot, rm);
5194 } else {
5195 /* NOTE: order is important too for MMU exceptions */
5196 s->popl_esp_hack = 1 << ot;
5197 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5198 s->popl_esp_hack = 0;
5199 gen_pop_update(s);
5200 }
5201 break;
5202 case 0xc8: /* enter */
5203 {
5204 int level;
5205 val = cpu_lduw_code(env, s->pc);
5206 s->pc += 2;
5207 level = cpu_ldub_code(env, s->pc++);
5208 gen_enter(s, val, level);
5209 }
5210 break;
5211 case 0xc9: /* leave */
5212 /* XXX: exception not precise (ESP is updated before potential exception) */
5213 if (CODE64(s)) {
5214 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5215 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5216 } else if (s->ss32) {
5217 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5218 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5219 } else {
5220 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5221 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5222 }
5223 gen_pop_T0(s);
5224 if (CODE64(s)) {
5225 ot = dflag ? OT_QUAD : OT_WORD;
5226 } else {
5227 ot = dflag + OT_WORD;
5228 }
5229 gen_op_mov_reg_T0(ot, R_EBP);
5230 gen_pop_update(s);
5231 break;
5232 case 0x06: /* push es */
5233 case 0x0e: /* push cs */
5234 case 0x16: /* push ss */
5235 case 0x1e: /* push ds */
5236 if (CODE64(s))
5237 goto illegal_op;
5238 gen_op_movl_T0_seg(b >> 3);
5239 gen_push_T0(s);
5240 break;
5241 case 0x1a0: /* push fs */
5242 case 0x1a8: /* push gs */
5243 gen_op_movl_T0_seg((b >> 3) & 7);
5244 gen_push_T0(s);
5245 break;
5246 case 0x07: /* pop es */
5247 case 0x17: /* pop ss */
5248 case 0x1f: /* pop ds */
5249 if (CODE64(s))
5250 goto illegal_op;
5251 reg = b >> 3;
5252 gen_pop_T0(s);
5253 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5254 gen_pop_update(s);
5255 if (reg == R_SS) {
5256 /* if reg == SS, inhibit interrupts/trace. */
5257 /* If several instructions disable interrupts, only the
5258 _first_ does it */
5259 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5260 gen_helper_set_inhibit_irq(cpu_env);
5261 s->tf = 0;
5262 }
5263 if (s->is_jmp) {
5264 gen_jmp_im(s->pc - s->cs_base);
5265 gen_eob(s);
5266 }
5267 break;
5268 case 0x1a1: /* pop fs */
5269 case 0x1a9: /* pop gs */
5270 gen_pop_T0(s);
5271 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5272 gen_pop_update(s);
5273 if (s->is_jmp) {
5274 gen_jmp_im(s->pc - s->cs_base);
5275 gen_eob(s);
5276 }
5277 break;
5278
5279 /**************************/
5280 /* mov */
5281 case 0x88:
5282 case 0x89: /* mov Gv, Ev */
5283 if ((b & 1) == 0)
5284 ot = OT_BYTE;
5285 else
5286 ot = dflag + OT_WORD;
5287 modrm = cpu_ldub_code(env, s->pc++);
5288 reg = ((modrm >> 3) & 7) | rex_r;
5289
5290 /* generate a generic store */
5291 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
5292 break;
5293 case 0xc6:
5294 case 0xc7: /* mov Ev, Iv */
5295 if ((b & 1) == 0)
5296 ot = OT_BYTE;
5297 else
5298 ot = dflag + OT_WORD;
5299 modrm = cpu_ldub_code(env, s->pc++);
5300 mod = (modrm >> 6) & 3;
5301 if (mod != 3) {
5302 s->rip_offset = insn_const_size(ot);
5303 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5304 }
5305 val = insn_get(env, s, ot);
5306 gen_op_movl_T0_im(val);
5307 if (mod != 3)
5308 gen_op_st_T0_A0(ot + s->mem_index);
5309 else
5310 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5311 break;
5312 case 0x8a:
5313 case 0x8b: /* mov Ev, Gv */
5314 if ((b & 1) == 0)
5315 ot = OT_BYTE;
5316 else
5317 ot = OT_WORD + dflag;
5318 modrm = cpu_ldub_code(env, s->pc++);
5319 reg = ((modrm >> 3) & 7) | rex_r;
5320
5321 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
5322 gen_op_mov_reg_T0(ot, reg);
5323 break;
5324 case 0x8e: /* mov seg, Gv */
5325 modrm = cpu_ldub_code(env, s->pc++);
5326 reg = (modrm >> 3) & 7;
5327 if (reg >= 6 || reg == R_CS)
5328 goto illegal_op;
5329 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
5330 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5331 if (reg == R_SS) {
5332 /* if reg == SS, inhibit interrupts/trace */
5333 /* If several instructions disable interrupts, only the
5334 _first_ does it */
5335 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5336 gen_helper_set_inhibit_irq(cpu_env);
5337 s->tf = 0;
5338 }
5339 if (s->is_jmp) {
5340 gen_jmp_im(s->pc - s->cs_base);
5341 gen_eob(s);
5342 }
5343 break;
5344 case 0x8c: /* mov Gv, seg */
5345 modrm = cpu_ldub_code(env, s->pc++);
5346 reg = (modrm >> 3) & 7;
5347 mod = (modrm >> 6) & 3;
5348 if (reg >= 6)
5349 goto illegal_op;
5350 gen_op_movl_T0_seg(reg);
5351 if (mod == 3)
5352 ot = OT_WORD + dflag;
5353 else
5354 ot = OT_WORD;
5355 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
5356 break;
5357
5358 case 0x1b6: /* movzbS Gv, Eb */
5359 case 0x1b7: /* movzwS Gv, Eb */
5360 case 0x1be: /* movsbS Gv, Eb */
5361 case 0x1bf: /* movswS Gv, Eb */
5362 {
5363 int d_ot;
5364 /* d_ot is the size of destination */
5365 d_ot = dflag + OT_WORD;
5366 /* ot is the size of source */
5367 ot = (b & 1) + OT_BYTE;
5368 modrm = cpu_ldub_code(env, s->pc++);
5369 reg = ((modrm >> 3) & 7) | rex_r;
5370 mod = (modrm >> 6) & 3;
5371 rm = (modrm & 7) | REX_B(s);
5372
5373 if (mod == 3) {
5374 gen_op_mov_TN_reg(ot, 0, rm);
5375 switch(ot | (b & 8)) {
5376 case OT_BYTE:
5377 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5378 break;
5379 case OT_BYTE | 8:
5380 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5381 break;
5382 case OT_WORD:
5383 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5384 break;
5385 default:
5386 case OT_WORD | 8:
5387 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5388 break;
5389 }
5390 gen_op_mov_reg_T0(d_ot, reg);
5391 } else {
5392 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5393 if (b & 8) {
5394 gen_op_lds_T0_A0(ot + s->mem_index);
5395 } else {
5396 gen_op_ldu_T0_A0(ot + s->mem_index);
5397 }
5398 gen_op_mov_reg_T0(d_ot, reg);
5399 }
5400 }
5401 break;
5402
5403 case 0x8d: /* lea */
5404 ot = dflag + OT_WORD;
5405 modrm = cpu_ldub_code(env, s->pc++);
5406 mod = (modrm >> 6) & 3;
5407 if (mod == 3)
5408 goto illegal_op;
5409 reg = ((modrm >> 3) & 7) | rex_r;
5410 /* we must ensure that no segment is added */
5411 s->override = -1;
5412 val = s->addseg;
5413 s->addseg = 0;
5414 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5415 s->addseg = val;
5416 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5417 break;
5418
5419 case 0xa0: /* mov EAX, Ov */
5420 case 0xa1:
5421 case 0xa2: /* mov Ov, EAX */
5422 case 0xa3:
5423 {
5424 target_ulong offset_addr;
5425
5426 if ((b & 1) == 0)
5427 ot = OT_BYTE;
5428 else
5429 ot = dflag + OT_WORD;
5430 #ifdef TARGET_X86_64
5431 if (s->aflag == 2) {
5432 offset_addr = cpu_ldq_code(env, s->pc);
5433 s->pc += 8;
5434 gen_op_movq_A0_im(offset_addr);
5435 } else
5436 #endif
5437 {
5438 if (s->aflag) {
5439 offset_addr = insn_get(env, s, OT_LONG);
5440 } else {
5441 offset_addr = insn_get(env, s, OT_WORD);
5442 }
5443 gen_op_movl_A0_im(offset_addr);
5444 }
5445 gen_add_A0_ds_seg(s);
5446 if ((b & 2) == 0) {
5447 gen_op_ld_T0_A0(ot + s->mem_index);
5448 gen_op_mov_reg_T0(ot, R_EAX);
5449 } else {
5450 gen_op_mov_TN_reg(ot, 0, R_EAX);
5451 gen_op_st_T0_A0(ot + s->mem_index);
5452 }
5453 }
5454 break;
5455 case 0xd7: /* xlat */
5456 #ifdef TARGET_X86_64
5457 if (s->aflag == 2) {
5458 gen_op_movq_A0_reg(R_EBX);
5459 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5460 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5461 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5462 } else
5463 #endif
5464 {
5465 gen_op_movl_A0_reg(R_EBX);
5466 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5467 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5468 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5469 if (s->aflag == 0)
5470 gen_op_andl_A0_ffff();
5471 else
5472 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5473 }
5474 gen_add_A0_ds_seg(s);
5475 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5476 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5477 break;
5478 case 0xb0 ... 0xb7: /* mov R, Ib */
5479 val = insn_get(env, s, OT_BYTE);
5480 gen_op_movl_T0_im(val);
5481 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5482 break;
5483 case 0xb8 ... 0xbf: /* mov R, Iv */
5484 #ifdef TARGET_X86_64
5485 if (dflag == 2) {
5486 uint64_t tmp;
5487 /* 64 bit case */
5488 tmp = cpu_ldq_code(env, s->pc);
5489 s->pc += 8;
5490 reg = (b & 7) | REX_B(s);
5491 gen_movtl_T0_im(tmp);
5492 gen_op_mov_reg_T0(OT_QUAD, reg);
5493 } else
5494 #endif
5495 {
5496 ot = dflag ? OT_LONG : OT_WORD;
5497 val = insn_get(env, s, ot);
5498 reg = (b & 7) | REX_B(s);
5499 gen_op_movl_T0_im(val);
5500 gen_op_mov_reg_T0(ot, reg);
5501 }
5502 break;
5503
5504 case 0x91 ... 0x97: /* xchg R, EAX */
5505 do_xchg_reg_eax:
5506 ot = dflag + OT_WORD;
5507 reg = (b & 7) | REX_B(s);
5508 rm = R_EAX;
5509 goto do_xchg_reg;
5510 case 0x86:
5511 case 0x87: /* xchg Ev, Gv */
5512 if ((b & 1) == 0)
5513 ot = OT_BYTE;
5514 else
5515 ot = dflag + OT_WORD;
5516 modrm = cpu_ldub_code(env, s->pc++);
5517 reg = ((modrm >> 3) & 7) | rex_r;
5518 mod = (modrm >> 6) & 3;
5519 if (mod == 3) {
5520 rm = (modrm & 7) | REX_B(s);
5521 do_xchg_reg:
5522 gen_op_mov_TN_reg(ot, 0, reg);
5523 gen_op_mov_TN_reg(ot, 1, rm);
5524 gen_op_mov_reg_T0(ot, rm);
5525 gen_op_mov_reg_T1(ot, reg);
5526 } else {
5527 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5528 gen_op_mov_TN_reg(ot, 0, reg);
5529 /* for xchg, lock is implicit */
5530 if (!(prefixes & PREFIX_LOCK))
5531 gen_helper_lock();
5532 gen_op_ld_T1_A0(ot + s->mem_index);
5533 gen_op_st_T0_A0(ot + s->mem_index);
5534 if (!(prefixes & PREFIX_LOCK))
5535 gen_helper_unlock();
5536 gen_op_mov_reg_T1(ot, reg);
5537 }
5538 break;
5539 case 0xc4: /* les Gv */
5540 if (CODE64(s))
5541 goto illegal_op;
5542 op = R_ES;
5543 goto do_lxx;
5544 case 0xc5: /* lds Gv */
5545 if (CODE64(s))
5546 goto illegal_op;
5547 op = R_DS;
5548 goto do_lxx;
5549 case 0x1b2: /* lss Gv */
5550 op = R_SS;
5551 goto do_lxx;
5552 case 0x1b4: /* lfs Gv */
5553 op = R_FS;
5554 goto do_lxx;
5555 case 0x1b5: /* lgs Gv */
5556 op = R_GS;
5557 do_lxx:
5558 ot = dflag ? OT_LONG : OT_WORD;
5559 modrm = cpu_ldub_code(env, s->pc++);
5560 reg = ((modrm >> 3) & 7) | rex_r;
5561 mod = (modrm >> 6) & 3;
5562 if (mod == 3)
5563 goto illegal_op;
5564 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5565 gen_op_ld_T1_A0(ot + s->mem_index);
5566 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5567 /* load the segment first to handle exceptions properly */
5568 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5569 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5570 /* then put the data */
5571 gen_op_mov_reg_T1(ot, reg);
5572 if (s->is_jmp) {
5573 gen_jmp_im(s->pc - s->cs_base);
5574 gen_eob(s);
5575 }
5576 break;
5577
5578 /************************/
5579 /* shifts */
5580 case 0xc0:
5581 case 0xc1:
5582 /* shift Ev,Ib */
5583 shift = 2;
5584 grp2:
5585 {
5586 if ((b & 1) == 0)
5587 ot = OT_BYTE;
5588 else
5589 ot = dflag + OT_WORD;
5590
5591 modrm = cpu_ldub_code(env, s->pc++);
5592 mod = (modrm >> 6) & 3;
5593 op = (modrm >> 3) & 7;
5594
5595 if (mod != 3) {
5596 if (shift == 2) {
5597 s->rip_offset = 1;
5598 }
5599 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5600 opreg = OR_TMP0;
5601 } else {
5602 opreg = (modrm & 7) | REX_B(s);
5603 }
5604
5605 /* simpler op */
5606 if (shift == 0) {
5607 gen_shift(s, op, ot, opreg, OR_ECX);
5608 } else {
5609 if (shift == 2) {
5610 shift = cpu_ldub_code(env, s->pc++);
5611 }
5612 gen_shifti(s, op, ot, opreg, shift);
5613 }
5614 }
5615 break;
5616 case 0xd0:
5617 case 0xd1:
5618 /* shift Ev,1 */
5619 shift = 1;
5620 goto grp2;
5621 case 0xd2:
5622 case 0xd3:
5623 /* shift Ev,cl */
5624 shift = 0;
5625 goto grp2;
5626
5627 case 0x1a4: /* shld imm */
5628 op = 0;
5629 shift = 1;
5630 goto do_shiftd;
5631 case 0x1a5: /* shld cl */
5632 op = 0;
5633 shift = 0;
5634 goto do_shiftd;
5635 case 0x1ac: /* shrd imm */
5636 op = 1;
5637 shift = 1;
5638 goto do_shiftd;
5639 case 0x1ad: /* shrd cl */
5640 op = 1;
5641 shift = 0;
5642 do_shiftd:
5643 ot = dflag + OT_WORD;
5644 modrm = cpu_ldub_code(env, s->pc++);
5645 mod = (modrm >> 6) & 3;
5646 rm = (modrm & 7) | REX_B(s);
5647 reg = ((modrm >> 3) & 7) | rex_r;
5648 if (mod != 3) {
5649 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5650 opreg = OR_TMP0;
5651 } else {
5652 opreg = rm;
5653 }
5654 gen_op_mov_TN_reg(ot, 1, reg);
5655
5656 if (shift) {
5657 val = cpu_ldub_code(env, s->pc++);
5658 tcg_gen_movi_tl(cpu_T3, val);
5659 } else {
5660 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5661 }
5662 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5663 break;
5664
5665 /************************/
5666 /* floats */
5667 case 0xd8 ... 0xdf:
5668 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5669 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5670 /* XXX: what to do if illegal op ? */
5671 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5672 break;
5673 }
5674 modrm = cpu_ldub_code(env, s->pc++);
5675 mod = (modrm >> 6) & 3;
5676 rm = modrm & 7;
5677 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5678 if (mod != 3) {
5679 /* memory op */
5680 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
5681 switch(op) {
5682 case 0x00 ... 0x07: /* fxxxs */
5683 case 0x10 ... 0x17: /* fixxxl */
5684 case 0x20 ... 0x27: /* fxxxl */
5685 case 0x30 ... 0x37: /* fixxx */
5686 {
5687 int op1;
5688 op1 = op & 7;
5689
5690 switch(op >> 4) {
5691 case 0:
5692 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5693 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5694 gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
5695 break;
5696 case 1:
5697 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5698 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5699 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5700 break;
5701 case 2:
5702 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5703 (s->mem_index >> 2) - 1);
5704 gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
5705 break;
5706 case 3:
5707 default:
5708 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5709 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5710 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5711 break;
5712 }
5713
5714 gen_helper_fp_arith_ST0_FT0(op1);
5715 if (op1 == 3) {
5716 /* fcomp needs pop */
5717 gen_helper_fpop(cpu_env);
5718 }
5719 }
5720 break;
5721 case 0x08: /* flds */
5722 case 0x0a: /* fsts */
5723 case 0x0b: /* fstps */
5724 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5725 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5726 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5727 switch(op & 7) {
5728 case 0:
5729 switch(op >> 4) {
5730 case 0:
5731 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5732 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5733 gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
5734 break;
5735 case 1:
5736 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5737 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5738 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5739 break;
5740 case 2:
5741 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5742 (s->mem_index >> 2) - 1);
5743 gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
5744 break;
5745 case 3:
5746 default:
5747 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5748 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5749 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5750 break;
5751 }
5752 break;
5753 case 1:
5754 /* XXX: the corresponding CPUID bit must be tested ! */
5755 switch(op >> 4) {
5756 case 1:
5757 gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
5758 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5759 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5760 break;
5761 case 2:
5762 gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
5763 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5764 (s->mem_index >> 2) - 1);
5765 break;
5766 case 3:
5767 default:
5768 gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
5769 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5770 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5771 break;
5772 }
5773 gen_helper_fpop(cpu_env);
5774 break;
5775 default:
5776 switch(op >> 4) {
5777 case 0:
5778 gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
5779 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5780 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5781 break;
5782 case 1:
5783 gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
5784 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5785 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5786 break;
5787 case 2:
5788 gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
5789 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5790 (s->mem_index >> 2) - 1);
5791 break;
5792 case 3:
5793 default:
5794 gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
5795 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5796 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5797 break;
5798 }
5799 if ((op & 7) == 3)
5800 gen_helper_fpop(cpu_env);
5801 break;
5802 }
5803 break;
5804 case 0x0c: /* fldenv mem */
5805 gen_update_cc_op(s);
5806 gen_jmp_im(pc_start - s->cs_base);
5807 gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5808 break;
5809 case 0x0d: /* fldcw mem */
5810 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5811 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5812 gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
5813 break;
5814 case 0x0e: /* fnstenv mem */
5815 gen_update_cc_op(s);
5816 gen_jmp_im(pc_start - s->cs_base);
5817 gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5818 break;
5819 case 0x0f: /* fnstcw mem */
5820 gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
5821 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5822 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5823 break;
5824 case 0x1d: /* fldt mem */
5825 gen_update_cc_op(s);
5826 gen_jmp_im(pc_start - s->cs_base);
5827 gen_helper_fldt_ST0(cpu_env, cpu_A0);
5828 break;
5829 case 0x1f: /* fstpt mem */
5830 gen_update_cc_op(s);
5831 gen_jmp_im(pc_start - s->cs_base);
5832 gen_helper_fstt_ST0(cpu_env, cpu_A0);
5833 gen_helper_fpop(cpu_env);
5834 break;
5835 case 0x2c: /* frstor mem */
5836 gen_update_cc_op(s);
5837 gen_jmp_im(pc_start - s->cs_base);
5838 gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5839 break;
5840 case 0x2e: /* fnsave mem */
5841 gen_update_cc_op(s);
5842 gen_jmp_im(pc_start - s->cs_base);
5843 gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5844 break;
5845 case 0x2f: /* fnstsw mem */
5846 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
5847 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5848 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5849 break;
5850 case 0x3c: /* fbld */
5851 gen_update_cc_op(s);
5852 gen_jmp_im(pc_start - s->cs_base);
5853 gen_helper_fbld_ST0(cpu_env, cpu_A0);
5854 break;
5855 case 0x3e: /* fbstp */
5856 gen_update_cc_op(s);
5857 gen_jmp_im(pc_start - s->cs_base);
5858 gen_helper_fbst_ST0(cpu_env, cpu_A0);
5859 gen_helper_fpop(cpu_env);
5860 break;
5861 case 0x3d: /* fildll */
5862 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5863 (s->mem_index >> 2) - 1);
5864 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
5865 break;
5866 case 0x3f: /* fistpll */
5867 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
5868 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5869 (s->mem_index >> 2) - 1);
5870 gen_helper_fpop(cpu_env);
5871 break;
5872 default:
5873 goto illegal_op;
5874 }
5875 } else {
5876 /* register float ops */
5877 opreg = rm;
5878
5879 switch(op) {
5880 case 0x08: /* fld sti */
5881 gen_helper_fpush(cpu_env);
5882 gen_helper_fmov_ST0_STN(cpu_env,
5883 tcg_const_i32((opreg + 1) & 7));
5884 break;
5885 case 0x09: /* fxchg sti */
5886 case 0x29: /* fxchg4 sti, undocumented op */
5887 case 0x39: /* fxchg7 sti, undocumented op */
5888 gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
5889 break;
5890 case 0x0a: /* grp d9/2 */
5891 switch(rm) {
5892 case 0: /* fnop */
5893 /* check exceptions (FreeBSD FPU probe) */
5894 gen_update_cc_op(s);
5895 gen_jmp_im(pc_start - s->cs_base);
5896 gen_helper_fwait(cpu_env);
5897 break;
5898 default:
5899 goto illegal_op;
5900 }
5901 break;
5902 case 0x0c: /* grp d9/4 */
5903 switch(rm) {
5904 case 0: /* fchs */
5905 gen_helper_fchs_ST0(cpu_env);
5906 break;
5907 case 1: /* fabs */
5908 gen_helper_fabs_ST0(cpu_env);
5909 break;
5910 case 4: /* ftst */
5911 gen_helper_fldz_FT0(cpu_env);
5912 gen_helper_fcom_ST0_FT0(cpu_env);
5913 break;
5914 case 5: /* fxam */
5915 gen_helper_fxam_ST0(cpu_env);
5916 break;
5917 default:
5918 goto illegal_op;
5919 }
5920 break;
5921 case 0x0d: /* grp d9/5 */
5922 {
5923 switch(rm) {
5924 case 0:
5925 gen_helper_fpush(cpu_env);
5926 gen_helper_fld1_ST0(cpu_env);
5927 break;
5928 case 1:
5929 gen_helper_fpush(cpu_env);
5930 gen_helper_fldl2t_ST0(cpu_env);
5931 break;
5932 case 2:
5933 gen_helper_fpush(cpu_env);
5934 gen_helper_fldl2e_ST0(cpu_env);
5935 break;
5936 case 3:
5937 gen_helper_fpush(cpu_env);
5938 gen_helper_fldpi_ST0(cpu_env);
5939 break;
5940 case 4:
5941 gen_helper_fpush(cpu_env);
5942 gen_helper_fldlg2_ST0(cpu_env);
5943 break;
5944 case 5:
5945 gen_helper_fpush(cpu_env);
5946 gen_helper_fldln2_ST0(cpu_env);
5947 break;
5948 case 6:
5949 gen_helper_fpush(cpu_env);
5950 gen_helper_fldz_ST0(cpu_env);
5951 break;
5952 default:
5953 goto illegal_op;
5954 }
5955 }
5956 break;
5957 case 0x0e: /* grp d9/6 */
5958 switch(rm) {
5959 case 0: /* f2xm1 */
5960 gen_helper_f2xm1(cpu_env);
5961 break;
5962 case 1: /* fyl2x */
5963 gen_helper_fyl2x(cpu_env);
5964 break;
5965 case 2: /* fptan */
5966 gen_helper_fptan(cpu_env);
5967 break;
5968 case 3: /* fpatan */
5969 gen_helper_fpatan(cpu_env);
5970 break;
5971 case 4: /* fxtract */
5972 gen_helper_fxtract(cpu_env);
5973 break;
5974 case 5: /* fprem1 */
5975 gen_helper_fprem1(cpu_env);
5976 break;
5977 case 6: /* fdecstp */
5978 gen_helper_fdecstp(cpu_env);
5979 break;
5980 default:
5981 case 7: /* fincstp */
5982 gen_helper_fincstp(cpu_env);
5983 break;
5984 }
5985 break;
5986 case 0x0f: /* grp d9/7 */
5987 switch(rm) {
5988 case 0: /* fprem */
5989 gen_helper_fprem(cpu_env);
5990 break;
5991 case 1: /* fyl2xp1 */
5992 gen_helper_fyl2xp1(cpu_env);
5993 break;
5994 case 2: /* fsqrt */
5995 gen_helper_fsqrt(cpu_env);
5996 break;
5997 case 3: /* fsincos */
5998 gen_helper_fsincos(cpu_env);
5999 break;
6000 case 5: /* fscale */
6001 gen_helper_fscale(cpu_env);
6002 break;
6003 case 4: /* frndint */
6004 gen_helper_frndint(cpu_env);
6005 break;
6006 case 6: /* fsin */
6007 gen_helper_fsin(cpu_env);
6008 break;
6009 default:
6010 case 7: /* fcos */
6011 gen_helper_fcos(cpu_env);
6012 break;
6013 }
6014 break;
6015 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6016 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6017 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6018 {
6019 int op1;
6020
6021 op1 = op & 7;
6022 if (op >= 0x20) {
6023 gen_helper_fp_arith_STN_ST0(op1, opreg);
6024 if (op >= 0x30)
6025 gen_helper_fpop(cpu_env);
6026 } else {
6027 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6028 gen_helper_fp_arith_ST0_FT0(op1);
6029 }
6030 }
6031 break;
6032 case 0x02: /* fcom */
6033 case 0x22: /* fcom2, undocumented op */
6034 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6035 gen_helper_fcom_ST0_FT0(cpu_env);
6036 break;
6037 case 0x03: /* fcomp */
6038 case 0x23: /* fcomp3, undocumented op */
6039 case 0x32: /* fcomp5, undocumented op */
6040 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6041 gen_helper_fcom_ST0_FT0(cpu_env);
6042 gen_helper_fpop(cpu_env);
6043 break;
6044 case 0x15: /* da/5 */
6045 switch(rm) {
6046 case 1: /* fucompp */
6047 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6048 gen_helper_fucom_ST0_FT0(cpu_env);
6049 gen_helper_fpop(cpu_env);
6050 gen_helper_fpop(cpu_env);
6051 break;
6052 default:
6053 goto illegal_op;
6054 }
6055 break;
6056 case 0x1c:
6057 switch(rm) {
6058 case 0: /* feni (287 only, just do nop here) */
6059 break;
6060 case 1: /* fdisi (287 only, just do nop here) */
6061 break;
6062 case 2: /* fclex */
6063 gen_helper_fclex(cpu_env);
6064 break;
6065 case 3: /* fninit */
6066 gen_helper_fninit(cpu_env);
6067 break;
6068 case 4: /* fsetpm (287 only, just do nop here) */
6069 break;
6070 default:
6071 goto illegal_op;
6072 }
6073 break;
6074 case 0x1d: /* fucomi */
6075 gen_update_cc_op(s);
6076 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6077 gen_helper_fucomi_ST0_FT0(cpu_env);
6078 set_cc_op(s, CC_OP_EFLAGS);
6079 break;
6080 case 0x1e: /* fcomi */
6081 gen_update_cc_op(s);
6082 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6083 gen_helper_fcomi_ST0_FT0(cpu_env);
6084 set_cc_op(s, CC_OP_EFLAGS);
6085 break;
6086 case 0x28: /* ffree sti */
6087 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6088 break;
6089 case 0x2a: /* fst sti */
6090 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6091 break;
6092 case 0x2b: /* fstp sti */
6093 case 0x0b: /* fstp1 sti, undocumented op */
6094 case 0x3a: /* fstp8 sti, undocumented op */
6095 case 0x3b: /* fstp9 sti, undocumented op */
6096 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6097 gen_helper_fpop(cpu_env);
6098 break;
6099 case 0x2c: /* fucom st(i) */
6100 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6101 gen_helper_fucom_ST0_FT0(cpu_env);
6102 break;
6103 case 0x2d: /* fucomp st(i) */
6104 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6105 gen_helper_fucom_ST0_FT0(cpu_env);
6106 gen_helper_fpop(cpu_env);
6107 break;
6108 case 0x33: /* de/3 */
6109 switch(rm) {
6110 case 1: /* fcompp */
6111 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6112 gen_helper_fcom_ST0_FT0(cpu_env);
6113 gen_helper_fpop(cpu_env);
6114 gen_helper_fpop(cpu_env);
6115 break;
6116 default:
6117 goto illegal_op;
6118 }
6119 break;
6120 case 0x38: /* ffreep sti, undocumented op */
6121 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6122 gen_helper_fpop(cpu_env);
6123 break;
6124 case 0x3c: /* df/4 */
6125 switch(rm) {
6126 case 0:
6127 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
6128 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
6129 gen_op_mov_reg_T0(OT_WORD, R_EAX);
6130 break;
6131 default:
6132 goto illegal_op;
6133 }
6134 break;
6135 case 0x3d: /* fucomip */
6136 gen_update_cc_op(s);
6137 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6138 gen_helper_fucomi_ST0_FT0(cpu_env);
6139 gen_helper_fpop(cpu_env);
6140 set_cc_op(s, CC_OP_EFLAGS);
6141 break;
6142 case 0x3e: /* fcomip */
6143 gen_update_cc_op(s);
6144 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6145 gen_helper_fcomi_ST0_FT0(cpu_env);
6146 gen_helper_fpop(cpu_env);
6147 set_cc_op(s, CC_OP_EFLAGS);
6148 break;
6149 case 0x10 ... 0x13: /* fcmovxx */
6150 case 0x18 ... 0x1b:
6151 {
6152 int op1, l1;
6153 static const uint8_t fcmov_cc[8] = {
6154 (JCC_B << 1),
6155 (JCC_Z << 1),
6156 (JCC_BE << 1),
6157 (JCC_P << 1),
6158 };
6159 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6160 l1 = gen_new_label();
6161 gen_jcc1(s, op1, l1);
6162 gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
6163 gen_set_label(l1);
6164 }
6165 break;
6166 default:
6167 goto illegal_op;
6168 }
6169 }
6170 break;
6171 /************************/
6172 /* string ops */
6173
6174 case 0xa4: /* movsS */
6175 case 0xa5:
6176 if ((b & 1) == 0)
6177 ot = OT_BYTE;
6178 else
6179 ot = dflag + OT_WORD;
6180
6181 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6182 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6183 } else {
6184 gen_movs(s, ot);
6185 }
6186 break;
6187
6188 case 0xaa: /* stosS */
6189 case 0xab:
6190 if ((b & 1) == 0)
6191 ot = OT_BYTE;
6192 else
6193 ot = dflag + OT_WORD;
6194
6195 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6196 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6197 } else {
6198 gen_stos(s, ot);
6199 }
6200 break;
6201 case 0xac: /* lodsS */
6202 case 0xad:
6203 if ((b & 1) == 0)
6204 ot = OT_BYTE;
6205 else
6206 ot = dflag + OT_WORD;
6207 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6208 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6209 } else {
6210 gen_lods(s, ot);
6211 }
6212 break;
6213 case 0xae: /* scasS */
6214 case 0xaf:
6215 if ((b & 1) == 0)
6216 ot = OT_BYTE;
6217 else
6218 ot = dflag + OT_WORD;
6219 if (prefixes & PREFIX_REPNZ) {
6220 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6221 } else if (prefixes & PREFIX_REPZ) {
6222 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6223 } else {
6224 gen_scas(s, ot);
6225 }
6226 break;
6227
6228 case 0xa6: /* cmpsS */
6229 case 0xa7:
6230 if ((b & 1) == 0)
6231 ot = OT_BYTE;
6232 else
6233 ot = dflag + OT_WORD;
6234 if (prefixes & PREFIX_REPNZ) {
6235 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6236 } else if (prefixes & PREFIX_REPZ) {
6237 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6238 } else {
6239 gen_cmps(s, ot);
6240 }
6241 break;
6242 case 0x6c: /* insS */
6243 case 0x6d:
6244 if ((b & 1) == 0)
6245 ot = OT_BYTE;
6246 else
6247 ot = dflag ? OT_LONG : OT_WORD;
6248 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6249 gen_op_andl_T0_ffff();
6250 gen_check_io(s, ot, pc_start - s->cs_base,
6251 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6252 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6253 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6254 } else {
6255 gen_ins(s, ot);
6256 if (use_icount) {
6257 gen_jmp(s, s->pc - s->cs_base);
6258 }
6259 }
6260 break;
6261 case 0x6e: /* outsS */
6262 case 0x6f:
6263 if ((b & 1) == 0)
6264 ot = OT_BYTE;
6265 else
6266 ot = dflag ? OT_LONG : OT_WORD;
6267 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6268 gen_op_andl_T0_ffff();
6269 gen_check_io(s, ot, pc_start - s->cs_base,
6270 svm_is_rep(prefixes) | 4);
6271 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6272 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6273 } else {
6274 gen_outs(s, ot);
6275 if (use_icount) {
6276 gen_jmp(s, s->pc - s->cs_base);
6277 }
6278 }
6279 break;
6280
6281 /************************/
6282 /* port I/O */
6283
6284 case 0xe4:
6285 case 0xe5:
6286 if ((b & 1) == 0)
6287 ot = OT_BYTE;
6288 else
6289 ot = dflag ? OT_LONG : OT_WORD;
6290 val = cpu_ldub_code(env, s->pc++);
6291 gen_op_movl_T0_im(val);
6292 gen_check_io(s, ot, pc_start - s->cs_base,
6293 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6294 if (use_icount)
6295 gen_io_start();
6296 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6297 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6298 gen_op_mov_reg_T1(ot, R_EAX);
6299 if (use_icount) {
6300 gen_io_end();
6301 gen_jmp(s, s->pc - s->cs_base);
6302 }
6303 break;
6304 case 0xe6:
6305 case 0xe7:
6306 if ((b & 1) == 0)
6307 ot = OT_BYTE;
6308 else
6309 ot = dflag ? OT_LONG : OT_WORD;
6310 val = cpu_ldub_code(env, s->pc++);
6311 gen_op_movl_T0_im(val);
6312 gen_check_io(s, ot, pc_start - s->cs_base,
6313 svm_is_rep(prefixes));
6314 gen_op_mov_TN_reg(ot, 1, R_EAX);
6315
6316 if (use_icount)
6317 gen_io_start();
6318 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6319 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6320 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6321 if (use_icount) {
6322 gen_io_end();
6323 gen_jmp(s, s->pc - s->cs_base);
6324 }
6325 break;
6326 case 0xec:
6327 case 0xed:
6328 if ((b & 1) == 0)
6329 ot = OT_BYTE;
6330 else
6331 ot = dflag ? OT_LONG : OT_WORD;
6332 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6333 gen_op_andl_T0_ffff();
6334 gen_check_io(s, ot, pc_start - s->cs_base,
6335 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6336 if (use_icount)
6337 gen_io_start();
6338 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6339 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6340 gen_op_mov_reg_T1(ot, R_EAX);
6341 if (use_icount) {
6342 gen_io_end();
6343 gen_jmp(s, s->pc - s->cs_base);
6344 }
6345 break;
6346 case 0xee:
6347 case 0xef:
6348 if ((b & 1) == 0)
6349 ot = OT_BYTE;
6350 else
6351 ot = dflag ? OT_LONG : OT_WORD;
6352 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6353 gen_op_andl_T0_ffff();
6354 gen_check_io(s, ot, pc_start - s->cs_base,
6355 svm_is_rep(prefixes));
6356 gen_op_mov_TN_reg(ot, 1, R_EAX);
6357
6358 if (use_icount)
6359 gen_io_start();
6360 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6361 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6362 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6363 if (use_icount) {
6364 gen_io_end();
6365 gen_jmp(s, s->pc - s->cs_base);
6366 }
6367 break;
6368
6369 /************************/
6370 /* control */
6371 case 0xc2: /* ret im */
6372 val = cpu_ldsw_code(env, s->pc);
6373 s->pc += 2;
6374 gen_pop_T0(s);
6375 if (CODE64(s) && s->dflag)
6376 s->dflag = 2;
6377 gen_stack_update(s, val + (2 << s->dflag));
6378 if (s->dflag == 0)
6379 gen_op_andl_T0_ffff();
6380 gen_op_jmp_T0();
6381 gen_eob(s);
6382 break;
6383 case 0xc3: /* ret */
6384 gen_pop_T0(s);
6385 gen_pop_update(s);
6386 if (s->dflag == 0)
6387 gen_op_andl_T0_ffff();
6388 gen_op_jmp_T0();
6389 gen_eob(s);
6390 break;
6391 case 0xca: /* lret im */
6392 val = cpu_ldsw_code(env, s->pc);
6393 s->pc += 2;
6394 do_lret:
6395 if (s->pe && !s->vm86) {
6396 gen_update_cc_op(s);
6397 gen_jmp_im(pc_start - s->cs_base);
6398 gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
6399 tcg_const_i32(val));
6400 } else {
6401 gen_stack_A0(s);
6402 /* pop offset */
6403 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6404 if (s->dflag == 0)
6405 gen_op_andl_T0_ffff();
6406 /* NOTE: keeping EIP updated is not a problem in case of
6407 exception */
6408 gen_op_jmp_T0();
6409 /* pop selector */
6410 gen_op_addl_A0_im(2 << s->dflag);
6411 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6412 gen_op_movl_seg_T0_vm(R_CS);
6413 /* add stack offset */
6414 gen_stack_update(s, val + (4 << s->dflag));
6415 }
6416 gen_eob(s);
6417 break;
6418 case 0xcb: /* lret */
6419 val = 0;
6420 goto do_lret;
6421 case 0xcf: /* iret */
6422 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6423 if (!s->pe) {
6424 /* real mode */
6425 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6426 set_cc_op(s, CC_OP_EFLAGS);
6427 } else if (s->vm86) {
6428 if (s->iopl != 3) {
6429 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6430 } else {
6431 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6432 set_cc_op(s, CC_OP_EFLAGS);
6433 }
6434 } else {
6435 gen_update_cc_op(s);
6436 gen_jmp_im(pc_start - s->cs_base);
6437 gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
6438 tcg_const_i32(s->pc - s->cs_base));
6439 set_cc_op(s, CC_OP_EFLAGS);
6440 }
6441 gen_eob(s);
6442 break;
6443 case 0xe8: /* call im */
6444 {
6445 if (dflag)
6446 tval = (int32_t)insn_get(env, s, OT_LONG);
6447 else
6448 tval = (int16_t)insn_get(env, s, OT_WORD);
6449 next_eip = s->pc - s->cs_base;
6450 tval += next_eip;
6451 if (s->dflag == 0)
6452 tval &= 0xffff;
6453 else if(!CODE64(s))
6454 tval &= 0xffffffff;
6455 gen_movtl_T0_im(next_eip);
6456 gen_push_T0(s);
6457 gen_jmp(s, tval);
6458 }
6459 break;
6460 case 0x9a: /* lcall im */
6461 {
6462 unsigned int selector, offset;
6463
6464 if (CODE64(s))
6465 goto illegal_op;
6466 ot = dflag ? OT_LONG : OT_WORD;
6467 offset = insn_get(env, s, ot);
6468 selector = insn_get(env, s, OT_WORD);
6469
6470 gen_op_movl_T0_im(selector);
6471 gen_op_movl_T1_imu(offset);
6472 }
6473 goto do_lcall;
6474 case 0xe9: /* jmp im */
6475 if (dflag)
6476 tval = (int32_t)insn_get(env, s, OT_LONG);
6477 else
6478 tval = (int16_t)insn_get(env, s, OT_WORD);
6479 tval += s->pc - s->cs_base;
6480 if (s->dflag == 0)
6481 tval &= 0xffff;
6482 else if(!CODE64(s))
6483 tval &= 0xffffffff;
6484 gen_jmp(s, tval);
6485 break;
6486 case 0xea: /* ljmp im */
6487 {
6488 unsigned int selector, offset;
6489
6490 if (CODE64(s))
6491 goto illegal_op;
6492 ot = dflag ? OT_LONG : OT_WORD;
6493 offset = insn_get(env, s, ot);
6494 selector = insn_get(env, s, OT_WORD);
6495
6496 gen_op_movl_T0_im(selector);
6497 gen_op_movl_T1_imu(offset);
6498 }
6499 goto do_ljmp;
6500 case 0xeb: /* jmp Jb */
6501 tval = (int8_t)insn_get(env, s, OT_BYTE);
6502 tval += s->pc - s->cs_base;
6503 if (s->dflag == 0)
6504 tval &= 0xffff;
6505 gen_jmp(s, tval);
6506 break;
6507 case 0x70 ... 0x7f: /* jcc Jb */
6508 tval = (int8_t)insn_get(env, s, OT_BYTE);
6509 goto do_jcc;
6510 case 0x180 ... 0x18f: /* jcc Jv */
6511 if (dflag) {
6512 tval = (int32_t)insn_get(env, s, OT_LONG);
6513 } else {
6514 tval = (int16_t)insn_get(env, s, OT_WORD);
6515 }
6516 do_jcc:
6517 next_eip = s->pc - s->cs_base;
6518 tval += next_eip;
6519 if (s->dflag == 0)
6520 tval &= 0xffff;
6521 gen_jcc(s, b, tval, next_eip);
6522 break;
6523
6524 case 0x190 ... 0x19f: /* setcc Gv */
6525 modrm = cpu_ldub_code(env, s->pc++);
6526 gen_setcc(s, b);
6527 gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1);
6528 break;
6529 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6530 {
6531 int l1;
6532 TCGv t0;
6533
6534 ot = dflag + OT_WORD;
6535 modrm = cpu_ldub_code(env, s->pc++);
6536 reg = ((modrm >> 3) & 7) | rex_r;
6537 mod = (modrm >> 6) & 3;
6538 t0 = tcg_temp_local_new();
6539 if (mod != 3) {
6540 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6541 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6542 } else {
6543 rm = (modrm & 7) | REX_B(s);
6544 gen_op_mov_v_reg(ot, t0, rm);
6545 }
6546 #ifdef TARGET_X86_64
6547 if (ot == OT_LONG) {
6548 /* XXX: specific Intel behaviour ? */
6549 l1 = gen_new_label();
6550 gen_jcc1(s, b ^ 1, l1);
6551 tcg_gen_mov_tl(cpu_regs[reg], t0);
6552 gen_set_label(l1);
6553 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6554 } else
6555 #endif
6556 {
6557 l1 = gen_new_label();
6558 gen_jcc1(s, b ^ 1, l1);
6559 gen_op_mov_reg_v(ot, reg, t0);
6560 gen_set_label(l1);
6561 }
6562 tcg_temp_free(t0);
6563 }
6564 break;
6565
6566 /************************/
6567 /* flags */
6568 case 0x9c: /* pushf */
6569 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6570 if (s->vm86 && s->iopl != 3) {
6571 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6572 } else {
6573 gen_update_cc_op(s);
6574 gen_helper_read_eflags(cpu_T[0], cpu_env);
6575 gen_push_T0(s);
6576 }
6577 break;
6578 case 0x9d: /* popf */
6579 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6580 if (s->vm86 && s->iopl != 3) {
6581 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6582 } else {
6583 gen_pop_T0(s);
6584 if (s->cpl == 0) {
6585 if (s->dflag) {
6586 gen_helper_write_eflags(cpu_env, cpu_T[0],
6587 tcg_const_i32((TF_MASK | AC_MASK |
6588 ID_MASK | NT_MASK |
6589 IF_MASK |
6590 IOPL_MASK)));
6591 } else {
6592 gen_helper_write_eflags(cpu_env, cpu_T[0],
6593 tcg_const_i32((TF_MASK | AC_MASK |
6594 ID_MASK | NT_MASK |
6595 IF_MASK | IOPL_MASK)
6596 & 0xffff));
6597 }
6598 } else {
6599 if (s->cpl <= s->iopl) {
6600 if (s->dflag) {
6601 gen_helper_write_eflags(cpu_env, cpu_T[0],
6602 tcg_const_i32((TF_MASK |
6603 AC_MASK |
6604 ID_MASK |
6605 NT_MASK |
6606 IF_MASK)));
6607 } else {
6608 gen_helper_write_eflags(cpu_env, cpu_T[0],
6609 tcg_const_i32((TF_MASK |
6610 AC_MASK |
6611 ID_MASK |
6612 NT_MASK |
6613 IF_MASK)
6614 & 0xffff));
6615 }
6616 } else {
6617 if (s->dflag) {
6618 gen_helper_write_eflags(cpu_env, cpu_T[0],
6619 tcg_const_i32((TF_MASK | AC_MASK |
6620 ID_MASK | NT_MASK)));
6621 } else {
6622 gen_helper_write_eflags(cpu_env, cpu_T[0],
6623 tcg_const_i32((TF_MASK | AC_MASK |
6624 ID_MASK | NT_MASK)
6625 & 0xffff));
6626 }
6627 }
6628 }
6629 gen_pop_update(s);
6630 set_cc_op(s, CC_OP_EFLAGS);
6631 /* abort translation because TF/AC flag may change */
6632 gen_jmp_im(s->pc - s->cs_base);
6633 gen_eob(s);
6634 }
6635 break;
6636 case 0x9e: /* sahf */
6637 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6638 goto illegal_op;
6639 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6640 gen_compute_eflags(s);
6641 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6642 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6643 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6644 break;
6645 case 0x9f: /* lahf */
6646 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6647 goto illegal_op;
6648 gen_compute_eflags(s);
6649 /* Note: gen_compute_eflags() only gives the condition codes */
6650 tcg_gen_ori_tl(cpu_T[0], cpu_cc_src, 0x02);
6651 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6652 break;
6653 case 0xf5: /* cmc */
6654 gen_compute_eflags(s);
6655 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6656 break;
6657 case 0xf8: /* clc */
6658 gen_compute_eflags(s);
6659 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6660 break;
6661 case 0xf9: /* stc */
6662 gen_compute_eflags(s);
6663 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6664 break;
6665 case 0xfc: /* cld */
6666 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6667 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6668 break;
6669 case 0xfd: /* std */
6670 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6671 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6672 break;
6673
6674 /************************/
6675 /* bit operations */
6676 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6677 ot = dflag + OT_WORD;
6678 modrm = cpu_ldub_code(env, s->pc++);
6679 op = (modrm >> 3) & 7;
6680 mod = (modrm >> 6) & 3;
6681 rm = (modrm & 7) | REX_B(s);
6682 if (mod != 3) {
6683 s->rip_offset = 1;
6684 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6685 gen_op_ld_T0_A0(ot + s->mem_index);
6686 } else {
6687 gen_op_mov_TN_reg(ot, 0, rm);
6688 }
6689 /* load shift */
6690 val = cpu_ldub_code(env, s->pc++);
6691 gen_op_movl_T1_im(val);
6692 if (op < 4)
6693 goto illegal_op;
6694 op -= 4;
6695 goto bt_op;
6696 case 0x1a3: /* bt Gv, Ev */
6697 op = 0;
6698 goto do_btx;
6699 case 0x1ab: /* bts */
6700 op = 1;
6701 goto do_btx;
6702 case 0x1b3: /* btr */
6703 op = 2;
6704 goto do_btx;
6705 case 0x1bb: /* btc */
6706 op = 3;
6707 do_btx:
6708 ot = dflag + OT_WORD;
6709 modrm = cpu_ldub_code(env, s->pc++);
6710 reg = ((modrm >> 3) & 7) | rex_r;
6711 mod = (modrm >> 6) & 3;
6712 rm = (modrm & 7) | REX_B(s);
6713 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6714 if (mod != 3) {
6715 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6716 /* specific case: we need to add a displacement */
6717 gen_exts(ot, cpu_T[1]);
6718 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6719 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6720 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6721 gen_op_ld_T0_A0(ot + s->mem_index);
6722 } else {
6723 gen_op_mov_TN_reg(ot, 0, rm);
6724 }
6725 bt_op:
6726 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6727 switch(op) {
6728 case 0:
6729 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6730 tcg_gen_movi_tl(cpu_cc_dst, 0);
6731 break;
6732 case 1:
6733 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6734 tcg_gen_movi_tl(cpu_tmp0, 1);
6735 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6736 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6737 break;
6738 case 2:
6739 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6740 tcg_gen_movi_tl(cpu_tmp0, 1);
6741 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6742 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6743 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6744 break;
6745 default:
6746 case 3:
6747 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6748 tcg_gen_movi_tl(cpu_tmp0, 1);
6749 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6750 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6751 break;
6752 }
6753 set_cc_op(s, CC_OP_SARB + ot);
6754 if (op != 0) {
6755 if (mod != 3)
6756 gen_op_st_T0_A0(ot + s->mem_index);
6757 else
6758 gen_op_mov_reg_T0(ot, rm);
6759 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6760 tcg_gen_movi_tl(cpu_cc_dst, 0);
6761 }
6762 break;
6763 case 0x1bc: /* bsf */
6764 case 0x1bd: /* bsr */
6765 {
6766 int label1;
6767 TCGv t0;
6768
6769 ot = dflag + OT_WORD;
6770 modrm = cpu_ldub_code(env, s->pc++);
6771 reg = ((modrm >> 3) & 7) | rex_r;
6772 gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0);
6773 gen_extu(ot, cpu_T[0]);
6774 t0 = tcg_temp_local_new();
6775 tcg_gen_mov_tl(t0, cpu_T[0]);
6776 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6777 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6778 switch(ot) {
6779 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6780 tcg_const_i32(16)); break;
6781 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6782 tcg_const_i32(32)); break;
6783 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6784 tcg_const_i32(64)); break;
6785 }
6786 gen_op_mov_reg_T0(ot, reg);
6787 } else {
6788 label1 = gen_new_label();
6789 tcg_gen_movi_tl(cpu_cc_dst, 0);
6790 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6791 if (b & 1) {
6792 gen_helper_bsr(cpu_T[0], t0);
6793 } else {
6794 gen_helper_bsf(cpu_T[0], t0);
6795 }
6796 gen_op_mov_reg_T0(ot, reg);
6797 tcg_gen_movi_tl(cpu_cc_dst, 1);
6798 gen_set_label(label1);
6799 set_cc_op(s, CC_OP_LOGICB + ot);
6800 }
6801 tcg_temp_free(t0);
6802 }
6803 break;
6804 /************************/
6805 /* bcd */
6806 case 0x27: /* daa */
6807 if (CODE64(s))
6808 goto illegal_op;
6809 gen_update_cc_op(s);
6810 gen_helper_daa(cpu_env);
6811 set_cc_op(s, CC_OP_EFLAGS);
6812 break;
6813 case 0x2f: /* das */
6814 if (CODE64(s))
6815 goto illegal_op;
6816 gen_update_cc_op(s);
6817 gen_helper_das(cpu_env);
6818 set_cc_op(s, CC_OP_EFLAGS);
6819 break;
6820 case 0x37: /* aaa */
6821 if (CODE64(s))
6822 goto illegal_op;
6823 gen_update_cc_op(s);
6824 gen_helper_aaa(cpu_env);
6825 set_cc_op(s, CC_OP_EFLAGS);
6826 break;
6827 case 0x3f: /* aas */
6828 if (CODE64(s))
6829 goto illegal_op;
6830 gen_update_cc_op(s);
6831 gen_helper_aas(cpu_env);
6832 set_cc_op(s, CC_OP_EFLAGS);
6833 break;
6834 case 0xd4: /* aam */
6835 if (CODE64(s))
6836 goto illegal_op;
6837 val = cpu_ldub_code(env, s->pc++);
6838 if (val == 0) {
6839 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6840 } else {
6841 gen_helper_aam(cpu_env, tcg_const_i32(val));
6842 set_cc_op(s, CC_OP_LOGICB);
6843 }
6844 break;
6845 case 0xd5: /* aad */
6846 if (CODE64(s))
6847 goto illegal_op;
6848 val = cpu_ldub_code(env, s->pc++);
6849 gen_helper_aad(cpu_env, tcg_const_i32(val));
6850 set_cc_op(s, CC_OP_LOGICB);
6851 break;
6852 /************************/
6853 /* misc */
6854 case 0x90: /* nop */
6855 /* XXX: correct lock test for all insn */
6856 if (prefixes & PREFIX_LOCK) {
6857 goto illegal_op;
6858 }
6859 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6860 if (REX_B(s)) {
6861 goto do_xchg_reg_eax;
6862 }
6863 if (prefixes & PREFIX_REPZ) {
6864 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6865 }
6866 break;
6867 case 0x9b: /* fwait */
6868 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6869 (HF_MP_MASK | HF_TS_MASK)) {
6870 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6871 } else {
6872 gen_update_cc_op(s);
6873 gen_jmp_im(pc_start - s->cs_base);
6874 gen_helper_fwait(cpu_env);
6875 }
6876 break;
6877 case 0xcc: /* int3 */
6878 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6879 break;
6880 case 0xcd: /* int N */
6881 val = cpu_ldub_code(env, s->pc++);
6882 if (s->vm86 && s->iopl != 3) {
6883 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6884 } else {
6885 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6886 }
6887 break;
6888 case 0xce: /* into */
6889 if (CODE64(s))
6890 goto illegal_op;
6891 gen_update_cc_op(s);
6892 gen_jmp_im(pc_start - s->cs_base);
6893 gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start));
6894 break;
6895 #ifdef WANT_ICEBP
6896 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6897 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6898 #if 1
6899 gen_debug(s, pc_start - s->cs_base);
6900 #else
6901 /* start debug */
6902 tb_flush(env);
6903 qemu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6904 #endif
6905 break;
6906 #endif
6907 case 0xfa: /* cli */
6908 if (!s->vm86) {
6909 if (s->cpl <= s->iopl) {
6910 gen_helper_cli(cpu_env);
6911 } else {
6912 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6913 }
6914 } else {
6915 if (s->iopl == 3) {
6916 gen_helper_cli(cpu_env);
6917 } else {
6918 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6919 }
6920 }
6921 break;
6922 case 0xfb: /* sti */
6923 if (!s->vm86) {
6924 if (s->cpl <= s->iopl) {
6925 gen_sti:
6926 gen_helper_sti(cpu_env);
6927 /* interruptions are enabled only the first insn after sti */
6928 /* If several instructions disable interrupts, only the
6929 _first_ does it */
6930 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6931 gen_helper_set_inhibit_irq(cpu_env);
6932 /* give a chance to handle pending irqs */
6933 gen_jmp_im(s->pc - s->cs_base);
6934 gen_eob(s);
6935 } else {
6936 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6937 }
6938 } else {
6939 if (s->iopl == 3) {
6940 goto gen_sti;
6941 } else {
6942 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6943 }
6944 }
6945 break;
6946 case 0x62: /* bound */
6947 if (CODE64(s))
6948 goto illegal_op;
6949 ot = dflag ? OT_LONG : OT_WORD;
6950 modrm = cpu_ldub_code(env, s->pc++);
6951 reg = (modrm >> 3) & 7;
6952 mod = (modrm >> 6) & 3;
6953 if (mod == 3)
6954 goto illegal_op;
6955 gen_op_mov_TN_reg(ot, 0, reg);
6956 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
6957 gen_jmp_im(pc_start - s->cs_base);
6958 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6959 if (ot == OT_WORD) {
6960 gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
6961 } else {
6962 gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
6963 }
6964 break;
6965 case 0x1c8 ... 0x1cf: /* bswap reg */
6966 reg = (b & 7) | REX_B(s);
6967 #ifdef TARGET_X86_64
6968 if (dflag == 2) {
6969 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6970 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6971 gen_op_mov_reg_T0(OT_QUAD, reg);
6972 } else
6973 #endif
6974 {
6975 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6976 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6977 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6978 gen_op_mov_reg_T0(OT_LONG, reg);
6979 }
6980 break;
6981 case 0xd6: /* salc */
6982 if (CODE64(s))
6983 goto illegal_op;
6984 gen_compute_eflags_c(s, cpu_T[0], false);
6985 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6986 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6987 break;
6988 case 0xe0: /* loopnz */
6989 case 0xe1: /* loopz */
6990 case 0xe2: /* loop */
6991 case 0xe3: /* jecxz */
6992 {
6993 int l1, l2, l3;
6994
6995 tval = (int8_t)insn_get(env, s, OT_BYTE);
6996 next_eip = s->pc - s->cs_base;
6997 tval += next_eip;
6998 if (s->dflag == 0)
6999 tval &= 0xffff;
7000
7001 l1 = gen_new_label();
7002 l2 = gen_new_label();
7003 l3 = gen_new_label();
7004 b &= 3;
7005 switch(b) {
7006 case 0: /* loopnz */
7007 case 1: /* loopz */
7008 gen_op_add_reg_im(s->aflag, R_ECX, -1);
7009 gen_op_jz_ecx(s->aflag, l3);
7010 gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1);
7011 break;
7012 case 2: /* loop */
7013 gen_op_add_reg_im(s->aflag, R_ECX, -1);
7014 gen_op_jnz_ecx(s->aflag, l1);
7015 break;
7016 default:
7017 case 3: /* jcxz */
7018 gen_op_jz_ecx(s->aflag, l1);
7019 break;
7020 }
7021
7022 gen_set_label(l3);
7023 gen_jmp_im(next_eip);
7024 tcg_gen_br(l2);
7025
7026 gen_set_label(l1);
7027 gen_jmp_im(tval);
7028 gen_set_label(l2);
7029 gen_eob(s);
7030 }
7031 break;
7032 case 0x130: /* wrmsr */
7033 case 0x132: /* rdmsr */
7034 if (s->cpl != 0) {
7035 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7036 } else {
7037 gen_update_cc_op(s);
7038 gen_jmp_im(pc_start - s->cs_base);
7039 if (b & 2) {
7040 gen_helper_rdmsr(cpu_env);
7041 } else {
7042 gen_helper_wrmsr(cpu_env);
7043 }
7044 }
7045 break;
7046 case 0x131: /* rdtsc */
7047 gen_update_cc_op(s);
7048 gen_jmp_im(pc_start - s->cs_base);
7049 if (use_icount)
7050 gen_io_start();
7051 gen_helper_rdtsc(cpu_env);
7052 if (use_icount) {
7053 gen_io_end();
7054 gen_jmp(s, s->pc - s->cs_base);
7055 }
7056 break;
7057 case 0x133: /* rdpmc */
7058 gen_update_cc_op(s);
7059 gen_jmp_im(pc_start - s->cs_base);
7060 gen_helper_rdpmc(cpu_env);
7061 break;
7062 case 0x134: /* sysenter */
7063 /* For Intel SYSENTER is valid on 64-bit */
7064 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7065 goto illegal_op;
7066 if (!s->pe) {
7067 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7068 } else {
7069 gen_update_cc_op(s);
7070 gen_jmp_im(pc_start - s->cs_base);
7071 gen_helper_sysenter(cpu_env);
7072 gen_eob(s);
7073 }
7074 break;
7075 case 0x135: /* sysexit */
7076 /* For Intel SYSEXIT is valid on 64-bit */
7077 if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7078 goto illegal_op;
7079 if (!s->pe) {
7080 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7081 } else {
7082 gen_update_cc_op(s);
7083 gen_jmp_im(pc_start - s->cs_base);
7084 gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
7085 gen_eob(s);
7086 }
7087 break;
7088 #ifdef TARGET_X86_64
7089 case 0x105: /* syscall */
7090 /* XXX: is it usable in real mode ? */
7091 gen_update_cc_op(s);
7092 gen_jmp_im(pc_start - s->cs_base);
7093 gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start));
7094 gen_eob(s);
7095 break;
7096 case 0x107: /* sysret */
7097 if (!s->pe) {
7098 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7099 } else {
7100 gen_update_cc_op(s);
7101 gen_jmp_im(pc_start - s->cs_base);
7102 gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
7103 /* condition codes are modified only in long mode */
7104 if (s->lma) {
7105 set_cc_op(s, CC_OP_EFLAGS);
7106 }
7107 gen_eob(s);
7108 }
7109 break;
7110 #endif
7111 case 0x1a2: /* cpuid */
7112 gen_update_cc_op(s);
7113 gen_jmp_im(pc_start - s->cs_base);
7114 gen_helper_cpuid(cpu_env);
7115 break;
7116 case 0xf4: /* hlt */
7117 if (s->cpl != 0) {
7118 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7119 } else {
7120 gen_update_cc_op(s);
7121 gen_jmp_im(pc_start - s->cs_base);
7122 gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));
7123 s->is_jmp = DISAS_TB_JUMP;
7124 }
7125 break;
7126 case 0x100:
7127 modrm = cpu_ldub_code(env, s->pc++);
7128 mod = (modrm >> 6) & 3;
7129 op = (modrm >> 3) & 7;
7130 switch(op) {
7131 case 0: /* sldt */
7132 if (!s->pe || s->vm86)
7133 goto illegal_op;
7134 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7135 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7136 ot = OT_WORD;
7137 if (mod == 3)
7138 ot += s->dflag;
7139 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7140 break;
7141 case 2: /* lldt */
7142 if (!s->pe || s->vm86)
7143 goto illegal_op;
7144 if (s->cpl != 0) {
7145 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7146 } else {
7147 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7148 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7149 gen_jmp_im(pc_start - s->cs_base);
7150 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7151 gen_helper_lldt(cpu_env, cpu_tmp2_i32);
7152 }
7153 break;
7154 case 1: /* str */
7155 if (!s->pe || s->vm86)
7156 goto illegal_op;
7157 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7158 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7159 ot = OT_WORD;
7160 if (mod == 3)
7161 ot += s->dflag;
7162 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
7163 break;
7164 case 3: /* ltr */
7165 if (!s->pe || s->vm86)
7166 goto illegal_op;
7167 if (s->cpl != 0) {
7168 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7169 } else {
7170 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7171 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7172 gen_jmp_im(pc_start - s->cs_base);
7173 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7174 gen_helper_ltr(cpu_env, cpu_tmp2_i32);
7175 }
7176 break;
7177 case 4: /* verr */
7178 case 5: /* verw */
7179 if (!s->pe || s->vm86)
7180 goto illegal_op;
7181 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7182 gen_update_cc_op(s);
7183 if (op == 4) {
7184 gen_helper_verr(cpu_env, cpu_T[0]);
7185 } else {
7186 gen_helper_verw(cpu_env, cpu_T[0]);
7187 }
7188 set_cc_op(s, CC_OP_EFLAGS);
7189 break;
7190 default:
7191 goto illegal_op;
7192 }
7193 break;
7194 case 0x101:
7195 modrm = cpu_ldub_code(env, s->pc++);
7196 mod = (modrm >> 6) & 3;
7197 op = (modrm >> 3) & 7;
7198 rm = modrm & 7;
7199 switch(op) {
7200 case 0: /* sgdt */
7201 if (mod == 3)
7202 goto illegal_op;
7203 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7204 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7205 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7206 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7207 gen_add_A0_im(s, 2);
7208 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7209 if (!s->dflag)
7210 gen_op_andl_T0_im(0xffffff);
7211 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7212 break;
7213 case 1:
7214 if (mod == 3) {
7215 switch (rm) {
7216 case 0: /* monitor */
7217 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7218 s->cpl != 0)
7219 goto illegal_op;
7220 gen_update_cc_op(s);
7221 gen_jmp_im(pc_start - s->cs_base);
7222 #ifdef TARGET_X86_64
7223 if (s->aflag == 2) {
7224 gen_op_movq_A0_reg(R_EAX);
7225 } else
7226 #endif
7227 {
7228 gen_op_movl_A0_reg(R_EAX);
7229 if (s->aflag == 0)
7230 gen_op_andl_A0_ffff();
7231 }
7232 gen_add_A0_ds_seg(s);
7233 gen_helper_monitor(cpu_env, cpu_A0);
7234 break;
7235 case 1: /* mwait */
7236 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7237 s->cpl != 0)
7238 goto illegal_op;
7239 gen_update_cc_op(s);
7240 gen_jmp_im(pc_start - s->cs_base);
7241 gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start));
7242 gen_eob(s);
7243 break;
7244 case 2: /* clac */
7245 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7246 s->cpl != 0) {
7247 goto illegal_op;
7248 }
7249 gen_helper_clac(cpu_env);
7250 gen_jmp_im(s->pc - s->cs_base);
7251 gen_eob(s);
7252 break;
7253 case 3: /* stac */
7254 if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SMAP) ||
7255 s->cpl != 0) {
7256 goto illegal_op;
7257 }
7258 gen_helper_stac(cpu_env);
7259 gen_jmp_im(s->pc - s->cs_base);
7260 gen_eob(s);
7261 break;
7262 default:
7263 goto illegal_op;
7264 }
7265 } else { /* sidt */
7266 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7267 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7268 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7269 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7270 gen_add_A0_im(s, 2);
7271 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7272 if (!s->dflag)
7273 gen_op_andl_T0_im(0xffffff);
7274 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7275 }
7276 break;
7277 case 2: /* lgdt */
7278 case 3: /* lidt */
7279 if (mod == 3) {
7280 gen_update_cc_op(s);
7281 gen_jmp_im(pc_start - s->cs_base);
7282 switch(rm) {
7283 case 0: /* VMRUN */
7284 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7285 goto illegal_op;
7286 if (s->cpl != 0) {
7287 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7288 break;
7289 } else {
7290 gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag),
7291 tcg_const_i32(s->pc - pc_start));
7292 tcg_gen_exit_tb(0);
7293 s->is_jmp = DISAS_TB_JUMP;
7294 }
7295 break;
7296 case 1: /* VMMCALL */
7297 if (!(s->flags & HF_SVME_MASK))
7298 goto illegal_op;
7299 gen_helper_vmmcall(cpu_env);
7300 break;
7301 case 2: /* VMLOAD */
7302 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7303 goto illegal_op;
7304 if (s->cpl != 0) {
7305 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7306 break;
7307 } else {
7308 gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag));
7309 }
7310 break;
7311 case 3: /* VMSAVE */
7312 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7313 goto illegal_op;
7314 if (s->cpl != 0) {
7315 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7316 break;
7317 } else {
7318 gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag));
7319 }
7320 break;
7321 case 4: /* STGI */
7322 if ((!(s->flags & HF_SVME_MASK) &&
7323 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7324 !s->pe)
7325 goto illegal_op;
7326 if (s->cpl != 0) {
7327 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7328 break;
7329 } else {
7330 gen_helper_stgi(cpu_env);
7331 }
7332 break;
7333 case 5: /* CLGI */
7334 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7335 goto illegal_op;
7336 if (s->cpl != 0) {
7337 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7338 break;
7339 } else {
7340 gen_helper_clgi(cpu_env);
7341 }
7342 break;
7343 case 6: /* SKINIT */
7344 if ((!(s->flags & HF_SVME_MASK) &&
7345 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7346 !s->pe)
7347 goto illegal_op;
7348 gen_helper_skinit(cpu_env);
7349 break;
7350 case 7: /* INVLPGA */
7351 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7352 goto illegal_op;
7353 if (s->cpl != 0) {
7354 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7355 break;
7356 } else {
7357 gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag));
7358 }
7359 break;
7360 default:
7361 goto illegal_op;
7362 }
7363 } else if (s->cpl != 0) {
7364 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7365 } else {
7366 gen_svm_check_intercept(s, pc_start,
7367 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7368 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7369 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7370 gen_add_A0_im(s, 2);
7371 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7372 if (!s->dflag)
7373 gen_op_andl_T0_im(0xffffff);
7374 if (op == 2) {
7375 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7376 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7377 } else {
7378 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7379 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7380 }
7381 }
7382 break;
7383 case 4: /* smsw */
7384 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7385 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7386 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7387 #else
7388 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7389 #endif
7390 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1);
7391 break;
7392 case 6: /* lmsw */
7393 if (s->cpl != 0) {
7394 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7395 } else {
7396 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7397 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7398 gen_helper_lmsw(cpu_env, cpu_T[0]);
7399 gen_jmp_im(s->pc - s->cs_base);
7400 gen_eob(s);
7401 }
7402 break;
7403 case 7:
7404 if (mod != 3) { /* invlpg */
7405 if (s->cpl != 0) {
7406 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7407 } else {
7408 gen_update_cc_op(s);
7409 gen_jmp_im(pc_start - s->cs_base);
7410 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7411 gen_helper_invlpg(cpu_env, cpu_A0);
7412 gen_jmp_im(s->pc - s->cs_base);
7413 gen_eob(s);
7414 }
7415 } else {
7416 switch (rm) {
7417 case 0: /* swapgs */
7418 #ifdef TARGET_X86_64
7419 if (CODE64(s)) {
7420 if (s->cpl != 0) {
7421 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7422 } else {
7423 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7424 offsetof(CPUX86State,segs[R_GS].base));
7425 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7426 offsetof(CPUX86State,kernelgsbase));
7427 tcg_gen_st_tl(cpu_T[1], cpu_env,
7428 offsetof(CPUX86State,segs[R_GS].base));
7429 tcg_gen_st_tl(cpu_T[0], cpu_env,
7430 offsetof(CPUX86State,kernelgsbase));
7431 }
7432 } else
7433 #endif
7434 {
7435 goto illegal_op;
7436 }
7437 break;
7438 case 1: /* rdtscp */
7439 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7440 goto illegal_op;
7441 gen_update_cc_op(s);
7442 gen_jmp_im(pc_start - s->cs_base);
7443 if (use_icount)
7444 gen_io_start();
7445 gen_helper_rdtscp(cpu_env);
7446 if (use_icount) {
7447 gen_io_end();
7448 gen_jmp(s, s->pc - s->cs_base);
7449 }
7450 break;
7451 default:
7452 goto illegal_op;
7453 }
7454 }
7455 break;
7456 default:
7457 goto illegal_op;
7458 }
7459 break;
7460 case 0x108: /* invd */
7461 case 0x109: /* wbinvd */
7462 if (s->cpl != 0) {
7463 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7464 } else {
7465 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7466 /* nothing to do */
7467 }
7468 break;
7469 case 0x63: /* arpl or movslS (x86_64) */
7470 #ifdef TARGET_X86_64
7471 if (CODE64(s)) {
7472 int d_ot;
7473 /* d_ot is the size of destination */
7474 d_ot = dflag + OT_WORD;
7475
7476 modrm = cpu_ldub_code(env, s->pc++);
7477 reg = ((modrm >> 3) & 7) | rex_r;
7478 mod = (modrm >> 6) & 3;
7479 rm = (modrm & 7) | REX_B(s);
7480
7481 if (mod == 3) {
7482 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7483 /* sign extend */
7484 if (d_ot == OT_QUAD)
7485 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7486 gen_op_mov_reg_T0(d_ot, reg);
7487 } else {
7488 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7489 if (d_ot == OT_QUAD) {
7490 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7491 } else {
7492 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7493 }
7494 gen_op_mov_reg_T0(d_ot, reg);
7495 }
7496 } else
7497 #endif
7498 {
7499 int label1;
7500 TCGv t0, t1, t2, a0;
7501
7502 if (!s->pe || s->vm86)
7503 goto illegal_op;
7504 t0 = tcg_temp_local_new();
7505 t1 = tcg_temp_local_new();
7506 t2 = tcg_temp_local_new();
7507 ot = OT_WORD;
7508 modrm = cpu_ldub_code(env, s->pc++);
7509 reg = (modrm >> 3) & 7;
7510 mod = (modrm >> 6) & 3;
7511 rm = modrm & 7;
7512 if (mod != 3) {
7513 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7514 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7515 a0 = tcg_temp_local_new();
7516 tcg_gen_mov_tl(a0, cpu_A0);
7517 } else {
7518 gen_op_mov_v_reg(ot, t0, rm);
7519 TCGV_UNUSED(a0);
7520 }
7521 gen_op_mov_v_reg(ot, t1, reg);
7522 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7523 tcg_gen_andi_tl(t1, t1, 3);
7524 tcg_gen_movi_tl(t2, 0);
7525 label1 = gen_new_label();
7526 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7527 tcg_gen_andi_tl(t0, t0, ~3);
7528 tcg_gen_or_tl(t0, t0, t1);
7529 tcg_gen_movi_tl(t2, CC_Z);
7530 gen_set_label(label1);
7531 if (mod != 3) {
7532 gen_op_st_v(ot + s->mem_index, t0, a0);
7533 tcg_temp_free(a0);
7534 } else {
7535 gen_op_mov_reg_v(ot, rm, t0);
7536 }
7537 gen_compute_eflags(s);
7538 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7539 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7540 tcg_temp_free(t0);
7541 tcg_temp_free(t1);
7542 tcg_temp_free(t2);
7543 }
7544 break;
7545 case 0x102: /* lar */
7546 case 0x103: /* lsl */
7547 {
7548 int label1;
7549 TCGv t0;
7550 if (!s->pe || s->vm86)
7551 goto illegal_op;
7552 ot = dflag ? OT_LONG : OT_WORD;
7553 modrm = cpu_ldub_code(env, s->pc++);
7554 reg = ((modrm >> 3) & 7) | rex_r;
7555 gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
7556 t0 = tcg_temp_local_new();
7557 gen_update_cc_op(s);
7558 if (b == 0x102) {
7559 gen_helper_lar(t0, cpu_env, cpu_T[0]);
7560 } else {
7561 gen_helper_lsl(t0, cpu_env, cpu_T[0]);
7562 }
7563 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7564 label1 = gen_new_label();
7565 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7566 gen_op_mov_reg_v(ot, reg, t0);
7567 gen_set_label(label1);
7568 set_cc_op(s, CC_OP_EFLAGS);
7569 tcg_temp_free(t0);
7570 }
7571 break;
7572 case 0x118:
7573 modrm = cpu_ldub_code(env, s->pc++);
7574 mod = (modrm >> 6) & 3;
7575 op = (modrm >> 3) & 7;
7576 switch(op) {
7577 case 0: /* prefetchnta */
7578 case 1: /* prefetchnt0 */
7579 case 2: /* prefetchnt0 */
7580 case 3: /* prefetchnt0 */
7581 if (mod == 3)
7582 goto illegal_op;
7583 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7584 /* nothing more to do */
7585 break;
7586 default: /* nop (multi byte) */
7587 gen_nop_modrm(env, s, modrm);
7588 break;
7589 }
7590 break;
7591 case 0x119 ... 0x11f: /* nop (multi byte) */
7592 modrm = cpu_ldub_code(env, s->pc++);
7593 gen_nop_modrm(env, s, modrm);
7594 break;
7595 case 0x120: /* mov reg, crN */
7596 case 0x122: /* mov crN, reg */
7597 if (s->cpl != 0) {
7598 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7599 } else {
7600 modrm = cpu_ldub_code(env, s->pc++);
7601 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7602 * AMD documentation (24594.pdf) and testing of
7603 * intel 386 and 486 processors all show that the mod bits
7604 * are assumed to be 1's, regardless of actual values.
7605 */
7606 rm = (modrm & 7) | REX_B(s);
7607 reg = ((modrm >> 3) & 7) | rex_r;
7608 if (CODE64(s))
7609 ot = OT_QUAD;
7610 else
7611 ot = OT_LONG;
7612 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7613 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7614 reg = 8;
7615 }
7616 switch(reg) {
7617 case 0:
7618 case 2:
7619 case 3:
7620 case 4:
7621 case 8:
7622 gen_update_cc_op(s);
7623 gen_jmp_im(pc_start - s->cs_base);
7624 if (b & 2) {
7625 gen_op_mov_TN_reg(ot, 0, rm);
7626 gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
7627 cpu_T[0]);
7628 gen_jmp_im(s->pc - s->cs_base);
7629 gen_eob(s);
7630 } else {
7631 gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
7632 gen_op_mov_reg_T0(ot, rm);
7633 }
7634 break;
7635 default:
7636 goto illegal_op;
7637 }
7638 }
7639 break;
7640 case 0x121: /* mov reg, drN */
7641 case 0x123: /* mov drN, reg */
7642 if (s->cpl != 0) {
7643 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7644 } else {
7645 modrm = cpu_ldub_code(env, s->pc++);
7646 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7647 * AMD documentation (24594.pdf) and testing of
7648 * intel 386 and 486 processors all show that the mod bits
7649 * are assumed to be 1's, regardless of actual values.
7650 */
7651 rm = (modrm & 7) | REX_B(s);
7652 reg = ((modrm >> 3) & 7) | rex_r;
7653 if (CODE64(s))
7654 ot = OT_QUAD;
7655 else
7656 ot = OT_LONG;
7657 /* XXX: do it dynamically with CR4.DE bit */
7658 if (reg == 4 || reg == 5 || reg >= 8)
7659 goto illegal_op;
7660 if (b & 2) {
7661 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7662 gen_op_mov_TN_reg(ot, 0, rm);
7663 gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
7664 gen_jmp_im(s->pc - s->cs_base);
7665 gen_eob(s);
7666 } else {
7667 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7668 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7669 gen_op_mov_reg_T0(ot, rm);
7670 }
7671 }
7672 break;
7673 case 0x106: /* clts */
7674 if (s->cpl != 0) {
7675 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7676 } else {
7677 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7678 gen_helper_clts(cpu_env);
7679 /* abort block because static cpu state changed */
7680 gen_jmp_im(s->pc - s->cs_base);
7681 gen_eob(s);
7682 }
7683 break;
7684 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7685 case 0x1c3: /* MOVNTI reg, mem */
7686 if (!(s->cpuid_features & CPUID_SSE2))
7687 goto illegal_op;
7688 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7689 modrm = cpu_ldub_code(env, s->pc++);
7690 mod = (modrm >> 6) & 3;
7691 if (mod == 3)
7692 goto illegal_op;
7693 reg = ((modrm >> 3) & 7) | rex_r;
7694 /* generate a generic store */
7695 gen_ldst_modrm(env, s, modrm, ot, reg, 1);
7696 break;
7697 case 0x1ae:
7698 modrm = cpu_ldub_code(env, s->pc++);
7699 mod = (modrm >> 6) & 3;
7700 op = (modrm >> 3) & 7;
7701 switch(op) {
7702 case 0: /* fxsave */
7703 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7704 (s->prefix & PREFIX_LOCK))
7705 goto illegal_op;
7706 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7707 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7708 break;
7709 }
7710 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7711 gen_update_cc_op(s);
7712 gen_jmp_im(pc_start - s->cs_base);
7713 gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
7714 break;
7715 case 1: /* fxrstor */
7716 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7717 (s->prefix & PREFIX_LOCK))
7718 goto illegal_op;
7719 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7720 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7721 break;
7722 }
7723 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7724 gen_update_cc_op(s);
7725 gen_jmp_im(pc_start - s->cs_base);
7726 gen_helper_fxrstor(cpu_env, cpu_A0,
7727 tcg_const_i32((s->dflag == 2)));
7728 break;
7729 case 2: /* ldmxcsr */
7730 case 3: /* stmxcsr */
7731 if (s->flags & HF_TS_MASK) {
7732 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7733 break;
7734 }
7735 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7736 mod == 3)
7737 goto illegal_op;
7738 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7739 if (op == 2) {
7740 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7741 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7742 gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
7743 } else {
7744 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7745 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7746 }
7747 break;
7748 case 5: /* lfence */
7749 case 6: /* mfence */
7750 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7751 goto illegal_op;
7752 break;
7753 case 7: /* sfence / clflush */
7754 if ((modrm & 0xc7) == 0xc0) {
7755 /* sfence */
7756 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7757 if (!(s->cpuid_features & CPUID_SSE))
7758 goto illegal_op;
7759 } else {
7760 /* clflush */
7761 if (!(s->cpuid_features & CPUID_CLFLUSH))
7762 goto illegal_op;
7763 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7764 }
7765 break;
7766 default:
7767 goto illegal_op;
7768 }
7769 break;
7770 case 0x10d: /* 3DNow! prefetch(w) */
7771 modrm = cpu_ldub_code(env, s->pc++);
7772 mod = (modrm >> 6) & 3;
7773 if (mod == 3)
7774 goto illegal_op;
7775 gen_lea_modrm(env, s, modrm, &reg_addr, &offset_addr);
7776 /* ignore for now */
7777 break;
7778 case 0x1aa: /* rsm */
7779 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7780 if (!(s->flags & HF_SMM_MASK))
7781 goto illegal_op;
7782 gen_update_cc_op(s);
7783 gen_jmp_im(s->pc - s->cs_base);
7784 gen_helper_rsm(cpu_env);
7785 gen_eob(s);
7786 break;
7787 case 0x1b8: /* SSE4.2 popcnt */
7788 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7789 PREFIX_REPZ)
7790 goto illegal_op;
7791 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7792 goto illegal_op;
7793
7794 modrm = cpu_ldub_code(env, s->pc++);
7795 reg = ((modrm >> 3) & 7) | rex_r;
7796
7797 if (s->prefix & PREFIX_DATA)
7798 ot = OT_WORD;
7799 else if (s->dflag != 2)
7800 ot = OT_LONG;
7801 else
7802 ot = OT_QUAD;
7803
7804 gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
7805 gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
7806 gen_op_mov_reg_T0(ot, reg);
7807
7808 set_cc_op(s, CC_OP_EFLAGS);
7809 break;
7810 case 0x10e ... 0x10f:
7811 /* 3DNow! instructions, ignore prefixes */
7812 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7813 case 0x110 ... 0x117:
7814 case 0x128 ... 0x12f:
7815 case 0x138 ... 0x13a:
7816 case 0x150 ... 0x179:
7817 case 0x17c ... 0x17f:
7818 case 0x1c2:
7819 case 0x1c4 ... 0x1c6:
7820 case 0x1d0 ... 0x1fe:
7821 gen_sse(env, s, b, pc_start, rex_r);
7822 break;
7823 default:
7824 goto illegal_op;
7825 }
7826 /* lock generation */
7827 if (s->prefix & PREFIX_LOCK)
7828 gen_helper_unlock();
7829 return s->pc;
7830 illegal_op:
7831 if (s->prefix & PREFIX_LOCK)
7832 gen_helper_unlock();
7833 /* XXX: ensure that no lock was generated */
7834 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7835 return s->pc;
7836 }
7837
7838 void optimize_flags_init(void)
7839 {
7840 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7841 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7842 offsetof(CPUX86State, cc_op), "cc_op");
7843 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7844 "cc_src");
7845 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7846 "cc_dst");
7847
7848 #ifdef TARGET_X86_64
7849 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7850 offsetof(CPUX86State, regs[R_EAX]), "rax");
7851 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7852 offsetof(CPUX86State, regs[R_ECX]), "rcx");
7853 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7854 offsetof(CPUX86State, regs[R_EDX]), "rdx");
7855 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7856 offsetof(CPUX86State, regs[R_EBX]), "rbx");
7857 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7858 offsetof(CPUX86State, regs[R_ESP]), "rsp");
7859 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7860 offsetof(CPUX86State, regs[R_EBP]), "rbp");
7861 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7862 offsetof(CPUX86State, regs[R_ESI]), "rsi");
7863 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7864 offsetof(CPUX86State, regs[R_EDI]), "rdi");
7865 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7866 offsetof(CPUX86State, regs[8]), "r8");
7867 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7868 offsetof(CPUX86State, regs[9]), "r9");
7869 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7870 offsetof(CPUX86State, regs[10]), "r10");
7871 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7872 offsetof(CPUX86State, regs[11]), "r11");
7873 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7874 offsetof(CPUX86State, regs[12]), "r12");
7875 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7876 offsetof(CPUX86State, regs[13]), "r13");
7877 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7878 offsetof(CPUX86State, regs[14]), "r14");
7879 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7880 offsetof(CPUX86State, regs[15]), "r15");
7881 #else
7882 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7883 offsetof(CPUX86State, regs[R_EAX]), "eax");
7884 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7885 offsetof(CPUX86State, regs[R_ECX]), "ecx");
7886 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7887 offsetof(CPUX86State, regs[R_EDX]), "edx");
7888 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7889 offsetof(CPUX86State, regs[R_EBX]), "ebx");
7890 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7891 offsetof(CPUX86State, regs[R_ESP]), "esp");
7892 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7893 offsetof(CPUX86State, regs[R_EBP]), "ebp");
7894 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7895 offsetof(CPUX86State, regs[R_ESI]), "esi");
7896 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7897 offsetof(CPUX86State, regs[R_EDI]), "edi");
7898 #endif
7899
7900 /* register helpers */
7901 #define GEN_HELPER 2
7902 #include "helper.h"
7903 }
7904
7905 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7906 basic block 'tb'. If search_pc is TRUE, also generate PC
7907 information for each intermediate instruction. */
7908 static inline void gen_intermediate_code_internal(CPUX86State *env,
7909 TranslationBlock *tb,
7910 int search_pc)
7911 {
7912 DisasContext dc1, *dc = &dc1;
7913 target_ulong pc_ptr;
7914 uint16_t *gen_opc_end;
7915 CPUBreakpoint *bp;
7916 int j, lj;
7917 uint64_t flags;
7918 target_ulong pc_start;
7919 target_ulong cs_base;
7920 int num_insns;
7921 int max_insns;
7922
7923 /* generate intermediate code */
7924 pc_start = tb->pc;
7925 cs_base = tb->cs_base;
7926 flags = tb->flags;
7927
7928 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7929 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7930 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7931 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7932 dc->f_st = 0;
7933 dc->vm86 = (flags >> VM_SHIFT) & 1;
7934 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7935 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7936 dc->tf = (flags >> TF_SHIFT) & 1;
7937 dc->singlestep_enabled = env->singlestep_enabled;
7938 dc->cc_op = CC_OP_DYNAMIC;
7939 dc->cc_op_dirty = false;
7940 dc->cs_base = cs_base;
7941 dc->tb = tb;
7942 dc->popl_esp_hack = 0;
7943 /* select memory access functions */
7944 dc->mem_index = 0;
7945 if (flags & HF_SOFTMMU_MASK) {
7946 dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
7947 }
7948 dc->cpuid_features = env->cpuid_features;
7949 dc->cpuid_ext_features = env->cpuid_ext_features;
7950 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7951 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7952 dc->cpuid_7_0_ebx_features = env->cpuid_7_0_ebx_features;
7953 #ifdef TARGET_X86_64
7954 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7955 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7956 #endif
7957 dc->flags = flags;
7958 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7959 (flags & HF_INHIBIT_IRQ_MASK)
7960 #ifndef CONFIG_SOFTMMU
7961 || (flags & HF_SOFTMMU_MASK)
7962 #endif
7963 );
7964 #if 0
7965 /* check addseg logic */
7966 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7967 printf("ERROR addseg\n");
7968 #endif
7969
7970 cpu_T[0] = tcg_temp_new();
7971 cpu_T[1] = tcg_temp_new();
7972 cpu_A0 = tcg_temp_new();
7973 cpu_T3 = tcg_temp_new();
7974
7975 cpu_tmp0 = tcg_temp_new();
7976 cpu_tmp1_i64 = tcg_temp_new_i64();
7977 cpu_tmp2_i32 = tcg_temp_new_i32();
7978 cpu_tmp3_i32 = tcg_temp_new_i32();
7979 cpu_tmp4 = tcg_temp_new();
7980 cpu_tmp5 = tcg_temp_new();
7981 cpu_ptr0 = tcg_temp_new_ptr();
7982 cpu_ptr1 = tcg_temp_new_ptr();
7983
7984 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
7985
7986 dc->is_jmp = DISAS_NEXT;
7987 pc_ptr = pc_start;
7988 lj = -1;
7989 num_insns = 0;
7990 max_insns = tb->cflags & CF_COUNT_MASK;
7991 if (max_insns == 0)
7992 max_insns = CF_COUNT_MASK;
7993
7994 gen_icount_start();
7995 for(;;) {
7996 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7997 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7998 if (bp->pc == pc_ptr &&
7999 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
8000 gen_debug(dc, pc_ptr - dc->cs_base);
8001 break;
8002 }
8003 }
8004 }
8005 if (search_pc) {
8006 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
8007 if (lj < j) {
8008 lj++;
8009 while (lj < j)
8010 tcg_ctx.gen_opc_instr_start[lj++] = 0;
8011 }
8012 tcg_ctx.gen_opc_pc[lj] = pc_ptr;
8013 gen_opc_cc_op[lj] = dc->cc_op;
8014 tcg_ctx.gen_opc_instr_start[lj] = 1;
8015 tcg_ctx.gen_opc_icount[lj] = num_insns;
8016 }
8017 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
8018 gen_io_start();
8019
8020 pc_ptr = disas_insn(env, dc, pc_ptr);
8021 num_insns++;
8022 /* stop translation if indicated */
8023 if (dc->is_jmp)
8024 break;
8025 /* if single step mode, we generate only one instruction and
8026 generate an exception */
8027 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8028 the flag and abort the translation to give the irqs a
8029 change to be happen */
8030 if (dc->tf || dc->singlestep_enabled ||
8031 (flags & HF_INHIBIT_IRQ_MASK)) {
8032 gen_jmp_im(pc_ptr - dc->cs_base);
8033 gen_eob(dc);
8034 break;
8035 }
8036 /* if too long translation, stop generation too */
8037 if (tcg_ctx.gen_opc_ptr >= gen_opc_end ||
8038 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
8039 num_insns >= max_insns) {
8040 gen_jmp_im(pc_ptr - dc->cs_base);
8041 gen_eob(dc);
8042 break;
8043 }
8044 if (singlestep) {
8045 gen_jmp_im(pc_ptr - dc->cs_base);
8046 gen_eob(dc);
8047 break;
8048 }
8049 }
8050 if (tb->cflags & CF_LAST_IO)
8051 gen_io_end();
8052 gen_icount_end(tb, num_insns);
8053 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
8054 /* we don't forget to fill the last values */
8055 if (search_pc) {
8056 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
8057 lj++;
8058 while (lj <= j)
8059 tcg_ctx.gen_opc_instr_start[lj++] = 0;
8060 }
8061
8062 #ifdef DEBUG_DISAS
8063 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8064 int disas_flags;
8065 qemu_log("----------------\n");
8066 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8067 #ifdef TARGET_X86_64
8068 if (dc->code64)
8069 disas_flags = 2;
8070 else
8071 #endif
8072 disas_flags = !dc->code32;
8073 log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags);
8074 qemu_log("\n");
8075 }
8076 #endif
8077
8078 if (!search_pc) {
8079 tb->size = pc_ptr - pc_start;
8080 tb->icount = num_insns;
8081 }
8082 }
8083
8084 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
8085 {
8086 gen_intermediate_code_internal(env, tb, 0);
8087 }
8088
8089 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
8090 {
8091 gen_intermediate_code_internal(env, tb, 1);
8092 }
8093
8094 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
8095 {
8096 int cc_op;
8097 #ifdef DEBUG_DISAS
8098 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
8099 int i;
8100 qemu_log("RESTORE:\n");
8101 for(i = 0;i <= pc_pos; i++) {
8102 if (tcg_ctx.gen_opc_instr_start[i]) {
8103 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i,
8104 tcg_ctx.gen_opc_pc[i]);
8105 }
8106 }
8107 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
8108 pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base,
8109 (uint32_t)tb->cs_base);
8110 }
8111 #endif
8112 env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base;
8113 cc_op = gen_opc_cc_op[pc_pos];
8114 if (cc_op != CC_OP_DYNAMIC)
8115 env->cc_op = cc_op;
8116 }