4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 /* XXX: move that elsewhere */
33 static uint16_t *gen_opc_ptr
;
34 static uint32_t *gen_opparam_ptr
;
36 #define PREFIX_REPZ 0x01
37 #define PREFIX_REPNZ 0x02
38 #define PREFIX_LOCK 0x04
39 #define PREFIX_DATA 0x08
40 #define PREFIX_ADR 0x10
42 typedef struct DisasContext
{
43 /* current insn context */
44 int override
; /* -1 if no override */
47 uint8_t *pc
; /* pc = eip + cs_base */
48 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
49 static state change (stop translation) */
50 /* current block context */
51 uint8_t *cs_base
; /* base of CS segment */
52 int pe
; /* protected mode */
53 int code32
; /* 32 bit code segment */
54 int ss32
; /* 32 bit stack segment */
55 int cc_op
; /* current CC operation */
56 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
57 int f_st
; /* currently unused */
58 int vm86
; /* vm86 mode */
61 int tf
; /* TF cpu flag */
62 int singlestep_enabled
; /* "hardware" single step enabled */
63 int jmp_opt
; /* use direct block chaining for direct jumps */
64 int mem_index
; /* select memory access functions */
65 int flags
; /* all execution flags */
66 struct TranslationBlock
*tb
;
67 int popl_esp_hack
; /* for correct popl with esp base handling */
70 static void gen_eob(DisasContext
*s
);
71 static void gen_jmp(DisasContext
*s
, unsigned int eip
);
73 /* i386 arith/logic operations */
93 OP_SHL1
, /* undocumented */
98 #define DEF(s, n, copy_size) INDEX_op_ ## s,
115 /* I386 int registers */
116 OR_EAX
, /* MUST be even numbered */
124 OR_TMP0
, /* temporary operand register */
126 OR_A0
, /* temporary register used when doing address evaluation */
127 OR_ZERO
, /* fixed zero register */
131 static GenOpFunc
*gen_op_mov_reg_T0
[3][8] = {
164 static GenOpFunc
*gen_op_mov_reg_T1
[3][8] = {
197 static GenOpFunc
*gen_op_mov_reg_A0
[2][8] = {
220 static GenOpFunc
*gen_op_mov_TN_reg
[3][2][8] =
290 static GenOpFunc
*gen_op_movl_A0_reg
[8] = {
301 static GenOpFunc
*gen_op_addl_A0_reg_sN
[4][8] = {
313 gen_op_addl_A0_EAX_s1
,
314 gen_op_addl_A0_ECX_s1
,
315 gen_op_addl_A0_EDX_s1
,
316 gen_op_addl_A0_EBX_s1
,
317 gen_op_addl_A0_ESP_s1
,
318 gen_op_addl_A0_EBP_s1
,
319 gen_op_addl_A0_ESI_s1
,
320 gen_op_addl_A0_EDI_s1
,
323 gen_op_addl_A0_EAX_s2
,
324 gen_op_addl_A0_ECX_s2
,
325 gen_op_addl_A0_EDX_s2
,
326 gen_op_addl_A0_EBX_s2
,
327 gen_op_addl_A0_ESP_s2
,
328 gen_op_addl_A0_EBP_s2
,
329 gen_op_addl_A0_ESI_s2
,
330 gen_op_addl_A0_EDI_s2
,
333 gen_op_addl_A0_EAX_s3
,
334 gen_op_addl_A0_ECX_s3
,
335 gen_op_addl_A0_EDX_s3
,
336 gen_op_addl_A0_EBX_s3
,
337 gen_op_addl_A0_ESP_s3
,
338 gen_op_addl_A0_EBP_s3
,
339 gen_op_addl_A0_ESI_s3
,
340 gen_op_addl_A0_EDI_s3
,
344 static GenOpFunc
*gen_op_cmov_reg_T1_T0
[2][8] = {
346 gen_op_cmovw_EAX_T1_T0
,
347 gen_op_cmovw_ECX_T1_T0
,
348 gen_op_cmovw_EDX_T1_T0
,
349 gen_op_cmovw_EBX_T1_T0
,
350 gen_op_cmovw_ESP_T1_T0
,
351 gen_op_cmovw_EBP_T1_T0
,
352 gen_op_cmovw_ESI_T1_T0
,
353 gen_op_cmovw_EDI_T1_T0
,
356 gen_op_cmovl_EAX_T1_T0
,
357 gen_op_cmovl_ECX_T1_T0
,
358 gen_op_cmovl_EDX_T1_T0
,
359 gen_op_cmovl_EBX_T1_T0
,
360 gen_op_cmovl_ESP_T1_T0
,
361 gen_op_cmovl_EBP_T1_T0
,
362 gen_op_cmovl_ESI_T1_T0
,
363 gen_op_cmovl_EDI_T1_T0
,
367 static GenOpFunc
*gen_op_arith_T0_T1_cc
[8] = {
378 #define DEF_ARITHC(SUFFIX)\
380 gen_op_adcb ## SUFFIX ## _T0_T1_cc,\
381 gen_op_sbbb ## SUFFIX ## _T0_T1_cc,\
384 gen_op_adcw ## SUFFIX ## _T0_T1_cc,\
385 gen_op_sbbw ## SUFFIX ## _T0_T1_cc,\
388 gen_op_adcl ## SUFFIX ## _T0_T1_cc,\
389 gen_op_sbbl ## SUFFIX ## _T0_T1_cc,\
392 static GenOpFunc
*gen_op_arithc_T0_T1_cc
[3][2] = {
396 static GenOpFunc
*gen_op_arithc_mem_T0_T1_cc
[9][2] = {
398 #ifndef CONFIG_USER_ONLY
404 static const int cc_op_arithb
[8] = {
415 #define DEF_CMPXCHG(SUFFIX)\
416 gen_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc,\
417 gen_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc,\
418 gen_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc,
421 static GenOpFunc
*gen_op_cmpxchg_T0_T1_EAX_cc
[3] = {
425 static GenOpFunc
*gen_op_cmpxchg_mem_T0_T1_EAX_cc
[9] = {
427 #ifndef CONFIG_USER_ONLY
433 #define DEF_SHIFT(SUFFIX)\
435 gen_op_rolb ## SUFFIX ## _T0_T1_cc,\
436 gen_op_rorb ## SUFFIX ## _T0_T1_cc,\
437 gen_op_rclb ## SUFFIX ## _T0_T1_cc,\
438 gen_op_rcrb ## SUFFIX ## _T0_T1_cc,\
439 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
440 gen_op_shrb ## SUFFIX ## _T0_T1_cc,\
441 gen_op_shlb ## SUFFIX ## _T0_T1_cc,\
442 gen_op_sarb ## SUFFIX ## _T0_T1_cc,\
445 gen_op_rolw ## SUFFIX ## _T0_T1_cc,\
446 gen_op_rorw ## SUFFIX ## _T0_T1_cc,\
447 gen_op_rclw ## SUFFIX ## _T0_T1_cc,\
448 gen_op_rcrw ## SUFFIX ## _T0_T1_cc,\
449 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
450 gen_op_shrw ## SUFFIX ## _T0_T1_cc,\
451 gen_op_shlw ## SUFFIX ## _T0_T1_cc,\
452 gen_op_sarw ## SUFFIX ## _T0_T1_cc,\
455 gen_op_roll ## SUFFIX ## _T0_T1_cc,\
456 gen_op_rorl ## SUFFIX ## _T0_T1_cc,\
457 gen_op_rcll ## SUFFIX ## _T0_T1_cc,\
458 gen_op_rcrl ## SUFFIX ## _T0_T1_cc,\
459 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
460 gen_op_shrl ## SUFFIX ## _T0_T1_cc,\
461 gen_op_shll ## SUFFIX ## _T0_T1_cc,\
462 gen_op_sarl ## SUFFIX ## _T0_T1_cc,\
465 static GenOpFunc
*gen_op_shift_T0_T1_cc
[3][8] = {
469 static GenOpFunc
*gen_op_shift_mem_T0_T1_cc
[9][8] = {
471 #ifndef CONFIG_USER_ONLY
477 #define DEF_SHIFTD(SUFFIX, op)\
483 gen_op_shldw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
484 gen_op_shrdw ## SUFFIX ## _T0_T1_ ## op ## _cc,\
487 gen_op_shldl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
488 gen_op_shrdl ## SUFFIX ## _T0_T1_ ## op ## _cc,\
492 static GenOpFunc1
*gen_op_shiftd_T0_T1_im_cc
[3][2] = {
496 static GenOpFunc
*gen_op_shiftd_T0_T1_ECX_cc
[3][2] = {
500 static GenOpFunc1
*gen_op_shiftd_mem_T0_T1_im_cc
[9][2] = {
502 #ifndef CONFIG_USER_ONLY
503 DEF_SHIFTD(_kernel
, im
)
504 DEF_SHIFTD(_user
, im
)
508 static GenOpFunc
*gen_op_shiftd_mem_T0_T1_ECX_cc
[9][2] = {
509 DEF_SHIFTD(_raw
, ECX
)
510 #ifndef CONFIG_USER_ONLY
511 DEF_SHIFTD(_kernel
, ECX
)
512 DEF_SHIFTD(_user
, ECX
)
516 static GenOpFunc
*gen_op_btx_T0_T1_cc
[2][4] = {
519 gen_op_btsw_T0_T1_cc
,
520 gen_op_btrw_T0_T1_cc
,
521 gen_op_btcw_T0_T1_cc
,
525 gen_op_btsl_T0_T1_cc
,
526 gen_op_btrl_T0_T1_cc
,
527 gen_op_btcl_T0_T1_cc
,
531 static GenOpFunc
*gen_op_bsx_T0_cc
[2][2] = {
542 static GenOpFunc
*gen_op_lds_T0_A0
[3 * 3] = {
543 gen_op_ldsb_raw_T0_A0
,
544 gen_op_ldsw_raw_T0_A0
,
546 #ifndef CONFIG_USER_ONLY
547 gen_op_ldsb_kernel_T0_A0
,
548 gen_op_ldsw_kernel_T0_A0
,
551 gen_op_ldsb_user_T0_A0
,
552 gen_op_ldsw_user_T0_A0
,
557 static GenOpFunc
*gen_op_ldu_T0_A0
[3 * 3] = {
558 gen_op_ldub_raw_T0_A0
,
559 gen_op_lduw_raw_T0_A0
,
562 #ifndef CONFIG_USER_ONLY
563 gen_op_ldub_kernel_T0_A0
,
564 gen_op_lduw_kernel_T0_A0
,
567 gen_op_ldub_user_T0_A0
,
568 gen_op_lduw_user_T0_A0
,
573 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
574 static GenOpFunc
*gen_op_ld_T0_A0
[3 * 3] = {
575 gen_op_ldub_raw_T0_A0
,
576 gen_op_lduw_raw_T0_A0
,
577 gen_op_ldl_raw_T0_A0
,
579 #ifndef CONFIG_USER_ONLY
580 gen_op_ldub_kernel_T0_A0
,
581 gen_op_lduw_kernel_T0_A0
,
582 gen_op_ldl_kernel_T0_A0
,
584 gen_op_ldub_user_T0_A0
,
585 gen_op_lduw_user_T0_A0
,
586 gen_op_ldl_user_T0_A0
,
590 static GenOpFunc
*gen_op_ld_T1_A0
[3 * 3] = {
591 gen_op_ldub_raw_T1_A0
,
592 gen_op_lduw_raw_T1_A0
,
593 gen_op_ldl_raw_T1_A0
,
595 #ifndef CONFIG_USER_ONLY
596 gen_op_ldub_kernel_T1_A0
,
597 gen_op_lduw_kernel_T1_A0
,
598 gen_op_ldl_kernel_T1_A0
,
600 gen_op_ldub_user_T1_A0
,
601 gen_op_lduw_user_T1_A0
,
602 gen_op_ldl_user_T1_A0
,
606 static GenOpFunc
*gen_op_st_T0_A0
[3 * 3] = {
607 gen_op_stb_raw_T0_A0
,
608 gen_op_stw_raw_T0_A0
,
609 gen_op_stl_raw_T0_A0
,
611 #ifndef CONFIG_USER_ONLY
612 gen_op_stb_kernel_T0_A0
,
613 gen_op_stw_kernel_T0_A0
,
614 gen_op_stl_kernel_T0_A0
,
616 gen_op_stb_user_T0_A0
,
617 gen_op_stw_user_T0_A0
,
618 gen_op_stl_user_T0_A0
,
622 static GenOpFunc
*gen_op_st_T1_A0
[3 * 3] = {
624 gen_op_stw_raw_T1_A0
,
625 gen_op_stl_raw_T1_A0
,
627 #ifndef CONFIG_USER_ONLY
629 gen_op_stw_kernel_T1_A0
,
630 gen_op_stl_kernel_T1_A0
,
633 gen_op_stw_user_T1_A0
,
634 gen_op_stl_user_T1_A0
,
638 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
642 override
= s
->override
;
645 if (s
->addseg
&& override
< 0)
648 gen_op_movl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
649 gen_op_addl_A0_reg_sN
[0][R_ESI
]();
651 gen_op_movl_A0_reg
[R_ESI
]();
654 /* 16 address, always override */
657 gen_op_movl_A0_reg
[R_ESI
]();
658 gen_op_andl_A0_ffff();
659 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
663 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
667 gen_op_movl_A0_seg(offsetof(CPUX86State
,segs
[R_ES
].base
));
668 gen_op_addl_A0_reg_sN
[0][R_EDI
]();
670 gen_op_movl_A0_reg
[R_EDI
]();
673 gen_op_movl_A0_reg
[R_EDI
]();
674 gen_op_andl_A0_ffff();
675 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[R_ES
].base
));
679 static GenOpFunc
*gen_op_movl_T0_Dshift
[3] = {
680 gen_op_movl_T0_Dshiftb
,
681 gen_op_movl_T0_Dshiftw
,
682 gen_op_movl_T0_Dshiftl
,
685 static GenOpFunc2
*gen_op_jz_ecx
[2] = {
690 static GenOpFunc1
*gen_op_jz_ecx_im
[2] = {
695 static GenOpFunc
*gen_op_dec_ECX
[2] = {
700 #ifdef USE_DIRECT_JUMP
701 typedef GenOpFunc GenOpFuncTB2
;
702 #define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot]()
704 typedef GenOpFunc1 GenOpFuncTB2
;
705 #define gen_op_string_jnz_sub(nz, ot, tb) gen_op_string_jnz_sub2[nz][ot](tb)
708 static GenOpFuncTB2
*gen_op_string_jnz_sub2
[2][3] = {
710 gen_op_string_jnz_subb
,
711 gen_op_string_jnz_subw
,
712 gen_op_string_jnz_subl
,
715 gen_op_string_jz_subb
,
716 gen_op_string_jz_subw
,
717 gen_op_string_jz_subl
,
721 static GenOpFunc1
*gen_op_string_jnz_sub_im
[2][3] = {
723 gen_op_string_jnz_subb_im
,
724 gen_op_string_jnz_subw_im
,
725 gen_op_string_jnz_subl_im
,
728 gen_op_string_jz_subb_im
,
729 gen_op_string_jz_subw_im
,
730 gen_op_string_jz_subl_im
,
734 static GenOpFunc
*gen_op_in_DX_T0
[3] = {
740 static GenOpFunc
*gen_op_out_DX_T0
[3] = {
746 static GenOpFunc
*gen_op_in
[3] = {
752 static GenOpFunc
*gen_op_out
[3] = {
758 static GenOpFunc
*gen_check_io_T0
[3] = {
764 static GenOpFunc
*gen_check_io_DX
[3] = {
770 static void gen_check_io(DisasContext
*s
, int ot
, int use_dx
, int cur_eip
)
772 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
773 if (s
->cc_op
!= CC_OP_DYNAMIC
)
774 gen_op_set_cc_op(s
->cc_op
);
775 gen_op_jmp_im(cur_eip
);
777 gen_check_io_DX
[ot
]();
779 gen_check_io_T0
[ot
]();
783 static inline void gen_movs(DisasContext
*s
, int ot
)
785 gen_string_movl_A0_ESI(s
);
786 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
787 gen_string_movl_A0_EDI(s
);
788 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
789 gen_op_movl_T0_Dshift
[ot
]();
791 gen_op_addl_ESI_T0();
792 gen_op_addl_EDI_T0();
794 gen_op_addw_ESI_T0();
795 gen_op_addw_EDI_T0();
799 static inline void gen_update_cc_op(DisasContext
*s
)
801 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
802 gen_op_set_cc_op(s
->cc_op
);
803 s
->cc_op
= CC_OP_DYNAMIC
;
807 static inline void gen_jz_ecx_string(DisasContext
*s
, unsigned int next_eip
)
810 gen_op_jz_ecx
[s
->aflag
]((long)s
->tb
, next_eip
);
812 /* XXX: does not work with gdbstub "ice" single step - not a
814 gen_op_jz_ecx_im
[s
->aflag
](next_eip
);
818 static inline void gen_stos(DisasContext
*s
, int ot
)
820 gen_op_mov_TN_reg
[OT_LONG
][0][R_EAX
]();
821 gen_string_movl_A0_EDI(s
);
822 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
823 gen_op_movl_T0_Dshift
[ot
]();
825 gen_op_addl_EDI_T0();
827 gen_op_addw_EDI_T0();
831 static inline void gen_lods(DisasContext
*s
, int ot
)
833 gen_string_movl_A0_ESI(s
);
834 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
835 gen_op_mov_reg_T0
[ot
][R_EAX
]();
836 gen_op_movl_T0_Dshift
[ot
]();
838 gen_op_addl_ESI_T0();
840 gen_op_addw_ESI_T0();
844 static inline void gen_scas(DisasContext
*s
, int ot
)
846 gen_op_mov_TN_reg
[OT_LONG
][0][R_EAX
]();
847 gen_string_movl_A0_EDI(s
);
848 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
849 gen_op_cmpl_T0_T1_cc();
850 gen_op_movl_T0_Dshift
[ot
]();
852 gen_op_addl_EDI_T0();
854 gen_op_addw_EDI_T0();
858 static inline void gen_cmps(DisasContext
*s
, int ot
)
860 gen_string_movl_A0_ESI(s
);
861 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
862 gen_string_movl_A0_EDI(s
);
863 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
864 gen_op_cmpl_T0_T1_cc();
865 gen_op_movl_T0_Dshift
[ot
]();
867 gen_op_addl_ESI_T0();
868 gen_op_addl_EDI_T0();
870 gen_op_addw_ESI_T0();
871 gen_op_addw_EDI_T0();
875 static inline void gen_ins(DisasContext
*s
, int ot
)
877 gen_op_in_DX_T0
[ot
]();
878 gen_string_movl_A0_EDI(s
);
879 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
880 gen_op_movl_T0_Dshift
[ot
]();
882 gen_op_addl_EDI_T0();
884 gen_op_addw_EDI_T0();
888 static inline void gen_outs(DisasContext
*s
, int ot
)
890 gen_string_movl_A0_ESI(s
);
891 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
892 gen_op_out_DX_T0
[ot
]();
893 gen_op_movl_T0_Dshift
[ot
]();
895 gen_op_addl_ESI_T0();
897 gen_op_addw_ESI_T0();
901 /* same method as Valgrind : we generate jumps to current or next
903 #define GEN_REPZ(op) \
904 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
905 unsigned int cur_eip, unsigned int next_eip) \
907 gen_update_cc_op(s); \
908 gen_jz_ecx_string(s, next_eip); \
910 gen_op_dec_ECX[s->aflag](); \
911 /* a loop would cause two single step exceptions if ECX = 1 \
912 before rep string_insn */ \
914 gen_op_jz_ecx_im[s->aflag](next_eip); \
915 gen_jmp(s, cur_eip); \
918 #define GEN_REPZ2(op) \
919 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
920 unsigned int cur_eip, \
921 unsigned int next_eip, \
924 gen_update_cc_op(s); \
925 gen_jz_ecx_string(s, next_eip); \
927 gen_op_dec_ECX[s->aflag](); \
928 gen_op_set_cc_op(CC_OP_SUBB + ot); \
930 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
932 gen_op_string_jnz_sub(nz, ot, (long)s->tb); \
934 gen_op_jz_ecx_im[s->aflag](next_eip); \
935 gen_jmp(s, cur_eip); \
957 static GenOpFunc3
*gen_jcc_sub
[3][8] = {
989 static GenOpFunc2
*gen_op_loop
[2][4] = {
1004 static GenOpFunc
*gen_setcc_slow
[8] = {
1015 static GenOpFunc
*gen_setcc_sub
[3][8] = {
1018 gen_op_setb_T0_subb
,
1019 gen_op_setz_T0_subb
,
1020 gen_op_setbe_T0_subb
,
1021 gen_op_sets_T0_subb
,
1023 gen_op_setl_T0_subb
,
1024 gen_op_setle_T0_subb
,
1028 gen_op_setb_T0_subw
,
1029 gen_op_setz_T0_subw
,
1030 gen_op_setbe_T0_subw
,
1031 gen_op_sets_T0_subw
,
1033 gen_op_setl_T0_subw
,
1034 gen_op_setle_T0_subw
,
1038 gen_op_setb_T0_subl
,
1039 gen_op_setz_T0_subl
,
1040 gen_op_setbe_T0_subl
,
1041 gen_op_sets_T0_subl
,
1043 gen_op_setl_T0_subl
,
1044 gen_op_setle_T0_subl
,
1048 static GenOpFunc
*gen_op_fp_arith_ST0_FT0
[8] = {
1049 gen_op_fadd_ST0_FT0
,
1050 gen_op_fmul_ST0_FT0
,
1051 gen_op_fcom_ST0_FT0
,
1052 gen_op_fcom_ST0_FT0
,
1053 gen_op_fsub_ST0_FT0
,
1054 gen_op_fsubr_ST0_FT0
,
1055 gen_op_fdiv_ST0_FT0
,
1056 gen_op_fdivr_ST0_FT0
,
1059 /* NOTE the exception in "r" op ordering */
1060 static GenOpFunc1
*gen_op_fp_arith_STN_ST0
[8] = {
1061 gen_op_fadd_STN_ST0
,
1062 gen_op_fmul_STN_ST0
,
1065 gen_op_fsubr_STN_ST0
,
1066 gen_op_fsub_STN_ST0
,
1067 gen_op_fdivr_STN_ST0
,
1068 gen_op_fdiv_STN_ST0
,
1071 /* if d == OR_TMP0, it means memory operand (address in A0) */
1072 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1074 GenOpFunc
*gen_update_cc
;
1077 gen_op_mov_TN_reg
[ot
][0][d
]();
1079 gen_op_ld_T0_A0
[ot
+ s1
->mem_index
]();
1084 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1085 gen_op_set_cc_op(s1
->cc_op
);
1087 gen_op_arithc_T0_T1_cc
[ot
][op
- OP_ADCL
]();
1088 gen_op_mov_reg_T0
[ot
][d
]();
1090 gen_op_arithc_mem_T0_T1_cc
[ot
+ s1
->mem_index
][op
- OP_ADCL
]();
1092 s1
->cc_op
= CC_OP_DYNAMIC
;
1095 gen_op_addl_T0_T1();
1096 s1
->cc_op
= CC_OP_ADDB
+ ot
;
1097 gen_update_cc
= gen_op_update2_cc
;
1100 gen_op_subl_T0_T1();
1101 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1102 gen_update_cc
= gen_op_update2_cc
;
1108 gen_op_arith_T0_T1_cc
[op
]();
1109 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1110 gen_update_cc
= gen_op_update1_cc
;
1113 gen_op_cmpl_T0_T1_cc();
1114 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1115 gen_update_cc
= NULL
;
1118 if (op
!= OP_CMPL
) {
1120 gen_op_mov_reg_T0
[ot
][d
]();
1122 gen_op_st_T0_A0
[ot
+ s1
->mem_index
]();
1124 /* the flags update must happen after the memory write (precise
1125 exception support) */
1131 /* if d == OR_TMP0, it means memory operand (address in A0) */
1132 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1135 gen_op_mov_TN_reg
[ot
][0][d
]();
1137 gen_op_ld_T0_A0
[ot
+ s1
->mem_index
]();
1138 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1139 gen_op_set_cc_op(s1
->cc_op
);
1142 s1
->cc_op
= CC_OP_INCB
+ ot
;
1145 s1
->cc_op
= CC_OP_DECB
+ ot
;
1148 gen_op_mov_reg_T0
[ot
][d
]();
1150 gen_op_st_T0_A0
[ot
+ s1
->mem_index
]();
1151 gen_op_update_inc_cc();
1154 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1157 gen_op_mov_TN_reg
[ot
][0][d
]();
1159 gen_op_ld_T0_A0
[ot
+ s1
->mem_index
]();
1161 gen_op_mov_TN_reg
[ot
][1][s
]();
1162 /* for zero counts, flags are not updated, so must do it dynamically */
1163 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1164 gen_op_set_cc_op(s1
->cc_op
);
1167 gen_op_shift_T0_T1_cc
[ot
][op
]();
1169 gen_op_shift_mem_T0_T1_cc
[ot
+ s1
->mem_index
][op
]();
1171 gen_op_mov_reg_T0
[ot
][d
]();
1172 s1
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1175 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1177 /* currently not optimized */
1178 gen_op_movl_T1_im(c
);
1179 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1182 static void gen_lea_modrm(DisasContext
*s
, int modrm
, int *reg_ptr
, int *offset_ptr
)
1189 int mod
, rm
, code
, override
, must_add_seg
;
1191 override
= s
->override
;
1192 must_add_seg
= s
->addseg
;
1195 mod
= (modrm
>> 6) & 3;
1207 code
= ldub_code(s
->pc
++);
1208 scale
= (code
>> 6) & 3;
1209 index
= (code
>> 3) & 7;
1217 disp
= ldl_code(s
->pc
);
1224 disp
= (int8_t)ldub_code(s
->pc
++);
1228 disp
= ldl_code(s
->pc
);
1234 /* for correct popl handling with esp */
1235 if (base
== 4 && s
->popl_esp_hack
)
1236 disp
+= s
->popl_esp_hack
;
1237 gen_op_movl_A0_reg
[base
]();
1239 gen_op_addl_A0_im(disp
);
1241 gen_op_movl_A0_im(disp
);
1243 /* XXX: index == 4 is always invalid */
1244 if (havesib
&& (index
!= 4 || scale
!= 0)) {
1245 gen_op_addl_A0_reg_sN
[scale
][index
]();
1249 if (base
== R_EBP
|| base
== R_ESP
)
1254 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
1260 disp
= lduw_code(s
->pc
);
1262 gen_op_movl_A0_im(disp
);
1263 rm
= 0; /* avoid SS override */
1270 disp
= (int8_t)ldub_code(s
->pc
++);
1274 disp
= lduw_code(s
->pc
);
1280 gen_op_movl_A0_reg
[R_EBX
]();
1281 gen_op_addl_A0_reg_sN
[0][R_ESI
]();
1284 gen_op_movl_A0_reg
[R_EBX
]();
1285 gen_op_addl_A0_reg_sN
[0][R_EDI
]();
1288 gen_op_movl_A0_reg
[R_EBP
]();
1289 gen_op_addl_A0_reg_sN
[0][R_ESI
]();
1292 gen_op_movl_A0_reg
[R_EBP
]();
1293 gen_op_addl_A0_reg_sN
[0][R_EDI
]();
1296 gen_op_movl_A0_reg
[R_ESI
]();
1299 gen_op_movl_A0_reg
[R_EDI
]();
1302 gen_op_movl_A0_reg
[R_EBP
]();
1306 gen_op_movl_A0_reg
[R_EBX
]();
1310 gen_op_addl_A0_im(disp
);
1311 gen_op_andl_A0_ffff();
1315 if (rm
== 2 || rm
== 3 || rm
== 6)
1320 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
1330 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1332 static void gen_ldst_modrm(DisasContext
*s
, int modrm
, int ot
, int reg
, int is_store
)
1334 int mod
, rm
, opreg
, disp
;
1336 mod
= (modrm
>> 6) & 3;
1341 gen_op_mov_TN_reg
[ot
][0][reg
]();
1342 gen_op_mov_reg_T0
[ot
][rm
]();
1344 gen_op_mov_TN_reg
[ot
][0][rm
]();
1346 gen_op_mov_reg_T0
[ot
][reg
]();
1349 gen_lea_modrm(s
, modrm
, &opreg
, &disp
);
1352 gen_op_mov_TN_reg
[ot
][0][reg
]();
1353 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
1355 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
1357 gen_op_mov_reg_T0
[ot
][reg
]();
1362 static inline uint32_t insn_get(DisasContext
*s
, int ot
)
1368 ret
= ldub_code(s
->pc
);
1372 ret
= lduw_code(s
->pc
);
1377 ret
= ldl_code(s
->pc
);
1384 static inline void gen_jcc(DisasContext
*s
, int b
, int val
, int next_eip
)
1386 TranslationBlock
*tb
;
1391 jcc_op
= (b
>> 1) & 7;
1395 /* we optimize the cmp/jcc case */
1399 func
= gen_jcc_sub
[s
->cc_op
- CC_OP_SUBB
][jcc_op
];
1402 /* some jumps are easy to compute */
1429 func
= gen_jcc_sub
[(s
->cc_op
- CC_OP_ADDB
) % 3][jcc_op
];
1432 func
= gen_jcc_sub
[(s
->cc_op
- CC_OP_ADDB
) % 3][jcc_op
];
1444 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1445 gen_op_set_cc_op(s
->cc_op
);
1448 gen_setcc_slow
[jcc_op
]();
1454 func((long)tb
, val
, next_eip
);
1456 func((long)tb
, next_eip
, val
);
1460 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
1461 gen_op_set_cc_op(s
->cc_op
);
1462 s
->cc_op
= CC_OP_DYNAMIC
;
1464 gen_setcc_slow
[jcc_op
]();
1466 gen_op_jcc_im(val
, next_eip
);
1468 gen_op_jcc_im(next_eip
, val
);
1474 static void gen_setcc(DisasContext
*s
, int b
)
1480 jcc_op
= (b
>> 1) & 7;
1482 /* we optimize the cmp/jcc case */
1486 func
= gen_setcc_sub
[s
->cc_op
- CC_OP_SUBB
][jcc_op
];
1491 /* some jumps are easy to compute */
1509 func
= gen_setcc_sub
[(s
->cc_op
- CC_OP_ADDB
) % 3][jcc_op
];
1512 func
= gen_setcc_sub
[(s
->cc_op
- CC_OP_ADDB
) % 3][jcc_op
];
1520 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1521 gen_op_set_cc_op(s
->cc_op
);
1522 func
= gen_setcc_slow
[jcc_op
];
1531 /* move T0 to seg_reg and compute if the CPU state may change. Never
1532 call this function with seg_reg == R_CS */
1533 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, unsigned int cur_eip
)
1535 if (s
->pe
&& !s
->vm86
) {
1536 /* XXX: optimize by finding processor state dynamically */
1537 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1538 gen_op_set_cc_op(s
->cc_op
);
1539 gen_op_jmp_im(cur_eip
);
1540 gen_op_movl_seg_T0(seg_reg
);
1542 gen_op_movl_seg_T0_vm(offsetof(CPUX86State
,segs
[seg_reg
]));
1544 /* abort translation because the register may have a non zero base
1545 or because ss32 may change. For R_SS, translation must always
1546 stop as a special handling must be done to disable hardware
1547 interrupts for the next instruction */
1548 if (seg_reg
== R_SS
|| (!s
->addseg
&& seg_reg
< R_FS
))
1552 static inline void gen_stack_update(DisasContext
*s
, int addend
)
1556 gen_op_addl_ESP_2();
1557 else if (addend
== 4)
1558 gen_op_addl_ESP_4();
1560 gen_op_addl_ESP_im(addend
);
1563 gen_op_addw_ESP_2();
1564 else if (addend
== 4)
1565 gen_op_addw_ESP_4();
1567 gen_op_addw_ESP_im(addend
);
1571 /* generate a push. It depends on ss32, addseg and dflag */
1572 static void gen_push_T0(DisasContext
*s
)
1574 gen_op_movl_A0_reg
[R_ESP
]();
1581 gen_op_movl_T1_A0();
1582 gen_op_addl_A0_SS();
1585 gen_op_andl_A0_ffff();
1586 gen_op_movl_T1_A0();
1587 gen_op_addl_A0_SS();
1589 gen_op_st_T0_A0
[s
->dflag
+ 1 + s
->mem_index
]();
1590 if (s
->ss32
&& !s
->addseg
)
1591 gen_op_movl_ESP_A0();
1593 gen_op_mov_reg_T1
[s
->ss32
+ 1][R_ESP
]();
1596 /* generate a push. It depends on ss32, addseg and dflag */
1597 /* slower version for T1, only used for call Ev */
1598 static void gen_push_T1(DisasContext
*s
)
1600 gen_op_movl_A0_reg
[R_ESP
]();
1607 gen_op_addl_A0_SS();
1610 gen_op_andl_A0_ffff();
1611 gen_op_addl_A0_SS();
1613 gen_op_st_T1_A0
[s
->dflag
+ 1 + s
->mem_index
]();
1615 if (s
->ss32
&& !s
->addseg
)
1616 gen_op_movl_ESP_A0();
1618 gen_stack_update(s
, (-2) << s
->dflag
);
1621 /* two step pop is necessary for precise exceptions */
1622 static void gen_pop_T0(DisasContext
*s
)
1624 gen_op_movl_A0_reg
[R_ESP
]();
1627 gen_op_addl_A0_SS();
1629 gen_op_andl_A0_ffff();
1630 gen_op_addl_A0_SS();
1632 gen_op_ld_T0_A0
[s
->dflag
+ 1 + s
->mem_index
]();
1635 static void gen_pop_update(DisasContext
*s
)
1637 gen_stack_update(s
, 2 << s
->dflag
);
1640 static void gen_stack_A0(DisasContext
*s
)
1642 gen_op_movl_A0_ESP();
1644 gen_op_andl_A0_ffff();
1645 gen_op_movl_T1_A0();
1647 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[R_SS
].base
));
1650 /* NOTE: wrap around in 16 bit not fully handled */
1651 static void gen_pusha(DisasContext
*s
)
1654 gen_op_movl_A0_ESP();
1655 gen_op_addl_A0_im(-16 << s
->dflag
);
1657 gen_op_andl_A0_ffff();
1658 gen_op_movl_T1_A0();
1660 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[R_SS
].base
));
1661 for(i
= 0;i
< 8; i
++) {
1662 gen_op_mov_TN_reg
[OT_LONG
][0][7 - i
]();
1663 gen_op_st_T0_A0
[OT_WORD
+ s
->dflag
+ s
->mem_index
]();
1664 gen_op_addl_A0_im(2 << s
->dflag
);
1666 gen_op_mov_reg_T1
[OT_WORD
+ s
->dflag
][R_ESP
]();
1669 /* NOTE: wrap around in 16 bit not fully handled */
1670 static void gen_popa(DisasContext
*s
)
1673 gen_op_movl_A0_ESP();
1675 gen_op_andl_A0_ffff();
1676 gen_op_movl_T1_A0();
1677 gen_op_addl_T1_im(16 << s
->dflag
);
1679 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[R_SS
].base
));
1680 for(i
= 0;i
< 8; i
++) {
1681 /* ESP is not reloaded */
1683 gen_op_ld_T0_A0
[OT_WORD
+ s
->dflag
+ s
->mem_index
]();
1684 gen_op_mov_reg_T0
[OT_WORD
+ s
->dflag
][7 - i
]();
1686 gen_op_addl_A0_im(2 << s
->dflag
);
1688 gen_op_mov_reg_T1
[OT_WORD
+ s
->dflag
][R_ESP
]();
1691 /* NOTE: wrap around in 16 bit not fully handled */
1692 /* XXX: check this */
1693 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
1695 int ot
, level1
, addend
, opsize
;
1697 ot
= s
->dflag
+ OT_WORD
;
1700 opsize
= 2 << s
->dflag
;
1702 gen_op_movl_A0_ESP();
1703 gen_op_addl_A0_im(-opsize
);
1705 gen_op_andl_A0_ffff();
1706 gen_op_movl_T1_A0();
1708 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[R_SS
].base
));
1710 gen_op_mov_TN_reg
[OT_LONG
][0][R_EBP
]();
1711 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
1714 gen_op_addl_A0_im(-opsize
);
1715 gen_op_addl_T0_im(-opsize
);
1716 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
1718 gen_op_addl_A0_im(-opsize
);
1719 gen_op_st_T1_A0
[ot
+ s
->mem_index
]();
1721 gen_op_mov_reg_T1
[ot
][R_EBP
]();
1722 addend
= -esp_addend
;
1724 addend
-= opsize
* (level1
+ 1);
1725 gen_op_addl_T1_im(addend
);
1726 gen_op_mov_reg_T1
[ot
][R_ESP
]();
1729 static void gen_exception(DisasContext
*s
, int trapno
, unsigned int cur_eip
)
1731 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1732 gen_op_set_cc_op(s
->cc_op
);
1733 gen_op_jmp_im(cur_eip
);
1734 gen_op_raise_exception(trapno
);
1738 /* an interrupt is different from an exception because of the
1739 priviledge checks */
1740 static void gen_interrupt(DisasContext
*s
, int intno
,
1741 unsigned int cur_eip
, unsigned int next_eip
)
1743 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1744 gen_op_set_cc_op(s
->cc_op
);
1745 gen_op_jmp_im(cur_eip
);
1746 gen_op_raise_interrupt(intno
, next_eip
);
1750 static void gen_debug(DisasContext
*s
, unsigned int cur_eip
)
1752 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1753 gen_op_set_cc_op(s
->cc_op
);
1754 gen_op_jmp_im(cur_eip
);
1759 /* generate a generic end of block. Trace exception is also generated
1761 static void gen_eob(DisasContext
*s
)
1763 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1764 gen_op_set_cc_op(s
->cc_op
);
1765 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
1766 gen_op_reset_inhibit_irq();
1768 if (s
->singlestep_enabled
) {
1771 gen_op_raise_exception(EXCP01_SSTP
);
1779 /* generate a jump to eip. No segment change must happen before as a
1780 direct call to the next block may occur */
1781 static void gen_jmp(DisasContext
*s
, unsigned int eip
)
1783 TranslationBlock
*tb
= s
->tb
;
1786 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1787 gen_op_set_cc_op(s
->cc_op
);
1788 gen_op_jmp((long)tb
, eip
);
1796 /* convert one instruction. s->is_jmp is set if the translation must
1797 be stopped. Return the next pc value */
1798 static uint8_t *disas_insn(DisasContext
*s
, uint8_t *pc_start
)
1800 int b
, prefixes
, aflag
, dflag
;
1802 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
1803 unsigned int next_eip
;
1811 b
= ldub_code(s
->pc
);
1813 /* check prefixes */
1816 prefixes
|= PREFIX_REPZ
;
1819 prefixes
|= PREFIX_REPNZ
;
1822 prefixes
|= PREFIX_LOCK
;
1843 prefixes
|= PREFIX_DATA
;
1846 prefixes
|= PREFIX_ADR
;
1850 if (prefixes
& PREFIX_DATA
)
1852 if (prefixes
& PREFIX_ADR
)
1855 s
->prefix
= prefixes
;
1859 /* lock generation */
1860 if (prefixes
& PREFIX_LOCK
)
1863 /* now check op code */
1867 /**************************/
1868 /* extended op code */
1869 b
= ldub_code(s
->pc
++) | 0x100;
1872 /**************************/
1890 ot
= dflag
? OT_LONG
: OT_WORD
;
1893 case 0: /* OP Ev, Gv */
1894 modrm
= ldub_code(s
->pc
++);
1895 reg
= ((modrm
>> 3) & 7);
1896 mod
= (modrm
>> 6) & 3;
1899 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
1901 } else if (op
== OP_XORL
&& rm
== reg
) {
1903 /* xor reg, reg optimisation */
1905 s
->cc_op
= CC_OP_LOGICB
+ ot
;
1906 gen_op_mov_reg_T0
[ot
][reg
]();
1907 gen_op_update1_cc();
1912 gen_op_mov_TN_reg
[ot
][1][reg
]();
1913 gen_op(s
, op
, ot
, opreg
);
1915 case 1: /* OP Gv, Ev */
1916 modrm
= ldub_code(s
->pc
++);
1917 mod
= (modrm
>> 6) & 3;
1918 reg
= ((modrm
>> 3) & 7);
1921 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
1922 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
1923 } else if (op
== OP_XORL
&& rm
== reg
) {
1926 gen_op_mov_TN_reg
[ot
][1][rm
]();
1928 gen_op(s
, op
, ot
, reg
);
1930 case 2: /* OP A, Iv */
1931 val
= insn_get(s
, ot
);
1932 gen_op_movl_T1_im(val
);
1933 gen_op(s
, op
, ot
, OR_EAX
);
1939 case 0x80: /* GRP1 */
1949 ot
= dflag
? OT_LONG
: OT_WORD
;
1951 modrm
= ldub_code(s
->pc
++);
1952 mod
= (modrm
>> 6) & 3;
1954 op
= (modrm
>> 3) & 7;
1957 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
1960 opreg
= rm
+ OR_EAX
;
1968 val
= insn_get(s
, ot
);
1971 val
= (int8_t)insn_get(s
, OT_BYTE
);
1974 gen_op_movl_T1_im(val
);
1975 gen_op(s
, op
, ot
, opreg
);
1979 /**************************/
1980 /* inc, dec, and other misc arith */
1981 case 0x40 ... 0x47: /* inc Gv */
1982 ot
= dflag
? OT_LONG
: OT_WORD
;
1983 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
1985 case 0x48 ... 0x4f: /* dec Gv */
1986 ot
= dflag
? OT_LONG
: OT_WORD
;
1987 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
1989 case 0xf6: /* GRP3 */
1994 ot
= dflag
? OT_LONG
: OT_WORD
;
1996 modrm
= ldub_code(s
->pc
++);
1997 mod
= (modrm
>> 6) & 3;
1999 op
= (modrm
>> 3) & 7;
2001 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2002 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
2004 gen_op_mov_TN_reg
[ot
][0][rm
]();
2009 val
= insn_get(s
, ot
);
2010 gen_op_movl_T1_im(val
);
2011 gen_op_testl_T0_T1_cc();
2012 s
->cc_op
= CC_OP_LOGICB
+ ot
;
2017 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2019 gen_op_mov_reg_T0
[ot
][rm
]();
2025 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2027 gen_op_mov_reg_T0
[ot
][rm
]();
2029 gen_op_update_neg_cc();
2030 s
->cc_op
= CC_OP_SUBB
+ ot
;
2035 gen_op_mulb_AL_T0();
2036 s
->cc_op
= CC_OP_MULB
;
2039 gen_op_mulw_AX_T0();
2040 s
->cc_op
= CC_OP_MULW
;
2044 gen_op_mull_EAX_T0();
2045 s
->cc_op
= CC_OP_MULL
;
2052 gen_op_imulb_AL_T0();
2053 s
->cc_op
= CC_OP_MULB
;
2056 gen_op_imulw_AX_T0();
2057 s
->cc_op
= CC_OP_MULW
;
2061 gen_op_imull_EAX_T0();
2062 s
->cc_op
= CC_OP_MULL
;
2069 gen_op_divb_AL_T0(pc_start
- s
->cs_base
);
2072 gen_op_divw_AX_T0(pc_start
- s
->cs_base
);
2076 gen_op_divl_EAX_T0(pc_start
- s
->cs_base
);
2083 gen_op_idivb_AL_T0(pc_start
- s
->cs_base
);
2086 gen_op_idivw_AX_T0(pc_start
- s
->cs_base
);
2090 gen_op_idivl_EAX_T0(pc_start
- s
->cs_base
);
2099 case 0xfe: /* GRP4 */
2100 case 0xff: /* GRP5 */
2104 ot
= dflag
? OT_LONG
: OT_WORD
;
2106 modrm
= ldub_code(s
->pc
++);
2107 mod
= (modrm
>> 6) & 3;
2109 op
= (modrm
>> 3) & 7;
2110 if (op
>= 2 && b
== 0xfe) {
2114 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2115 if (op
>= 2 && op
!= 3 && op
!= 5)
2116 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
2118 gen_op_mov_TN_reg
[ot
][0][rm
]();
2122 case 0: /* inc Ev */
2127 gen_inc(s
, ot
, opreg
, 1);
2129 case 1: /* dec Ev */
2134 gen_inc(s
, ot
, opreg
, -1);
2136 case 2: /* call Ev */
2137 /* XXX: optimize if memory (no 'and' is necessary) */
2139 gen_op_andl_T0_ffff();
2140 next_eip
= s
->pc
- s
->cs_base
;
2141 gen_op_movl_T1_im(next_eip
);
2146 case 3: /* lcall Ev */
2147 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
2148 gen_op_addl_A0_im(1 << (ot
- OT_WORD
+ 1));
2149 gen_op_ldu_T0_A0
[OT_WORD
+ s
->mem_index
]();
2151 if (s
->pe
&& !s
->vm86
) {
2152 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2153 gen_op_set_cc_op(s
->cc_op
);
2154 gen_op_jmp_im(pc_start
- s
->cs_base
);
2155 gen_op_lcall_protected_T0_T1(dflag
, s
->pc
- s
->cs_base
);
2157 gen_op_lcall_real_T0_T1(dflag
, s
->pc
- s
->cs_base
);
2161 case 4: /* jmp Ev */
2163 gen_op_andl_T0_ffff();
2167 case 5: /* ljmp Ev */
2168 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
2169 gen_op_addl_A0_im(1 << (ot
- OT_WORD
+ 1));
2170 gen_op_ldu_T0_A0
[OT_WORD
+ s
->mem_index
]();
2172 if (s
->pe
&& !s
->vm86
) {
2173 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2174 gen_op_set_cc_op(s
->cc_op
);
2175 gen_op_jmp_im(pc_start
- s
->cs_base
);
2176 gen_op_ljmp_protected_T0_T1(s
->pc
- s
->cs_base
);
2178 gen_op_movl_seg_T0_vm(offsetof(CPUX86State
,segs
[R_CS
]));
2179 gen_op_movl_T0_T1();
2184 case 6: /* push Ev */
2192 case 0x84: /* test Ev, Gv */
2197 ot
= dflag
? OT_LONG
: OT_WORD
;
2199 modrm
= ldub_code(s
->pc
++);
2200 mod
= (modrm
>> 6) & 3;
2202 reg
= (modrm
>> 3) & 7;
2204 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
2205 gen_op_mov_TN_reg
[ot
][1][reg
+ OR_EAX
]();
2206 gen_op_testl_T0_T1_cc();
2207 s
->cc_op
= CC_OP_LOGICB
+ ot
;
2210 case 0xa8: /* test eAX, Iv */
2215 ot
= dflag
? OT_LONG
: OT_WORD
;
2216 val
= insn_get(s
, ot
);
2218 gen_op_mov_TN_reg
[ot
][0][OR_EAX
]();
2219 gen_op_movl_T1_im(val
);
2220 gen_op_testl_T0_T1_cc();
2221 s
->cc_op
= CC_OP_LOGICB
+ ot
;
2224 case 0x98: /* CWDE/CBW */
2226 gen_op_movswl_EAX_AX();
2228 gen_op_movsbw_AX_AL();
2230 case 0x99: /* CDQ/CWD */
2232 gen_op_movslq_EDX_EAX();
2234 gen_op_movswl_DX_AX();
2236 case 0x1af: /* imul Gv, Ev */
2237 case 0x69: /* imul Gv, Ev, I */
2239 ot
= dflag
? OT_LONG
: OT_WORD
;
2240 modrm
= ldub_code(s
->pc
++);
2241 reg
= ((modrm
>> 3) & 7) + OR_EAX
;
2242 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
2244 val
= insn_get(s
, ot
);
2245 gen_op_movl_T1_im(val
);
2246 } else if (b
== 0x6b) {
2247 val
= (int8_t)insn_get(s
, OT_BYTE
);
2248 gen_op_movl_T1_im(val
);
2250 gen_op_mov_TN_reg
[ot
][1][reg
]();
2253 if (ot
== OT_LONG
) {
2254 gen_op_imull_T0_T1();
2256 gen_op_imulw_T0_T1();
2258 gen_op_mov_reg_T0
[ot
][reg
]();
2259 s
->cc_op
= CC_OP_MULB
+ ot
;
2262 case 0x1c1: /* xadd Ev, Gv */
2266 ot
= dflag
? OT_LONG
: OT_WORD
;
2267 modrm
= ldub_code(s
->pc
++);
2268 reg
= (modrm
>> 3) & 7;
2269 mod
= (modrm
>> 6) & 3;
2272 gen_op_mov_TN_reg
[ot
][0][reg
]();
2273 gen_op_mov_TN_reg
[ot
][1][rm
]();
2274 gen_op_addl_T0_T1();
2275 gen_op_mov_reg_T1
[ot
][reg
]();
2276 gen_op_mov_reg_T0
[ot
][rm
]();
2278 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2279 gen_op_mov_TN_reg
[ot
][0][reg
]();
2280 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
2281 gen_op_addl_T0_T1();
2282 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2283 gen_op_mov_reg_T1
[ot
][reg
]();
2285 gen_op_update2_cc();
2286 s
->cc_op
= CC_OP_ADDB
+ ot
;
2289 case 0x1b1: /* cmpxchg Ev, Gv */
2293 ot
= dflag
? OT_LONG
: OT_WORD
;
2294 modrm
= ldub_code(s
->pc
++);
2295 reg
= (modrm
>> 3) & 7;
2296 mod
= (modrm
>> 6) & 3;
2297 gen_op_mov_TN_reg
[ot
][1][reg
]();
2300 gen_op_mov_TN_reg
[ot
][0][rm
]();
2301 gen_op_cmpxchg_T0_T1_EAX_cc
[ot
]();
2302 gen_op_mov_reg_T0
[ot
][rm
]();
2304 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2305 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
2306 gen_op_cmpxchg_mem_T0_T1_EAX_cc
[ot
+ s
->mem_index
]();
2308 s
->cc_op
= CC_OP_SUBB
+ ot
;
2310 case 0x1c7: /* cmpxchg8b */
2311 modrm
= ldub_code(s
->pc
++);
2312 mod
= (modrm
>> 6) & 3;
2315 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2316 gen_op_set_cc_op(s
->cc_op
);
2317 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2319 s
->cc_op
= CC_OP_EFLAGS
;
2322 /**************************/
2324 case 0x50 ... 0x57: /* push */
2325 gen_op_mov_TN_reg
[OT_LONG
][0][b
& 7]();
2328 case 0x58 ... 0x5f: /* pop */
2329 ot
= dflag
? OT_LONG
: OT_WORD
;
2331 /* NOTE: order is important for pop %sp */
2333 gen_op_mov_reg_T0
[ot
][b
& 7]();
2335 case 0x60: /* pusha */
2338 case 0x61: /* popa */
2341 case 0x68: /* push Iv */
2343 ot
= dflag
? OT_LONG
: OT_WORD
;
2345 val
= insn_get(s
, ot
);
2347 val
= (int8_t)insn_get(s
, OT_BYTE
);
2348 gen_op_movl_T0_im(val
);
2351 case 0x8f: /* pop Ev */
2352 ot
= dflag
? OT_LONG
: OT_WORD
;
2353 modrm
= ldub_code(s
->pc
++);
2354 mod
= (modrm
>> 6) & 3;
2357 /* NOTE: order is important for pop %sp */
2360 gen_op_mov_reg_T0
[ot
][rm
]();
2362 /* NOTE: order is important too for MMU exceptions */
2363 s
->popl_esp_hack
= 2 << dflag
;
2364 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
2365 s
->popl_esp_hack
= 0;
2369 case 0xc8: /* enter */
2372 val
= lduw_code(s
->pc
);
2374 level
= ldub_code(s
->pc
++);
2375 gen_enter(s
, val
, level
);
2378 case 0xc9: /* leave */
2379 /* XXX: exception not precise (ESP is updated before potential exception) */
2381 gen_op_mov_TN_reg
[OT_LONG
][0][R_EBP
]();
2382 gen_op_mov_reg_T0
[OT_LONG
][R_ESP
]();
2384 gen_op_mov_TN_reg
[OT_WORD
][0][R_EBP
]();
2385 gen_op_mov_reg_T0
[OT_WORD
][R_ESP
]();
2388 ot
= dflag
? OT_LONG
: OT_WORD
;
2389 gen_op_mov_reg_T0
[ot
][R_EBP
]();
2392 case 0x06: /* push es */
2393 case 0x0e: /* push cs */
2394 case 0x16: /* push ss */
2395 case 0x1e: /* push ds */
2396 gen_op_movl_T0_seg(b
>> 3);
2399 case 0x1a0: /* push fs */
2400 case 0x1a8: /* push gs */
2401 gen_op_movl_T0_seg((b
>> 3) & 7);
2404 case 0x07: /* pop es */
2405 case 0x17: /* pop ss */
2406 case 0x1f: /* pop ds */
2409 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
2412 /* if reg == SS, inhibit interrupts/trace. */
2413 /* If several instructions disable interrupts, only the
2415 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
2416 gen_op_set_inhibit_irq();
2420 gen_op_jmp_im(s
->pc
- s
->cs_base
);
2424 case 0x1a1: /* pop fs */
2425 case 0x1a9: /* pop gs */
2427 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
2430 gen_op_jmp_im(s
->pc
- s
->cs_base
);
2435 /**************************/
2438 case 0x89: /* mov Gv, Ev */
2442 ot
= dflag
? OT_LONG
: OT_WORD
;
2443 modrm
= ldub_code(s
->pc
++);
2444 reg
= (modrm
>> 3) & 7;
2446 /* generate a generic store */
2447 gen_ldst_modrm(s
, modrm
, ot
, OR_EAX
+ reg
, 1);
2450 case 0xc7: /* mov Ev, Iv */
2454 ot
= dflag
? OT_LONG
: OT_WORD
;
2455 modrm
= ldub_code(s
->pc
++);
2456 mod
= (modrm
>> 6) & 3;
2458 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2459 val
= insn_get(s
, ot
);
2460 gen_op_movl_T0_im(val
);
2462 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2464 gen_op_mov_reg_T0
[ot
][modrm
& 7]();
2467 case 0x8b: /* mov Ev, Gv */
2471 ot
= dflag
? OT_LONG
: OT_WORD
;
2472 modrm
= ldub_code(s
->pc
++);
2473 reg
= (modrm
>> 3) & 7;
2475 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
2476 gen_op_mov_reg_T0
[ot
][reg
]();
2478 case 0x8e: /* mov seg, Gv */
2479 modrm
= ldub_code(s
->pc
++);
2480 reg
= (modrm
>> 3) & 7;
2481 if (reg
>= 6 || reg
== R_CS
)
2483 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
2484 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
2486 /* if reg == SS, inhibit interrupts/trace */
2487 /* If several instructions disable interrupts, only the
2489 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
2490 gen_op_set_inhibit_irq();
2494 gen_op_jmp_im(s
->pc
- s
->cs_base
);
2498 case 0x8c: /* mov Gv, seg */
2499 modrm
= ldub_code(s
->pc
++);
2500 reg
= (modrm
>> 3) & 7;
2501 mod
= (modrm
>> 6) & 3;
2504 gen_op_movl_T0_seg(reg
);
2506 if (mod
== 3 && dflag
)
2508 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
2511 case 0x1b6: /* movzbS Gv, Eb */
2512 case 0x1b7: /* movzwS Gv, Eb */
2513 case 0x1be: /* movsbS Gv, Eb */
2514 case 0x1bf: /* movswS Gv, Eb */
2517 /* d_ot is the size of destination */
2518 d_ot
= dflag
+ OT_WORD
;
2519 /* ot is the size of source */
2520 ot
= (b
& 1) + OT_BYTE
;
2521 modrm
= ldub_code(s
->pc
++);
2522 reg
= ((modrm
>> 3) & 7) + OR_EAX
;
2523 mod
= (modrm
>> 6) & 3;
2527 gen_op_mov_TN_reg
[ot
][0][rm
]();
2528 switch(ot
| (b
& 8)) {
2530 gen_op_movzbl_T0_T0();
2533 gen_op_movsbl_T0_T0();
2536 gen_op_movzwl_T0_T0();
2540 gen_op_movswl_T0_T0();
2543 gen_op_mov_reg_T0
[d_ot
][reg
]();
2545 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2547 gen_op_lds_T0_A0
[ot
+ s
->mem_index
]();
2549 gen_op_ldu_T0_A0
[ot
+ s
->mem_index
]();
2551 gen_op_mov_reg_T0
[d_ot
][reg
]();
2556 case 0x8d: /* lea */
2557 ot
= dflag
? OT_LONG
: OT_WORD
;
2558 modrm
= ldub_code(s
->pc
++);
2559 mod
= (modrm
>> 6) & 3;
2562 reg
= (modrm
>> 3) & 7;
2563 /* we must ensure that no segment is added */
2567 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2569 gen_op_mov_reg_A0
[ot
- OT_WORD
][reg
]();
2572 case 0xa0: /* mov EAX, Ov */
2574 case 0xa2: /* mov Ov, EAX */
2579 ot
= dflag
? OT_LONG
: OT_WORD
;
2581 offset_addr
= insn_get(s
, OT_LONG
);
2583 offset_addr
= insn_get(s
, OT_WORD
);
2584 gen_op_movl_A0_im(offset_addr
);
2585 /* handle override */
2587 int override
, must_add_seg
;
2588 must_add_seg
= s
->addseg
;
2589 if (s
->override
>= 0) {
2590 override
= s
->override
;
2596 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
2600 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
2601 gen_op_mov_reg_T0
[ot
][R_EAX
]();
2603 gen_op_mov_TN_reg
[ot
][0][R_EAX
]();
2604 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2607 case 0xd7: /* xlat */
2608 gen_op_movl_A0_reg
[R_EBX
]();
2609 gen_op_addl_A0_AL();
2611 gen_op_andl_A0_ffff();
2612 /* handle override */
2614 int override
, must_add_seg
;
2615 must_add_seg
= s
->addseg
;
2617 if (s
->override
>= 0) {
2618 override
= s
->override
;
2624 gen_op_addl_A0_seg(offsetof(CPUX86State
,segs
[override
].base
));
2627 gen_op_ldu_T0_A0
[OT_BYTE
+ s
->mem_index
]();
2628 gen_op_mov_reg_T0
[OT_BYTE
][R_EAX
]();
2630 case 0xb0 ... 0xb7: /* mov R, Ib */
2631 val
= insn_get(s
, OT_BYTE
);
2632 gen_op_movl_T0_im(val
);
2633 gen_op_mov_reg_T0
[OT_BYTE
][b
& 7]();
2635 case 0xb8 ... 0xbf: /* mov R, Iv */
2636 ot
= dflag
? OT_LONG
: OT_WORD
;
2637 val
= insn_get(s
, ot
);
2638 reg
= OR_EAX
+ (b
& 7);
2639 gen_op_movl_T0_im(val
);
2640 gen_op_mov_reg_T0
[ot
][reg
]();
2643 case 0x91 ... 0x97: /* xchg R, EAX */
2644 ot
= dflag
? OT_LONG
: OT_WORD
;
2649 case 0x87: /* xchg Ev, Gv */
2653 ot
= dflag
? OT_LONG
: OT_WORD
;
2654 modrm
= ldub_code(s
->pc
++);
2655 reg
= (modrm
>> 3) & 7;
2656 mod
= (modrm
>> 6) & 3;
2660 gen_op_mov_TN_reg
[ot
][0][reg
]();
2661 gen_op_mov_TN_reg
[ot
][1][rm
]();
2662 gen_op_mov_reg_T0
[ot
][rm
]();
2663 gen_op_mov_reg_T1
[ot
][reg
]();
2665 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2666 gen_op_mov_TN_reg
[ot
][0][reg
]();
2667 /* for xchg, lock is implicit */
2668 if (!(prefixes
& PREFIX_LOCK
))
2670 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
2671 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
2672 if (!(prefixes
& PREFIX_LOCK
))
2674 gen_op_mov_reg_T1
[ot
][reg
]();
2677 case 0xc4: /* les Gv */
2680 case 0xc5: /* lds Gv */
2683 case 0x1b2: /* lss Gv */
2686 case 0x1b4: /* lfs Gv */
2689 case 0x1b5: /* lgs Gv */
2692 ot
= dflag
? OT_LONG
: OT_WORD
;
2693 modrm
= ldub_code(s
->pc
++);
2694 reg
= (modrm
>> 3) & 7;
2695 mod
= (modrm
>> 6) & 3;
2698 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2699 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
2700 gen_op_addl_A0_im(1 << (ot
- OT_WORD
+ 1));
2701 /* load the segment first to handle exceptions properly */
2702 gen_op_ldu_T0_A0
[OT_WORD
+ s
->mem_index
]();
2703 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
2704 /* then put the data */
2705 gen_op_mov_reg_T1
[ot
][reg
]();
2707 gen_op_jmp_im(s
->pc
- s
->cs_base
);
2712 /************************/
2723 ot
= dflag
? OT_LONG
: OT_WORD
;
2725 modrm
= ldub_code(s
->pc
++);
2726 mod
= (modrm
>> 6) & 3;
2728 op
= (modrm
>> 3) & 7;
2731 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2734 opreg
= rm
+ OR_EAX
;
2739 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
2742 shift
= ldub_code(s
->pc
++);
2744 gen_shifti(s
, op
, ot
, opreg
, shift
);
2759 case 0x1a4: /* shld imm */
2763 case 0x1a5: /* shld cl */
2767 case 0x1ac: /* shrd imm */
2771 case 0x1ad: /* shrd cl */
2775 ot
= dflag
? OT_LONG
: OT_WORD
;
2776 modrm
= ldub_code(s
->pc
++);
2777 mod
= (modrm
>> 6) & 3;
2779 reg
= (modrm
>> 3) & 7;
2782 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2783 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
2785 gen_op_mov_TN_reg
[ot
][0][rm
]();
2787 gen_op_mov_TN_reg
[ot
][1][reg
]();
2790 val
= ldub_code(s
->pc
++);
2794 gen_op_shiftd_T0_T1_im_cc
[ot
][op
](val
);
2796 gen_op_shiftd_mem_T0_T1_im_cc
[ot
+ s
->mem_index
][op
](val
);
2797 if (op
== 0 && ot
!= OT_WORD
)
2798 s
->cc_op
= CC_OP_SHLB
+ ot
;
2800 s
->cc_op
= CC_OP_SARB
+ ot
;
2803 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2804 gen_op_set_cc_op(s
->cc_op
);
2806 gen_op_shiftd_T0_T1_ECX_cc
[ot
][op
]();
2808 gen_op_shiftd_mem_T0_T1_ECX_cc
[ot
+ s
->mem_index
][op
]();
2809 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
2812 gen_op_mov_reg_T0
[ot
][rm
]();
2816 /************************/
2819 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
2820 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
2821 /* XXX: what to do if illegal op ? */
2822 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
2825 modrm
= ldub_code(s
->pc
++);
2826 mod
= (modrm
>> 6) & 3;
2828 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
2831 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2833 case 0x00 ... 0x07: /* fxxxs */
2834 case 0x10 ... 0x17: /* fixxxl */
2835 case 0x20 ... 0x27: /* fxxxl */
2836 case 0x30 ... 0x37: /* fixxx */
2843 gen_op_flds_FT0_A0();
2846 gen_op_fildl_FT0_A0();
2849 gen_op_fldl_FT0_A0();
2853 gen_op_fild_FT0_A0();
2857 gen_op_fp_arith_ST0_FT0
[op1
]();
2859 /* fcomp needs pop */
2864 case 0x08: /* flds */
2865 case 0x0a: /* fsts */
2866 case 0x0b: /* fstps */
2867 case 0x18: /* fildl */
2868 case 0x1a: /* fistl */
2869 case 0x1b: /* fistpl */
2870 case 0x28: /* fldl */
2871 case 0x2a: /* fstl */
2872 case 0x2b: /* fstpl */
2873 case 0x38: /* filds */
2874 case 0x3a: /* fists */
2875 case 0x3b: /* fistps */
2881 gen_op_flds_ST0_A0();
2884 gen_op_fildl_ST0_A0();
2887 gen_op_fldl_ST0_A0();
2891 gen_op_fild_ST0_A0();
2898 gen_op_fsts_ST0_A0();
2901 gen_op_fistl_ST0_A0();
2904 gen_op_fstl_ST0_A0();
2908 gen_op_fist_ST0_A0();
2916 case 0x0c: /* fldenv mem */
2917 gen_op_fldenv_A0(s
->dflag
);
2919 case 0x0d: /* fldcw mem */
2922 case 0x0e: /* fnstenv mem */
2923 gen_op_fnstenv_A0(s
->dflag
);
2925 case 0x0f: /* fnstcw mem */
2928 case 0x1d: /* fldt mem */
2929 gen_op_fldt_ST0_A0();
2931 case 0x1f: /* fstpt mem */
2932 gen_op_fstt_ST0_A0();
2935 case 0x2c: /* frstor mem */
2936 gen_op_frstor_A0(s
->dflag
);
2938 case 0x2e: /* fnsave mem */
2939 gen_op_fnsave_A0(s
->dflag
);
2941 case 0x2f: /* fnstsw mem */
2944 case 0x3c: /* fbld */
2945 gen_op_fbld_ST0_A0();
2947 case 0x3e: /* fbstp */
2948 gen_op_fbst_ST0_A0();
2951 case 0x3d: /* fildll */
2952 gen_op_fildll_ST0_A0();
2954 case 0x3f: /* fistpll */
2955 gen_op_fistll_ST0_A0();
2962 /* register float ops */
2966 case 0x08: /* fld sti */
2968 gen_op_fmov_ST0_STN((opreg
+ 1) & 7);
2970 case 0x09: /* fxchg sti */
2971 gen_op_fxchg_ST0_STN(opreg
);
2973 case 0x0a: /* grp d9/2 */
2981 case 0x0c: /* grp d9/4 */
2991 gen_op_fcom_ST0_FT0();
3000 case 0x0d: /* grp d9/5 */
3009 gen_op_fldl2t_ST0();
3013 gen_op_fldl2e_ST0();
3021 gen_op_fldlg2_ST0();
3025 gen_op_fldln2_ST0();
3036 case 0x0e: /* grp d9/6 */
3047 case 3: /* fpatan */
3050 case 4: /* fxtract */
3053 case 5: /* fprem1 */
3056 case 6: /* fdecstp */
3060 case 7: /* fincstp */
3065 case 0x0f: /* grp d9/7 */
3070 case 1: /* fyl2xp1 */
3076 case 3: /* fsincos */
3079 case 5: /* fscale */
3082 case 4: /* frndint */
3094 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3095 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3096 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3102 gen_op_fp_arith_STN_ST0
[op1
](opreg
);
3106 gen_op_fmov_FT0_STN(opreg
);
3107 gen_op_fp_arith_ST0_FT0
[op1
]();
3111 case 0x02: /* fcom */
3112 gen_op_fmov_FT0_STN(opreg
);
3113 gen_op_fcom_ST0_FT0();
3115 case 0x03: /* fcomp */
3116 gen_op_fmov_FT0_STN(opreg
);
3117 gen_op_fcom_ST0_FT0();
3120 case 0x15: /* da/5 */
3122 case 1: /* fucompp */
3123 gen_op_fmov_FT0_STN(1);
3124 gen_op_fucom_ST0_FT0();
3134 case 0: /* feni (287 only, just do nop here) */
3136 case 1: /* fdisi (287 only, just do nop here) */
3141 case 3: /* fninit */
3144 case 4: /* fsetpm (287 only, just do nop here) */
3150 case 0x1d: /* fucomi */
3151 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3152 gen_op_set_cc_op(s
->cc_op
);
3153 gen_op_fmov_FT0_STN(opreg
);
3154 gen_op_fucomi_ST0_FT0();
3155 s
->cc_op
= CC_OP_EFLAGS
;
3157 case 0x1e: /* fcomi */
3158 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3159 gen_op_set_cc_op(s
->cc_op
);
3160 gen_op_fmov_FT0_STN(opreg
);
3161 gen_op_fcomi_ST0_FT0();
3162 s
->cc_op
= CC_OP_EFLAGS
;
3164 case 0x2a: /* fst sti */
3165 gen_op_fmov_STN_ST0(opreg
);
3167 case 0x2b: /* fstp sti */
3168 gen_op_fmov_STN_ST0(opreg
);
3171 case 0x2c: /* fucom st(i) */
3172 gen_op_fmov_FT0_STN(opreg
);
3173 gen_op_fucom_ST0_FT0();
3175 case 0x2d: /* fucomp st(i) */
3176 gen_op_fmov_FT0_STN(opreg
);
3177 gen_op_fucom_ST0_FT0();
3180 case 0x33: /* de/3 */
3182 case 1: /* fcompp */
3183 gen_op_fmov_FT0_STN(1);
3184 gen_op_fcom_ST0_FT0();
3192 case 0x3c: /* df/4 */
3195 gen_op_fnstsw_EAX();
3201 case 0x3d: /* fucomip */
3202 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3203 gen_op_set_cc_op(s
->cc_op
);
3204 gen_op_fmov_FT0_STN(opreg
);
3205 gen_op_fucomi_ST0_FT0();
3207 s
->cc_op
= CC_OP_EFLAGS
;
3209 case 0x3e: /* fcomip */
3210 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3211 gen_op_set_cc_op(s
->cc_op
);
3212 gen_op_fmov_FT0_STN(opreg
);
3213 gen_op_fcomi_ST0_FT0();
3215 s
->cc_op
= CC_OP_EFLAGS
;
3217 case 0x10 ... 0x13: /* fcmovxx */
3221 const static uint8_t fcmov_cc
[8] = {
3227 op1
= fcmov_cc
[op
& 3] | ((op
>> 3) & 1);
3229 gen_op_fcmov_ST0_STN_T0(opreg
);
3236 #ifdef USE_CODE_COPY
3237 s
->tb
->cflags
|= CF_TB_FP_USED
;
3240 /************************/
3243 case 0xa4: /* movsS */
3248 ot
= dflag
? OT_LONG
: OT_WORD
;
3250 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
3251 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3257 case 0xaa: /* stosS */
3262 ot
= dflag
? OT_LONG
: OT_WORD
;
3264 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
3265 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3270 case 0xac: /* lodsS */
3275 ot
= dflag
? OT_LONG
: OT_WORD
;
3276 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
3277 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3282 case 0xae: /* scasS */
3287 ot
= dflag
? OT_LONG
: OT_WORD
;
3288 if (prefixes
& PREFIX_REPNZ
) {
3289 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
3290 } else if (prefixes
& PREFIX_REPZ
) {
3291 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
3294 s
->cc_op
= CC_OP_SUBB
+ ot
;
3298 case 0xa6: /* cmpsS */
3303 ot
= dflag
? OT_LONG
: OT_WORD
;
3304 if (prefixes
& PREFIX_REPNZ
) {
3305 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
3306 } else if (prefixes
& PREFIX_REPZ
) {
3307 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
3310 s
->cc_op
= CC_OP_SUBB
+ ot
;
3313 case 0x6c: /* insS */
3318 ot
= dflag
? OT_LONG
: OT_WORD
;
3319 gen_check_io(s
, ot
, 1, pc_start
- s
->cs_base
);
3320 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
3321 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3326 case 0x6e: /* outsS */
3331 ot
= dflag
? OT_LONG
: OT_WORD
;
3332 gen_check_io(s
, ot
, 1, pc_start
- s
->cs_base
);
3333 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
3334 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3340 /************************/
3347 ot
= dflag
? OT_LONG
: OT_WORD
;
3348 val
= ldub_code(s
->pc
++);
3349 gen_op_movl_T0_im(val
);
3350 gen_check_io(s
, ot
, 0, pc_start
- s
->cs_base
);
3352 gen_op_mov_reg_T1
[ot
][R_EAX
]();
3359 ot
= dflag
? OT_LONG
: OT_WORD
;
3360 val
= ldub_code(s
->pc
++);
3361 gen_op_movl_T0_im(val
);
3362 gen_check_io(s
, ot
, 0, pc_start
- s
->cs_base
);
3363 gen_op_mov_TN_reg
[ot
][1][R_EAX
]();
3371 ot
= dflag
? OT_LONG
: OT_WORD
;
3372 gen_op_mov_TN_reg
[OT_WORD
][0][R_EDX
]();
3373 gen_op_andl_T0_ffff();
3374 gen_check_io(s
, ot
, 0, pc_start
- s
->cs_base
);
3376 gen_op_mov_reg_T1
[ot
][R_EAX
]();
3383 ot
= dflag
? OT_LONG
: OT_WORD
;
3384 gen_op_mov_TN_reg
[OT_WORD
][0][R_EDX
]();
3385 gen_op_andl_T0_ffff();
3386 gen_check_io(s
, ot
, 0, pc_start
- s
->cs_base
);
3387 gen_op_mov_TN_reg
[ot
][1][R_EAX
]();
3391 /************************/
3393 case 0xc2: /* ret im */
3394 val
= ldsw_code(s
->pc
);
3397 gen_stack_update(s
, val
+ (2 << s
->dflag
));
3399 gen_op_andl_T0_ffff();
3403 case 0xc3: /* ret */
3407 gen_op_andl_T0_ffff();
3411 case 0xca: /* lret im */
3412 val
= ldsw_code(s
->pc
);
3415 if (s
->pe
&& !s
->vm86
) {
3416 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3417 gen_op_set_cc_op(s
->cc_op
);
3418 gen_op_jmp_im(pc_start
- s
->cs_base
);
3419 gen_op_lret_protected(s
->dflag
, val
);
3423 gen_op_ld_T0_A0
[1 + s
->dflag
+ s
->mem_index
]();
3425 gen_op_andl_T0_ffff();
3426 /* NOTE: keeping EIP updated is not a problem in case of
3430 gen_op_addl_A0_im(2 << s
->dflag
);
3431 gen_op_ld_T0_A0
[1 + s
->dflag
+ s
->mem_index
]();
3432 gen_op_movl_seg_T0_vm(offsetof(CPUX86State
,segs
[R_CS
]));
3433 /* add stack offset */
3434 gen_stack_update(s
, val
+ (4 << s
->dflag
));
3438 case 0xcb: /* lret */
3441 case 0xcf: /* iret */
3444 gen_op_iret_real(s
->dflag
);
3445 s
->cc_op
= CC_OP_EFLAGS
;
3446 } else if (s
->vm86
) {
3448 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3450 gen_op_iret_real(s
->dflag
);
3451 s
->cc_op
= CC_OP_EFLAGS
;
3454 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3455 gen_op_set_cc_op(s
->cc_op
);
3456 gen_op_jmp_im(pc_start
- s
->cs_base
);
3457 gen_op_iret_protected(s
->dflag
, s
->pc
- s
->cs_base
);
3458 s
->cc_op
= CC_OP_EFLAGS
;
3462 case 0xe8: /* call im */
3464 unsigned int next_eip
;
3465 ot
= dflag
? OT_LONG
: OT_WORD
;
3466 val
= insn_get(s
, ot
);
3467 next_eip
= s
->pc
- s
->cs_base
;
3471 gen_op_movl_T0_im(next_eip
);
3476 case 0x9a: /* lcall im */
3478 unsigned int selector
, offset
;
3480 ot
= dflag
? OT_LONG
: OT_WORD
;
3481 offset
= insn_get(s
, ot
);
3482 selector
= insn_get(s
, OT_WORD
);
3484 gen_op_movl_T0_im(selector
);
3485 gen_op_movl_T1_im(offset
);
3488 case 0xe9: /* jmp */
3489 ot
= dflag
? OT_LONG
: OT_WORD
;
3490 val
= insn_get(s
, ot
);
3491 val
+= s
->pc
- s
->cs_base
;
3496 case 0xea: /* ljmp im */
3498 unsigned int selector
, offset
;
3500 ot
= dflag
? OT_LONG
: OT_WORD
;
3501 offset
= insn_get(s
, ot
);
3502 selector
= insn_get(s
, OT_WORD
);
3504 gen_op_movl_T0_im(selector
);
3505 gen_op_movl_T1_im(offset
);
3508 case 0xeb: /* jmp Jb */
3509 val
= (int8_t)insn_get(s
, OT_BYTE
);
3510 val
+= s
->pc
- s
->cs_base
;
3515 case 0x70 ... 0x7f: /* jcc Jb */
3516 val
= (int8_t)insn_get(s
, OT_BYTE
);
3518 case 0x180 ... 0x18f: /* jcc Jv */
3520 val
= insn_get(s
, OT_LONG
);
3522 val
= (int16_t)insn_get(s
, OT_WORD
);
3525 next_eip
= s
->pc
- s
->cs_base
;
3529 gen_jcc(s
, b
, val
, next_eip
);
3532 case 0x190 ... 0x19f: /* setcc Gv */
3533 modrm
= ldub_code(s
->pc
++);
3535 gen_ldst_modrm(s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
3537 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3538 ot
= dflag
? OT_LONG
: OT_WORD
;
3539 modrm
= ldub_code(s
->pc
++);
3540 reg
= (modrm
>> 3) & 7;
3541 mod
= (modrm
>> 6) & 3;
3544 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3545 gen_op_ld_T1_A0
[ot
+ s
->mem_index
]();
3548 gen_op_mov_TN_reg
[ot
][1][rm
]();
3550 gen_op_cmov_reg_T1_T0
[ot
- OT_WORD
][reg
]();
3553 /************************/
3555 case 0x9c: /* pushf */
3556 if (s
->vm86
&& s
->iopl
!= 3) {
3557 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3559 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3560 gen_op_set_cc_op(s
->cc_op
);
3561 gen_op_movl_T0_eflags();
3565 case 0x9d: /* popf */
3566 if (s
->vm86
&& s
->iopl
!= 3) {
3567 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3572 gen_op_movl_eflags_T0_cpl0();
3574 gen_op_movw_eflags_T0_cpl0();
3577 if (s
->cpl
<= s
->iopl
) {
3579 gen_op_movl_eflags_T0_io();
3581 gen_op_movw_eflags_T0_io();
3585 gen_op_movl_eflags_T0();
3587 gen_op_movw_eflags_T0();
3592 s
->cc_op
= CC_OP_EFLAGS
;
3593 /* abort translation because TF flag may change */
3594 gen_op_jmp_im(s
->pc
- s
->cs_base
);
3598 case 0x9e: /* sahf */
3599 gen_op_mov_TN_reg
[OT_BYTE
][0][R_AH
]();
3600 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3601 gen_op_set_cc_op(s
->cc_op
);
3602 gen_op_movb_eflags_T0();
3603 s
->cc_op
= CC_OP_EFLAGS
;
3605 case 0x9f: /* lahf */
3606 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3607 gen_op_set_cc_op(s
->cc_op
);
3608 gen_op_movl_T0_eflags();
3609 gen_op_mov_reg_T0
[OT_BYTE
][R_AH
]();
3611 case 0xf5: /* cmc */
3612 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3613 gen_op_set_cc_op(s
->cc_op
);
3615 s
->cc_op
= CC_OP_EFLAGS
;
3617 case 0xf8: /* clc */
3618 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3619 gen_op_set_cc_op(s
->cc_op
);
3621 s
->cc_op
= CC_OP_EFLAGS
;
3623 case 0xf9: /* stc */
3624 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3625 gen_op_set_cc_op(s
->cc_op
);
3627 s
->cc_op
= CC_OP_EFLAGS
;
3629 case 0xfc: /* cld */
3632 case 0xfd: /* std */
3636 /************************/
3637 /* bit operations */
3638 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3639 ot
= dflag
? OT_LONG
: OT_WORD
;
3640 modrm
= ldub_code(s
->pc
++);
3641 op
= (modrm
>> 3) & 7;
3642 mod
= (modrm
>> 6) & 3;
3645 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3646 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
3648 gen_op_mov_TN_reg
[ot
][0][rm
]();
3651 val
= ldub_code(s
->pc
++);
3652 gen_op_movl_T1_im(val
);
3656 gen_op_btx_T0_T1_cc
[ot
- OT_WORD
][op
]();
3657 s
->cc_op
= CC_OP_SARB
+ ot
;
3660 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
3662 gen_op_mov_reg_T0
[ot
][rm
]();
3663 gen_op_update_bt_cc();
3666 case 0x1a3: /* bt Gv, Ev */
3669 case 0x1ab: /* bts */
3672 case 0x1b3: /* btr */
3675 case 0x1bb: /* btc */
3678 ot
= dflag
? OT_LONG
: OT_WORD
;
3679 modrm
= ldub_code(s
->pc
++);
3680 reg
= (modrm
>> 3) & 7;
3681 mod
= (modrm
>> 6) & 3;
3683 gen_op_mov_TN_reg
[OT_LONG
][1][reg
]();
3685 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3686 /* specific case: we need to add a displacement */
3688 gen_op_add_bitw_A0_T1();
3690 gen_op_add_bitl_A0_T1();
3691 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
3693 gen_op_mov_TN_reg
[ot
][0][rm
]();
3695 gen_op_btx_T0_T1_cc
[ot
- OT_WORD
][op
]();
3696 s
->cc_op
= CC_OP_SARB
+ ot
;
3699 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
3701 gen_op_mov_reg_T0
[ot
][rm
]();
3702 gen_op_update_bt_cc();
3705 case 0x1bc: /* bsf */
3706 case 0x1bd: /* bsr */
3707 ot
= dflag
? OT_LONG
: OT_WORD
;
3708 modrm
= ldub_code(s
->pc
++);
3709 reg
= (modrm
>> 3) & 7;
3710 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3711 gen_op_bsx_T0_cc
[ot
- OT_WORD
][b
& 1]();
3712 /* NOTE: we always write back the result. Intel doc says it is
3713 undefined if T0 == 0 */
3714 gen_op_mov_reg_T0
[ot
][reg
]();
3715 s
->cc_op
= CC_OP_LOGICB
+ ot
;
3717 /************************/
3719 case 0x27: /* daa */
3720 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3721 gen_op_set_cc_op(s
->cc_op
);
3723 s
->cc_op
= CC_OP_EFLAGS
;
3725 case 0x2f: /* das */
3726 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3727 gen_op_set_cc_op(s
->cc_op
);
3729 s
->cc_op
= CC_OP_EFLAGS
;
3731 case 0x37: /* aaa */
3732 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3733 gen_op_set_cc_op(s
->cc_op
);
3735 s
->cc_op
= CC_OP_EFLAGS
;
3737 case 0x3f: /* aas */
3738 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3739 gen_op_set_cc_op(s
->cc_op
);
3741 s
->cc_op
= CC_OP_EFLAGS
;
3743 case 0xd4: /* aam */
3744 val
= ldub_code(s
->pc
++);
3746 s
->cc_op
= CC_OP_LOGICB
;
3748 case 0xd5: /* aad */
3749 val
= ldub_code(s
->pc
++);
3751 s
->cc_op
= CC_OP_LOGICB
;
3753 /************************/
3755 case 0x90: /* nop */
3756 /* XXX: correct lock test for all insn */
3757 if (prefixes
& PREFIX_LOCK
)
3760 case 0x9b: /* fwait */
3761 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
3762 (HF_MP_MASK
| HF_TS_MASK
)) {
3763 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3765 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3766 gen_op_set_cc_op(s
->cc_op
);
3767 gen_op_jmp_im(pc_start
- s
->cs_base
);
3771 case 0xcc: /* int3 */
3772 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3774 case 0xcd: /* int N */
3775 val
= ldub_code(s
->pc
++);
3776 if (s
->vm86
&& s
->iopl
!= 3) {
3777 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3779 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
3782 case 0xce: /* into */
3783 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3784 gen_op_set_cc_op(s
->cc_op
);
3785 gen_op_into(s
->pc
- s
->cs_base
);
3787 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3788 gen_debug(s
, pc_start
- s
->cs_base
);
3790 case 0xfa: /* cli */
3792 if (s
->cpl
<= s
->iopl
) {
3795 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3801 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3805 case 0xfb: /* sti */
3807 if (s
->cpl
<= s
->iopl
) {
3810 /* interruptions are enabled only the first insn after sti */
3811 /* If several instructions disable interrupts, only the
3813 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
3814 gen_op_set_inhibit_irq();
3815 /* give a chance to handle pending irqs */
3816 gen_op_jmp_im(s
->pc
- s
->cs_base
);
3819 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3825 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3829 case 0x62: /* bound */
3830 ot
= dflag
? OT_LONG
: OT_WORD
;
3831 modrm
= ldub_code(s
->pc
++);
3832 reg
= (modrm
>> 3) & 7;
3833 mod
= (modrm
>> 6) & 3;
3836 gen_op_mov_reg_T0
[ot
][reg
]();
3837 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3839 gen_op_boundw(pc_start
- s
->cs_base
);
3841 gen_op_boundl(pc_start
- s
->cs_base
);
3843 case 0x1c8 ... 0x1cf: /* bswap reg */
3845 gen_op_mov_TN_reg
[OT_LONG
][0][reg
]();
3847 gen_op_mov_reg_T0
[OT_LONG
][reg
]();
3849 case 0xd6: /* salc */
3850 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3851 gen_op_set_cc_op(s
->cc_op
);
3854 case 0xe0: /* loopnz */
3855 case 0xe1: /* loopz */
3856 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3857 gen_op_set_cc_op(s
->cc_op
);
3859 case 0xe2: /* loop */
3860 case 0xe3: /* jecxz */
3861 val
= (int8_t)insn_get(s
, OT_BYTE
);
3862 next_eip
= s
->pc
- s
->cs_base
;
3866 gen_op_loop
[s
->aflag
][b
& 3](val
, next_eip
);
3869 case 0x130: /* wrmsr */
3870 case 0x132: /* rdmsr */
3872 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3880 case 0x131: /* rdtsc */
3883 case 0x1a2: /* cpuid */
3886 case 0xf4: /* hlt */
3888 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3890 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3891 gen_op_set_cc_op(s
->cc_op
);
3892 gen_op_jmp_im(s
->pc
- s
->cs_base
);
3898 modrm
= ldub_code(s
->pc
++);
3899 mod
= (modrm
>> 6) & 3;
3900 op
= (modrm
>> 3) & 7;
3903 if (!s
->pe
|| s
->vm86
)
3905 gen_op_movl_T0_env(offsetof(CPUX86State
,ldt
.selector
));
3909 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
3912 if (!s
->pe
|| s
->vm86
)
3915 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3917 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3918 gen_op_jmp_im(pc_start
- s
->cs_base
);
3923 if (!s
->pe
|| s
->vm86
)
3925 gen_op_movl_T0_env(offsetof(CPUX86State
,tr
.selector
));
3929 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
3932 if (!s
->pe
|| s
->vm86
)
3935 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3937 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3938 gen_op_jmp_im(pc_start
- s
->cs_base
);
3944 if (!s
->pe
|| s
->vm86
)
3946 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3947 if (s
->cc_op
!= CC_OP_DYNAMIC
)
3948 gen_op_set_cc_op(s
->cc_op
);
3953 s
->cc_op
= CC_OP_EFLAGS
;
3960 modrm
= ldub_code(s
->pc
++);
3961 mod
= (modrm
>> 6) & 3;
3962 op
= (modrm
>> 3) & 7;
3968 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3970 gen_op_movl_T0_env(offsetof(CPUX86State
,gdt
.limit
));
3972 gen_op_movl_T0_env(offsetof(CPUX86State
,idt
.limit
));
3973 gen_op_st_T0_A0
[OT_WORD
+ s
->mem_index
]();
3974 gen_op_addl_A0_im(2);
3976 gen_op_movl_T0_env(offsetof(CPUX86State
,gdt
.base
));
3978 gen_op_movl_T0_env(offsetof(CPUX86State
,idt
.base
));
3980 gen_op_andl_T0_im(0xffffff);
3981 gen_op_st_T0_A0
[OT_LONG
+ s
->mem_index
]();
3988 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
3990 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3991 gen_op_ld_T1_A0
[OT_WORD
+ s
->mem_index
]();
3992 gen_op_addl_A0_im(2);
3993 gen_op_ld_T0_A0
[OT_LONG
+ s
->mem_index
]();
3995 gen_op_andl_T0_im(0xffffff);
3997 gen_op_movl_env_T0(offsetof(CPUX86State
,gdt
.base
));
3998 gen_op_movl_env_T1(offsetof(CPUX86State
,gdt
.limit
));
4000 gen_op_movl_env_T0(offsetof(CPUX86State
,idt
.base
));
4001 gen_op_movl_env_T1(offsetof(CPUX86State
,idt
.limit
));
4006 gen_op_movl_T0_env(offsetof(CPUX86State
,cr
[0]));
4007 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 1);
4011 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4013 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
4015 gen_op_jmp_im(s
->pc
- s
->cs_base
);
4019 case 7: /* invlpg */
4021 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4025 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4027 gen_op_jmp_im(s
->pc
- s
->cs_base
);
4035 case 0x108: /* invd */
4036 case 0x109: /* wbinvd */
4038 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4043 case 0x63: /* arpl */
4044 if (!s
->pe
|| s
->vm86
)
4046 ot
= dflag
? OT_LONG
: OT_WORD
;
4047 modrm
= ldub_code(s
->pc
++);
4048 reg
= (modrm
>> 3) & 7;
4049 mod
= (modrm
>> 6) & 3;
4052 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4053 gen_op_ld_T0_A0
[ot
+ s
->mem_index
]();
4055 gen_op_mov_TN_reg
[ot
][0][rm
]();
4057 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4058 gen_op_set_cc_op(s
->cc_op
);
4060 s
->cc_op
= CC_OP_EFLAGS
;
4062 gen_op_st_T0_A0
[ot
+ s
->mem_index
]();
4064 gen_op_mov_reg_T0
[ot
][rm
]();
4066 gen_op_arpl_update();
4068 case 0x102: /* lar */
4069 case 0x103: /* lsl */
4070 if (!s
->pe
|| s
->vm86
)
4072 ot
= dflag
? OT_LONG
: OT_WORD
;
4073 modrm
= ldub_code(s
->pc
++);
4074 reg
= (modrm
>> 3) & 7;
4075 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4076 gen_op_mov_TN_reg
[ot
][1][reg
]();
4077 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4078 gen_op_set_cc_op(s
->cc_op
);
4083 s
->cc_op
= CC_OP_EFLAGS
;
4084 gen_op_mov_reg_T1
[ot
][reg
]();
4087 modrm
= ldub_code(s
->pc
++);
4088 mod
= (modrm
>> 6) & 3;
4089 op
= (modrm
>> 3) & 7;
4091 case 0: /* prefetchnta */
4092 case 1: /* prefetchnt0 */
4093 case 2: /* prefetchnt0 */
4094 case 3: /* prefetchnt0 */
4097 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4098 /* nothing more to do */
4104 case 0x120: /* mov reg, crN */
4105 case 0x122: /* mov crN, reg */
4107 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4109 modrm
= ldub_code(s
->pc
++);
4110 if ((modrm
& 0xc0) != 0xc0)
4113 reg
= (modrm
>> 3) & 7;
4120 gen_op_mov_TN_reg
[OT_LONG
][0][rm
]();
4121 gen_op_movl_crN_T0(reg
);
4122 gen_op_jmp_im(s
->pc
- s
->cs_base
);
4125 gen_op_movl_T0_env(offsetof(CPUX86State
,cr
[reg
]));
4126 gen_op_mov_reg_T0
[OT_LONG
][rm
]();
4134 case 0x121: /* mov reg, drN */
4135 case 0x123: /* mov drN, reg */
4137 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4139 modrm
= ldub_code(s
->pc
++);
4140 if ((modrm
& 0xc0) != 0xc0)
4143 reg
= (modrm
>> 3) & 7;
4144 /* XXX: do it dynamically with CR4.DE bit */
4145 if (reg
== 4 || reg
== 5)
4148 gen_op_mov_TN_reg
[OT_LONG
][0][rm
]();
4149 gen_op_movl_drN_T0(reg
);
4150 gen_op_jmp_im(s
->pc
- s
->cs_base
);
4153 gen_op_movl_T0_env(offsetof(CPUX86State
,dr
[reg
]));
4154 gen_op_mov_reg_T0
[OT_LONG
][rm
]();
4158 case 0x106: /* clts */
4160 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
4163 /* abort block because static cpu state changed */
4164 gen_op_jmp_im(s
->pc
- s
->cs_base
);
4171 /* lock generation */
4172 if (s
->prefix
& PREFIX_LOCK
)
4176 if (s
->prefix
& PREFIX_LOCK
)
4178 /* XXX: ensure that no lock was generated */
4179 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
4183 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4184 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4186 /* flags read by an operation */
4187 static uint16_t opc_read_flags
[NB_OPS
] = {
4188 [INDEX_op_aas
] = CC_A
,
4189 [INDEX_op_aaa
] = CC_A
,
4190 [INDEX_op_das
] = CC_A
| CC_C
,
4191 [INDEX_op_daa
] = CC_A
| CC_C
,
4193 /* subtle: due to the incl/decl implementation, C is used */
4194 [INDEX_op_update_inc_cc
] = CC_C
,
4196 [INDEX_op_into
] = CC_O
,
4198 [INDEX_op_jb_subb
] = CC_C
,
4199 [INDEX_op_jb_subw
] = CC_C
,
4200 [INDEX_op_jb_subl
] = CC_C
,
4202 [INDEX_op_jz_subb
] = CC_Z
,
4203 [INDEX_op_jz_subw
] = CC_Z
,
4204 [INDEX_op_jz_subl
] = CC_Z
,
4206 [INDEX_op_jbe_subb
] = CC_Z
| CC_C
,
4207 [INDEX_op_jbe_subw
] = CC_Z
| CC_C
,
4208 [INDEX_op_jbe_subl
] = CC_Z
| CC_C
,
4210 [INDEX_op_js_subb
] = CC_S
,
4211 [INDEX_op_js_subw
] = CC_S
,
4212 [INDEX_op_js_subl
] = CC_S
,
4214 [INDEX_op_jl_subb
] = CC_O
| CC_S
,
4215 [INDEX_op_jl_subw
] = CC_O
| CC_S
,
4216 [INDEX_op_jl_subl
] = CC_O
| CC_S
,
4218 [INDEX_op_jle_subb
] = CC_O
| CC_S
| CC_Z
,
4219 [INDEX_op_jle_subw
] = CC_O
| CC_S
| CC_Z
,
4220 [INDEX_op_jle_subl
] = CC_O
| CC_S
| CC_Z
,
4222 [INDEX_op_loopnzw
] = CC_Z
,
4223 [INDEX_op_loopnzl
] = CC_Z
,
4224 [INDEX_op_loopzw
] = CC_Z
,
4225 [INDEX_op_loopzl
] = CC_Z
,
4227 [INDEX_op_seto_T0_cc
] = CC_O
,
4228 [INDEX_op_setb_T0_cc
] = CC_C
,
4229 [INDEX_op_setz_T0_cc
] = CC_Z
,
4230 [INDEX_op_setbe_T0_cc
] = CC_Z
| CC_C
,
4231 [INDEX_op_sets_T0_cc
] = CC_S
,
4232 [INDEX_op_setp_T0_cc
] = CC_P
,
4233 [INDEX_op_setl_T0_cc
] = CC_O
| CC_S
,
4234 [INDEX_op_setle_T0_cc
] = CC_O
| CC_S
| CC_Z
,
4236 [INDEX_op_setb_T0_subb
] = CC_C
,
4237 [INDEX_op_setb_T0_subw
] = CC_C
,
4238 [INDEX_op_setb_T0_subl
] = CC_C
,
4240 [INDEX_op_setz_T0_subb
] = CC_Z
,
4241 [INDEX_op_setz_T0_subw
] = CC_Z
,
4242 [INDEX_op_setz_T0_subl
] = CC_Z
,
4244 [INDEX_op_setbe_T0_subb
] = CC_Z
| CC_C
,
4245 [INDEX_op_setbe_T0_subw
] = CC_Z
| CC_C
,
4246 [INDEX_op_setbe_T0_subl
] = CC_Z
| CC_C
,
4248 [INDEX_op_sets_T0_subb
] = CC_S
,
4249 [INDEX_op_sets_T0_subw
] = CC_S
,
4250 [INDEX_op_sets_T0_subl
] = CC_S
,
4252 [INDEX_op_setl_T0_subb
] = CC_O
| CC_S
,
4253 [INDEX_op_setl_T0_subw
] = CC_O
| CC_S
,
4254 [INDEX_op_setl_T0_subl
] = CC_O
| CC_S
,
4256 [INDEX_op_setle_T0_subb
] = CC_O
| CC_S
| CC_Z
,
4257 [INDEX_op_setle_T0_subw
] = CC_O
| CC_S
| CC_Z
,
4258 [INDEX_op_setle_T0_subl
] = CC_O
| CC_S
| CC_Z
,
4260 [INDEX_op_movl_T0_eflags
] = CC_OSZAPC
,
4261 [INDEX_op_cmc
] = CC_C
,
4262 [INDEX_op_salc
] = CC_C
,
4264 /* needed for correct flag optimisation before string ops */
4265 [INDEX_op_jz_ecxw
] = CC_OSZAPC
,
4266 [INDEX_op_jz_ecxl
] = CC_OSZAPC
,
4267 [INDEX_op_jz_ecxw_im
] = CC_OSZAPC
,
4268 [INDEX_op_jz_ecxl_im
] = CC_OSZAPC
,
4270 #define DEF_READF(SUFFIX)\
4271 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4272 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4273 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4274 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4275 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4276 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_C,\
4278 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4279 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4280 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_C,\
4281 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_C,\
4282 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_C,\
4283 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_C,
4288 #ifndef CONFIG_USER_ONLY
4294 /* flags written by an operation */
4295 static uint16_t opc_write_flags
[NB_OPS
] = {
4296 [INDEX_op_update2_cc
] = CC_OSZAPC
,
4297 [INDEX_op_update1_cc
] = CC_OSZAPC
,
4298 [INDEX_op_cmpl_T0_T1_cc
] = CC_OSZAPC
,
4299 [INDEX_op_update_neg_cc
] = CC_OSZAPC
,
4300 /* subtle: due to the incl/decl implementation, C is used */
4301 [INDEX_op_update_inc_cc
] = CC_OSZAPC
,
4302 [INDEX_op_testl_T0_T1_cc
] = CC_OSZAPC
,
4304 [INDEX_op_mulb_AL_T0
] = CC_OSZAPC
,
4305 [INDEX_op_imulb_AL_T0
] = CC_OSZAPC
,
4306 [INDEX_op_mulw_AX_T0
] = CC_OSZAPC
,
4307 [INDEX_op_imulw_AX_T0
] = CC_OSZAPC
,
4308 [INDEX_op_mull_EAX_T0
] = CC_OSZAPC
,
4309 [INDEX_op_imull_EAX_T0
] = CC_OSZAPC
,
4310 [INDEX_op_imulw_T0_T1
] = CC_OSZAPC
,
4311 [INDEX_op_imull_T0_T1
] = CC_OSZAPC
,
4314 [INDEX_op_aam
] = CC_OSZAPC
,
4315 [INDEX_op_aad
] = CC_OSZAPC
,
4316 [INDEX_op_aas
] = CC_OSZAPC
,
4317 [INDEX_op_aaa
] = CC_OSZAPC
,
4318 [INDEX_op_das
] = CC_OSZAPC
,
4319 [INDEX_op_daa
] = CC_OSZAPC
,
4321 [INDEX_op_movb_eflags_T0
] = CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
,
4322 [INDEX_op_movw_eflags_T0
] = CC_OSZAPC
,
4323 [INDEX_op_movl_eflags_T0
] = CC_OSZAPC
,
4324 [INDEX_op_movw_eflags_T0_io
] = CC_OSZAPC
,
4325 [INDEX_op_movl_eflags_T0_io
] = CC_OSZAPC
,
4326 [INDEX_op_movw_eflags_T0_cpl0
] = CC_OSZAPC
,
4327 [INDEX_op_movl_eflags_T0_cpl0
] = CC_OSZAPC
,
4328 [INDEX_op_clc
] = CC_C
,
4329 [INDEX_op_stc
] = CC_C
,
4330 [INDEX_op_cmc
] = CC_C
,
4332 [INDEX_op_btw_T0_T1_cc
] = CC_OSZAPC
,
4333 [INDEX_op_btl_T0_T1_cc
] = CC_OSZAPC
,
4334 [INDEX_op_btsw_T0_T1_cc
] = CC_OSZAPC
,
4335 [INDEX_op_btsl_T0_T1_cc
] = CC_OSZAPC
,
4336 [INDEX_op_btrw_T0_T1_cc
] = CC_OSZAPC
,
4337 [INDEX_op_btrl_T0_T1_cc
] = CC_OSZAPC
,
4338 [INDEX_op_btcw_T0_T1_cc
] = CC_OSZAPC
,
4339 [INDEX_op_btcl_T0_T1_cc
] = CC_OSZAPC
,
4341 [INDEX_op_bsfw_T0_cc
] = CC_OSZAPC
,
4342 [INDEX_op_bsfl_T0_cc
] = CC_OSZAPC
,
4343 [INDEX_op_bsrw_T0_cc
] = CC_OSZAPC
,
4344 [INDEX_op_bsrl_T0_cc
] = CC_OSZAPC
,
4346 [INDEX_op_cmpxchgb_T0_T1_EAX_cc
] = CC_OSZAPC
,
4347 [INDEX_op_cmpxchgw_T0_T1_EAX_cc
] = CC_OSZAPC
,
4348 [INDEX_op_cmpxchgl_T0_T1_EAX_cc
] = CC_OSZAPC
,
4350 [INDEX_op_cmpxchg8b
] = CC_Z
,
4351 [INDEX_op_lar
] = CC_Z
,
4352 [INDEX_op_lsl
] = CC_Z
,
4353 [INDEX_op_fcomi_ST0_FT0
] = CC_Z
| CC_P
| CC_C
,
4354 [INDEX_op_fucomi_ST0_FT0
] = CC_Z
| CC_P
| CC_C
,
4356 #define DEF_WRITEF(SUFFIX)\
4357 [INDEX_op_adcb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4358 [INDEX_op_adcw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4359 [INDEX_op_adcl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4360 [INDEX_op_sbbb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4361 [INDEX_op_sbbw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4362 [INDEX_op_sbbl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4364 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4365 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4366 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4367 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4368 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4369 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4371 [INDEX_op_rclb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4372 [INDEX_op_rclw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4373 [INDEX_op_rcll ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4374 [INDEX_op_rcrb ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4375 [INDEX_op_rcrw ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4376 [INDEX_op_rcrl ## SUFFIX ## _T0_T1_cc] = CC_O | CC_C,\
4378 [INDEX_op_shlb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4379 [INDEX_op_shlw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4380 [INDEX_op_shll ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4382 [INDEX_op_shrb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4383 [INDEX_op_shrw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4384 [INDEX_op_shrl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4386 [INDEX_op_sarb ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4387 [INDEX_op_sarw ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4388 [INDEX_op_sarl ## SUFFIX ## _T0_T1_cc] = CC_OSZAPC,\
4390 [INDEX_op_shldw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4391 [INDEX_op_shldl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4392 [INDEX_op_shldw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4393 [INDEX_op_shldl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4395 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4396 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_ECX_cc] = CC_OSZAPC,\
4397 [INDEX_op_shrdw ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4398 [INDEX_op_shrdl ## SUFFIX ## _T0_T1_im_cc] = CC_OSZAPC,\
4400 [INDEX_op_cmpxchgb ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4401 [INDEX_op_cmpxchgw ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,\
4402 [INDEX_op_cmpxchgl ## SUFFIX ## _T0_T1_EAX_cc] = CC_OSZAPC,
4407 #ifndef CONFIG_USER_ONLY
4413 /* simpler form of an operation if no flags need to be generated */
4414 static uint16_t opc_simpler
[NB_OPS
] = {
4415 [INDEX_op_update2_cc
] = INDEX_op_nop
,
4416 [INDEX_op_update1_cc
] = INDEX_op_nop
,
4417 [INDEX_op_update_neg_cc
] = INDEX_op_nop
,
4419 /* broken: CC_OP logic must be rewritten */
4420 [INDEX_op_update_inc_cc
] = INDEX_op_nop
,
4423 [INDEX_op_shlb_T0_T1_cc
] = INDEX_op_shlb_T0_T1
,
4424 [INDEX_op_shlw_T0_T1_cc
] = INDEX_op_shlw_T0_T1
,
4425 [INDEX_op_shll_T0_T1_cc
] = INDEX_op_shll_T0_T1
,
4427 [INDEX_op_shrb_T0_T1_cc
] = INDEX_op_shrb_T0_T1
,
4428 [INDEX_op_shrw_T0_T1_cc
] = INDEX_op_shrw_T0_T1
,
4429 [INDEX_op_shrl_T0_T1_cc
] = INDEX_op_shrl_T0_T1
,
4431 [INDEX_op_sarb_T0_T1_cc
] = INDEX_op_sarb_T0_T1
,
4432 [INDEX_op_sarw_T0_T1_cc
] = INDEX_op_sarw_T0_T1
,
4433 [INDEX_op_sarl_T0_T1_cc
] = INDEX_op_sarl_T0_T1
,
4435 #define DEF_SIMPLER(SUFFIX)\
4436 [INDEX_op_rolb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolb ## SUFFIX ## _T0_T1,\
4437 [INDEX_op_rolw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rolw ## SUFFIX ## _T0_T1,\
4438 [INDEX_op_roll ## SUFFIX ## _T0_T1_cc] = INDEX_op_roll ## SUFFIX ## _T0_T1,\
4440 [INDEX_op_rorb ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorb ## SUFFIX ## _T0_T1,\
4441 [INDEX_op_rorw ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorw ## SUFFIX ## _T0_T1,\
4442 [INDEX_op_rorl ## SUFFIX ## _T0_T1_cc] = INDEX_op_rorl ## SUFFIX ## _T0_T1,
4446 #ifndef CONFIG_USER_ONLY
4447 DEF_SIMPLER(_kernel
)
4452 void optimize_flags_init(void)
4455 /* put default values in arrays */
4456 for(i
= 0; i
< NB_OPS
; i
++) {
4457 if (opc_simpler
[i
] == 0)
4462 /* CPU flags computation optimization: we move backward thru the
4463 generated code to see which flags are needed. The operation is
4464 modified if suitable */
4465 static void optimize_flags(uint16_t *opc_buf
, int opc_buf_len
)
4468 int live_flags
, write_flags
, op
;
4470 opc_ptr
= opc_buf
+ opc_buf_len
;
4471 /* live_flags contains the flags needed by the next instructions
4472 in the code. At the end of the bloc, we consider that all the
4474 live_flags
= CC_OSZAPC
;
4475 while (opc_ptr
> opc_buf
) {
4477 /* if none of the flags written by the instruction is used,
4478 then we can try to find a simpler instruction */
4479 write_flags
= opc_write_flags
[op
];
4480 if ((live_flags
& write_flags
) == 0) {
4481 *opc_ptr
= opc_simpler
[op
];
4483 /* compute the live flags before the instruction */
4484 live_flags
&= ~write_flags
;
4485 live_flags
|= opc_read_flags
[op
];
4489 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4490 basic block 'tb'. If search_pc is TRUE, also generate PC
4491 information for each intermediate instruction. */
4492 static inline int gen_intermediate_code_internal(CPUState
*env
,
4493 TranslationBlock
*tb
,
4496 DisasContext dc1
, *dc
= &dc1
;
4498 uint16_t *gen_opc_end
;
4499 int flags
, j
, lj
, cflags
;
4503 /* generate intermediate code */
4504 pc_start
= (uint8_t *)tb
->pc
;
4505 cs_base
= (uint8_t *)tb
->cs_base
;
4507 cflags
= tb
->cflags
;
4509 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
4510 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
4511 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
4512 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
4514 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
4515 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
4516 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
4517 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
4518 dc
->singlestep_enabled
= env
->singlestep_enabled
;
4519 dc
->cc_op
= CC_OP_DYNAMIC
;
4520 dc
->cs_base
= cs_base
;
4522 dc
->popl_esp_hack
= 0;
4523 /* select memory access functions */
4525 if (flags
& HF_SOFTMMU_MASK
) {
4532 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
4533 (flags
& HF_INHIBIT_IRQ_MASK
)
4534 #ifndef CONFIG_SOFTMMU
4535 || (flags
& HF_SOFTMMU_MASK
)
4539 /* check addseg logic */
4540 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
))
4541 printf("ERROR addseg\n");
4544 gen_opc_ptr
= gen_opc_buf
;
4545 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
4546 gen_opparam_ptr
= gen_opparam_buf
;
4548 dc
->is_jmp
= DISAS_NEXT
;
4553 if (env
->nb_breakpoints
> 0) {
4554 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
4555 if (env
->breakpoints
[j
] == (unsigned long)pc_ptr
) {
4556 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
4562 j
= gen_opc_ptr
- gen_opc_buf
;
4566 gen_opc_instr_start
[lj
++] = 0;
4568 gen_opc_pc
[lj
] = (uint32_t)pc_ptr
;
4569 gen_opc_cc_op
[lj
] = dc
->cc_op
;
4570 gen_opc_instr_start
[lj
] = 1;
4572 pc_ptr
= disas_insn(dc
, pc_ptr
);
4573 /* stop translation if indicated */
4576 /* if single step mode, we generate only one instruction and
4577 generate an exception */
4578 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4579 the flag and abort the translation to give the irqs a
4580 change to be happen */
4581 if (dc
->tf
|| dc
->singlestep_enabled
||
4582 (flags
& HF_INHIBIT_IRQ_MASK
) ||
4583 (cflags
& CF_SINGLE_INSN
)) {
4584 gen_op_jmp_im(pc_ptr
- dc
->cs_base
);
4588 /* if too long translation, stop generation too */
4589 if (gen_opc_ptr
>= gen_opc_end
||
4590 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32)) {
4591 gen_op_jmp_im(pc_ptr
- dc
->cs_base
);
4596 *gen_opc_ptr
= INDEX_op_end
;
4597 /* we don't forget to fill the last values */
4599 j
= gen_opc_ptr
- gen_opc_buf
;
4602 gen_opc_instr_start
[lj
++] = 0;
4606 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
4607 fprintf(logfile
, "----------------\n");
4608 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
4609 disas(logfile
, pc_start
, pc_ptr
- pc_start
, 0, !dc
->code32
);
4610 fprintf(logfile
, "\n");
4611 if (loglevel
& CPU_LOG_TB_OP
) {
4612 fprintf(logfile
, "OP:\n");
4613 dump_ops(gen_opc_buf
, gen_opparam_buf
);
4614 fprintf(logfile
, "\n");
4619 /* optimize flag computations */
4620 optimize_flags(gen_opc_buf
, gen_opc_ptr
- gen_opc_buf
);
4623 if (loglevel
& CPU_LOG_TB_OP_OPT
) {
4624 fprintf(logfile
, "AFTER FLAGS OPT:\n");
4625 dump_ops(gen_opc_buf
, gen_opparam_buf
);
4626 fprintf(logfile
, "\n");
4630 tb
->size
= pc_ptr
- pc_start
;
4634 int gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
4636 return gen_intermediate_code_internal(env
, tb
, 0);
4639 int gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
4641 return gen_intermediate_code_internal(env
, tb
, 1);