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proper helper definition registering (all targets must do that)
[qemu.git] / target-i386 / translate.c
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27
28 #include "cpu.h"
29 #include "exec-all.h"
30 #include "disas.h"
31 #include "helper.h"
32 #include "tcg-op.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
47 #if 1
48 #define BUGGY_64(x) NULL
49 #endif
50 #else
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
53 #define CODE64(s) 0
54 #define REX_X(s) 0
55 #define REX_B(s) 0
56 #endif
57
58 //#define MACRO_TEST 1
59
60 /* global register indexes */
61 static TCGv cpu_env, cpu_T[2], cpu_A0, cpu_cc_op, cpu_cc_src, cpu_cc_dst;
62 static TCGv cpu_T3;
63 /* local register indexes (only used inside old micro ops) */
64 static TCGv cpu_tmp0, cpu_tmp1_i64, cpu_tmp2_i32, cpu_tmp3_i32, cpu_tmp4, cpu_ptr0, cpu_ptr1;
65 static TCGv cpu_tmp5, cpu_tmp6;
66
67 #ifdef TARGET_X86_64
68 static int x86_64_hregs;
69 #endif
70
71 typedef struct DisasContext {
72 /* current insn context */
73 int override; /* -1 if no override */
74 int prefix;
75 int aflag, dflag;
76 target_ulong pc; /* pc = eip + cs_base */
77 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
78 static state change (stop translation) */
79 /* current block context */
80 target_ulong cs_base; /* base of CS segment */
81 int pe; /* protected mode */
82 int code32; /* 32 bit code segment */
83 #ifdef TARGET_X86_64
84 int lma; /* long mode active */
85 int code64; /* 64 bit code segment */
86 int rex_x, rex_b;
87 #endif
88 int ss32; /* 32 bit stack segment */
89 int cc_op; /* current CC operation */
90 int addseg; /* non zero if either DS/ES/SS have a non zero base */
91 int f_st; /* currently unused */
92 int vm86; /* vm86 mode */
93 int cpl;
94 int iopl;
95 int tf; /* TF cpu flag */
96 int singlestep_enabled; /* "hardware" single step enabled */
97 int jmp_opt; /* use direct block chaining for direct jumps */
98 int mem_index; /* select memory access functions */
99 uint64_t flags; /* all execution flags */
100 struct TranslationBlock *tb;
101 int popl_esp_hack; /* for correct popl with esp base handling */
102 int rip_offset; /* only used in x86_64, but left for simplicity */
103 int cpuid_features;
104 int cpuid_ext_features;
105 int cpuid_ext2_features;
106 int cpuid_ext3_features;
107 } DisasContext;
108
109 static void gen_eob(DisasContext *s);
110 static void gen_jmp(DisasContext *s, target_ulong eip);
111 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
112
113 /* i386 arith/logic operations */
114 enum {
115 OP_ADDL,
116 OP_ORL,
117 OP_ADCL,
118 OP_SBBL,
119 OP_ANDL,
120 OP_SUBL,
121 OP_XORL,
122 OP_CMPL,
123 };
124
125 /* i386 shift ops */
126 enum {
127 OP_ROL,
128 OP_ROR,
129 OP_RCL,
130 OP_RCR,
131 OP_SHL,
132 OP_SHR,
133 OP_SHL1, /* undocumented */
134 OP_SAR = 7,
135 };
136
137 enum {
138 JCC_O,
139 JCC_B,
140 JCC_Z,
141 JCC_BE,
142 JCC_S,
143 JCC_P,
144 JCC_L,
145 JCC_LE,
146 };
147
148 /* operand size */
149 enum {
150 OT_BYTE = 0,
151 OT_WORD,
152 OT_LONG,
153 OT_QUAD,
154 };
155
156 enum {
157 /* I386 int registers */
158 OR_EAX, /* MUST be even numbered */
159 OR_ECX,
160 OR_EDX,
161 OR_EBX,
162 OR_ESP,
163 OR_EBP,
164 OR_ESI,
165 OR_EDI,
166
167 OR_TMP0 = 16, /* temporary operand register */
168 OR_TMP1,
169 OR_A0, /* temporary register used when doing address evaluation */
170 };
171
172 static inline void gen_op_movl_T0_0(void)
173 {
174 tcg_gen_movi_tl(cpu_T[0], 0);
175 }
176
177 static inline void gen_op_movl_T0_im(int32_t val)
178 {
179 tcg_gen_movi_tl(cpu_T[0], val);
180 }
181
182 static inline void gen_op_movl_T0_imu(uint32_t val)
183 {
184 tcg_gen_movi_tl(cpu_T[0], val);
185 }
186
187 static inline void gen_op_movl_T1_im(int32_t val)
188 {
189 tcg_gen_movi_tl(cpu_T[1], val);
190 }
191
192 static inline void gen_op_movl_T1_imu(uint32_t val)
193 {
194 tcg_gen_movi_tl(cpu_T[1], val);
195 }
196
197 static inline void gen_op_movl_A0_im(uint32_t val)
198 {
199 tcg_gen_movi_tl(cpu_A0, val);
200 }
201
202 #ifdef TARGET_X86_64
203 static inline void gen_op_movq_A0_im(int64_t val)
204 {
205 tcg_gen_movi_tl(cpu_A0, val);
206 }
207 #endif
208
209 static inline void gen_movtl_T0_im(target_ulong val)
210 {
211 tcg_gen_movi_tl(cpu_T[0], val);
212 }
213
214 static inline void gen_movtl_T1_im(target_ulong val)
215 {
216 tcg_gen_movi_tl(cpu_T[1], val);
217 }
218
219 static inline void gen_op_andl_T0_ffff(void)
220 {
221 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
222 }
223
224 static inline void gen_op_andl_T0_im(uint32_t val)
225 {
226 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
227 }
228
229 static inline void gen_op_movl_T0_T1(void)
230 {
231 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
232 }
233
234 static inline void gen_op_andl_A0_ffff(void)
235 {
236 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
237 }
238
239 #ifdef TARGET_X86_64
240
241 #define NB_OP_SIZES 4
242
243 #else /* !TARGET_X86_64 */
244
245 #define NB_OP_SIZES 3
246
247 #endif /* !TARGET_X86_64 */
248
249 #if defined(WORDS_BIGENDIAN)
250 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
251 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
252 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
253 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
254 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
255 #else
256 #define REG_B_OFFSET 0
257 #define REG_H_OFFSET 1
258 #define REG_W_OFFSET 0
259 #define REG_L_OFFSET 0
260 #define REG_LH_OFFSET 4
261 #endif
262
263 static inline void gen_op_mov_reg_TN(int ot, int t_index, int reg)
264 {
265 switch(ot) {
266 case OT_BYTE:
267 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
268 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);
269 } else {
270 tcg_gen_st8_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
271 }
272 break;
273 case OT_WORD:
274 tcg_gen_st16_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
275 break;
276 #ifdef TARGET_X86_64
277 case OT_LONG:
278 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
279 /* high part of register set to zero */
280 tcg_gen_movi_tl(cpu_tmp0, 0);
281 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
282 break;
283 default:
284 case OT_QUAD:
285 tcg_gen_st_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
286 break;
287 #else
288 default:
289 case OT_LONG:
290 tcg_gen_st32_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
291 break;
292 #endif
293 }
294 }
295
296 static inline void gen_op_mov_reg_T0(int ot, int reg)
297 {
298 gen_op_mov_reg_TN(ot, 0, reg);
299 }
300
301 static inline void gen_op_mov_reg_T1(int ot, int reg)
302 {
303 gen_op_mov_reg_TN(ot, 1, reg);
304 }
305
306 static inline void gen_op_mov_reg_A0(int size, int reg)
307 {
308 switch(size) {
309 case 0:
310 tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
311 break;
312 #ifdef TARGET_X86_64
313 case 1:
314 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
315 /* high part of register set to zero */
316 tcg_gen_movi_tl(cpu_tmp0, 0);
317 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
318 break;
319 default:
320 case 2:
321 tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
322 break;
323 #else
324 default:
325 case 1:
326 tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
327 break;
328 #endif
329 }
330 }
331
332 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
333 {
334 switch(ot) {
335 case OT_BYTE:
336 if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {
337 goto std_case;
338 } else {
339 tcg_gen_ld8u_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);
340 }
341 break;
342 default:
343 std_case:
344 tcg_gen_ld_tl(cpu_T[t_index], cpu_env, offsetof(CPUState, regs[reg]));
345 break;
346 }
347 }
348
349 static inline void gen_op_movl_A0_reg(int reg)
350 {
351 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
352 }
353
354 static inline void gen_op_addl_A0_im(int32_t val)
355 {
356 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
357 #ifdef TARGET_X86_64
358 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
359 #endif
360 }
361
362 #ifdef TARGET_X86_64
363 static inline void gen_op_addq_A0_im(int64_t val)
364 {
365 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
366 }
367 #endif
368
369 static void gen_add_A0_im(DisasContext *s, int val)
370 {
371 #ifdef TARGET_X86_64
372 if (CODE64(s))
373 gen_op_addq_A0_im(val);
374 else
375 #endif
376 gen_op_addl_A0_im(val);
377 }
378
379 static inline void gen_op_addl_T0_T1(void)
380 {
381 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
382 }
383
384 static inline void gen_op_jmp_T0(void)
385 {
386 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));
387 }
388
389 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
390 {
391 switch(size) {
392 case 0:
393 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
394 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
395 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
396 break;
397 case 1:
398 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
399 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
400 #ifdef TARGET_X86_64
401 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
402 #endif
403 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
404 break;
405 #ifdef TARGET_X86_64
406 case 2:
407 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
408 tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);
409 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
410 break;
411 #endif
412 }
413 }
414
415 static inline void gen_op_add_reg_T0(int size, int reg)
416 {
417 switch(size) {
418 case 0:
419 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
420 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
421 tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);
422 break;
423 case 1:
424 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
425 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
426 #ifdef TARGET_X86_64
427 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);
428 #endif
429 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
430 break;
431 #ifdef TARGET_X86_64
432 case 2:
433 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
434 tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);
435 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
436 break;
437 #endif
438 }
439 }
440
441 static inline void gen_op_set_cc_op(int32_t val)
442 {
443 tcg_gen_movi_i32(cpu_cc_op, val);
444 }
445
446 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
447 {
448 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
449 if (shift != 0)
450 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
451 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
452 #ifdef TARGET_X86_64
453 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
454 #endif
455 }
456
457 static inline void gen_op_movl_A0_seg(int reg)
458 {
459 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);
460 }
461
462 static inline void gen_op_addl_A0_seg(int reg)
463 {
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
465 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
466 #ifdef TARGET_X86_64
467 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
468 #endif
469 }
470
471 #ifdef TARGET_X86_64
472 static inline void gen_op_movq_A0_seg(int reg)
473 {
474 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));
475 }
476
477 static inline void gen_op_addq_A0_seg(int reg)
478 {
479 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));
480 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
481 }
482
483 static inline void gen_op_movq_A0_reg(int reg)
484 {
485 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));
486 }
487
488 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
489 {
490 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));
491 if (shift != 0)
492 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
493 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
494 }
495 #endif
496
497 static inline void gen_op_lds_T0_A0(int idx)
498 {
499 int mem_index = (idx >> 2) - 1;
500 switch(idx & 3) {
501 case 0:
502 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
503 break;
504 case 1:
505 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
506 break;
507 default:
508 case 2:
509 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
510 break;
511 }
512 }
513
514 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
515 static inline void gen_op_ld_T0_A0(int idx)
516 {
517 int mem_index = (idx >> 2) - 1;
518 switch(idx & 3) {
519 case 0:
520 tcg_gen_qemu_ld8u(cpu_T[0], cpu_A0, mem_index);
521 break;
522 case 1:
523 tcg_gen_qemu_ld16u(cpu_T[0], cpu_A0, mem_index);
524 break;
525 case 2:
526 tcg_gen_qemu_ld32u(cpu_T[0], cpu_A0, mem_index);
527 break;
528 default:
529 case 3:
530 tcg_gen_qemu_ld64(cpu_T[0], cpu_A0, mem_index);
531 break;
532 }
533 }
534
535 static inline void gen_op_ldu_T0_A0(int idx)
536 {
537 gen_op_ld_T0_A0(idx);
538 }
539
540 static inline void gen_op_ld_T1_A0(int idx)
541 {
542 int mem_index = (idx >> 2) - 1;
543 switch(idx & 3) {
544 case 0:
545 tcg_gen_qemu_ld8u(cpu_T[1], cpu_A0, mem_index);
546 break;
547 case 1:
548 tcg_gen_qemu_ld16u(cpu_T[1], cpu_A0, mem_index);
549 break;
550 case 2:
551 tcg_gen_qemu_ld32u(cpu_T[1], cpu_A0, mem_index);
552 break;
553 default:
554 case 3:
555 tcg_gen_qemu_ld64(cpu_T[1], cpu_A0, mem_index);
556 break;
557 }
558 }
559
560 static inline void gen_op_st_T0_A0(int idx)
561 {
562 int mem_index = (idx >> 2) - 1;
563 switch(idx & 3) {
564 case 0:
565 tcg_gen_qemu_st8(cpu_T[0], cpu_A0, mem_index);
566 break;
567 case 1:
568 tcg_gen_qemu_st16(cpu_T[0], cpu_A0, mem_index);
569 break;
570 case 2:
571 tcg_gen_qemu_st32(cpu_T[0], cpu_A0, mem_index);
572 break;
573 default:
574 case 3:
575 tcg_gen_qemu_st64(cpu_T[0], cpu_A0, mem_index);
576 break;
577 }
578 }
579
580 static inline void gen_op_st_T1_A0(int idx)
581 {
582 int mem_index = (idx >> 2) - 1;
583 switch(idx & 3) {
584 case 0:
585 tcg_gen_qemu_st8(cpu_T[1], cpu_A0, mem_index);
586 break;
587 case 1:
588 tcg_gen_qemu_st16(cpu_T[1], cpu_A0, mem_index);
589 break;
590 case 2:
591 tcg_gen_qemu_st32(cpu_T[1], cpu_A0, mem_index);
592 break;
593 default:
594 case 3:
595 tcg_gen_qemu_st64(cpu_T[1], cpu_A0, mem_index);
596 break;
597 }
598 }
599
600 static inline void gen_jmp_im(target_ulong pc)
601 {
602 tcg_gen_movi_tl(cpu_tmp0, pc);
603 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));
604 }
605
606 static inline void gen_string_movl_A0_ESI(DisasContext *s)
607 {
608 int override;
609
610 override = s->override;
611 #ifdef TARGET_X86_64
612 if (s->aflag == 2) {
613 if (override >= 0) {
614 gen_op_movq_A0_seg(override);
615 gen_op_addq_A0_reg_sN(0, R_ESI);
616 } else {
617 gen_op_movq_A0_reg(R_ESI);
618 }
619 } else
620 #endif
621 if (s->aflag) {
622 /* 32 bit address */
623 if (s->addseg && override < 0)
624 override = R_DS;
625 if (override >= 0) {
626 gen_op_movl_A0_seg(override);
627 gen_op_addl_A0_reg_sN(0, R_ESI);
628 } else {
629 gen_op_movl_A0_reg(R_ESI);
630 }
631 } else {
632 /* 16 address, always override */
633 if (override < 0)
634 override = R_DS;
635 gen_op_movl_A0_reg(R_ESI);
636 gen_op_andl_A0_ffff();
637 gen_op_addl_A0_seg(override);
638 }
639 }
640
641 static inline void gen_string_movl_A0_EDI(DisasContext *s)
642 {
643 #ifdef TARGET_X86_64
644 if (s->aflag == 2) {
645 gen_op_movq_A0_reg(R_EDI);
646 } else
647 #endif
648 if (s->aflag) {
649 if (s->addseg) {
650 gen_op_movl_A0_seg(R_ES);
651 gen_op_addl_A0_reg_sN(0, R_EDI);
652 } else {
653 gen_op_movl_A0_reg(R_EDI);
654 }
655 } else {
656 gen_op_movl_A0_reg(R_EDI);
657 gen_op_andl_A0_ffff();
658 gen_op_addl_A0_seg(R_ES);
659 }
660 }
661
662 static inline void gen_op_movl_T0_Dshift(int ot)
663 {
664 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));
665 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
666 };
667
668 static void gen_extu(int ot, TCGv reg)
669 {
670 switch(ot) {
671 case OT_BYTE:
672 tcg_gen_ext8u_tl(reg, reg);
673 break;
674 case OT_WORD:
675 tcg_gen_ext16u_tl(reg, reg);
676 break;
677 case OT_LONG:
678 tcg_gen_ext32u_tl(reg, reg);
679 break;
680 default:
681 break;
682 }
683 }
684
685 static void gen_exts(int ot, TCGv reg)
686 {
687 switch(ot) {
688 case OT_BYTE:
689 tcg_gen_ext8s_tl(reg, reg);
690 break;
691 case OT_WORD:
692 tcg_gen_ext16s_tl(reg, reg);
693 break;
694 case OT_LONG:
695 tcg_gen_ext32s_tl(reg, reg);
696 break;
697 default:
698 break;
699 }
700 }
701
702 static inline void gen_op_jnz_ecx(int size, int label1)
703 {
704 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
705 gen_extu(size + 1, cpu_tmp0);
706 tcg_gen_brcond_tl(TCG_COND_NE, cpu_tmp0, tcg_const_tl(0), label1);
707 }
708
709 static inline void gen_op_jz_ecx(int size, int label1)
710 {
711 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));
712 gen_extu(size + 1, cpu_tmp0);
713 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1);
714 }
715
716 static void *helper_in_func[3] = {
717 helper_inb,
718 helper_inw,
719 helper_inl,
720 };
721
722 static void *helper_out_func[3] = {
723 helper_outb,
724 helper_outw,
725 helper_outl,
726 };
727
728 static void *gen_check_io_func[3] = {
729 helper_check_iob,
730 helper_check_iow,
731 helper_check_iol,
732 };
733
734 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
735 uint32_t svm_flags)
736 {
737 int state_saved;
738 target_ulong next_eip;
739
740 state_saved = 0;
741 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
742 if (s->cc_op != CC_OP_DYNAMIC)
743 gen_op_set_cc_op(s->cc_op);
744 gen_jmp_im(cur_eip);
745 state_saved = 1;
746 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
747 tcg_gen_helper_0_1(gen_check_io_func[ot],
748 cpu_tmp2_i32);
749 }
750 if(s->flags & (1ULL << INTERCEPT_IOIO_PROT)) {
751 if (!state_saved) {
752 if (s->cc_op != CC_OP_DYNAMIC)
753 gen_op_set_cc_op(s->cc_op);
754 gen_jmp_im(cur_eip);
755 state_saved = 1;
756 }
757 svm_flags |= (1 << (4 + ot));
758 next_eip = s->pc - s->cs_base;
759 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
760 tcg_gen_helper_0_3(helper_svm_check_io,
761 cpu_tmp2_i32,
762 tcg_const_i32(svm_flags),
763 tcg_const_i32(next_eip - cur_eip));
764 }
765 }
766
767 static inline void gen_movs(DisasContext *s, int ot)
768 {
769 gen_string_movl_A0_ESI(s);
770 gen_op_ld_T0_A0(ot + s->mem_index);
771 gen_string_movl_A0_EDI(s);
772 gen_op_st_T0_A0(ot + s->mem_index);
773 gen_op_movl_T0_Dshift(ot);
774 gen_op_add_reg_T0(s->aflag, R_ESI);
775 gen_op_add_reg_T0(s->aflag, R_EDI);
776 }
777
778 static inline void gen_update_cc_op(DisasContext *s)
779 {
780 if (s->cc_op != CC_OP_DYNAMIC) {
781 gen_op_set_cc_op(s->cc_op);
782 s->cc_op = CC_OP_DYNAMIC;
783 }
784 }
785
786 static void gen_op_update1_cc(void)
787 {
788 tcg_gen_discard_tl(cpu_cc_src);
789 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
790 }
791
792 static void gen_op_update2_cc(void)
793 {
794 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
795 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
796 }
797
798 static inline void gen_op_cmpl_T0_T1_cc(void)
799 {
800 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
801 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
802 }
803
804 static inline void gen_op_testl_T0_T1_cc(void)
805 {
806 tcg_gen_discard_tl(cpu_cc_src);
807 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
808 }
809
810 static void gen_op_update_neg_cc(void)
811 {
812 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
813 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
814 }
815
816 /* compute eflags.C to reg */
817 static void gen_compute_eflags_c(TCGv reg)
818 {
819 #if TCG_TARGET_REG_BITS == 32
820 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
821 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
822 (long)cc_table + offsetof(CCTable, compute_c));
823 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
824 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
825 1, &cpu_tmp2_i32, 0, NULL);
826 #else
827 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
828 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
829 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
830 (long)cc_table + offsetof(CCTable, compute_c));
831 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
832 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
833 1, &cpu_tmp2_i32, 0, NULL);
834 #endif
835 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
836 }
837
838 /* compute all eflags to cc_src */
839 static void gen_compute_eflags(TCGv reg)
840 {
841 #if TCG_TARGET_REG_BITS == 32
842 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3);
843 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32,
844 (long)cc_table + offsetof(CCTable, compute_all));
845 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0);
846 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE,
847 1, &cpu_tmp2_i32, 0, NULL);
848 #else
849 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op);
850 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4);
851 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64,
852 (long)cc_table + offsetof(CCTable, compute_all));
853 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0);
854 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE,
855 1, &cpu_tmp2_i32, 0, NULL);
856 #endif
857 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
858 }
859
860 static inline void gen_setcc_slow_T0(int op)
861 {
862 switch(op) {
863 case JCC_O:
864 gen_compute_eflags(cpu_T[0]);
865 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
866 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
867 break;
868 case JCC_B:
869 gen_compute_eflags_c(cpu_T[0]);
870 break;
871 case JCC_Z:
872 gen_compute_eflags(cpu_T[0]);
873 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
874 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
875 break;
876 case JCC_BE:
877 gen_compute_eflags(cpu_tmp0);
878 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
879 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
880 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
881 break;
882 case JCC_S:
883 gen_compute_eflags(cpu_T[0]);
884 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
885 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
886 break;
887 case JCC_P:
888 gen_compute_eflags(cpu_T[0]);
889 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
890 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
891 break;
892 case JCC_L:
893 gen_compute_eflags(cpu_tmp0);
894 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
895 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
896 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
897 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
898 break;
899 default:
900 case JCC_LE:
901 gen_compute_eflags(cpu_tmp0);
902 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
903 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
904 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
905 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
906 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
907 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
908 break;
909 }
910 }
911
912 /* return true if setcc_slow is not needed (WARNING: must be kept in
913 sync with gen_jcc1) */
914 static int is_fast_jcc_case(DisasContext *s, int b)
915 {
916 int jcc_op;
917 jcc_op = (b >> 1) & 7;
918 switch(s->cc_op) {
919 /* we optimize the cmp/jcc case */
920 case CC_OP_SUBB:
921 case CC_OP_SUBW:
922 case CC_OP_SUBL:
923 case CC_OP_SUBQ:
924 if (jcc_op == JCC_O || jcc_op == JCC_P)
925 goto slow_jcc;
926 break;
927
928 /* some jumps are easy to compute */
929 case CC_OP_ADDB:
930 case CC_OP_ADDW:
931 case CC_OP_ADDL:
932 case CC_OP_ADDQ:
933
934 case CC_OP_LOGICB:
935 case CC_OP_LOGICW:
936 case CC_OP_LOGICL:
937 case CC_OP_LOGICQ:
938
939 case CC_OP_INCB:
940 case CC_OP_INCW:
941 case CC_OP_INCL:
942 case CC_OP_INCQ:
943
944 case CC_OP_DECB:
945 case CC_OP_DECW:
946 case CC_OP_DECL:
947 case CC_OP_DECQ:
948
949 case CC_OP_SHLB:
950 case CC_OP_SHLW:
951 case CC_OP_SHLL:
952 case CC_OP_SHLQ:
953 if (jcc_op != JCC_Z && jcc_op != JCC_S)
954 goto slow_jcc;
955 break;
956 default:
957 slow_jcc:
958 return 0;
959 }
960 return 1;
961 }
962
963 /* generate a conditional jump to label 'l1' according to jump opcode
964 value 'b'. In the fast case, T0 is guaranted not to be used. */
965 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
966 {
967 int inv, jcc_op, size, cond;
968 TCGv t0;
969
970 inv = b & 1;
971 jcc_op = (b >> 1) & 7;
972
973 switch(cc_op) {
974 /* we optimize the cmp/jcc case */
975 case CC_OP_SUBB:
976 case CC_OP_SUBW:
977 case CC_OP_SUBL:
978 case CC_OP_SUBQ:
979
980 size = cc_op - CC_OP_SUBB;
981 switch(jcc_op) {
982 case JCC_Z:
983 fast_jcc_z:
984 switch(size) {
985 case 0:
986 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
987 t0 = cpu_tmp0;
988 break;
989 case 1:
990 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
991 t0 = cpu_tmp0;
992 break;
993 #ifdef TARGET_X86_64
994 case 2:
995 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
996 t0 = cpu_tmp0;
997 break;
998 #endif
999 default:
1000 t0 = cpu_cc_dst;
1001 break;
1002 }
1003 tcg_gen_brcond_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0,
1004 tcg_const_tl(0), l1);
1005 break;
1006 case JCC_S:
1007 fast_jcc_s:
1008 switch(size) {
1009 case 0:
1010 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
1011 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1012 tcg_const_tl(0), l1);
1013 break;
1014 case 1:
1015 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
1016 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1017 tcg_const_tl(0), l1);
1018 break;
1019 #ifdef TARGET_X86_64
1020 case 2:
1021 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
1022 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
1023 tcg_const_tl(0), l1);
1024 break;
1025 #endif
1026 default:
1027 tcg_gen_brcond_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1028 tcg_const_tl(0), l1);
1029 break;
1030 }
1031 break;
1032
1033 case JCC_B:
1034 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1035 goto fast_jcc_b;
1036 case JCC_BE:
1037 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1038 fast_jcc_b:
1039 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1040 switch(size) {
1041 case 0:
1042 t0 = cpu_tmp0;
1043 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1044 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1045 break;
1046 case 1:
1047 t0 = cpu_tmp0;
1048 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1049 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1050 break;
1051 #ifdef TARGET_X86_64
1052 case 2:
1053 t0 = cpu_tmp0;
1054 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1055 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1056 break;
1057 #endif
1058 default:
1059 t0 = cpu_cc_src;
1060 break;
1061 }
1062 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1063 break;
1064
1065 case JCC_L:
1066 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1067 goto fast_jcc_l;
1068 case JCC_LE:
1069 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1070 fast_jcc_l:
1071 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1072 switch(size) {
1073 case 0:
1074 t0 = cpu_tmp0;
1075 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1076 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1077 break;
1078 case 1:
1079 t0 = cpu_tmp0;
1080 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1081 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1082 break;
1083 #ifdef TARGET_X86_64
1084 case 2:
1085 t0 = cpu_tmp0;
1086 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1087 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1088 break;
1089 #endif
1090 default:
1091 t0 = cpu_cc_src;
1092 break;
1093 }
1094 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1095 break;
1096
1097 default:
1098 goto slow_jcc;
1099 }
1100 break;
1101
1102 /* some jumps are easy to compute */
1103 case CC_OP_ADDB:
1104 case CC_OP_ADDW:
1105 case CC_OP_ADDL:
1106 case CC_OP_ADDQ:
1107
1108 case CC_OP_ADCB:
1109 case CC_OP_ADCW:
1110 case CC_OP_ADCL:
1111 case CC_OP_ADCQ:
1112
1113 case CC_OP_SBBB:
1114 case CC_OP_SBBW:
1115 case CC_OP_SBBL:
1116 case CC_OP_SBBQ:
1117
1118 case CC_OP_LOGICB:
1119 case CC_OP_LOGICW:
1120 case CC_OP_LOGICL:
1121 case CC_OP_LOGICQ:
1122
1123 case CC_OP_INCB:
1124 case CC_OP_INCW:
1125 case CC_OP_INCL:
1126 case CC_OP_INCQ:
1127
1128 case CC_OP_DECB:
1129 case CC_OP_DECW:
1130 case CC_OP_DECL:
1131 case CC_OP_DECQ:
1132
1133 case CC_OP_SHLB:
1134 case CC_OP_SHLW:
1135 case CC_OP_SHLL:
1136 case CC_OP_SHLQ:
1137
1138 case CC_OP_SARB:
1139 case CC_OP_SARW:
1140 case CC_OP_SARL:
1141 case CC_OP_SARQ:
1142 switch(jcc_op) {
1143 case JCC_Z:
1144 size = (cc_op - CC_OP_ADDB) & 3;
1145 goto fast_jcc_z;
1146 case JCC_S:
1147 size = (cc_op - CC_OP_ADDB) & 3;
1148 goto fast_jcc_s;
1149 default:
1150 goto slow_jcc;
1151 }
1152 break;
1153 default:
1154 slow_jcc:
1155 gen_setcc_slow_T0(jcc_op);
1156 tcg_gen_brcond_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1157 cpu_T[0], tcg_const_tl(0), l1);
1158 break;
1159 }
1160 }
1161
1162 /* XXX: does not work with gdbstub "ice" single step - not a
1163 serious problem */
1164 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1165 {
1166 int l1, l2;
1167
1168 l1 = gen_new_label();
1169 l2 = gen_new_label();
1170 gen_op_jnz_ecx(s->aflag, l1);
1171 gen_set_label(l2);
1172 gen_jmp_tb(s, next_eip, 1);
1173 gen_set_label(l1);
1174 return l2;
1175 }
1176
1177 static inline void gen_stos(DisasContext *s, int ot)
1178 {
1179 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1180 gen_string_movl_A0_EDI(s);
1181 gen_op_st_T0_A0(ot + s->mem_index);
1182 gen_op_movl_T0_Dshift(ot);
1183 gen_op_add_reg_T0(s->aflag, R_EDI);
1184 }
1185
1186 static inline void gen_lods(DisasContext *s, int ot)
1187 {
1188 gen_string_movl_A0_ESI(s);
1189 gen_op_ld_T0_A0(ot + s->mem_index);
1190 gen_op_mov_reg_T0(ot, R_EAX);
1191 gen_op_movl_T0_Dshift(ot);
1192 gen_op_add_reg_T0(s->aflag, R_ESI);
1193 }
1194
1195 static inline void gen_scas(DisasContext *s, int ot)
1196 {
1197 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1198 gen_string_movl_A0_EDI(s);
1199 gen_op_ld_T1_A0(ot + s->mem_index);
1200 gen_op_cmpl_T0_T1_cc();
1201 gen_op_movl_T0_Dshift(ot);
1202 gen_op_add_reg_T0(s->aflag, R_EDI);
1203 }
1204
1205 static inline void gen_cmps(DisasContext *s, int ot)
1206 {
1207 gen_string_movl_A0_ESI(s);
1208 gen_op_ld_T0_A0(ot + s->mem_index);
1209 gen_string_movl_A0_EDI(s);
1210 gen_op_ld_T1_A0(ot + s->mem_index);
1211 gen_op_cmpl_T0_T1_cc();
1212 gen_op_movl_T0_Dshift(ot);
1213 gen_op_add_reg_T0(s->aflag, R_ESI);
1214 gen_op_add_reg_T0(s->aflag, R_EDI);
1215 }
1216
1217 static inline void gen_ins(DisasContext *s, int ot)
1218 {
1219 gen_string_movl_A0_EDI(s);
1220 /* Note: we must do this dummy write first to be restartable in
1221 case of page fault. */
1222 gen_op_movl_T0_0();
1223 gen_op_st_T0_A0(ot + s->mem_index);
1224 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1225 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1226 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1227 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[0], cpu_tmp2_i32);
1228 gen_op_st_T0_A0(ot + s->mem_index);
1229 gen_op_movl_T0_Dshift(ot);
1230 gen_op_add_reg_T0(s->aflag, R_EDI);
1231 }
1232
1233 static inline void gen_outs(DisasContext *s, int ot)
1234 {
1235 gen_string_movl_A0_ESI(s);
1236 gen_op_ld_T0_A0(ot + s->mem_index);
1237
1238 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1239 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1240 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1241 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1242 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
1243
1244 gen_op_movl_T0_Dshift(ot);
1245 gen_op_add_reg_T0(s->aflag, R_ESI);
1246 }
1247
1248 /* same method as Valgrind : we generate jumps to current or next
1249 instruction */
1250 #define GEN_REPZ(op) \
1251 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1252 target_ulong cur_eip, target_ulong next_eip) \
1253 { \
1254 int l2;\
1255 gen_update_cc_op(s); \
1256 l2 = gen_jz_ecx_string(s, next_eip); \
1257 gen_ ## op(s, ot); \
1258 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1259 /* a loop would cause two single step exceptions if ECX = 1 \
1260 before rep string_insn */ \
1261 if (!s->jmp_opt) \
1262 gen_op_jz_ecx(s->aflag, l2); \
1263 gen_jmp(s, cur_eip); \
1264 }
1265
1266 #define GEN_REPZ2(op) \
1267 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1268 target_ulong cur_eip, \
1269 target_ulong next_eip, \
1270 int nz) \
1271 { \
1272 int l2;\
1273 gen_update_cc_op(s); \
1274 l2 = gen_jz_ecx_string(s, next_eip); \
1275 gen_ ## op(s, ot); \
1276 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1277 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1278 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1279 if (!s->jmp_opt) \
1280 gen_op_jz_ecx(s->aflag, l2); \
1281 gen_jmp(s, cur_eip); \
1282 }
1283
1284 GEN_REPZ(movs)
1285 GEN_REPZ(stos)
1286 GEN_REPZ(lods)
1287 GEN_REPZ(ins)
1288 GEN_REPZ(outs)
1289 GEN_REPZ2(scas)
1290 GEN_REPZ2(cmps)
1291
1292 static void *helper_fp_arith_ST0_FT0[8] = {
1293 helper_fadd_ST0_FT0,
1294 helper_fmul_ST0_FT0,
1295 helper_fcom_ST0_FT0,
1296 helper_fcom_ST0_FT0,
1297 helper_fsub_ST0_FT0,
1298 helper_fsubr_ST0_FT0,
1299 helper_fdiv_ST0_FT0,
1300 helper_fdivr_ST0_FT0,
1301 };
1302
1303 /* NOTE the exception in "r" op ordering */
1304 static void *helper_fp_arith_STN_ST0[8] = {
1305 helper_fadd_STN_ST0,
1306 helper_fmul_STN_ST0,
1307 NULL,
1308 NULL,
1309 helper_fsubr_STN_ST0,
1310 helper_fsub_STN_ST0,
1311 helper_fdivr_STN_ST0,
1312 helper_fdiv_STN_ST0,
1313 };
1314
1315 /* if d == OR_TMP0, it means memory operand (address in A0) */
1316 static void gen_op(DisasContext *s1, int op, int ot, int d)
1317 {
1318 if (d != OR_TMP0) {
1319 gen_op_mov_TN_reg(ot, 0, d);
1320 } else {
1321 gen_op_ld_T0_A0(ot + s1->mem_index);
1322 }
1323 switch(op) {
1324 case OP_ADCL:
1325 if (s1->cc_op != CC_OP_DYNAMIC)
1326 gen_op_set_cc_op(s1->cc_op);
1327 gen_compute_eflags_c(cpu_tmp4);
1328 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1329 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1330 if (d != OR_TMP0)
1331 gen_op_mov_reg_T0(ot, d);
1332 else
1333 gen_op_st_T0_A0(ot + s1->mem_index);
1334 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1335 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1336 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1337 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1338 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1339 s1->cc_op = CC_OP_DYNAMIC;
1340 break;
1341 case OP_SBBL:
1342 if (s1->cc_op != CC_OP_DYNAMIC)
1343 gen_op_set_cc_op(s1->cc_op);
1344 gen_compute_eflags_c(cpu_tmp4);
1345 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1346 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1347 if (d != OR_TMP0)
1348 gen_op_mov_reg_T0(ot, d);
1349 else
1350 gen_op_st_T0_A0(ot + s1->mem_index);
1351 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1352 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1353 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1354 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1355 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1356 s1->cc_op = CC_OP_DYNAMIC;
1357 break;
1358 case OP_ADDL:
1359 gen_op_addl_T0_T1();
1360 if (d != OR_TMP0)
1361 gen_op_mov_reg_T0(ot, d);
1362 else
1363 gen_op_st_T0_A0(ot + s1->mem_index);
1364 gen_op_update2_cc();
1365 s1->cc_op = CC_OP_ADDB + ot;
1366 break;
1367 case OP_SUBL:
1368 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1369 if (d != OR_TMP0)
1370 gen_op_mov_reg_T0(ot, d);
1371 else
1372 gen_op_st_T0_A0(ot + s1->mem_index);
1373 gen_op_update2_cc();
1374 s1->cc_op = CC_OP_SUBB + ot;
1375 break;
1376 default:
1377 case OP_ANDL:
1378 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1379 if (d != OR_TMP0)
1380 gen_op_mov_reg_T0(ot, d);
1381 else
1382 gen_op_st_T0_A0(ot + s1->mem_index);
1383 gen_op_update1_cc();
1384 s1->cc_op = CC_OP_LOGICB + ot;
1385 break;
1386 case OP_ORL:
1387 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1388 if (d != OR_TMP0)
1389 gen_op_mov_reg_T0(ot, d);
1390 else
1391 gen_op_st_T0_A0(ot + s1->mem_index);
1392 gen_op_update1_cc();
1393 s1->cc_op = CC_OP_LOGICB + ot;
1394 break;
1395 case OP_XORL:
1396 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1397 if (d != OR_TMP0)
1398 gen_op_mov_reg_T0(ot, d);
1399 else
1400 gen_op_st_T0_A0(ot + s1->mem_index);
1401 gen_op_update1_cc();
1402 s1->cc_op = CC_OP_LOGICB + ot;
1403 break;
1404 case OP_CMPL:
1405 gen_op_cmpl_T0_T1_cc();
1406 s1->cc_op = CC_OP_SUBB + ot;
1407 break;
1408 }
1409 }
1410
1411 /* if d == OR_TMP0, it means memory operand (address in A0) */
1412 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1413 {
1414 if (d != OR_TMP0)
1415 gen_op_mov_TN_reg(ot, 0, d);
1416 else
1417 gen_op_ld_T0_A0(ot + s1->mem_index);
1418 if (s1->cc_op != CC_OP_DYNAMIC)
1419 gen_op_set_cc_op(s1->cc_op);
1420 if (c > 0) {
1421 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1422 s1->cc_op = CC_OP_INCB + ot;
1423 } else {
1424 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1425 s1->cc_op = CC_OP_DECB + ot;
1426 }
1427 if (d != OR_TMP0)
1428 gen_op_mov_reg_T0(ot, d);
1429 else
1430 gen_op_st_T0_A0(ot + s1->mem_index);
1431 gen_compute_eflags_c(cpu_cc_src);
1432 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1433 }
1434
1435 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1436 int is_right, int is_arith)
1437 {
1438 target_ulong mask;
1439 int shift_label;
1440
1441 if (ot == OT_QUAD)
1442 mask = 0x3f;
1443 else
1444 mask = 0x1f;
1445
1446 /* load */
1447 if (op1 == OR_TMP0)
1448 gen_op_ld_T0_A0(ot + s->mem_index);
1449 else
1450 gen_op_mov_TN_reg(ot, 0, op1);
1451
1452 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1453
1454 tcg_gen_addi_tl(cpu_tmp5, cpu_T[1], -1);
1455
1456 if (is_right) {
1457 if (is_arith) {
1458 gen_exts(ot, cpu_T[0]);
1459 tcg_gen_sar_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1460 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1461 } else {
1462 gen_extu(ot, cpu_T[0]);
1463 tcg_gen_shr_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1464 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1465 }
1466 } else {
1467 tcg_gen_shl_tl(cpu_T3, cpu_T[0], cpu_tmp5);
1468 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1469 }
1470
1471 /* store */
1472 if (op1 == OR_TMP0)
1473 gen_op_st_T0_A0(ot + s->mem_index);
1474 else
1475 gen_op_mov_reg_T0(ot, op1);
1476
1477 /* update eflags if non zero shift */
1478 if (s->cc_op != CC_OP_DYNAMIC)
1479 gen_op_set_cc_op(s->cc_op);
1480
1481 shift_label = gen_new_label();
1482 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), shift_label);
1483
1484 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1485 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1486 if (is_right)
1487 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1488 else
1489 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1490
1491 gen_set_label(shift_label);
1492 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1493 }
1494
1495 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1496 int is_right, int is_arith)
1497 {
1498 int mask;
1499
1500 if (ot == OT_QUAD)
1501 mask = 0x3f;
1502 else
1503 mask = 0x1f;
1504
1505 /* load */
1506 if (op1 == OR_TMP0)
1507 gen_op_ld_T0_A0(ot + s->mem_index);
1508 else
1509 gen_op_mov_TN_reg(ot, 0, op1);
1510
1511 op2 &= mask;
1512 if (op2 != 0) {
1513 if (is_right) {
1514 if (is_arith) {
1515 gen_exts(ot, cpu_T[0]);
1516 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1517 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1518 } else {
1519 gen_extu(ot, cpu_T[0]);
1520 tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1521 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1522 }
1523 } else {
1524 tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1);
1525 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1526 }
1527 }
1528
1529 /* store */
1530 if (op1 == OR_TMP0)
1531 gen_op_st_T0_A0(ot + s->mem_index);
1532 else
1533 gen_op_mov_reg_T0(ot, op1);
1534
1535 /* update eflags if non zero shift */
1536 if (op2 != 0) {
1537 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0);
1538 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1539 if (is_right)
1540 s->cc_op = CC_OP_SARB + ot;
1541 else
1542 s->cc_op = CC_OP_SHLB + ot;
1543 }
1544 }
1545
1546 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1547 {
1548 if (arg2 >= 0)
1549 tcg_gen_shli_tl(ret, arg1, arg2);
1550 else
1551 tcg_gen_shri_tl(ret, arg1, -arg2);
1552 }
1553
1554 /* XXX: add faster immediate case */
1555 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1556 int is_right)
1557 {
1558 target_ulong mask;
1559 int label1, label2, data_bits;
1560
1561 if (ot == OT_QUAD)
1562 mask = 0x3f;
1563 else
1564 mask = 0x1f;
1565
1566 /* load */
1567 if (op1 == OR_TMP0)
1568 gen_op_ld_T0_A0(ot + s->mem_index);
1569 else
1570 gen_op_mov_TN_reg(ot, 0, op1);
1571
1572 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], mask);
1573
1574 /* Must test zero case to avoid using undefined behaviour in TCG
1575 shifts. */
1576 label1 = gen_new_label();
1577 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label1);
1578
1579 if (ot <= OT_WORD)
1580 tcg_gen_andi_tl(cpu_tmp0, cpu_T[1], (1 << (3 + ot)) - 1);
1581 else
1582 tcg_gen_mov_tl(cpu_tmp0, cpu_T[1]);
1583
1584 gen_extu(ot, cpu_T[0]);
1585 tcg_gen_mov_tl(cpu_T3, cpu_T[0]);
1586
1587 data_bits = 8 << ot;
1588 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1589 fix TCG definition) */
1590 if (is_right) {
1591 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1592 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1593 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1594 } else {
1595 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp0);
1596 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(data_bits), cpu_tmp0);
1597 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1598 }
1599 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1600
1601 gen_set_label(label1);
1602 /* store */
1603 if (op1 == OR_TMP0)
1604 gen_op_st_T0_A0(ot + s->mem_index);
1605 else
1606 gen_op_mov_reg_T0(ot, op1);
1607
1608 /* update eflags */
1609 if (s->cc_op != CC_OP_DYNAMIC)
1610 gen_op_set_cc_op(s->cc_op);
1611
1612 label2 = gen_new_label();
1613 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[1], tcg_const_tl(0), label2);
1614
1615 gen_compute_eflags(cpu_cc_src);
1616 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1617 tcg_gen_xor_tl(cpu_tmp0, cpu_T3, cpu_T[0]);
1618 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1619 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1620 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1621 if (is_right) {
1622 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], data_bits - 1);
1623 }
1624 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_C);
1625 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
1626
1627 tcg_gen_discard_tl(cpu_cc_dst);
1628 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1629
1630 gen_set_label(label2);
1631 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1632 }
1633
1634 static void *helper_rotc[8] = {
1635 helper_rclb,
1636 helper_rclw,
1637 helper_rcll,
1638 X86_64_ONLY(helper_rclq),
1639 helper_rcrb,
1640 helper_rcrw,
1641 helper_rcrl,
1642 X86_64_ONLY(helper_rcrq),
1643 };
1644
1645 /* XXX: add faster immediate = 1 case */
1646 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1647 int is_right)
1648 {
1649 int label1;
1650
1651 if (s->cc_op != CC_OP_DYNAMIC)
1652 gen_op_set_cc_op(s->cc_op);
1653
1654 /* load */
1655 if (op1 == OR_TMP0)
1656 gen_op_ld_T0_A0(ot + s->mem_index);
1657 else
1658 gen_op_mov_TN_reg(ot, 0, op1);
1659
1660 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)],
1661 cpu_T[0], cpu_T[0], cpu_T[1]);
1662 /* store */
1663 if (op1 == OR_TMP0)
1664 gen_op_st_T0_A0(ot + s->mem_index);
1665 else
1666 gen_op_mov_reg_T0(ot, op1);
1667
1668 /* update eflags */
1669 label1 = gen_new_label();
1670 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(-1), label1);
1671
1672 tcg_gen_mov_tl(cpu_cc_src, cpu_T3);
1673 tcg_gen_discard_tl(cpu_cc_dst);
1674 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1675
1676 gen_set_label(label1);
1677 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1678 }
1679
1680 /* XXX: add faster immediate case */
1681 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1682 int is_right)
1683 {
1684 int label1, label2, data_bits;
1685 target_ulong mask;
1686
1687 if (ot == OT_QUAD)
1688 mask = 0x3f;
1689 else
1690 mask = 0x1f;
1691
1692 /* load */
1693 if (op1 == OR_TMP0)
1694 gen_op_ld_T0_A0(ot + s->mem_index);
1695 else
1696 gen_op_mov_TN_reg(ot, 0, op1);
1697
1698 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1699 /* Must test zero case to avoid using undefined behaviour in TCG
1700 shifts. */
1701 label1 = gen_new_label();
1702 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
1703
1704 tcg_gen_addi_tl(cpu_tmp5, cpu_T3, -1);
1705 if (ot == OT_WORD) {
1706 /* Note: we implement the Intel behaviour for shift count > 16 */
1707 if (is_right) {
1708 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1709 tcg_gen_shli_tl(cpu_tmp0, cpu_T[1], 16);
1710 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1711 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1712
1713 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1714
1715 /* only needed if count > 16, but a test would complicate */
1716 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1717 tcg_gen_shl_tl(cpu_tmp0, cpu_T[0], cpu_tmp5);
1718
1719 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1720
1721 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
1722 } else {
1723 /* XXX: not optimal */
1724 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
1725 tcg_gen_shli_tl(cpu_T[1], cpu_T[1], 16);
1726 tcg_gen_or_tl(cpu_T[1], cpu_T[1], cpu_T[0]);
1727 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1728
1729 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1730 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5);
1731 tcg_gen_shr_tl(cpu_tmp6, cpu_T[1], cpu_tmp0);
1732 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp6);
1733
1734 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1735 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), cpu_T3);
1736 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1737 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1738 }
1739 } else {
1740 data_bits = 8 << ot;
1741 if (is_right) {
1742 if (ot == OT_LONG)
1743 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
1744
1745 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1746
1747 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], cpu_T3);
1748 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1749 tcg_gen_shl_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1750 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1751
1752 } else {
1753 if (ot == OT_LONG)
1754 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
1755
1756 tcg_gen_shl_tl(cpu_tmp4, cpu_T[0], cpu_tmp5);
1757
1758 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], cpu_T3);
1759 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), cpu_T3);
1760 tcg_gen_shr_tl(cpu_T[1], cpu_T[1], cpu_tmp5);
1761 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1762 }
1763 }
1764 tcg_gen_mov_tl(cpu_T[1], cpu_tmp4);
1765
1766 gen_set_label(label1);
1767 /* store */
1768 if (op1 == OR_TMP0)
1769 gen_op_st_T0_A0(ot + s->mem_index);
1770 else
1771 gen_op_mov_reg_T0(ot, op1);
1772
1773 /* update eflags */
1774 if (s->cc_op != CC_OP_DYNAMIC)
1775 gen_op_set_cc_op(s->cc_op);
1776
1777 label2 = gen_new_label();
1778 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label2);
1779
1780 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1781 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1782 if (is_right) {
1783 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1784 } else {
1785 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1786 }
1787 gen_set_label(label2);
1788 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1789 }
1790
1791 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1792 {
1793 if (s != OR_TMP1)
1794 gen_op_mov_TN_reg(ot, 1, s);
1795 switch(op) {
1796 case OP_ROL:
1797 gen_rot_rm_T1(s1, ot, d, 0);
1798 break;
1799 case OP_ROR:
1800 gen_rot_rm_T1(s1, ot, d, 1);
1801 break;
1802 case OP_SHL:
1803 case OP_SHL1:
1804 gen_shift_rm_T1(s1, ot, d, 0, 0);
1805 break;
1806 case OP_SHR:
1807 gen_shift_rm_T1(s1, ot, d, 1, 0);
1808 break;
1809 case OP_SAR:
1810 gen_shift_rm_T1(s1, ot, d, 1, 1);
1811 break;
1812 case OP_RCL:
1813 gen_rotc_rm_T1(s1, ot, d, 0);
1814 break;
1815 case OP_RCR:
1816 gen_rotc_rm_T1(s1, ot, d, 1);
1817 break;
1818 }
1819 }
1820
1821 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1822 {
1823 switch(op) {
1824 case OP_SHL:
1825 case OP_SHL1:
1826 gen_shift_rm_im(s1, ot, d, c, 0, 0);
1827 break;
1828 case OP_SHR:
1829 gen_shift_rm_im(s1, ot, d, c, 1, 0);
1830 break;
1831 case OP_SAR:
1832 gen_shift_rm_im(s1, ot, d, c, 1, 1);
1833 break;
1834 default:
1835 /* currently not optimized */
1836 gen_op_movl_T1_im(c);
1837 gen_shift(s1, op, ot, d, OR_TMP1);
1838 break;
1839 }
1840 }
1841
1842 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1843 {
1844 target_long disp;
1845 int havesib;
1846 int base;
1847 int index;
1848 int scale;
1849 int opreg;
1850 int mod, rm, code, override, must_add_seg;
1851
1852 override = s->override;
1853 must_add_seg = s->addseg;
1854 if (override >= 0)
1855 must_add_seg = 1;
1856 mod = (modrm >> 6) & 3;
1857 rm = modrm & 7;
1858
1859 if (s->aflag) {
1860
1861 havesib = 0;
1862 base = rm;
1863 index = 0;
1864 scale = 0;
1865
1866 if (base == 4) {
1867 havesib = 1;
1868 code = ldub_code(s->pc++);
1869 scale = (code >> 6) & 3;
1870 index = ((code >> 3) & 7) | REX_X(s);
1871 base = (code & 7);
1872 }
1873 base |= REX_B(s);
1874
1875 switch (mod) {
1876 case 0:
1877 if ((base & 7) == 5) {
1878 base = -1;
1879 disp = (int32_t)ldl_code(s->pc);
1880 s->pc += 4;
1881 if (CODE64(s) && !havesib) {
1882 disp += s->pc + s->rip_offset;
1883 }
1884 } else {
1885 disp = 0;
1886 }
1887 break;
1888 case 1:
1889 disp = (int8_t)ldub_code(s->pc++);
1890 break;
1891 default:
1892 case 2:
1893 disp = ldl_code(s->pc);
1894 s->pc += 4;
1895 break;
1896 }
1897
1898 if (base >= 0) {
1899 /* for correct popl handling with esp */
1900 if (base == 4 && s->popl_esp_hack)
1901 disp += s->popl_esp_hack;
1902 #ifdef TARGET_X86_64
1903 if (s->aflag == 2) {
1904 gen_op_movq_A0_reg(base);
1905 if (disp != 0) {
1906 gen_op_addq_A0_im(disp);
1907 }
1908 } else
1909 #endif
1910 {
1911 gen_op_movl_A0_reg(base);
1912 if (disp != 0)
1913 gen_op_addl_A0_im(disp);
1914 }
1915 } else {
1916 #ifdef TARGET_X86_64
1917 if (s->aflag == 2) {
1918 gen_op_movq_A0_im(disp);
1919 } else
1920 #endif
1921 {
1922 gen_op_movl_A0_im(disp);
1923 }
1924 }
1925 /* XXX: index == 4 is always invalid */
1926 if (havesib && (index != 4 || scale != 0)) {
1927 #ifdef TARGET_X86_64
1928 if (s->aflag == 2) {
1929 gen_op_addq_A0_reg_sN(scale, index);
1930 } else
1931 #endif
1932 {
1933 gen_op_addl_A0_reg_sN(scale, index);
1934 }
1935 }
1936 if (must_add_seg) {
1937 if (override < 0) {
1938 if (base == R_EBP || base == R_ESP)
1939 override = R_SS;
1940 else
1941 override = R_DS;
1942 }
1943 #ifdef TARGET_X86_64
1944 if (s->aflag == 2) {
1945 gen_op_addq_A0_seg(override);
1946 } else
1947 #endif
1948 {
1949 gen_op_addl_A0_seg(override);
1950 }
1951 }
1952 } else {
1953 switch (mod) {
1954 case 0:
1955 if (rm == 6) {
1956 disp = lduw_code(s->pc);
1957 s->pc += 2;
1958 gen_op_movl_A0_im(disp);
1959 rm = 0; /* avoid SS override */
1960 goto no_rm;
1961 } else {
1962 disp = 0;
1963 }
1964 break;
1965 case 1:
1966 disp = (int8_t)ldub_code(s->pc++);
1967 break;
1968 default:
1969 case 2:
1970 disp = lduw_code(s->pc);
1971 s->pc += 2;
1972 break;
1973 }
1974 switch(rm) {
1975 case 0:
1976 gen_op_movl_A0_reg(R_EBX);
1977 gen_op_addl_A0_reg_sN(0, R_ESI);
1978 break;
1979 case 1:
1980 gen_op_movl_A0_reg(R_EBX);
1981 gen_op_addl_A0_reg_sN(0, R_EDI);
1982 break;
1983 case 2:
1984 gen_op_movl_A0_reg(R_EBP);
1985 gen_op_addl_A0_reg_sN(0, R_ESI);
1986 break;
1987 case 3:
1988 gen_op_movl_A0_reg(R_EBP);
1989 gen_op_addl_A0_reg_sN(0, R_EDI);
1990 break;
1991 case 4:
1992 gen_op_movl_A0_reg(R_ESI);
1993 break;
1994 case 5:
1995 gen_op_movl_A0_reg(R_EDI);
1996 break;
1997 case 6:
1998 gen_op_movl_A0_reg(R_EBP);
1999 break;
2000 default:
2001 case 7:
2002 gen_op_movl_A0_reg(R_EBX);
2003 break;
2004 }
2005 if (disp != 0)
2006 gen_op_addl_A0_im(disp);
2007 gen_op_andl_A0_ffff();
2008 no_rm:
2009 if (must_add_seg) {
2010 if (override < 0) {
2011 if (rm == 2 || rm == 3 || rm == 6)
2012 override = R_SS;
2013 else
2014 override = R_DS;
2015 }
2016 gen_op_addl_A0_seg(override);
2017 }
2018 }
2019
2020 opreg = OR_A0;
2021 disp = 0;
2022 *reg_ptr = opreg;
2023 *offset_ptr = disp;
2024 }
2025
2026 static void gen_nop_modrm(DisasContext *s, int modrm)
2027 {
2028 int mod, rm, base, code;
2029
2030 mod = (modrm >> 6) & 3;
2031 if (mod == 3)
2032 return;
2033 rm = modrm & 7;
2034
2035 if (s->aflag) {
2036
2037 base = rm;
2038
2039 if (base == 4) {
2040 code = ldub_code(s->pc++);
2041 base = (code & 7);
2042 }
2043
2044 switch (mod) {
2045 case 0:
2046 if (base == 5) {
2047 s->pc += 4;
2048 }
2049 break;
2050 case 1:
2051 s->pc++;
2052 break;
2053 default:
2054 case 2:
2055 s->pc += 4;
2056 break;
2057 }
2058 } else {
2059 switch (mod) {
2060 case 0:
2061 if (rm == 6) {
2062 s->pc += 2;
2063 }
2064 break;
2065 case 1:
2066 s->pc++;
2067 break;
2068 default:
2069 case 2:
2070 s->pc += 2;
2071 break;
2072 }
2073 }
2074 }
2075
2076 /* used for LEA and MOV AX, mem */
2077 static void gen_add_A0_ds_seg(DisasContext *s)
2078 {
2079 int override, must_add_seg;
2080 must_add_seg = s->addseg;
2081 override = R_DS;
2082 if (s->override >= 0) {
2083 override = s->override;
2084 must_add_seg = 1;
2085 } else {
2086 override = R_DS;
2087 }
2088 if (must_add_seg) {
2089 #ifdef TARGET_X86_64
2090 if (CODE64(s)) {
2091 gen_op_addq_A0_seg(override);
2092 } else
2093 #endif
2094 {
2095 gen_op_addl_A0_seg(override);
2096 }
2097 }
2098 }
2099
2100 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2101 OR_TMP0 */
2102 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2103 {
2104 int mod, rm, opreg, disp;
2105
2106 mod = (modrm >> 6) & 3;
2107 rm = (modrm & 7) | REX_B(s);
2108 if (mod == 3) {
2109 if (is_store) {
2110 if (reg != OR_TMP0)
2111 gen_op_mov_TN_reg(ot, 0, reg);
2112 gen_op_mov_reg_T0(ot, rm);
2113 } else {
2114 gen_op_mov_TN_reg(ot, 0, rm);
2115 if (reg != OR_TMP0)
2116 gen_op_mov_reg_T0(ot, reg);
2117 }
2118 } else {
2119 gen_lea_modrm(s, modrm, &opreg, &disp);
2120 if (is_store) {
2121 if (reg != OR_TMP0)
2122 gen_op_mov_TN_reg(ot, 0, reg);
2123 gen_op_st_T0_A0(ot + s->mem_index);
2124 } else {
2125 gen_op_ld_T0_A0(ot + s->mem_index);
2126 if (reg != OR_TMP0)
2127 gen_op_mov_reg_T0(ot, reg);
2128 }
2129 }
2130 }
2131
2132 static inline uint32_t insn_get(DisasContext *s, int ot)
2133 {
2134 uint32_t ret;
2135
2136 switch(ot) {
2137 case OT_BYTE:
2138 ret = ldub_code(s->pc);
2139 s->pc++;
2140 break;
2141 case OT_WORD:
2142 ret = lduw_code(s->pc);
2143 s->pc += 2;
2144 break;
2145 default:
2146 case OT_LONG:
2147 ret = ldl_code(s->pc);
2148 s->pc += 4;
2149 break;
2150 }
2151 return ret;
2152 }
2153
2154 static inline int insn_const_size(unsigned int ot)
2155 {
2156 if (ot <= OT_LONG)
2157 return 1 << ot;
2158 else
2159 return 4;
2160 }
2161
2162 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2163 {
2164 TranslationBlock *tb;
2165 target_ulong pc;
2166
2167 pc = s->cs_base + eip;
2168 tb = s->tb;
2169 /* NOTE: we handle the case where the TB spans two pages here */
2170 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2171 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2172 /* jump to same page: we can use a direct jump */
2173 tcg_gen_goto_tb(tb_num);
2174 gen_jmp_im(eip);
2175 tcg_gen_exit_tb((long)tb + tb_num);
2176 } else {
2177 /* jump to another page: currently not optimized */
2178 gen_jmp_im(eip);
2179 gen_eob(s);
2180 }
2181 }
2182
2183 static inline void gen_jcc(DisasContext *s, int b,
2184 target_ulong val, target_ulong next_eip)
2185 {
2186 int l1, l2, cc_op;
2187
2188 cc_op = s->cc_op;
2189 if (s->cc_op != CC_OP_DYNAMIC) {
2190 gen_op_set_cc_op(s->cc_op);
2191 s->cc_op = CC_OP_DYNAMIC;
2192 }
2193 if (s->jmp_opt) {
2194 l1 = gen_new_label();
2195 gen_jcc1(s, cc_op, b, l1);
2196
2197 gen_goto_tb(s, 0, next_eip);
2198
2199 gen_set_label(l1);
2200 gen_goto_tb(s, 1, val);
2201 s->is_jmp = 3;
2202 } else {
2203
2204 l1 = gen_new_label();
2205 l2 = gen_new_label();
2206 gen_jcc1(s, cc_op, b, l1);
2207
2208 gen_jmp_im(next_eip);
2209 tcg_gen_br(l2);
2210
2211 gen_set_label(l1);
2212 gen_jmp_im(val);
2213 gen_set_label(l2);
2214 gen_eob(s);
2215 }
2216 }
2217
2218 static void gen_setcc(DisasContext *s, int b)
2219 {
2220 int inv, jcc_op, l1;
2221
2222 if (is_fast_jcc_case(s, b)) {
2223 /* nominal case: we use a jump */
2224 tcg_gen_movi_tl(cpu_T[0], 0);
2225 l1 = gen_new_label();
2226 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2227 tcg_gen_movi_tl(cpu_T[0], 1);
2228 gen_set_label(l1);
2229 } else {
2230 /* slow case: it is more efficient not to generate a jump,
2231 although it is questionnable whether this optimization is
2232 worth to */
2233 inv = b & 1;
2234 jcc_op = (b >> 1) & 7;
2235 if (s->cc_op != CC_OP_DYNAMIC)
2236 gen_op_set_cc_op(s->cc_op);
2237 gen_setcc_slow_T0(jcc_op);
2238 if (inv) {
2239 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2240 }
2241 }
2242 }
2243
2244 static inline void gen_op_movl_T0_seg(int seg_reg)
2245 {
2246 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2247 offsetof(CPUX86State,segs[seg_reg].selector));
2248 }
2249
2250 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2251 {
2252 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2253 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2254 offsetof(CPUX86State,segs[seg_reg].selector));
2255 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2256 tcg_gen_st_tl(cpu_T[0], cpu_env,
2257 offsetof(CPUX86State,segs[seg_reg].base));
2258 }
2259
2260 /* move T0 to seg_reg and compute if the CPU state may change. Never
2261 call this function with seg_reg == R_CS */
2262 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2263 {
2264 if (s->pe && !s->vm86) {
2265 /* XXX: optimize by finding processor state dynamically */
2266 if (s->cc_op != CC_OP_DYNAMIC)
2267 gen_op_set_cc_op(s->cc_op);
2268 gen_jmp_im(cur_eip);
2269 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2270 tcg_gen_helper_0_2(helper_load_seg, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2271 /* abort translation because the addseg value may change or
2272 because ss32 may change. For R_SS, translation must always
2273 stop as a special handling must be done to disable hardware
2274 interrupts for the next instruction */
2275 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2276 s->is_jmp = 3;
2277 } else {
2278 gen_op_movl_seg_T0_vm(seg_reg);
2279 if (seg_reg == R_SS)
2280 s->is_jmp = 3;
2281 }
2282 }
2283
2284 static inline int svm_is_rep(int prefixes)
2285 {
2286 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2287 }
2288
2289 static inline int
2290 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2291 uint32_t type, uint64_t param)
2292 {
2293 if(!(s->flags & (INTERCEPT_SVM_MASK)))
2294 /* no SVM activated */
2295 return 0;
2296 switch(type) {
2297 /* CRx and DRx reads/writes */
2298 case SVM_EXIT_READ_CR0 ... SVM_EXIT_EXCP_BASE - 1:
2299 if (s->cc_op != CC_OP_DYNAMIC) {
2300 gen_op_set_cc_op(s->cc_op);
2301 }
2302 gen_jmp_im(pc_start - s->cs_base);
2303 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2304 tcg_const_i32(type), tcg_const_i64(param));
2305 /* this is a special case as we do not know if the interception occurs
2306 so we assume there was none */
2307 return 0;
2308 case SVM_EXIT_MSR:
2309 if(s->flags & (1ULL << INTERCEPT_MSR_PROT)) {
2310 if (s->cc_op != CC_OP_DYNAMIC) {
2311 gen_op_set_cc_op(s->cc_op);
2312 }
2313 gen_jmp_im(pc_start - s->cs_base);
2314 tcg_gen_helper_0_2(helper_svm_check_intercept_param,
2315 tcg_const_i32(type), tcg_const_i64(param));
2316 /* this is a special case as we do not know if the interception occurs
2317 so we assume there was none */
2318 return 0;
2319 }
2320 break;
2321 default:
2322 if(s->flags & (1ULL << ((type - SVM_EXIT_INTR) + INTERCEPT_INTR))) {
2323 if (s->cc_op != CC_OP_DYNAMIC) {
2324 gen_op_set_cc_op(s->cc_op);
2325 }
2326 gen_jmp_im(pc_start - s->cs_base);
2327 tcg_gen_helper_0_2(helper_vmexit,
2328 tcg_const_i32(type), tcg_const_i64(param));
2329 /* we can optimize this one so TBs don't get longer
2330 than up to vmexit */
2331 gen_eob(s);
2332 return 1;
2333 }
2334 }
2335 return 0;
2336 }
2337
2338 static inline int
2339 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2340 {
2341 return gen_svm_check_intercept_param(s, pc_start, type, 0);
2342 }
2343
2344 static inline void gen_stack_update(DisasContext *s, int addend)
2345 {
2346 #ifdef TARGET_X86_64
2347 if (CODE64(s)) {
2348 gen_op_add_reg_im(2, R_ESP, addend);
2349 } else
2350 #endif
2351 if (s->ss32) {
2352 gen_op_add_reg_im(1, R_ESP, addend);
2353 } else {
2354 gen_op_add_reg_im(0, R_ESP, addend);
2355 }
2356 }
2357
2358 /* generate a push. It depends on ss32, addseg and dflag */
2359 static void gen_push_T0(DisasContext *s)
2360 {
2361 #ifdef TARGET_X86_64
2362 if (CODE64(s)) {
2363 gen_op_movq_A0_reg(R_ESP);
2364 if (s->dflag) {
2365 gen_op_addq_A0_im(-8);
2366 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2367 } else {
2368 gen_op_addq_A0_im(-2);
2369 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2370 }
2371 gen_op_mov_reg_A0(2, R_ESP);
2372 } else
2373 #endif
2374 {
2375 gen_op_movl_A0_reg(R_ESP);
2376 if (!s->dflag)
2377 gen_op_addl_A0_im(-2);
2378 else
2379 gen_op_addl_A0_im(-4);
2380 if (s->ss32) {
2381 if (s->addseg) {
2382 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2383 gen_op_addl_A0_seg(R_SS);
2384 }
2385 } else {
2386 gen_op_andl_A0_ffff();
2387 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2388 gen_op_addl_A0_seg(R_SS);
2389 }
2390 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2391 if (s->ss32 && !s->addseg)
2392 gen_op_mov_reg_A0(1, R_ESP);
2393 else
2394 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2395 }
2396 }
2397
2398 /* generate a push. It depends on ss32, addseg and dflag */
2399 /* slower version for T1, only used for call Ev */
2400 static void gen_push_T1(DisasContext *s)
2401 {
2402 #ifdef TARGET_X86_64
2403 if (CODE64(s)) {
2404 gen_op_movq_A0_reg(R_ESP);
2405 if (s->dflag) {
2406 gen_op_addq_A0_im(-8);
2407 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2408 } else {
2409 gen_op_addq_A0_im(-2);
2410 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2411 }
2412 gen_op_mov_reg_A0(2, R_ESP);
2413 } else
2414 #endif
2415 {
2416 gen_op_movl_A0_reg(R_ESP);
2417 if (!s->dflag)
2418 gen_op_addl_A0_im(-2);
2419 else
2420 gen_op_addl_A0_im(-4);
2421 if (s->ss32) {
2422 if (s->addseg) {
2423 gen_op_addl_A0_seg(R_SS);
2424 }
2425 } else {
2426 gen_op_andl_A0_ffff();
2427 gen_op_addl_A0_seg(R_SS);
2428 }
2429 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2430
2431 if (s->ss32 && !s->addseg)
2432 gen_op_mov_reg_A0(1, R_ESP);
2433 else
2434 gen_stack_update(s, (-2) << s->dflag);
2435 }
2436 }
2437
2438 /* two step pop is necessary for precise exceptions */
2439 static void gen_pop_T0(DisasContext *s)
2440 {
2441 #ifdef TARGET_X86_64
2442 if (CODE64(s)) {
2443 gen_op_movq_A0_reg(R_ESP);
2444 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2445 } else
2446 #endif
2447 {
2448 gen_op_movl_A0_reg(R_ESP);
2449 if (s->ss32) {
2450 if (s->addseg)
2451 gen_op_addl_A0_seg(R_SS);
2452 } else {
2453 gen_op_andl_A0_ffff();
2454 gen_op_addl_A0_seg(R_SS);
2455 }
2456 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2457 }
2458 }
2459
2460 static void gen_pop_update(DisasContext *s)
2461 {
2462 #ifdef TARGET_X86_64
2463 if (CODE64(s) && s->dflag) {
2464 gen_stack_update(s, 8);
2465 } else
2466 #endif
2467 {
2468 gen_stack_update(s, 2 << s->dflag);
2469 }
2470 }
2471
2472 static void gen_stack_A0(DisasContext *s)
2473 {
2474 gen_op_movl_A0_reg(R_ESP);
2475 if (!s->ss32)
2476 gen_op_andl_A0_ffff();
2477 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2478 if (s->addseg)
2479 gen_op_addl_A0_seg(R_SS);
2480 }
2481
2482 /* NOTE: wrap around in 16 bit not fully handled */
2483 static void gen_pusha(DisasContext *s)
2484 {
2485 int i;
2486 gen_op_movl_A0_reg(R_ESP);
2487 gen_op_addl_A0_im(-16 << s->dflag);
2488 if (!s->ss32)
2489 gen_op_andl_A0_ffff();
2490 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2491 if (s->addseg)
2492 gen_op_addl_A0_seg(R_SS);
2493 for(i = 0;i < 8; i++) {
2494 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2495 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2496 gen_op_addl_A0_im(2 << s->dflag);
2497 }
2498 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2499 }
2500
2501 /* NOTE: wrap around in 16 bit not fully handled */
2502 static void gen_popa(DisasContext *s)
2503 {
2504 int i;
2505 gen_op_movl_A0_reg(R_ESP);
2506 if (!s->ss32)
2507 gen_op_andl_A0_ffff();
2508 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2509 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2510 if (s->addseg)
2511 gen_op_addl_A0_seg(R_SS);
2512 for(i = 0;i < 8; i++) {
2513 /* ESP is not reloaded */
2514 if (i != 3) {
2515 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2516 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2517 }
2518 gen_op_addl_A0_im(2 << s->dflag);
2519 }
2520 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2521 }
2522
2523 static void gen_enter(DisasContext *s, int esp_addend, int level)
2524 {
2525 int ot, opsize;
2526
2527 level &= 0x1f;
2528 #ifdef TARGET_X86_64
2529 if (CODE64(s)) {
2530 ot = s->dflag ? OT_QUAD : OT_WORD;
2531 opsize = 1 << ot;
2532
2533 gen_op_movl_A0_reg(R_ESP);
2534 gen_op_addq_A0_im(-opsize);
2535 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2536
2537 /* push bp */
2538 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2539 gen_op_st_T0_A0(ot + s->mem_index);
2540 if (level) {
2541 /* XXX: must save state */
2542 tcg_gen_helper_0_3(helper_enter64_level,
2543 tcg_const_i32(level),
2544 tcg_const_i32((ot == OT_QUAD)),
2545 cpu_T[1]);
2546 }
2547 gen_op_mov_reg_T1(ot, R_EBP);
2548 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2549 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2550 } else
2551 #endif
2552 {
2553 ot = s->dflag + OT_WORD;
2554 opsize = 2 << s->dflag;
2555
2556 gen_op_movl_A0_reg(R_ESP);
2557 gen_op_addl_A0_im(-opsize);
2558 if (!s->ss32)
2559 gen_op_andl_A0_ffff();
2560 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2561 if (s->addseg)
2562 gen_op_addl_A0_seg(R_SS);
2563 /* push bp */
2564 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2565 gen_op_st_T0_A0(ot + s->mem_index);
2566 if (level) {
2567 /* XXX: must save state */
2568 tcg_gen_helper_0_3(helper_enter_level,
2569 tcg_const_i32(level),
2570 tcg_const_i32(s->dflag),
2571 cpu_T[1]);
2572 }
2573 gen_op_mov_reg_T1(ot, R_EBP);
2574 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2575 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2576 }
2577 }
2578
2579 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2580 {
2581 if (s->cc_op != CC_OP_DYNAMIC)
2582 gen_op_set_cc_op(s->cc_op);
2583 gen_jmp_im(cur_eip);
2584 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_i32(trapno));
2585 s->is_jmp = 3;
2586 }
2587
2588 /* an interrupt is different from an exception because of the
2589 privilege checks */
2590 static void gen_interrupt(DisasContext *s, int intno,
2591 target_ulong cur_eip, target_ulong next_eip)
2592 {
2593 if (s->cc_op != CC_OP_DYNAMIC)
2594 gen_op_set_cc_op(s->cc_op);
2595 gen_jmp_im(cur_eip);
2596 tcg_gen_helper_0_2(helper_raise_interrupt,
2597 tcg_const_i32(intno),
2598 tcg_const_i32(next_eip - cur_eip));
2599 s->is_jmp = 3;
2600 }
2601
2602 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2603 {
2604 if (s->cc_op != CC_OP_DYNAMIC)
2605 gen_op_set_cc_op(s->cc_op);
2606 gen_jmp_im(cur_eip);
2607 tcg_gen_helper_0_0(helper_debug);
2608 s->is_jmp = 3;
2609 }
2610
2611 /* generate a generic end of block. Trace exception is also generated
2612 if needed */
2613 static void gen_eob(DisasContext *s)
2614 {
2615 if (s->cc_op != CC_OP_DYNAMIC)
2616 gen_op_set_cc_op(s->cc_op);
2617 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2618 tcg_gen_helper_0_0(helper_reset_inhibit_irq);
2619 }
2620 if (s->singlestep_enabled) {
2621 tcg_gen_helper_0_0(helper_debug);
2622 } else if (s->tf) {
2623 tcg_gen_helper_0_0(helper_single_step);
2624 } else {
2625 tcg_gen_exit_tb(0);
2626 }
2627 s->is_jmp = 3;
2628 }
2629
2630 /* generate a jump to eip. No segment change must happen before as a
2631 direct call to the next block may occur */
2632 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2633 {
2634 if (s->jmp_opt) {
2635 if (s->cc_op != CC_OP_DYNAMIC) {
2636 gen_op_set_cc_op(s->cc_op);
2637 s->cc_op = CC_OP_DYNAMIC;
2638 }
2639 gen_goto_tb(s, tb_num, eip);
2640 s->is_jmp = 3;
2641 } else {
2642 gen_jmp_im(eip);
2643 gen_eob(s);
2644 }
2645 }
2646
2647 static void gen_jmp(DisasContext *s, target_ulong eip)
2648 {
2649 gen_jmp_tb(s, eip, 0);
2650 }
2651
2652 static inline void gen_ldq_env_A0(int idx, int offset)
2653 {
2654 int mem_index = (idx >> 2) - 1;
2655 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2656 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2657 }
2658
2659 static inline void gen_stq_env_A0(int idx, int offset)
2660 {
2661 int mem_index = (idx >> 2) - 1;
2662 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2663 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2664 }
2665
2666 static inline void gen_ldo_env_A0(int idx, int offset)
2667 {
2668 int mem_index = (idx >> 2) - 1;
2669 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2670 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2671 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2672 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2673 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2674 }
2675
2676 static inline void gen_sto_env_A0(int idx, int offset)
2677 {
2678 int mem_index = (idx >> 2) - 1;
2679 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2680 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2681 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2682 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2683 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2684 }
2685
2686 static inline void gen_op_movo(int d_offset, int s_offset)
2687 {
2688 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2689 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2690 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2691 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2692 }
2693
2694 static inline void gen_op_movq(int d_offset, int s_offset)
2695 {
2696 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2697 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2698 }
2699
2700 static inline void gen_op_movl(int d_offset, int s_offset)
2701 {
2702 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2703 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2704 }
2705
2706 static inline void gen_op_movq_env_0(int d_offset)
2707 {
2708 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2709 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2710 }
2711
2712 #define SSE_SPECIAL ((void *)1)
2713 #define SSE_DUMMY ((void *)2)
2714
2715 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2716 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2717 helper_ ## x ## ss, helper_ ## x ## sd, }
2718
2719 static void *sse_op_table1[256][4] = {
2720 /* 3DNow! extensions */
2721 [0x0e] = { SSE_DUMMY }, /* femms */
2722 [0x0f] = { SSE_DUMMY }, /* pf... */
2723 /* pure SSE operations */
2724 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2725 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2726 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2727 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2728 [0x14] = { helper_punpckldq_xmm, helper_punpcklqdq_xmm },
2729 [0x15] = { helper_punpckhdq_xmm, helper_punpckhqdq_xmm },
2730 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2731 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2732
2733 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2734 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2735 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2736 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd */
2737 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2738 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2739 [0x2e] = { helper_ucomiss, helper_ucomisd },
2740 [0x2f] = { helper_comiss, helper_comisd },
2741 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2742 [0x51] = SSE_FOP(sqrt),
2743 [0x52] = { helper_rsqrtps, NULL, helper_rsqrtss, NULL },
2744 [0x53] = { helper_rcpps, NULL, helper_rcpss, NULL },
2745 [0x54] = { helper_pand_xmm, helper_pand_xmm }, /* andps, andpd */
2746 [0x55] = { helper_pandn_xmm, helper_pandn_xmm }, /* andnps, andnpd */
2747 [0x56] = { helper_por_xmm, helper_por_xmm }, /* orps, orpd */
2748 [0x57] = { helper_pxor_xmm, helper_pxor_xmm }, /* xorps, xorpd */
2749 [0x58] = SSE_FOP(add),
2750 [0x59] = SSE_FOP(mul),
2751 [0x5a] = { helper_cvtps2pd, helper_cvtpd2ps,
2752 helper_cvtss2sd, helper_cvtsd2ss },
2753 [0x5b] = { helper_cvtdq2ps, helper_cvtps2dq, helper_cvttps2dq },
2754 [0x5c] = SSE_FOP(sub),
2755 [0x5d] = SSE_FOP(min),
2756 [0x5e] = SSE_FOP(div),
2757 [0x5f] = SSE_FOP(max),
2758
2759 [0xc2] = SSE_FOP(cmpeq),
2760 [0xc6] = { helper_shufps, helper_shufpd },
2761
2762 /* MMX ops and their SSE extensions */
2763 [0x60] = MMX_OP2(punpcklbw),
2764 [0x61] = MMX_OP2(punpcklwd),
2765 [0x62] = MMX_OP2(punpckldq),
2766 [0x63] = MMX_OP2(packsswb),
2767 [0x64] = MMX_OP2(pcmpgtb),
2768 [0x65] = MMX_OP2(pcmpgtw),
2769 [0x66] = MMX_OP2(pcmpgtl),
2770 [0x67] = MMX_OP2(packuswb),
2771 [0x68] = MMX_OP2(punpckhbw),
2772 [0x69] = MMX_OP2(punpckhwd),
2773 [0x6a] = MMX_OP2(punpckhdq),
2774 [0x6b] = MMX_OP2(packssdw),
2775 [0x6c] = { NULL, helper_punpcklqdq_xmm },
2776 [0x6d] = { NULL, helper_punpckhqdq_xmm },
2777 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2778 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2779 [0x70] = { helper_pshufw_mmx,
2780 helper_pshufd_xmm,
2781 helper_pshufhw_xmm,
2782 helper_pshuflw_xmm },
2783 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2784 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2785 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2786 [0x74] = MMX_OP2(pcmpeqb),
2787 [0x75] = MMX_OP2(pcmpeqw),
2788 [0x76] = MMX_OP2(pcmpeql),
2789 [0x77] = { SSE_DUMMY }, /* emms */
2790 [0x7c] = { NULL, helper_haddpd, NULL, helper_haddps },
2791 [0x7d] = { NULL, helper_hsubpd, NULL, helper_hsubps },
2792 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2793 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2794 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2795 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2796 [0xd0] = { NULL, helper_addsubpd, NULL, helper_addsubps },
2797 [0xd1] = MMX_OP2(psrlw),
2798 [0xd2] = MMX_OP2(psrld),
2799 [0xd3] = MMX_OP2(psrlq),
2800 [0xd4] = MMX_OP2(paddq),
2801 [0xd5] = MMX_OP2(pmullw),
2802 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2803 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2804 [0xd8] = MMX_OP2(psubusb),
2805 [0xd9] = MMX_OP2(psubusw),
2806 [0xda] = MMX_OP2(pminub),
2807 [0xdb] = MMX_OP2(pand),
2808 [0xdc] = MMX_OP2(paddusb),
2809 [0xdd] = MMX_OP2(paddusw),
2810 [0xde] = MMX_OP2(pmaxub),
2811 [0xdf] = MMX_OP2(pandn),
2812 [0xe0] = MMX_OP2(pavgb),
2813 [0xe1] = MMX_OP2(psraw),
2814 [0xe2] = MMX_OP2(psrad),
2815 [0xe3] = MMX_OP2(pavgw),
2816 [0xe4] = MMX_OP2(pmulhuw),
2817 [0xe5] = MMX_OP2(pmulhw),
2818 [0xe6] = { NULL, helper_cvttpd2dq, helper_cvtdq2pd, helper_cvtpd2dq },
2819 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2820 [0xe8] = MMX_OP2(psubsb),
2821 [0xe9] = MMX_OP2(psubsw),
2822 [0xea] = MMX_OP2(pminsw),
2823 [0xeb] = MMX_OP2(por),
2824 [0xec] = MMX_OP2(paddsb),
2825 [0xed] = MMX_OP2(paddsw),
2826 [0xee] = MMX_OP2(pmaxsw),
2827 [0xef] = MMX_OP2(pxor),
2828 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2829 [0xf1] = MMX_OP2(psllw),
2830 [0xf2] = MMX_OP2(pslld),
2831 [0xf3] = MMX_OP2(psllq),
2832 [0xf4] = MMX_OP2(pmuludq),
2833 [0xf5] = MMX_OP2(pmaddwd),
2834 [0xf6] = MMX_OP2(psadbw),
2835 [0xf7] = MMX_OP2(maskmov),
2836 [0xf8] = MMX_OP2(psubb),
2837 [0xf9] = MMX_OP2(psubw),
2838 [0xfa] = MMX_OP2(psubl),
2839 [0xfb] = MMX_OP2(psubq),
2840 [0xfc] = MMX_OP2(paddb),
2841 [0xfd] = MMX_OP2(paddw),
2842 [0xfe] = MMX_OP2(paddl),
2843 };
2844
2845 static void *sse_op_table2[3 * 8][2] = {
2846 [0 + 2] = MMX_OP2(psrlw),
2847 [0 + 4] = MMX_OP2(psraw),
2848 [0 + 6] = MMX_OP2(psllw),
2849 [8 + 2] = MMX_OP2(psrld),
2850 [8 + 4] = MMX_OP2(psrad),
2851 [8 + 6] = MMX_OP2(pslld),
2852 [16 + 2] = MMX_OP2(psrlq),
2853 [16 + 3] = { NULL, helper_psrldq_xmm },
2854 [16 + 6] = MMX_OP2(psllq),
2855 [16 + 7] = { NULL, helper_pslldq_xmm },
2856 };
2857
2858 static void *sse_op_table3[4 * 3] = {
2859 helper_cvtsi2ss,
2860 helper_cvtsi2sd,
2861 X86_64_ONLY(helper_cvtsq2ss),
2862 X86_64_ONLY(helper_cvtsq2sd),
2863
2864 helper_cvttss2si,
2865 helper_cvttsd2si,
2866 X86_64_ONLY(helper_cvttss2sq),
2867 X86_64_ONLY(helper_cvttsd2sq),
2868
2869 helper_cvtss2si,
2870 helper_cvtsd2si,
2871 X86_64_ONLY(helper_cvtss2sq),
2872 X86_64_ONLY(helper_cvtsd2sq),
2873 };
2874
2875 static void *sse_op_table4[8][4] = {
2876 SSE_FOP(cmpeq),
2877 SSE_FOP(cmplt),
2878 SSE_FOP(cmple),
2879 SSE_FOP(cmpunord),
2880 SSE_FOP(cmpneq),
2881 SSE_FOP(cmpnlt),
2882 SSE_FOP(cmpnle),
2883 SSE_FOP(cmpord),
2884 };
2885
2886 static void *sse_op_table5[256] = {
2887 [0x0c] = helper_pi2fw,
2888 [0x0d] = helper_pi2fd,
2889 [0x1c] = helper_pf2iw,
2890 [0x1d] = helper_pf2id,
2891 [0x8a] = helper_pfnacc,
2892 [0x8e] = helper_pfpnacc,
2893 [0x90] = helper_pfcmpge,
2894 [0x94] = helper_pfmin,
2895 [0x96] = helper_pfrcp,
2896 [0x97] = helper_pfrsqrt,
2897 [0x9a] = helper_pfsub,
2898 [0x9e] = helper_pfadd,
2899 [0xa0] = helper_pfcmpgt,
2900 [0xa4] = helper_pfmax,
2901 [0xa6] = helper_movq, /* pfrcpit1; no need to actually increase precision */
2902 [0xa7] = helper_movq, /* pfrsqit1 */
2903 [0xaa] = helper_pfsubr,
2904 [0xae] = helper_pfacc,
2905 [0xb0] = helper_pfcmpeq,
2906 [0xb4] = helper_pfmul,
2907 [0xb6] = helper_movq, /* pfrcpit2 */
2908 [0xb7] = helper_pmulhrw_mmx,
2909 [0xbb] = helper_pswapd,
2910 [0xbf] = helper_pavgb_mmx /* pavgusb */
2911 };
2912
2913 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
2914 {
2915 int b1, op1_offset, op2_offset, is_xmm, val, ot;
2916 int modrm, mod, rm, reg, reg_addr, offset_addr;
2917 void *sse_op2;
2918
2919 b &= 0xff;
2920 if (s->prefix & PREFIX_DATA)
2921 b1 = 1;
2922 else if (s->prefix & PREFIX_REPZ)
2923 b1 = 2;
2924 else if (s->prefix & PREFIX_REPNZ)
2925 b1 = 3;
2926 else
2927 b1 = 0;
2928 sse_op2 = sse_op_table1[b][b1];
2929 if (!sse_op2)
2930 goto illegal_op;
2931 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
2932 is_xmm = 1;
2933 } else {
2934 if (b1 == 0) {
2935 /* MMX case */
2936 is_xmm = 0;
2937 } else {
2938 is_xmm = 1;
2939 }
2940 }
2941 /* simple MMX/SSE operation */
2942 if (s->flags & HF_TS_MASK) {
2943 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
2944 return;
2945 }
2946 if (s->flags & HF_EM_MASK) {
2947 illegal_op:
2948 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
2949 return;
2950 }
2951 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
2952 goto illegal_op;
2953 if (b == 0x0e) {
2954 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
2955 goto illegal_op;
2956 /* femms */
2957 tcg_gen_helper_0_0(helper_emms);
2958 return;
2959 }
2960 if (b == 0x77) {
2961 /* emms */
2962 tcg_gen_helper_0_0(helper_emms);
2963 return;
2964 }
2965 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
2966 the static cpu state) */
2967 if (!is_xmm) {
2968 tcg_gen_helper_0_0(helper_enter_mmx);
2969 }
2970
2971 modrm = ldub_code(s->pc++);
2972 reg = ((modrm >> 3) & 7);
2973 if (is_xmm)
2974 reg |= rex_r;
2975 mod = (modrm >> 6) & 3;
2976 if (sse_op2 == SSE_SPECIAL) {
2977 b |= (b1 << 8);
2978 switch(b) {
2979 case 0x0e7: /* movntq */
2980 if (mod == 3)
2981 goto illegal_op;
2982 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2983 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
2984 break;
2985 case 0x1e7: /* movntdq */
2986 case 0x02b: /* movntps */
2987 case 0x12b: /* movntps */
2988 case 0x3f0: /* lddqu */
2989 if (mod == 3)
2990 goto illegal_op;
2991 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2992 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
2993 break;
2994 case 0x6e: /* movd mm, ea */
2995 #ifdef TARGET_X86_64
2996 if (s->dflag == 2) {
2997 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
2998 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
2999 } else
3000 #endif
3001 {
3002 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3003 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3004 offsetof(CPUX86State,fpregs[reg].mmx));
3005 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]);
3006 }
3007 break;
3008 case 0x16e: /* movd xmm, ea */
3009 #ifdef TARGET_X86_64
3010 if (s->dflag == 2) {
3011 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3012 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3013 offsetof(CPUX86State,xmm_regs[reg]));
3014 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]);
3015 } else
3016 #endif
3017 {
3018 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3019 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3020 offsetof(CPUX86State,xmm_regs[reg]));
3021 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3022 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm, cpu_ptr0, cpu_tmp2_i32);
3023 }
3024 break;
3025 case 0x6f: /* movq mm, ea */
3026 if (mod != 3) {
3027 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3028 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3029 } else {
3030 rm = (modrm & 7);
3031 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3032 offsetof(CPUX86State,fpregs[rm].mmx));
3033 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3034 offsetof(CPUX86State,fpregs[reg].mmx));
3035 }
3036 break;
3037 case 0x010: /* movups */
3038 case 0x110: /* movupd */
3039 case 0x028: /* movaps */
3040 case 0x128: /* movapd */
3041 case 0x16f: /* movdqa xmm, ea */
3042 case 0x26f: /* movdqu xmm, ea */
3043 if (mod != 3) {
3044 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3045 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3046 } else {
3047 rm = (modrm & 7) | REX_B(s);
3048 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3049 offsetof(CPUX86State,xmm_regs[rm]));
3050 }
3051 break;
3052 case 0x210: /* movss xmm, ea */
3053 if (mod != 3) {
3054 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3055 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3056 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3057 gen_op_movl_T0_0();
3058 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3059 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3060 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3061 } else {
3062 rm = (modrm & 7) | REX_B(s);
3063 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3064 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3065 }
3066 break;
3067 case 0x310: /* movsd xmm, ea */
3068 if (mod != 3) {
3069 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3070 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3071 gen_op_movl_T0_0();
3072 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3073 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3074 } else {
3075 rm = (modrm & 7) | REX_B(s);
3076 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3077 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3078 }
3079 break;
3080 case 0x012: /* movlps */
3081 case 0x112: /* movlpd */
3082 if (mod != 3) {
3083 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3084 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3085 } else {
3086 /* movhlps */
3087 rm = (modrm & 7) | REX_B(s);
3088 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3089 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3090 }
3091 break;
3092 case 0x212: /* movsldup */
3093 if (mod != 3) {
3094 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3095 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3096 } else {
3097 rm = (modrm & 7) | REX_B(s);
3098 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3099 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3100 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3101 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3102 }
3103 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3104 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3105 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3106 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3107 break;
3108 case 0x312: /* movddup */
3109 if (mod != 3) {
3110 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3111 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3112 } else {
3113 rm = (modrm & 7) | REX_B(s);
3114 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3115 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3116 }
3117 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3118 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3119 break;
3120 case 0x016: /* movhps */
3121 case 0x116: /* movhpd */
3122 if (mod != 3) {
3123 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3124 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3125 } else {
3126 /* movlhps */
3127 rm = (modrm & 7) | REX_B(s);
3128 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3129 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3130 }
3131 break;
3132 case 0x216: /* movshdup */
3133 if (mod != 3) {
3134 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3135 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3136 } else {
3137 rm = (modrm & 7) | REX_B(s);
3138 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3139 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3140 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3141 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3142 }
3143 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3144 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3145 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3146 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3147 break;
3148 case 0x7e: /* movd ea, mm */
3149 #ifdef TARGET_X86_64
3150 if (s->dflag == 2) {
3151 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3152 offsetof(CPUX86State,fpregs[reg].mmx));
3153 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3154 } else
3155 #endif
3156 {
3157 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3158 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3159 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3160 }
3161 break;
3162 case 0x17e: /* movd ea, xmm */
3163 #ifdef TARGET_X86_64
3164 if (s->dflag == 2) {
3165 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3166 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3167 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3168 } else
3169 #endif
3170 {
3171 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3172 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3173 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3174 }
3175 break;
3176 case 0x27e: /* movq xmm, ea */
3177 if (mod != 3) {
3178 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3179 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3180 } else {
3181 rm = (modrm & 7) | REX_B(s);
3182 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3183 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3184 }
3185 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3186 break;
3187 case 0x7f: /* movq ea, mm */
3188 if (mod != 3) {
3189 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3190 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3191 } else {
3192 rm = (modrm & 7);
3193 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3194 offsetof(CPUX86State,fpregs[reg].mmx));
3195 }
3196 break;
3197 case 0x011: /* movups */
3198 case 0x111: /* movupd */
3199 case 0x029: /* movaps */
3200 case 0x129: /* movapd */
3201 case 0x17f: /* movdqa ea, xmm */
3202 case 0x27f: /* movdqu ea, xmm */
3203 if (mod != 3) {
3204 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3205 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3206 } else {
3207 rm = (modrm & 7) | REX_B(s);
3208 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3209 offsetof(CPUX86State,xmm_regs[reg]));
3210 }
3211 break;
3212 case 0x211: /* movss ea, xmm */
3213 if (mod != 3) {
3214 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3215 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3216 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3217 } else {
3218 rm = (modrm & 7) | REX_B(s);
3219 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3220 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3221 }
3222 break;
3223 case 0x311: /* movsd ea, xmm */
3224 if (mod != 3) {
3225 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3226 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3227 } else {
3228 rm = (modrm & 7) | REX_B(s);
3229 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3230 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3231 }
3232 break;
3233 case 0x013: /* movlps */
3234 case 0x113: /* movlpd */
3235 if (mod != 3) {
3236 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3237 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3238 } else {
3239 goto illegal_op;
3240 }
3241 break;
3242 case 0x017: /* movhps */
3243 case 0x117: /* movhpd */
3244 if (mod != 3) {
3245 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3246 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3247 } else {
3248 goto illegal_op;
3249 }
3250 break;
3251 case 0x71: /* shift mm, im */
3252 case 0x72:
3253 case 0x73:
3254 case 0x171: /* shift xmm, im */
3255 case 0x172:
3256 case 0x173:
3257 val = ldub_code(s->pc++);
3258 if (is_xmm) {
3259 gen_op_movl_T0_im(val);
3260 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3261 gen_op_movl_T0_0();
3262 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3263 op1_offset = offsetof(CPUX86State,xmm_t0);
3264 } else {
3265 gen_op_movl_T0_im(val);
3266 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3267 gen_op_movl_T0_0();
3268 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3269 op1_offset = offsetof(CPUX86State,mmx_t0);
3270 }
3271 sse_op2 = sse_op_table2[((b - 1) & 3) * 8 + (((modrm >> 3)) & 7)][b1];
3272 if (!sse_op2)
3273 goto illegal_op;
3274 if (is_xmm) {
3275 rm = (modrm & 7) | REX_B(s);
3276 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3277 } else {
3278 rm = (modrm & 7);
3279 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3280 }
3281 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3282 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3283 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3284 break;
3285 case 0x050: /* movmskps */
3286 rm = (modrm & 7) | REX_B(s);
3287 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3288 offsetof(CPUX86State,xmm_regs[rm]));
3289 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0);
3290 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3291 gen_op_mov_reg_T0(OT_LONG, reg);
3292 break;
3293 case 0x150: /* movmskpd */
3294 rm = (modrm & 7) | REX_B(s);
3295 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3296 offsetof(CPUX86State,xmm_regs[rm]));
3297 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0);
3298 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3299 gen_op_mov_reg_T0(OT_LONG, reg);
3300 break;
3301 case 0x02a: /* cvtpi2ps */
3302 case 0x12a: /* cvtpi2pd */
3303 tcg_gen_helper_0_0(helper_enter_mmx);
3304 if (mod != 3) {
3305 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3306 op2_offset = offsetof(CPUX86State,mmx_t0);
3307 gen_ldq_env_A0(s->mem_index, op2_offset);
3308 } else {
3309 rm = (modrm & 7);
3310 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3311 }
3312 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3313 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3314 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3315 switch(b >> 8) {
3316 case 0x0:
3317 tcg_gen_helper_0_2(helper_cvtpi2ps, cpu_ptr0, cpu_ptr1);
3318 break;
3319 default:
3320 case 0x1:
3321 tcg_gen_helper_0_2(helper_cvtpi2pd, cpu_ptr0, cpu_ptr1);
3322 break;
3323 }
3324 break;
3325 case 0x22a: /* cvtsi2ss */
3326 case 0x32a: /* cvtsi2sd */
3327 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3328 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3329 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3330 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3331 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2)];
3332 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3333 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_tmp2_i32);
3334 break;
3335 case 0x02c: /* cvttps2pi */
3336 case 0x12c: /* cvttpd2pi */
3337 case 0x02d: /* cvtps2pi */
3338 case 0x12d: /* cvtpd2pi */
3339 tcg_gen_helper_0_0(helper_enter_mmx);
3340 if (mod != 3) {
3341 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3342 op2_offset = offsetof(CPUX86State,xmm_t0);
3343 gen_ldo_env_A0(s->mem_index, op2_offset);
3344 } else {
3345 rm = (modrm & 7) | REX_B(s);
3346 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3347 }
3348 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3349 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3350 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3351 switch(b) {
3352 case 0x02c:
3353 tcg_gen_helper_0_2(helper_cvttps2pi, cpu_ptr0, cpu_ptr1);
3354 break;
3355 case 0x12c:
3356 tcg_gen_helper_0_2(helper_cvttpd2pi, cpu_ptr0, cpu_ptr1);
3357 break;
3358 case 0x02d:
3359 tcg_gen_helper_0_2(helper_cvtps2pi, cpu_ptr0, cpu_ptr1);
3360 break;
3361 case 0x12d:
3362 tcg_gen_helper_0_2(helper_cvtpd2pi, cpu_ptr0, cpu_ptr1);
3363 break;
3364 }
3365 break;
3366 case 0x22c: /* cvttss2si */
3367 case 0x32c: /* cvttsd2si */
3368 case 0x22d: /* cvtss2si */
3369 case 0x32d: /* cvtsd2si */
3370 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3371 if (mod != 3) {
3372 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3373 if ((b >> 8) & 1) {
3374 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3375 } else {
3376 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3377 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3378 }
3379 op2_offset = offsetof(CPUX86State,xmm_t0);
3380 } else {
3381 rm = (modrm & 7) | REX_B(s);
3382 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3383 }
3384 sse_op2 = sse_op_table3[(s->dflag == 2) * 2 + ((b >> 8) - 2) + 4 +
3385 (b & 1) * 4];
3386 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3387 if (ot == OT_LONG) {
3388 tcg_gen_helper_1_1(sse_op2, cpu_tmp2_i32, cpu_ptr0);
3389 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3390 } else {
3391 tcg_gen_helper_1_1(sse_op2, cpu_T[0], cpu_ptr0);
3392 }
3393 gen_op_mov_reg_T0(ot, reg);
3394 break;
3395 case 0xc4: /* pinsrw */
3396 case 0x1c4:
3397 s->rip_offset = 1;
3398 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3399 val = ldub_code(s->pc++);
3400 if (b1) {
3401 val &= 7;
3402 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3403 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3404 } else {
3405 val &= 3;
3406 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3407 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3408 }
3409 break;
3410 case 0xc5: /* pextrw */
3411 case 0x1c5:
3412 if (mod != 3)
3413 goto illegal_op;
3414 val = ldub_code(s->pc++);
3415 if (b1) {
3416 val &= 7;
3417 rm = (modrm & 7) | REX_B(s);
3418 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3419 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3420 } else {
3421 val &= 3;
3422 rm = (modrm & 7);
3423 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3424 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3425 }
3426 reg = ((modrm >> 3) & 7) | rex_r;
3427 gen_op_mov_reg_T0(OT_LONG, reg);
3428 break;
3429 case 0x1d6: /* movq ea, xmm */
3430 if (mod != 3) {
3431 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3432 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3433 } else {
3434 rm = (modrm & 7) | REX_B(s);
3435 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3436 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3437 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3438 }
3439 break;
3440 case 0x2d6: /* movq2dq */
3441 tcg_gen_helper_0_0(helper_enter_mmx);
3442 rm = (modrm & 7);
3443 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3444 offsetof(CPUX86State,fpregs[rm].mmx));
3445 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3446 break;
3447 case 0x3d6: /* movdq2q */
3448 tcg_gen_helper_0_0(helper_enter_mmx);
3449 rm = (modrm & 7) | REX_B(s);
3450 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3451 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3452 break;
3453 case 0xd7: /* pmovmskb */
3454 case 0x1d7:
3455 if (mod != 3)
3456 goto illegal_op;
3457 if (b1) {
3458 rm = (modrm & 7) | REX_B(s);
3459 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3460 tcg_gen_helper_1_1(helper_pmovmskb_xmm, cpu_tmp2_i32, cpu_ptr0);
3461 } else {
3462 rm = (modrm & 7);
3463 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3464 tcg_gen_helper_1_1(helper_pmovmskb_mmx, cpu_tmp2_i32, cpu_ptr0);
3465 }
3466 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3467 reg = ((modrm >> 3) & 7) | rex_r;
3468 gen_op_mov_reg_T0(OT_LONG, reg);
3469 break;
3470 default:
3471 goto illegal_op;
3472 }
3473 } else {
3474 /* generic MMX or SSE operation */
3475 switch(b) {
3476 case 0x70: /* pshufx insn */
3477 case 0xc6: /* pshufx insn */
3478 case 0xc2: /* compare insns */
3479 s->rip_offset = 1;
3480 break;
3481 default:
3482 break;
3483 }
3484 if (is_xmm) {
3485 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3486 if (mod != 3) {
3487 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3488 op2_offset = offsetof(CPUX86State,xmm_t0);
3489 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
3490 b == 0xc2)) {
3491 /* specific case for SSE single instructions */
3492 if (b1 == 2) {
3493 /* 32 bit access */
3494 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3495 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3496 } else {
3497 /* 64 bit access */
3498 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
3499 }
3500 } else {
3501 gen_ldo_env_A0(s->mem_index, op2_offset);
3502 }
3503 } else {
3504 rm = (modrm & 7) | REX_B(s);
3505 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3506 }
3507 } else {
3508 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3509 if (mod != 3) {
3510 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3511 op2_offset = offsetof(CPUX86State,mmx_t0);
3512 gen_ldq_env_A0(s->mem_index, op2_offset);
3513 } else {
3514 rm = (modrm & 7);
3515 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3516 }
3517 }
3518 switch(b) {
3519 case 0x0f: /* 3DNow! data insns */
3520 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3521 goto illegal_op;
3522 val = ldub_code(s->pc++);
3523 sse_op2 = sse_op_table5[val];
3524 if (!sse_op2)
3525 goto illegal_op;
3526 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3527 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3528 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3529 break;
3530 case 0x70: /* pshufx insn */
3531 case 0xc6: /* pshufx insn */
3532 val = ldub_code(s->pc++);
3533 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3534 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3535 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
3536 break;
3537 case 0xc2:
3538 /* compare insns */
3539 val = ldub_code(s->pc++);
3540 if (val >= 8)
3541 goto illegal_op;
3542 sse_op2 = sse_op_table4[val][b1];
3543 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3544 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3545 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3546 break;
3547 case 0xf7:
3548 /* maskmov : we must prepare A0 */
3549 if (mod != 3)
3550 goto illegal_op;
3551 #ifdef TARGET_X86_64
3552 if (s->aflag == 2) {
3553 gen_op_movq_A0_reg(R_EDI);
3554 } else
3555 #endif
3556 {
3557 gen_op_movl_A0_reg(R_EDI);
3558 if (s->aflag == 0)
3559 gen_op_andl_A0_ffff();
3560 }
3561 gen_add_A0_ds_seg(s);
3562
3563 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3564 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3565 tcg_gen_helper_0_3(sse_op2, cpu_ptr0, cpu_ptr1, cpu_A0);
3566 break;
3567 default:
3568 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3569 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3570 tcg_gen_helper_0_2(sse_op2, cpu_ptr0, cpu_ptr1);
3571 break;
3572 }
3573 if (b == 0x2e || b == 0x2f) {
3574 s->cc_op = CC_OP_EFLAGS;
3575 }
3576 }
3577 }
3578
3579 /* convert one instruction. s->is_jmp is set if the translation must
3580 be stopped. Return the next pc value */
3581 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
3582 {
3583 int b, prefixes, aflag, dflag;
3584 int shift, ot;
3585 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
3586 target_ulong next_eip, tval;
3587 int rex_w, rex_r;
3588
3589 s->pc = pc_start;
3590 prefixes = 0;
3591 aflag = s->code32;
3592 dflag = s->code32;
3593 s->override = -1;
3594 rex_w = -1;
3595 rex_r = 0;
3596 #ifdef TARGET_X86_64
3597 s->rex_x = 0;
3598 s->rex_b = 0;
3599 x86_64_hregs = 0;
3600 #endif
3601 s->rip_offset = 0; /* for relative ip address */
3602 next_byte:
3603 b = ldub_code(s->pc);
3604 s->pc++;
3605 /* check prefixes */
3606 #ifdef TARGET_X86_64
3607 if (CODE64(s)) {
3608 switch (b) {
3609 case 0xf3:
3610 prefixes |= PREFIX_REPZ;
3611 goto next_byte;
3612 case 0xf2:
3613 prefixes |= PREFIX_REPNZ;
3614 goto next_byte;
3615 case 0xf0:
3616 prefixes |= PREFIX_LOCK;
3617 goto next_byte;
3618 case 0x2e:
3619 s->override = R_CS;
3620 goto next_byte;
3621 case 0x36:
3622 s->override = R_SS;
3623 goto next_byte;
3624 case 0x3e:
3625 s->override = R_DS;
3626 goto next_byte;
3627 case 0x26:
3628 s->override = R_ES;
3629 goto next_byte;
3630 case 0x64:
3631 s->override = R_FS;
3632 goto next_byte;
3633 case 0x65:
3634 s->override = R_GS;
3635 goto next_byte;
3636 case 0x66:
3637 prefixes |= PREFIX_DATA;
3638 goto next_byte;
3639 case 0x67:
3640 prefixes |= PREFIX_ADR;
3641 goto next_byte;
3642 case 0x40 ... 0x4f:
3643 /* REX prefix */
3644 rex_w = (b >> 3) & 1;
3645 rex_r = (b & 0x4) << 1;
3646 s->rex_x = (b & 0x2) << 2;
3647 REX_B(s) = (b & 0x1) << 3;
3648 x86_64_hregs = 1; /* select uniform byte register addressing */
3649 goto next_byte;
3650 }
3651 if (rex_w == 1) {
3652 /* 0x66 is ignored if rex.w is set */
3653 dflag = 2;
3654 } else {
3655 if (prefixes & PREFIX_DATA)
3656 dflag ^= 1;
3657 }
3658 if (!(prefixes & PREFIX_ADR))
3659 aflag = 2;
3660 } else
3661 #endif
3662 {
3663 switch (b) {
3664 case 0xf3:
3665 prefixes |= PREFIX_REPZ;
3666 goto next_byte;
3667 case 0xf2:
3668 prefixes |= PREFIX_REPNZ;
3669 goto next_byte;
3670 case 0xf0:
3671 prefixes |= PREFIX_LOCK;
3672 goto next_byte;
3673 case 0x2e:
3674 s->override = R_CS;
3675 goto next_byte;
3676 case 0x36:
3677 s->override = R_SS;
3678 goto next_byte;
3679 case 0x3e:
3680 s->override = R_DS;
3681 goto next_byte;
3682 case 0x26:
3683 s->override = R_ES;
3684 goto next_byte;
3685 case 0x64:
3686 s->override = R_FS;
3687 goto next_byte;
3688 case 0x65:
3689 s->override = R_GS;
3690 goto next_byte;
3691 case 0x66:
3692 prefixes |= PREFIX_DATA;
3693 goto next_byte;
3694 case 0x67:
3695 prefixes |= PREFIX_ADR;
3696 goto next_byte;
3697 }
3698 if (prefixes & PREFIX_DATA)
3699 dflag ^= 1;
3700 if (prefixes & PREFIX_ADR)
3701 aflag ^= 1;
3702 }
3703
3704 s->prefix = prefixes;
3705 s->aflag = aflag;
3706 s->dflag = dflag;
3707
3708 /* lock generation */
3709 if (prefixes & PREFIX_LOCK)
3710 tcg_gen_helper_0_0(helper_lock);
3711
3712 /* now check op code */
3713 reswitch:
3714 switch(b) {
3715 case 0x0f:
3716 /**************************/
3717 /* extended op code */
3718 b = ldub_code(s->pc++) | 0x100;
3719 goto reswitch;
3720
3721 /**************************/
3722 /* arith & logic */
3723 case 0x00 ... 0x05:
3724 case 0x08 ... 0x0d:
3725 case 0x10 ... 0x15:
3726 case 0x18 ... 0x1d:
3727 case 0x20 ... 0x25:
3728 case 0x28 ... 0x2d:
3729 case 0x30 ... 0x35:
3730 case 0x38 ... 0x3d:
3731 {
3732 int op, f, val;
3733 op = (b >> 3) & 7;
3734 f = (b >> 1) & 3;
3735
3736 if ((b & 1) == 0)
3737 ot = OT_BYTE;
3738 else
3739 ot = dflag + OT_WORD;
3740
3741 switch(f) {
3742 case 0: /* OP Ev, Gv */
3743 modrm = ldub_code(s->pc++);
3744 reg = ((modrm >> 3) & 7) | rex_r;
3745 mod = (modrm >> 6) & 3;
3746 rm = (modrm & 7) | REX_B(s);
3747 if (mod != 3) {
3748 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3749 opreg = OR_TMP0;
3750 } else if (op == OP_XORL && rm == reg) {
3751 xor_zero:
3752 /* xor reg, reg optimisation */
3753 gen_op_movl_T0_0();
3754 s->cc_op = CC_OP_LOGICB + ot;
3755 gen_op_mov_reg_T0(ot, reg);
3756 gen_op_update1_cc();
3757 break;
3758 } else {
3759 opreg = rm;
3760 }
3761 gen_op_mov_TN_reg(ot, 1, reg);
3762 gen_op(s, op, ot, opreg);
3763 break;
3764 case 1: /* OP Gv, Ev */
3765 modrm = ldub_code(s->pc++);
3766 mod = (modrm >> 6) & 3;
3767 reg = ((modrm >> 3) & 7) | rex_r;
3768 rm = (modrm & 7) | REX_B(s);
3769 if (mod != 3) {
3770 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3771 gen_op_ld_T1_A0(ot + s->mem_index);
3772 } else if (op == OP_XORL && rm == reg) {
3773 goto xor_zero;
3774 } else {
3775 gen_op_mov_TN_reg(ot, 1, rm);
3776 }
3777 gen_op(s, op, ot, reg);
3778 break;
3779 case 2: /* OP A, Iv */
3780 val = insn_get(s, ot);
3781 gen_op_movl_T1_im(val);
3782 gen_op(s, op, ot, OR_EAX);
3783 break;
3784 }
3785 }
3786 break;
3787
3788 case 0x80: /* GRP1 */
3789 case 0x81:
3790 case 0x82:
3791 case 0x83:
3792 {
3793 int val;
3794
3795 if ((b & 1) == 0)
3796 ot = OT_BYTE;
3797 else
3798 ot = dflag + OT_WORD;
3799
3800 modrm = ldub_code(s->pc++);
3801 mod = (modrm >> 6) & 3;
3802 rm = (modrm & 7) | REX_B(s);
3803 op = (modrm >> 3) & 7;
3804
3805 if (mod != 3) {
3806 if (b == 0x83)
3807 s->rip_offset = 1;
3808 else
3809 s->rip_offset = insn_const_size(ot);
3810 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3811 opreg = OR_TMP0;
3812 } else {
3813 opreg = rm;
3814 }
3815
3816 switch(b) {
3817 default:
3818 case 0x80:
3819 case 0x81:
3820 case 0x82:
3821 val = insn_get(s, ot);
3822 break;
3823 case 0x83:
3824 val = (int8_t)insn_get(s, OT_BYTE);
3825 break;
3826 }
3827 gen_op_movl_T1_im(val);
3828 gen_op(s, op, ot, opreg);
3829 }
3830 break;
3831
3832 /**************************/
3833 /* inc, dec, and other misc arith */
3834 case 0x40 ... 0x47: /* inc Gv */
3835 ot = dflag ? OT_LONG : OT_WORD;
3836 gen_inc(s, ot, OR_EAX + (b & 7), 1);
3837 break;
3838 case 0x48 ... 0x4f: /* dec Gv */
3839 ot = dflag ? OT_LONG : OT_WORD;
3840 gen_inc(s, ot, OR_EAX + (b & 7), -1);
3841 break;
3842 case 0xf6: /* GRP3 */
3843 case 0xf7:
3844 if ((b & 1) == 0)
3845 ot = OT_BYTE;
3846 else
3847 ot = dflag + OT_WORD;
3848
3849 modrm = ldub_code(s->pc++);
3850 mod = (modrm >> 6) & 3;
3851 rm = (modrm & 7) | REX_B(s);
3852 op = (modrm >> 3) & 7;
3853 if (mod != 3) {
3854 if (op == 0)
3855 s->rip_offset = insn_const_size(ot);
3856 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3857 gen_op_ld_T0_A0(ot + s->mem_index);
3858 } else {
3859 gen_op_mov_TN_reg(ot, 0, rm);
3860 }
3861
3862 switch(op) {
3863 case 0: /* test */
3864 val = insn_get(s, ot);
3865 gen_op_movl_T1_im(val);
3866 gen_op_testl_T0_T1_cc();
3867 s->cc_op = CC_OP_LOGICB + ot;
3868 break;
3869 case 2: /* not */
3870 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
3871 if (mod != 3) {
3872 gen_op_st_T0_A0(ot + s->mem_index);
3873 } else {
3874 gen_op_mov_reg_T0(ot, rm);
3875 }
3876 break;
3877 case 3: /* neg */
3878 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
3879 if (mod != 3) {
3880 gen_op_st_T0_A0(ot + s->mem_index);
3881 } else {
3882 gen_op_mov_reg_T0(ot, rm);
3883 }
3884 gen_op_update_neg_cc();
3885 s->cc_op = CC_OP_SUBB + ot;
3886 break;
3887 case 4: /* mul */
3888 switch(ot) {
3889 case OT_BYTE:
3890 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
3891 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
3892 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
3893 /* XXX: use 32 bit mul which could be faster */
3894 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3895 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3896 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3897 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
3898 s->cc_op = CC_OP_MULB;
3899 break;
3900 case OT_WORD:
3901 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
3902 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
3903 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
3904 /* XXX: use 32 bit mul which could be faster */
3905 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3906 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3907 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3908 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
3909 gen_op_mov_reg_T0(OT_WORD, R_EDX);
3910 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3911 s->cc_op = CC_OP_MULW;
3912 break;
3913 default:
3914 case OT_LONG:
3915 #ifdef TARGET_X86_64
3916 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3917 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
3918 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
3919 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3920 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3921 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3922 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
3923 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3924 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3925 #else
3926 {
3927 TCGv t0, t1;
3928 t0 = tcg_temp_new(TCG_TYPE_I64);
3929 t1 = tcg_temp_new(TCG_TYPE_I64);
3930 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3931 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
3932 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
3933 tcg_gen_mul_i64(t0, t0, t1);
3934 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
3935 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3936 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3937 tcg_gen_shri_i64(t0, t0, 32);
3938 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
3939 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3940 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
3941 }
3942 #endif
3943 s->cc_op = CC_OP_MULL;
3944 break;
3945 #ifdef TARGET_X86_64
3946 case OT_QUAD:
3947 tcg_gen_helper_0_1(helper_mulq_EAX_T0, cpu_T[0]);
3948 s->cc_op = CC_OP_MULQ;
3949 break;
3950 #endif
3951 }
3952 break;
3953 case 5: /* imul */
3954 switch(ot) {
3955 case OT_BYTE:
3956 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
3957 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
3958 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
3959 /* XXX: use 32 bit mul which could be faster */
3960 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3961 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3962 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3963 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
3964 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3965 s->cc_op = CC_OP_MULB;
3966 break;
3967 case OT_WORD:
3968 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
3969 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
3970 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
3971 /* XXX: use 32 bit mul which could be faster */
3972 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3973 gen_op_mov_reg_T0(OT_WORD, R_EAX);
3974 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3975 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
3976 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3977 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
3978 gen_op_mov_reg_T0(OT_WORD, R_EDX);
3979 s->cc_op = CC_OP_MULW;
3980 break;
3981 default:
3982 case OT_LONG:
3983 #ifdef TARGET_X86_64
3984 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
3985 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
3986 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
3987 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3988 gen_op_mov_reg_T0(OT_LONG, R_EAX);
3989 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
3990 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
3991 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
3992 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
3993 gen_op_mov_reg_T0(OT_LONG, R_EDX);
3994 #else
3995 {
3996 TCGv t0, t1;
3997 t0 = tcg_temp_new(TCG_TYPE_I64);
3998 t1 = tcg_temp_new(TCG_TYPE_I64);
3999 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4000 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4001 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4002 tcg_gen_mul_i64(t0, t0, t1);
4003 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4004 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4005 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4006 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4007 tcg_gen_shri_i64(t0, t0, 32);
4008 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4009 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4010 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4011 }
4012 #endif
4013 s->cc_op = CC_OP_MULL;
4014 break;
4015 #ifdef TARGET_X86_64
4016 case OT_QUAD:
4017 tcg_gen_helper_0_1(helper_imulq_EAX_T0, cpu_T[0]);
4018 s->cc_op = CC_OP_MULQ;
4019 break;
4020 #endif
4021 }
4022 break;
4023 case 6: /* div */
4024 switch(ot) {
4025 case OT_BYTE:
4026 gen_jmp_im(pc_start - s->cs_base);
4027 tcg_gen_helper_0_1(helper_divb_AL, cpu_T[0]);
4028 break;
4029 case OT_WORD:
4030 gen_jmp_im(pc_start - s->cs_base);
4031 tcg_gen_helper_0_1(helper_divw_AX, cpu_T[0]);
4032 break;
4033 default:
4034 case OT_LONG:
4035 gen_jmp_im(pc_start - s->cs_base);
4036 tcg_gen_helper_0_1(helper_divl_EAX, cpu_T[0]);
4037 break;
4038 #ifdef TARGET_X86_64
4039 case OT_QUAD:
4040 gen_jmp_im(pc_start - s->cs_base);
4041 tcg_gen_helper_0_1(helper_divq_EAX, cpu_T[0]);
4042 break;
4043 #endif
4044 }
4045 break;
4046 case 7: /* idiv */
4047 switch(ot) {
4048 case OT_BYTE:
4049 gen_jmp_im(pc_start - s->cs_base);
4050 tcg_gen_helper_0_1(helper_idivb_AL, cpu_T[0]);
4051 break;
4052 case OT_WORD:
4053 gen_jmp_im(pc_start - s->cs_base);
4054 tcg_gen_helper_0_1(helper_idivw_AX, cpu_T[0]);
4055 break;
4056 default:
4057 case OT_LONG:
4058 gen_jmp_im(pc_start - s->cs_base);
4059 tcg_gen_helper_0_1(helper_idivl_EAX, cpu_T[0]);
4060 break;
4061 #ifdef TARGET_X86_64
4062 case OT_QUAD:
4063 gen_jmp_im(pc_start - s->cs_base);
4064 tcg_gen_helper_0_1(helper_idivq_EAX, cpu_T[0]);
4065 break;
4066 #endif
4067 }
4068 break;
4069 default:
4070 goto illegal_op;
4071 }
4072 break;
4073
4074 case 0xfe: /* GRP4 */
4075 case 0xff: /* GRP5 */
4076 if ((b & 1) == 0)
4077 ot = OT_BYTE;
4078 else
4079 ot = dflag + OT_WORD;
4080
4081 modrm = ldub_code(s->pc++);
4082 mod = (modrm >> 6) & 3;
4083 rm = (modrm & 7) | REX_B(s);
4084 op = (modrm >> 3) & 7;
4085 if (op >= 2 && b == 0xfe) {
4086 goto illegal_op;
4087 }
4088 if (CODE64(s)) {
4089 if (op == 2 || op == 4) {
4090 /* operand size for jumps is 64 bit */
4091 ot = OT_QUAD;
4092 } else if (op == 3 || op == 5) {
4093 /* for call calls, the operand is 16 or 32 bit, even
4094 in long mode */
4095 ot = dflag ? OT_LONG : OT_WORD;
4096 } else if (op == 6) {
4097 /* default push size is 64 bit */
4098 ot = dflag ? OT_QUAD : OT_WORD;
4099 }
4100 }
4101 if (mod != 3) {
4102 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4103 if (op >= 2 && op != 3 && op != 5)
4104 gen_op_ld_T0_A0(ot + s->mem_index);
4105 } else {
4106 gen_op_mov_TN_reg(ot, 0, rm);
4107 }
4108
4109 switch(op) {
4110 case 0: /* inc Ev */
4111 if (mod != 3)
4112 opreg = OR_TMP0;
4113 else
4114 opreg = rm;
4115 gen_inc(s, ot, opreg, 1);
4116 break;
4117 case 1: /* dec Ev */
4118 if (mod != 3)
4119 opreg = OR_TMP0;
4120 else
4121 opreg = rm;
4122 gen_inc(s, ot, opreg, -1);
4123 break;
4124 case 2: /* call Ev */
4125 /* XXX: optimize if memory (no 'and' is necessary) */
4126 if (s->dflag == 0)
4127 gen_op_andl_T0_ffff();
4128 next_eip = s->pc - s->cs_base;
4129 gen_movtl_T1_im(next_eip);
4130 gen_push_T1(s);
4131 gen_op_jmp_T0();
4132 gen_eob(s);
4133 break;
4134 case 3: /* lcall Ev */
4135 gen_op_ld_T1_A0(ot + s->mem_index);
4136 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4137 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4138 do_lcall:
4139 if (s->pe && !s->vm86) {
4140 if (s->cc_op != CC_OP_DYNAMIC)
4141 gen_op_set_cc_op(s->cc_op);
4142 gen_jmp_im(pc_start - s->cs_base);
4143 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4144 tcg_gen_helper_0_4(helper_lcall_protected,
4145 cpu_tmp2_i32, cpu_T[1],
4146 tcg_const_i32(dflag),
4147 tcg_const_i32(s->pc - pc_start));
4148 } else {
4149 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4150 tcg_gen_helper_0_4(helper_lcall_real,
4151 cpu_tmp2_i32, cpu_T[1],
4152 tcg_const_i32(dflag),
4153 tcg_const_i32(s->pc - s->cs_base));
4154 }
4155 gen_eob(s);
4156 break;
4157 case 4: /* jmp Ev */
4158 if (s->dflag == 0)
4159 gen_op_andl_T0_ffff();
4160 gen_op_jmp_T0();
4161 gen_eob(s);
4162 break;
4163 case 5: /* ljmp Ev */
4164 gen_op_ld_T1_A0(ot + s->mem_index);
4165 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4166 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4167 do_ljmp:
4168 if (s->pe && !s->vm86) {
4169 if (s->cc_op != CC_OP_DYNAMIC)
4170 gen_op_set_cc_op(s->cc_op);
4171 gen_jmp_im(pc_start - s->cs_base);
4172 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4173 tcg_gen_helper_0_3(helper_ljmp_protected,
4174 cpu_tmp2_i32,
4175 cpu_T[1],
4176 tcg_const_i32(s->pc - pc_start));
4177 } else {
4178 gen_op_movl_seg_T0_vm(R_CS);
4179 gen_op_movl_T0_T1();
4180 gen_op_jmp_T0();
4181 }
4182 gen_eob(s);
4183 break;
4184 case 6: /* push Ev */
4185 gen_push_T0(s);
4186 break;
4187 default:
4188 goto illegal_op;
4189 }
4190 break;
4191
4192 case 0x84: /* test Ev, Gv */
4193 case 0x85:
4194 if ((b & 1) == 0)
4195 ot = OT_BYTE;
4196 else
4197 ot = dflag + OT_WORD;
4198
4199 modrm = ldub_code(s->pc++);
4200 mod = (modrm >> 6) & 3;
4201 rm = (modrm & 7) | REX_B(s);
4202 reg = ((modrm >> 3) & 7) | rex_r;
4203
4204 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4205 gen_op_mov_TN_reg(ot, 1, reg);
4206 gen_op_testl_T0_T1_cc();
4207 s->cc_op = CC_OP_LOGICB + ot;
4208 break;
4209
4210 case 0xa8: /* test eAX, Iv */
4211 case 0xa9:
4212 if ((b & 1) == 0)
4213 ot = OT_BYTE;
4214 else
4215 ot = dflag + OT_WORD;
4216 val = insn_get(s, ot);
4217
4218 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4219 gen_op_movl_T1_im(val);
4220 gen_op_testl_T0_T1_cc();
4221 s->cc_op = CC_OP_LOGICB + ot;
4222 break;
4223
4224 case 0x98: /* CWDE/CBW */
4225 #ifdef TARGET_X86_64
4226 if (dflag == 2) {
4227 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4228 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4229 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4230 } else
4231 #endif
4232 if (dflag == 1) {
4233 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4234 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4235 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4236 } else {
4237 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4238 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4239 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4240 }
4241 break;
4242 case 0x99: /* CDQ/CWD */
4243 #ifdef TARGET_X86_64
4244 if (dflag == 2) {
4245 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4246 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4247 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4248 } else
4249 #endif
4250 if (dflag == 1) {
4251 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4252 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4253 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4254 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4255 } else {
4256 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4257 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4258 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4259 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4260 }
4261 break;
4262 case 0x1af: /* imul Gv, Ev */
4263 case 0x69: /* imul Gv, Ev, I */
4264 case 0x6b:
4265 ot = dflag + OT_WORD;
4266 modrm = ldub_code(s->pc++);
4267 reg = ((modrm >> 3) & 7) | rex_r;
4268 if (b == 0x69)
4269 s->rip_offset = insn_const_size(ot);
4270 else if (b == 0x6b)
4271 s->rip_offset = 1;
4272 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4273 if (b == 0x69) {
4274 val = insn_get(s, ot);
4275 gen_op_movl_T1_im(val);
4276 } else if (b == 0x6b) {
4277 val = (int8_t)insn_get(s, OT_BYTE);
4278 gen_op_movl_T1_im(val);
4279 } else {
4280 gen_op_mov_TN_reg(ot, 1, reg);
4281 }
4282
4283 #ifdef TARGET_X86_64
4284 if (ot == OT_QUAD) {
4285 tcg_gen_helper_1_2(helper_imulq_T0_T1, cpu_T[0], cpu_T[0], cpu_T[1]);
4286 } else
4287 #endif
4288 if (ot == OT_LONG) {
4289 #ifdef TARGET_X86_64
4290 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4291 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4292 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4293 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4294 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4295 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4296 #else
4297 {
4298 TCGv t0, t1;
4299 t0 = tcg_temp_new(TCG_TYPE_I64);
4300 t1 = tcg_temp_new(TCG_TYPE_I64);
4301 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4302 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4303 tcg_gen_mul_i64(t0, t0, t1);
4304 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4305 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4306 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4307 tcg_gen_shri_i64(t0, t0, 32);
4308 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4309 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4310 }
4311 #endif
4312 } else {
4313 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4314 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4315 /* XXX: use 32 bit mul which could be faster */
4316 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4317 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4318 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4319 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4320 }
4321 gen_op_mov_reg_T0(ot, reg);
4322 s->cc_op = CC_OP_MULB + ot;
4323 break;
4324 case 0x1c0:
4325 case 0x1c1: /* xadd Ev, Gv */
4326 if ((b & 1) == 0)
4327 ot = OT_BYTE;
4328 else
4329 ot = dflag + OT_WORD;
4330 modrm = ldub_code(s->pc++);
4331 reg = ((modrm >> 3) & 7) | rex_r;
4332 mod = (modrm >> 6) & 3;
4333 if (mod == 3) {
4334 rm = (modrm & 7) | REX_B(s);
4335 gen_op_mov_TN_reg(ot, 0, reg);
4336 gen_op_mov_TN_reg(ot, 1, rm);
4337 gen_op_addl_T0_T1();
4338 gen_op_mov_reg_T1(ot, reg);
4339 gen_op_mov_reg_T0(ot, rm);
4340 } else {
4341 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4342 gen_op_mov_TN_reg(ot, 0, reg);
4343 gen_op_ld_T1_A0(ot + s->mem_index);
4344 gen_op_addl_T0_T1();
4345 gen_op_st_T0_A0(ot + s->mem_index);
4346 gen_op_mov_reg_T1(ot, reg);
4347 }
4348 gen_op_update2_cc();
4349 s->cc_op = CC_OP_ADDB + ot;
4350 break;
4351 case 0x1b0:
4352 case 0x1b1: /* cmpxchg Ev, Gv */
4353 {
4354 int label1, label2;
4355
4356 if ((b & 1) == 0)
4357 ot = OT_BYTE;
4358 else
4359 ot = dflag + OT_WORD;
4360 modrm = ldub_code(s->pc++);
4361 reg = ((modrm >> 3) & 7) | rex_r;
4362 mod = (modrm >> 6) & 3;
4363 gen_op_mov_TN_reg(ot, 1, reg);
4364 if (mod == 3) {
4365 rm = (modrm & 7) | REX_B(s);
4366 gen_op_mov_TN_reg(ot, 0, rm);
4367 } else {
4368 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4369 gen_op_ld_T0_A0(ot + s->mem_index);
4370 rm = 0; /* avoid warning */
4371 }
4372 label1 = gen_new_label();
4373 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_EAX]));
4374 tcg_gen_sub_tl(cpu_T3, cpu_T3, cpu_T[0]);
4375 gen_extu(ot, cpu_T3);
4376 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T3, tcg_const_tl(0), label1);
4377 if (mod == 3) {
4378 label2 = gen_new_label();
4379 gen_op_mov_reg_T0(ot, R_EAX);
4380 tcg_gen_br(label2);
4381 gen_set_label(label1);
4382 gen_op_mov_reg_T1(ot, rm);
4383 gen_set_label(label2);
4384 } else {
4385 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
4386 gen_op_mov_reg_T0(ot, R_EAX);
4387 gen_set_label(label1);
4388 /* always store */
4389 gen_op_st_T1_A0(ot + s->mem_index);
4390 }
4391 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4392 tcg_gen_mov_tl(cpu_cc_dst, cpu_T3);
4393 s->cc_op = CC_OP_SUBB + ot;
4394 }
4395 break;
4396 case 0x1c7: /* cmpxchg8b */
4397 modrm = ldub_code(s->pc++);
4398 mod = (modrm >> 6) & 3;
4399 if ((mod == 3) || ((modrm & 0x38) != 0x8))
4400 goto illegal_op;
4401 #ifdef TARGET_X86_64
4402 if (dflag == 2) {
4403 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
4404 goto illegal_op;
4405 gen_jmp_im(pc_start - s->cs_base);
4406 if (s->cc_op != CC_OP_DYNAMIC)
4407 gen_op_set_cc_op(s->cc_op);
4408 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4409 tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0);
4410 } else
4411 #endif
4412 {
4413 if (!(s->cpuid_features & CPUID_CX8))
4414 goto illegal_op;
4415 gen_jmp_im(pc_start - s->cs_base);
4416 if (s->cc_op != CC_OP_DYNAMIC)
4417 gen_op_set_cc_op(s->cc_op);
4418 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4419 tcg_gen_helper_0_1(helper_cmpxchg8b, cpu_A0);
4420 }
4421 s->cc_op = CC_OP_EFLAGS;
4422 break;
4423
4424 /**************************/
4425 /* push/pop */
4426 case 0x50 ... 0x57: /* push */
4427 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
4428 gen_push_T0(s);
4429 break;
4430 case 0x58 ... 0x5f: /* pop */
4431 if (CODE64(s)) {
4432 ot = dflag ? OT_QUAD : OT_WORD;
4433 } else {
4434 ot = dflag + OT_WORD;
4435 }
4436 gen_pop_T0(s);
4437 /* NOTE: order is important for pop %sp */
4438 gen_pop_update(s);
4439 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
4440 break;
4441 case 0x60: /* pusha */
4442 if (CODE64(s))
4443 goto illegal_op;
4444 gen_pusha(s);
4445 break;
4446 case 0x61: /* popa */
4447 if (CODE64(s))
4448 goto illegal_op;
4449 gen_popa(s);
4450 break;
4451 case 0x68: /* push Iv */
4452 case 0x6a:
4453 if (CODE64(s)) {
4454 ot = dflag ? OT_QUAD : OT_WORD;
4455 } else {
4456 ot = dflag + OT_WORD;
4457 }
4458 if (b == 0x68)
4459 val = insn_get(s, ot);
4460 else
4461 val = (int8_t)insn_get(s, OT_BYTE);
4462 gen_op_movl_T0_im(val);
4463 gen_push_T0(s);
4464 break;
4465 case 0x8f: /* pop Ev */
4466 if (CODE64(s)) {
4467 ot = dflag ? OT_QUAD : OT_WORD;
4468 } else {
4469 ot = dflag + OT_WORD;
4470 }
4471 modrm = ldub_code(s->pc++);
4472 mod = (modrm >> 6) & 3;
4473 gen_pop_T0(s);
4474 if (mod == 3) {
4475 /* NOTE: order is important for pop %sp */
4476 gen_pop_update(s);
4477 rm = (modrm & 7) | REX_B(s);
4478 gen_op_mov_reg_T0(ot, rm);
4479 } else {
4480 /* NOTE: order is important too for MMU exceptions */
4481 s->popl_esp_hack = 1 << ot;
4482 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4483 s->popl_esp_hack = 0;
4484 gen_pop_update(s);
4485 }
4486 break;
4487 case 0xc8: /* enter */
4488 {
4489 int level;
4490 val = lduw_code(s->pc);
4491 s->pc += 2;
4492 level = ldub_code(s->pc++);
4493 gen_enter(s, val, level);
4494 }
4495 break;
4496 case 0xc9: /* leave */
4497 /* XXX: exception not precise (ESP is updated before potential exception) */
4498 if (CODE64(s)) {
4499 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
4500 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
4501 } else if (s->ss32) {
4502 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
4503 gen_op_mov_reg_T0(OT_LONG, R_ESP);
4504 } else {
4505 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
4506 gen_op_mov_reg_T0(OT_WORD, R_ESP);
4507 }
4508 gen_pop_T0(s);
4509 if (CODE64(s)) {
4510 ot = dflag ? OT_QUAD : OT_WORD;
4511 } else {
4512 ot = dflag + OT_WORD;
4513 }
4514 gen_op_mov_reg_T0(ot, R_EBP);
4515 gen_pop_update(s);
4516 break;
4517 case 0x06: /* push es */
4518 case 0x0e: /* push cs */
4519 case 0x16: /* push ss */
4520 case 0x1e: /* push ds */
4521 if (CODE64(s))
4522 goto illegal_op;
4523 gen_op_movl_T0_seg(b >> 3);
4524 gen_push_T0(s);
4525 break;
4526 case 0x1a0: /* push fs */
4527 case 0x1a8: /* push gs */
4528 gen_op_movl_T0_seg((b >> 3) & 7);
4529 gen_push_T0(s);
4530 break;
4531 case 0x07: /* pop es */
4532 case 0x17: /* pop ss */
4533 case 0x1f: /* pop ds */
4534 if (CODE64(s))
4535 goto illegal_op;
4536 reg = b >> 3;
4537 gen_pop_T0(s);
4538 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4539 gen_pop_update(s);
4540 if (reg == R_SS) {
4541 /* if reg == SS, inhibit interrupts/trace. */
4542 /* If several instructions disable interrupts, only the
4543 _first_ does it */
4544 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4545 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4546 s->tf = 0;
4547 }
4548 if (s->is_jmp) {
4549 gen_jmp_im(s->pc - s->cs_base);
4550 gen_eob(s);
4551 }
4552 break;
4553 case 0x1a1: /* pop fs */
4554 case 0x1a9: /* pop gs */
4555 gen_pop_T0(s);
4556 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
4557 gen_pop_update(s);
4558 if (s->is_jmp) {
4559 gen_jmp_im(s->pc - s->cs_base);
4560 gen_eob(s);
4561 }
4562 break;
4563
4564 /**************************/
4565 /* mov */
4566 case 0x88:
4567 case 0x89: /* mov Gv, Ev */
4568 if ((b & 1) == 0)
4569 ot = OT_BYTE;
4570 else
4571 ot = dflag + OT_WORD;
4572 modrm = ldub_code(s->pc++);
4573 reg = ((modrm >> 3) & 7) | rex_r;
4574
4575 /* generate a generic store */
4576 gen_ldst_modrm(s, modrm, ot, reg, 1);
4577 break;
4578 case 0xc6:
4579 case 0xc7: /* mov Ev, Iv */
4580 if ((b & 1) == 0)
4581 ot = OT_BYTE;
4582 else
4583 ot = dflag + OT_WORD;
4584 modrm = ldub_code(s->pc++);
4585 mod = (modrm >> 6) & 3;
4586 if (mod != 3) {
4587 s->rip_offset = insn_const_size(ot);
4588 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4589 }
4590 val = insn_get(s, ot);
4591 gen_op_movl_T0_im(val);
4592 if (mod != 3)
4593 gen_op_st_T0_A0(ot + s->mem_index);
4594 else
4595 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
4596 break;
4597 case 0x8a:
4598 case 0x8b: /* mov Ev, Gv */
4599 if ((b & 1) == 0)
4600 ot = OT_BYTE;
4601 else
4602 ot = OT_WORD + dflag;
4603 modrm = ldub_code(s->pc++);
4604 reg = ((modrm >> 3) & 7) | rex_r;
4605
4606 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4607 gen_op_mov_reg_T0(ot, reg);
4608 break;
4609 case 0x8e: /* mov seg, Gv */
4610 modrm = ldub_code(s->pc++);
4611 reg = (modrm >> 3) & 7;
4612 if (reg >= 6 || reg == R_CS)
4613 goto illegal_op;
4614 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
4615 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
4616 if (reg == R_SS) {
4617 /* if reg == SS, inhibit interrupts/trace */
4618 /* If several instructions disable interrupts, only the
4619 _first_ does it */
4620 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
4621 tcg_gen_helper_0_0(helper_set_inhibit_irq);
4622 s->tf = 0;
4623 }
4624 if (s->is_jmp) {
4625 gen_jmp_im(s->pc - s->cs_base);
4626 gen_eob(s);
4627 }
4628 break;
4629 case 0x8c: /* mov Gv, seg */
4630 modrm = ldub_code(s->pc++);
4631 reg = (modrm >> 3) & 7;
4632 mod = (modrm >> 6) & 3;
4633 if (reg >= 6)
4634 goto illegal_op;
4635 gen_op_movl_T0_seg(reg);
4636 if (mod == 3)
4637 ot = OT_WORD + dflag;
4638 else
4639 ot = OT_WORD;
4640 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
4641 break;
4642
4643 case 0x1b6: /* movzbS Gv, Eb */
4644 case 0x1b7: /* movzwS Gv, Eb */
4645 case 0x1be: /* movsbS Gv, Eb */
4646 case 0x1bf: /* movswS Gv, Eb */
4647 {
4648 int d_ot;
4649 /* d_ot is the size of destination */
4650 d_ot = dflag + OT_WORD;
4651 /* ot is the size of source */
4652 ot = (b & 1) + OT_BYTE;
4653 modrm = ldub_code(s->pc++);
4654 reg = ((modrm >> 3) & 7) | rex_r;
4655 mod = (modrm >> 6) & 3;
4656 rm = (modrm & 7) | REX_B(s);
4657
4658 if (mod == 3) {
4659 gen_op_mov_TN_reg(ot, 0, rm);
4660 switch(ot | (b & 8)) {
4661 case OT_BYTE:
4662 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4663 break;
4664 case OT_BYTE | 8:
4665 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4666 break;
4667 case OT_WORD:
4668 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4669 break;
4670 default:
4671 case OT_WORD | 8:
4672 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4673 break;
4674 }
4675 gen_op_mov_reg_T0(d_ot, reg);
4676 } else {
4677 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4678 if (b & 8) {
4679 gen_op_lds_T0_A0(ot + s->mem_index);
4680 } else {
4681 gen_op_ldu_T0_A0(ot + s->mem_index);
4682 }
4683 gen_op_mov_reg_T0(d_ot, reg);
4684 }
4685 }
4686 break;
4687
4688 case 0x8d: /* lea */
4689 ot = dflag + OT_WORD;
4690 modrm = ldub_code(s->pc++);
4691 mod = (modrm >> 6) & 3;
4692 if (mod == 3)
4693 goto illegal_op;
4694 reg = ((modrm >> 3) & 7) | rex_r;
4695 /* we must ensure that no segment is added */
4696 s->override = -1;
4697 val = s->addseg;
4698 s->addseg = 0;
4699 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4700 s->addseg = val;
4701 gen_op_mov_reg_A0(ot - OT_WORD, reg);
4702 break;
4703
4704 case 0xa0: /* mov EAX, Ov */
4705 case 0xa1:
4706 case 0xa2: /* mov Ov, EAX */
4707 case 0xa3:
4708 {
4709 target_ulong offset_addr;
4710
4711 if ((b & 1) == 0)
4712 ot = OT_BYTE;
4713 else
4714 ot = dflag + OT_WORD;
4715 #ifdef TARGET_X86_64
4716 if (s->aflag == 2) {
4717 offset_addr = ldq_code(s->pc);
4718 s->pc += 8;
4719 gen_op_movq_A0_im(offset_addr);
4720 } else
4721 #endif
4722 {
4723 if (s->aflag) {
4724 offset_addr = insn_get(s, OT_LONG);
4725 } else {
4726 offset_addr = insn_get(s, OT_WORD);
4727 }
4728 gen_op_movl_A0_im(offset_addr);
4729 }
4730 gen_add_A0_ds_seg(s);
4731 if ((b & 2) == 0) {
4732 gen_op_ld_T0_A0(ot + s->mem_index);
4733 gen_op_mov_reg_T0(ot, R_EAX);
4734 } else {
4735 gen_op_mov_TN_reg(ot, 0, R_EAX);
4736 gen_op_st_T0_A0(ot + s->mem_index);
4737 }
4738 }
4739 break;
4740 case 0xd7: /* xlat */
4741 #ifdef TARGET_X86_64
4742 if (s->aflag == 2) {
4743 gen_op_movq_A0_reg(R_EBX);
4744 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4745 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4746 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4747 } else
4748 #endif
4749 {
4750 gen_op_movl_A0_reg(R_EBX);
4751 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4752 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
4753 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
4754 if (s->aflag == 0)
4755 gen_op_andl_A0_ffff();
4756 else
4757 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
4758 }
4759 gen_add_A0_ds_seg(s);
4760 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
4761 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
4762 break;
4763 case 0xb0 ... 0xb7: /* mov R, Ib */
4764 val = insn_get(s, OT_BYTE);
4765 gen_op_movl_T0_im(val);
4766 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
4767 break;
4768 case 0xb8 ... 0xbf: /* mov R, Iv */
4769 #ifdef TARGET_X86_64
4770 if (dflag == 2) {
4771 uint64_t tmp;
4772 /* 64 bit case */
4773 tmp = ldq_code(s->pc);
4774 s->pc += 8;
4775 reg = (b & 7) | REX_B(s);
4776 gen_movtl_T0_im(tmp);
4777 gen_op_mov_reg_T0(OT_QUAD, reg);
4778 } else
4779 #endif
4780 {
4781 ot = dflag ? OT_LONG : OT_WORD;
4782 val = insn_get(s, ot);
4783 reg = (b & 7) | REX_B(s);
4784 gen_op_movl_T0_im(val);
4785 gen_op_mov_reg_T0(ot, reg);
4786 }
4787 break;
4788
4789 case 0x91 ... 0x97: /* xchg R, EAX */
4790 ot = dflag + OT_WORD;
4791 reg = (b & 7) | REX_B(s);
4792 rm = R_EAX;
4793 goto do_xchg_reg;
4794 case 0x86:
4795 case 0x87: /* xchg Ev, Gv */
4796 if ((b & 1) == 0)
4797 ot = OT_BYTE;
4798 else
4799 ot = dflag + OT_WORD;
4800 modrm = ldub_code(s->pc++);
4801 reg = ((modrm >> 3) & 7) | rex_r;
4802 mod = (modrm >> 6) & 3;
4803 if (mod == 3) {
4804 rm = (modrm & 7) | REX_B(s);
4805 do_xchg_reg:
4806 gen_op_mov_TN_reg(ot, 0, reg);
4807 gen_op_mov_TN_reg(ot, 1, rm);
4808 gen_op_mov_reg_T0(ot, rm);
4809 gen_op_mov_reg_T1(ot, reg);
4810 } else {
4811 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4812 gen_op_mov_TN_reg(ot, 0, reg);
4813 /* for xchg, lock is implicit */
4814 if (!(prefixes & PREFIX_LOCK))
4815 tcg_gen_helper_0_0(helper_lock);
4816 gen_op_ld_T1_A0(ot + s->mem_index);
4817 gen_op_st_T0_A0(ot + s->mem_index);
4818 if (!(prefixes & PREFIX_LOCK))
4819 tcg_gen_helper_0_0(helper_unlock);
4820 gen_op_mov_reg_T1(ot, reg);
4821 }
4822 break;
4823 case 0xc4: /* les Gv */
4824 if (CODE64(s))
4825 goto illegal_op;
4826 op = R_ES;
4827 goto do_lxx;
4828 case 0xc5: /* lds Gv */
4829 if (CODE64(s))
4830 goto illegal_op;
4831 op = R_DS;
4832 goto do_lxx;
4833 case 0x1b2: /* lss Gv */
4834 op = R_SS;
4835 goto do_lxx;
4836 case 0x1b4: /* lfs Gv */
4837 op = R_FS;
4838 goto do_lxx;
4839 case 0x1b5: /* lgs Gv */
4840 op = R_GS;
4841 do_lxx:
4842 ot = dflag ? OT_LONG : OT_WORD;
4843 modrm = ldub_code(s->pc++);
4844 reg = ((modrm >> 3) & 7) | rex_r;
4845 mod = (modrm >> 6) & 3;
4846 if (mod == 3)
4847 goto illegal_op;
4848 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4849 gen_op_ld_T1_A0(ot + s->mem_index);
4850 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4851 /* load the segment first to handle exceptions properly */
4852 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4853 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
4854 /* then put the data */
4855 gen_op_mov_reg_T1(ot, reg);
4856 if (s->is_jmp) {
4857 gen_jmp_im(s->pc - s->cs_base);
4858 gen_eob(s);
4859 }
4860 break;
4861
4862 /************************/
4863 /* shifts */
4864 case 0xc0:
4865 case 0xc1:
4866 /* shift Ev,Ib */
4867 shift = 2;
4868 grp2:
4869 {
4870 if ((b & 1) == 0)
4871 ot = OT_BYTE;
4872 else
4873 ot = dflag + OT_WORD;
4874
4875 modrm = ldub_code(s->pc++);
4876 mod = (modrm >> 6) & 3;
4877 op = (modrm >> 3) & 7;
4878
4879 if (mod != 3) {
4880 if (shift == 2) {
4881 s->rip_offset = 1;
4882 }
4883 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4884 opreg = OR_TMP0;
4885 } else {
4886 opreg = (modrm & 7) | REX_B(s);
4887 }
4888
4889 /* simpler op */
4890 if (shift == 0) {
4891 gen_shift(s, op, ot, opreg, OR_ECX);
4892 } else {
4893 if (shift == 2) {
4894 shift = ldub_code(s->pc++);
4895 }
4896 gen_shifti(s, op, ot, opreg, shift);
4897 }
4898 }
4899 break;
4900 case 0xd0:
4901 case 0xd1:
4902 /* shift Ev,1 */
4903 shift = 1;
4904 goto grp2;
4905 case 0xd2:
4906 case 0xd3:
4907 /* shift Ev,cl */
4908 shift = 0;
4909 goto grp2;
4910
4911 case 0x1a4: /* shld imm */
4912 op = 0;
4913 shift = 1;
4914 goto do_shiftd;
4915 case 0x1a5: /* shld cl */
4916 op = 0;
4917 shift = 0;
4918 goto do_shiftd;
4919 case 0x1ac: /* shrd imm */
4920 op = 1;
4921 shift = 1;
4922 goto do_shiftd;
4923 case 0x1ad: /* shrd cl */
4924 op = 1;
4925 shift = 0;
4926 do_shiftd:
4927 ot = dflag + OT_WORD;
4928 modrm = ldub_code(s->pc++);
4929 mod = (modrm >> 6) & 3;
4930 rm = (modrm & 7) | REX_B(s);
4931 reg = ((modrm >> 3) & 7) | rex_r;
4932 if (mod != 3) {
4933 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4934 opreg = OR_TMP0;
4935 } else {
4936 opreg = rm;
4937 }
4938 gen_op_mov_TN_reg(ot, 1, reg);
4939
4940 if (shift) {
4941 val = ldub_code(s->pc++);
4942 tcg_gen_movi_tl(cpu_T3, val);
4943 } else {
4944 tcg_gen_ld_tl(cpu_T3, cpu_env, offsetof(CPUState, regs[R_ECX]));
4945 }
4946 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
4947 break;
4948
4949 /************************/
4950 /* floats */
4951 case 0xd8 ... 0xdf:
4952 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
4953 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4954 /* XXX: what to do if illegal op ? */
4955 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
4956 break;
4957 }
4958 modrm = ldub_code(s->pc++);
4959 mod = (modrm >> 6) & 3;
4960 rm = modrm & 7;
4961 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
4962 if (mod != 3) {
4963 /* memory op */
4964 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4965 switch(op) {
4966 case 0x00 ... 0x07: /* fxxxs */
4967 case 0x10 ... 0x17: /* fixxxl */
4968 case 0x20 ... 0x27: /* fxxxl */
4969 case 0x30 ... 0x37: /* fixxx */
4970 {
4971 int op1;
4972 op1 = op & 7;
4973
4974 switch(op >> 4) {
4975 case 0:
4976 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4977 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4978 tcg_gen_helper_0_1(helper_flds_FT0, cpu_tmp2_i32);
4979 break;
4980 case 1:
4981 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4982 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4983 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4984 break;
4985 case 2:
4986 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4987 (s->mem_index >> 2) - 1);
4988 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64);
4989 break;
4990 case 3:
4991 default:
4992 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
4993 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4994 tcg_gen_helper_0_1(helper_fildl_FT0, cpu_tmp2_i32);
4995 break;
4996 }
4997
4998 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
4999 if (op1 == 3) {
5000 /* fcomp needs pop */
5001 tcg_gen_helper_0_0(helper_fpop);
5002 }
5003 }
5004 break;
5005 case 0x08: /* flds */
5006 case 0x0a: /* fsts */
5007 case 0x0b: /* fstps */
5008 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5009 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5010 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5011 switch(op & 7) {
5012 case 0:
5013 switch(op >> 4) {
5014 case 0:
5015 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5016 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5017 tcg_gen_helper_0_1(helper_flds_ST0, cpu_tmp2_i32);
5018 break;
5019 case 1:
5020 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5021 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5022 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5023 break;
5024 case 2:
5025 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5026 (s->mem_index >> 2) - 1);
5027 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64);
5028 break;
5029 case 3:
5030 default:
5031 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5032 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5033 tcg_gen_helper_0_1(helper_fildl_ST0, cpu_tmp2_i32);
5034 break;
5035 }
5036 break;
5037 case 1:
5038 /* XXX: the corresponding CPUID bit must be tested ! */
5039 switch(op >> 4) {
5040 case 1:
5041 tcg_gen_helper_1_0(helper_fisttl_ST0, cpu_tmp2_i32);
5042 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5043 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5044 break;
5045 case 2:
5046 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64);
5047 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5048 (s->mem_index >> 2) - 1);
5049 break;
5050 case 3:
5051 default:
5052 tcg_gen_helper_1_0(helper_fistt_ST0, cpu_tmp2_i32);
5053 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5054 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5055 break;
5056 }
5057 tcg_gen_helper_0_0(helper_fpop);
5058 break;
5059 default:
5060 switch(op >> 4) {
5061 case 0:
5062 tcg_gen_helper_1_0(helper_fsts_ST0, cpu_tmp2_i32);
5063 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5064 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5065 break;
5066 case 1:
5067 tcg_gen_helper_1_0(helper_fistl_ST0, cpu_tmp2_i32);
5068 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5069 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5070 break;
5071 case 2:
5072 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64);
5073 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5074 (s->mem_index >> 2) - 1);
5075 break;
5076 case 3:
5077 default:
5078 tcg_gen_helper_1_0(helper_fist_ST0, cpu_tmp2_i32);
5079 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5080 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5081 break;
5082 }
5083 if ((op & 7) == 3)
5084 tcg_gen_helper_0_0(helper_fpop);
5085 break;
5086 }
5087 break;
5088 case 0x0c: /* fldenv mem */
5089 if (s->cc_op != CC_OP_DYNAMIC)
5090 gen_op_set_cc_op(s->cc_op);
5091 gen_jmp_im(pc_start - s->cs_base);
5092 tcg_gen_helper_0_2(helper_fldenv,
5093 cpu_A0, tcg_const_i32(s->dflag));
5094 break;
5095 case 0x0d: /* fldcw mem */
5096 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5097 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5098 tcg_gen_helper_0_1(helper_fldcw, cpu_tmp2_i32);
5099 break;
5100 case 0x0e: /* fnstenv mem */
5101 if (s->cc_op != CC_OP_DYNAMIC)
5102 gen_op_set_cc_op(s->cc_op);
5103 gen_jmp_im(pc_start - s->cs_base);
5104 tcg_gen_helper_0_2(helper_fstenv,
5105 cpu_A0, tcg_const_i32(s->dflag));
5106 break;
5107 case 0x0f: /* fnstcw mem */
5108 tcg_gen_helper_1_0(helper_fnstcw, cpu_tmp2_i32);
5109 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5110 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5111 break;
5112 case 0x1d: /* fldt mem */
5113 if (s->cc_op != CC_OP_DYNAMIC)
5114 gen_op_set_cc_op(s->cc_op);
5115 gen_jmp_im(pc_start - s->cs_base);
5116 tcg_gen_helper_0_1(helper_fldt_ST0, cpu_A0);
5117 break;
5118 case 0x1f: /* fstpt mem */
5119 if (s->cc_op != CC_OP_DYNAMIC)
5120 gen_op_set_cc_op(s->cc_op);
5121 gen_jmp_im(pc_start - s->cs_base);
5122 tcg_gen_helper_0_1(helper_fstt_ST0, cpu_A0);
5123 tcg_gen_helper_0_0(helper_fpop);
5124 break;
5125 case 0x2c: /* frstor mem */
5126 if (s->cc_op != CC_OP_DYNAMIC)
5127 gen_op_set_cc_op(s->cc_op);
5128 gen_jmp_im(pc_start - s->cs_base);
5129 tcg_gen_helper_0_2(helper_frstor,
5130 cpu_A0, tcg_const_i32(s->dflag));
5131 break;
5132 case 0x2e: /* fnsave mem */
5133 if (s->cc_op != CC_OP_DYNAMIC)
5134 gen_op_set_cc_op(s->cc_op);
5135 gen_jmp_im(pc_start - s->cs_base);
5136 tcg_gen_helper_0_2(helper_fsave,
5137 cpu_A0, tcg_const_i32(s->dflag));
5138 break;
5139 case 0x2f: /* fnstsw mem */
5140 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5141 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5142 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5143 break;
5144 case 0x3c: /* fbld */
5145 if (s->cc_op != CC_OP_DYNAMIC)
5146 gen_op_set_cc_op(s->cc_op);
5147 gen_jmp_im(pc_start - s->cs_base);
5148 tcg_gen_helper_0_1(helper_fbld_ST0, cpu_A0);
5149 break;
5150 case 0x3e: /* fbstp */
5151 if (s->cc_op != CC_OP_DYNAMIC)
5152 gen_op_set_cc_op(s->cc_op);
5153 gen_jmp_im(pc_start - s->cs_base);
5154 tcg_gen_helper_0_1(helper_fbst_ST0, cpu_A0);
5155 tcg_gen_helper_0_0(helper_fpop);
5156 break;
5157 case 0x3d: /* fildll */
5158 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5159 (s->mem_index >> 2) - 1);
5160 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64);
5161 break;
5162 case 0x3f: /* fistpll */
5163 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64);
5164 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5165 (s->mem_index >> 2) - 1);
5166 tcg_gen_helper_0_0(helper_fpop);
5167 break;
5168 default:
5169 goto illegal_op;
5170 }
5171 } else {
5172 /* register float ops */
5173 opreg = rm;
5174
5175 switch(op) {
5176 case 0x08: /* fld sti */
5177 tcg_gen_helper_0_0(helper_fpush);
5178 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32((opreg + 1) & 7));
5179 break;
5180 case 0x09: /* fxchg sti */
5181 case 0x29: /* fxchg4 sti, undocumented op */
5182 case 0x39: /* fxchg7 sti, undocumented op */
5183 tcg_gen_helper_0_1(helper_fxchg_ST0_STN, tcg_const_i32(opreg));
5184 break;
5185 case 0x0a: /* grp d9/2 */
5186 switch(rm) {
5187 case 0: /* fnop */
5188 /* check exceptions (FreeBSD FPU probe) */
5189 if (s->cc_op != CC_OP_DYNAMIC)
5190 gen_op_set_cc_op(s->cc_op);
5191 gen_jmp_im(pc_start - s->cs_base);
5192 tcg_gen_helper_0_0(helper_fwait);
5193 break;
5194 default:
5195 goto illegal_op;
5196 }
5197 break;
5198 case 0x0c: /* grp d9/4 */
5199 switch(rm) {
5200 case 0: /* fchs */
5201 tcg_gen_helper_0_0(helper_fchs_ST0);
5202 break;
5203 case 1: /* fabs */
5204 tcg_gen_helper_0_0(helper_fabs_ST0);
5205 break;
5206 case 4: /* ftst */
5207 tcg_gen_helper_0_0(helper_fldz_FT0);
5208 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5209 break;
5210 case 5: /* fxam */
5211 tcg_gen_helper_0_0(helper_fxam_ST0);
5212 break;
5213 default:
5214 goto illegal_op;
5215 }
5216 break;
5217 case 0x0d: /* grp d9/5 */
5218 {
5219 switch(rm) {
5220 case 0:
5221 tcg_gen_helper_0_0(helper_fpush);
5222 tcg_gen_helper_0_0(helper_fld1_ST0);
5223 break;
5224 case 1:
5225 tcg_gen_helper_0_0(helper_fpush);
5226 tcg_gen_helper_0_0(helper_fldl2t_ST0);
5227 break;
5228 case 2:
5229 tcg_gen_helper_0_0(helper_fpush);
5230 tcg_gen_helper_0_0(helper_fldl2e_ST0);
5231 break;
5232 case 3:
5233 tcg_gen_helper_0_0(helper_fpush);
5234 tcg_gen_helper_0_0(helper_fldpi_ST0);
5235 break;
5236 case 4:
5237 tcg_gen_helper_0_0(helper_fpush);
5238 tcg_gen_helper_0_0(helper_fldlg2_ST0);
5239 break;
5240 case 5:
5241 tcg_gen_helper_0_0(helper_fpush);
5242 tcg_gen_helper_0_0(helper_fldln2_ST0);
5243 break;
5244 case 6:
5245 tcg_gen_helper_0_0(helper_fpush);
5246 tcg_gen_helper_0_0(helper_fldz_ST0);
5247 break;
5248 default:
5249 goto illegal_op;
5250 }
5251 }
5252 break;
5253 case 0x0e: /* grp d9/6 */
5254 switch(rm) {
5255 case 0: /* f2xm1 */
5256 tcg_gen_helper_0_0(helper_f2xm1);
5257 break;
5258 case 1: /* fyl2x */
5259 tcg_gen_helper_0_0(helper_fyl2x);
5260 break;
5261 case 2: /* fptan */
5262 tcg_gen_helper_0_0(helper_fptan);
5263 break;
5264 case 3: /* fpatan */
5265 tcg_gen_helper_0_0(helper_fpatan);
5266 break;
5267 case 4: /* fxtract */
5268 tcg_gen_helper_0_0(helper_fxtract);
5269 break;
5270 case 5: /* fprem1 */
5271 tcg_gen_helper_0_0(helper_fprem1);
5272 break;
5273 case 6: /* fdecstp */
5274 tcg_gen_helper_0_0(helper_fdecstp);
5275 break;
5276 default:
5277 case 7: /* fincstp */
5278 tcg_gen_helper_0_0(helper_fincstp);
5279 break;
5280 }
5281 break;
5282 case 0x0f: /* grp d9/7 */
5283 switch(rm) {
5284 case 0: /* fprem */
5285 tcg_gen_helper_0_0(helper_fprem);
5286 break;
5287 case 1: /* fyl2xp1 */
5288 tcg_gen_helper_0_0(helper_fyl2xp1);
5289 break;
5290 case 2: /* fsqrt */
5291 tcg_gen_helper_0_0(helper_fsqrt);
5292 break;
5293 case 3: /* fsincos */
5294 tcg_gen_helper_0_0(helper_fsincos);
5295 break;
5296 case 5: /* fscale */
5297 tcg_gen_helper_0_0(helper_fscale);
5298 break;
5299 case 4: /* frndint */
5300 tcg_gen_helper_0_0(helper_frndint);
5301 break;
5302 case 6: /* fsin */
5303 tcg_gen_helper_0_0(helper_fsin);
5304 break;
5305 default:
5306 case 7: /* fcos */
5307 tcg_gen_helper_0_0(helper_fcos);
5308 break;
5309 }
5310 break;
5311 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5312 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5313 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5314 {
5315 int op1;
5316
5317 op1 = op & 7;
5318 if (op >= 0x20) {
5319 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0[op1], tcg_const_i32(opreg));
5320 if (op >= 0x30)
5321 tcg_gen_helper_0_0(helper_fpop);
5322 } else {
5323 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5324 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0[op1]);
5325 }
5326 }
5327 break;
5328 case 0x02: /* fcom */
5329 case 0x22: /* fcom2, undocumented op */
5330 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5331 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5332 break;
5333 case 0x03: /* fcomp */
5334 case 0x23: /* fcomp3, undocumented op */
5335 case 0x32: /* fcomp5, undocumented op */
5336 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5337 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5338 tcg_gen_helper_0_0(helper_fpop);
5339 break;
5340 case 0x15: /* da/5 */
5341 switch(rm) {
5342 case 1: /* fucompp */
5343 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5344 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5345 tcg_gen_helper_0_0(helper_fpop);
5346 tcg_gen_helper_0_0(helper_fpop);
5347 break;
5348 default:
5349 goto illegal_op;
5350 }
5351 break;
5352 case 0x1c:
5353 switch(rm) {
5354 case 0: /* feni (287 only, just do nop here) */
5355 break;
5356 case 1: /* fdisi (287 only, just do nop here) */
5357 break;
5358 case 2: /* fclex */
5359 tcg_gen_helper_0_0(helper_fclex);
5360 break;
5361 case 3: /* fninit */
5362 tcg_gen_helper_0_0(helper_fninit);
5363 break;
5364 case 4: /* fsetpm (287 only, just do nop here) */
5365 break;
5366 default:
5367 goto illegal_op;
5368 }
5369 break;
5370 case 0x1d: /* fucomi */
5371 if (s->cc_op != CC_OP_DYNAMIC)
5372 gen_op_set_cc_op(s->cc_op);
5373 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5374 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5375 s->cc_op = CC_OP_EFLAGS;
5376 break;
5377 case 0x1e: /* fcomi */
5378 if (s->cc_op != CC_OP_DYNAMIC)
5379 gen_op_set_cc_op(s->cc_op);
5380 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5381 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5382 s->cc_op = CC_OP_EFLAGS;
5383 break;
5384 case 0x28: /* ffree sti */
5385 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5386 break;
5387 case 0x2a: /* fst sti */
5388 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5389 break;
5390 case 0x2b: /* fstp sti */
5391 case 0x0b: /* fstp1 sti, undocumented op */
5392 case 0x3a: /* fstp8 sti, undocumented op */
5393 case 0x3b: /* fstp9 sti, undocumented op */
5394 tcg_gen_helper_0_1(helper_fmov_STN_ST0, tcg_const_i32(opreg));
5395 tcg_gen_helper_0_0(helper_fpop);
5396 break;
5397 case 0x2c: /* fucom st(i) */
5398 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5399 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5400 break;
5401 case 0x2d: /* fucomp st(i) */
5402 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5403 tcg_gen_helper_0_0(helper_fucom_ST0_FT0);
5404 tcg_gen_helper_0_0(helper_fpop);
5405 break;
5406 case 0x33: /* de/3 */
5407 switch(rm) {
5408 case 1: /* fcompp */
5409 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(1));
5410 tcg_gen_helper_0_0(helper_fcom_ST0_FT0);
5411 tcg_gen_helper_0_0(helper_fpop);
5412 tcg_gen_helper_0_0(helper_fpop);
5413 break;
5414 default:
5415 goto illegal_op;
5416 }
5417 break;
5418 case 0x38: /* ffreep sti, undocumented op */
5419 tcg_gen_helper_0_1(helper_ffree_STN, tcg_const_i32(opreg));
5420 tcg_gen_helper_0_0(helper_fpop);
5421 break;
5422 case 0x3c: /* df/4 */
5423 switch(rm) {
5424 case 0:
5425 tcg_gen_helper_1_0(helper_fnstsw, cpu_tmp2_i32);
5426 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5427 gen_op_mov_reg_T0(OT_WORD, R_EAX);
5428 break;
5429 default:
5430 goto illegal_op;
5431 }
5432 break;
5433 case 0x3d: /* fucomip */
5434 if (s->cc_op != CC_OP_DYNAMIC)
5435 gen_op_set_cc_op(s->cc_op);
5436 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5437 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0);
5438 tcg_gen_helper_0_0(helper_fpop);
5439 s->cc_op = CC_OP_EFLAGS;
5440 break;
5441 case 0x3e: /* fcomip */
5442 if (s->cc_op != CC_OP_DYNAMIC)
5443 gen_op_set_cc_op(s->cc_op);
5444 tcg_gen_helper_0_1(helper_fmov_FT0_STN, tcg_const_i32(opreg));
5445 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0);
5446 tcg_gen_helper_0_0(helper_fpop);
5447 s->cc_op = CC_OP_EFLAGS;
5448 break;
5449 case 0x10 ... 0x13: /* fcmovxx */
5450 case 0x18 ... 0x1b:
5451 {
5452 int op1, l1;
5453 const static uint8_t fcmov_cc[8] = {
5454 (JCC_B << 1),
5455 (JCC_Z << 1),
5456 (JCC_BE << 1),
5457 (JCC_P << 1),
5458 };
5459 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
5460 gen_setcc(s, op1);
5461 l1 = gen_new_label();
5462 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), l1);
5463 tcg_gen_helper_0_1(helper_fmov_ST0_STN, tcg_const_i32(opreg));
5464 gen_set_label(l1);
5465 }
5466 break;
5467 default:
5468 goto illegal_op;
5469 }
5470 }
5471 break;
5472 /************************/
5473 /* string ops */
5474
5475 case 0xa4: /* movsS */
5476 case 0xa5:
5477 if ((b & 1) == 0)
5478 ot = OT_BYTE;
5479 else
5480 ot = dflag + OT_WORD;
5481
5482 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5483 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5484 } else {
5485 gen_movs(s, ot);
5486 }
5487 break;
5488
5489 case 0xaa: /* stosS */
5490 case 0xab:
5491 if ((b & 1) == 0)
5492 ot = OT_BYTE;
5493 else
5494 ot = dflag + OT_WORD;
5495
5496 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5497 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5498 } else {
5499 gen_stos(s, ot);
5500 }
5501 break;
5502 case 0xac: /* lodsS */
5503 case 0xad:
5504 if ((b & 1) == 0)
5505 ot = OT_BYTE;
5506 else
5507 ot = dflag + OT_WORD;
5508 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5509 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5510 } else {
5511 gen_lods(s, ot);
5512 }
5513 break;
5514 case 0xae: /* scasS */
5515 case 0xaf:
5516 if ((b & 1) == 0)
5517 ot = OT_BYTE;
5518 else
5519 ot = dflag + OT_WORD;
5520 if (prefixes & PREFIX_REPNZ) {
5521 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5522 } else if (prefixes & PREFIX_REPZ) {
5523 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5524 } else {
5525 gen_scas(s, ot);
5526 s->cc_op = CC_OP_SUBB + ot;
5527 }
5528 break;
5529
5530 case 0xa6: /* cmpsS */
5531 case 0xa7:
5532 if ((b & 1) == 0)
5533 ot = OT_BYTE;
5534 else
5535 ot = dflag + OT_WORD;
5536 if (prefixes & PREFIX_REPNZ) {
5537 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
5538 } else if (prefixes & PREFIX_REPZ) {
5539 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
5540 } else {
5541 gen_cmps(s, ot);
5542 s->cc_op = CC_OP_SUBB + ot;
5543 }
5544 break;
5545 case 0x6c: /* insS */
5546 case 0x6d:
5547 if ((b & 1) == 0)
5548 ot = OT_BYTE;
5549 else
5550 ot = dflag ? OT_LONG : OT_WORD;
5551 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5552 gen_op_andl_T0_ffff();
5553 gen_check_io(s, ot, pc_start - s->cs_base,
5554 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
5555 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5556 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5557 } else {
5558 gen_ins(s, ot);
5559 }
5560 break;
5561 case 0x6e: /* outsS */
5562 case 0x6f:
5563 if ((b & 1) == 0)
5564 ot = OT_BYTE;
5565 else
5566 ot = dflag ? OT_LONG : OT_WORD;
5567 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5568 gen_op_andl_T0_ffff();
5569 gen_check_io(s, ot, pc_start - s->cs_base,
5570 svm_is_rep(prefixes) | 4);
5571 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
5572 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
5573 } else {
5574 gen_outs(s, ot);
5575 }
5576 break;
5577
5578 /************************/
5579 /* port I/O */
5580
5581 case 0xe4:
5582 case 0xe5:
5583 if ((b & 1) == 0)
5584 ot = OT_BYTE;
5585 else
5586 ot = dflag ? OT_LONG : OT_WORD;
5587 val = ldub_code(s->pc++);
5588 gen_op_movl_T0_im(val);
5589 gen_check_io(s, ot, pc_start - s->cs_base,
5590 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5591 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5592 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5593 gen_op_mov_reg_T1(ot, R_EAX);
5594 break;
5595 case 0xe6:
5596 case 0xe7:
5597 if ((b & 1) == 0)
5598 ot = OT_BYTE;
5599 else
5600 ot = dflag ? OT_LONG : OT_WORD;
5601 val = ldub_code(s->pc++);
5602 gen_op_movl_T0_im(val);
5603 gen_check_io(s, ot, pc_start - s->cs_base,
5604 svm_is_rep(prefixes));
5605 gen_op_mov_TN_reg(ot, 1, R_EAX);
5606
5607 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5608 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5609 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5610 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5611 break;
5612 case 0xec:
5613 case 0xed:
5614 if ((b & 1) == 0)
5615 ot = OT_BYTE;
5616 else
5617 ot = dflag ? OT_LONG : OT_WORD;
5618 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5619 gen_op_andl_T0_ffff();
5620 gen_check_io(s, ot, pc_start - s->cs_base,
5621 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
5622 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5623 tcg_gen_helper_1_1(helper_in_func[ot], cpu_T[1], cpu_tmp2_i32);
5624 gen_op_mov_reg_T1(ot, R_EAX);
5625 break;
5626 case 0xee:
5627 case 0xef:
5628 if ((b & 1) == 0)
5629 ot = OT_BYTE;
5630 else
5631 ot = dflag ? OT_LONG : OT_WORD;
5632 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
5633 gen_op_andl_T0_ffff();
5634 gen_check_io(s, ot, pc_start - s->cs_base,
5635 svm_is_rep(prefixes));
5636 gen_op_mov_TN_reg(ot, 1, R_EAX);
5637
5638 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5639 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
5640 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
5641 tcg_gen_helper_0_2(helper_out_func[ot], cpu_tmp2_i32, cpu_tmp3_i32);
5642 break;
5643
5644 /************************/
5645 /* control */
5646 case 0xc2: /* ret im */
5647 val = ldsw_code(s->pc);
5648 s->pc += 2;
5649 gen_pop_T0(s);
5650 if (CODE64(s) && s->dflag)
5651 s->dflag = 2;
5652 gen_stack_update(s, val + (2 << s->dflag));
5653 if (s->dflag == 0)
5654 gen_op_andl_T0_ffff();
5655 gen_op_jmp_T0();
5656 gen_eob(s);
5657 break;
5658 case 0xc3: /* ret */
5659 gen_pop_T0(s);
5660 gen_pop_update(s);
5661 if (s->dflag == 0)
5662 gen_op_andl_T0_ffff();
5663 gen_op_jmp_T0();
5664 gen_eob(s);
5665 break;
5666 case 0xca: /* lret im */
5667 val = ldsw_code(s->pc);
5668 s->pc += 2;
5669 do_lret:
5670 if (s->pe && !s->vm86) {
5671 if (s->cc_op != CC_OP_DYNAMIC)
5672 gen_op_set_cc_op(s->cc_op);
5673 gen_jmp_im(pc_start - s->cs_base);
5674 tcg_gen_helper_0_2(helper_lret_protected,
5675 tcg_const_i32(s->dflag),
5676 tcg_const_i32(val));
5677 } else {
5678 gen_stack_A0(s);
5679 /* pop offset */
5680 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5681 if (s->dflag == 0)
5682 gen_op_andl_T0_ffff();
5683 /* NOTE: keeping EIP updated is not a problem in case of
5684 exception */
5685 gen_op_jmp_T0();
5686 /* pop selector */
5687 gen_op_addl_A0_im(2 << s->dflag);
5688 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
5689 gen_op_movl_seg_T0_vm(R_CS);
5690 /* add stack offset */
5691 gen_stack_update(s, val + (4 << s->dflag));
5692 }
5693 gen_eob(s);
5694 break;
5695 case 0xcb: /* lret */
5696 val = 0;
5697 goto do_lret;
5698 case 0xcf: /* iret */
5699 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET))
5700 break;
5701 if (!s->pe) {
5702 /* real mode */
5703 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5704 s->cc_op = CC_OP_EFLAGS;
5705 } else if (s->vm86) {
5706 if (s->iopl != 3) {
5707 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5708 } else {
5709 tcg_gen_helper_0_1(helper_iret_real, tcg_const_i32(s->dflag));
5710 s->cc_op = CC_OP_EFLAGS;
5711 }
5712 } else {
5713 if (s->cc_op != CC_OP_DYNAMIC)
5714 gen_op_set_cc_op(s->cc_op);
5715 gen_jmp_im(pc_start - s->cs_base);
5716 tcg_gen_helper_0_2(helper_iret_protected,
5717 tcg_const_i32(s->dflag),
5718 tcg_const_i32(s->pc - s->cs_base));
5719 s->cc_op = CC_OP_EFLAGS;
5720 }
5721 gen_eob(s);
5722 break;
5723 case 0xe8: /* call im */
5724 {
5725 if (dflag)
5726 tval = (int32_t)insn_get(s, OT_LONG);
5727 else
5728 tval = (int16_t)insn_get(s, OT_WORD);
5729 next_eip = s->pc - s->cs_base;
5730 tval += next_eip;
5731 if (s->dflag == 0)
5732 tval &= 0xffff;
5733 gen_movtl_T0_im(next_eip);
5734 gen_push_T0(s);
5735 gen_jmp(s, tval);
5736 }
5737 break;
5738 case 0x9a: /* lcall im */
5739 {
5740 unsigned int selector, offset;
5741
5742 if (CODE64(s))
5743 goto illegal_op;
5744 ot = dflag ? OT_LONG : OT_WORD;
5745 offset = insn_get(s, ot);
5746 selector = insn_get(s, OT_WORD);
5747
5748 gen_op_movl_T0_im(selector);
5749 gen_op_movl_T1_imu(offset);
5750 }
5751 goto do_lcall;
5752 case 0xe9: /* jmp im */
5753 if (dflag)
5754 tval = (int32_t)insn_get(s, OT_LONG);
5755 else
5756 tval = (int16_t)insn_get(s, OT_WORD);
5757 tval += s->pc - s->cs_base;
5758 if (s->dflag == 0)
5759 tval &= 0xffff;
5760 gen_jmp(s, tval);
5761 break;
5762 case 0xea: /* ljmp im */
5763 {
5764 unsigned int selector, offset;
5765
5766 if (CODE64(s))
5767 goto illegal_op;
5768 ot = dflag ? OT_LONG : OT_WORD;
5769 offset = insn_get(s, ot);
5770 selector = insn_get(s, OT_WORD);
5771
5772 gen_op_movl_T0_im(selector);
5773 gen_op_movl_T1_imu(offset);
5774 }
5775 goto do_ljmp;
5776 case 0xeb: /* jmp Jb */
5777 tval = (int8_t)insn_get(s, OT_BYTE);
5778 tval += s->pc - s->cs_base;
5779 if (s->dflag == 0)
5780 tval &= 0xffff;
5781 gen_jmp(s, tval);
5782 break;
5783 case 0x70 ... 0x7f: /* jcc Jb */
5784 tval = (int8_t)insn_get(s, OT_BYTE);
5785 goto do_jcc;
5786 case 0x180 ... 0x18f: /* jcc Jv */
5787 if (dflag) {
5788 tval = (int32_t)insn_get(s, OT_LONG);
5789 } else {
5790 tval = (int16_t)insn_get(s, OT_WORD);
5791 }
5792 do_jcc:
5793 next_eip = s->pc - s->cs_base;
5794 tval += next_eip;
5795 if (s->dflag == 0)
5796 tval &= 0xffff;
5797 gen_jcc(s, b, tval, next_eip);
5798 break;
5799
5800 case 0x190 ... 0x19f: /* setcc Gv */
5801 modrm = ldub_code(s->pc++);
5802 gen_setcc(s, b);
5803 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
5804 break;
5805 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5806 {
5807 int l1;
5808 ot = dflag + OT_WORD;
5809 modrm = ldub_code(s->pc++);
5810 reg = ((modrm >> 3) & 7) | rex_r;
5811 mod = (modrm >> 6) & 3;
5812 if (mod != 3) {
5813 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5814 gen_op_ld_T1_A0(ot + s->mem_index);
5815 } else {
5816 rm = (modrm & 7) | REX_B(s);
5817 gen_op_mov_TN_reg(ot, 1, rm);
5818 }
5819 if (s->cc_op != CC_OP_DYNAMIC)
5820 gen_op_set_cc_op(s->cc_op);
5821 #ifdef TARGET_X86_64
5822 if (ot == OT_LONG) {
5823 /* XXX: specific Intel behaviour ? */
5824 l1 = gen_new_label();
5825 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5826 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);
5827 gen_set_label(l1);
5828 tcg_gen_movi_tl(cpu_tmp0, 0);
5829 tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);
5830 } else
5831 #endif
5832 {
5833 l1 = gen_new_label();
5834 gen_jcc1(s, s->cc_op, b ^ 1, l1);
5835 gen_op_mov_reg_T1(ot, reg);
5836 gen_set_label(l1);
5837 }
5838 }
5839 break;
5840
5841 /************************/
5842 /* flags */
5843 case 0x9c: /* pushf */
5844 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF))
5845 break;
5846 if (s->vm86 && s->iopl != 3) {
5847 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5848 } else {
5849 if (s->cc_op != CC_OP_DYNAMIC)
5850 gen_op_set_cc_op(s->cc_op);
5851 tcg_gen_helper_1_0(helper_read_eflags, cpu_T[0]);
5852 gen_push_T0(s);
5853 }
5854 break;
5855 case 0x9d: /* popf */
5856 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF))
5857 break;
5858 if (s->vm86 && s->iopl != 3) {
5859 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
5860 } else {
5861 gen_pop_T0(s);
5862 if (s->cpl == 0) {
5863 if (s->dflag) {
5864 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5865 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK)));
5866 } else {
5867 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5868 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK | IOPL_MASK) & 0xffff));
5869 }
5870 } else {
5871 if (s->cpl <= s->iopl) {
5872 if (s->dflag) {
5873 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5874 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK)));
5875 } else {
5876 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5877 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK | IF_MASK) & 0xffff));
5878 }
5879 } else {
5880 if (s->dflag) {
5881 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5882 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK)));
5883 } else {
5884 tcg_gen_helper_0_2(helper_write_eflags, cpu_T[0],
5885 tcg_const_i32((TF_MASK | AC_MASK | ID_MASK | NT_MASK) & 0xffff));
5886 }
5887 }
5888 }
5889 gen_pop_update(s);
5890 s->cc_op = CC_OP_EFLAGS;
5891 /* abort translation because TF flag may change */
5892 gen_jmp_im(s->pc - s->cs_base);
5893 gen_eob(s);
5894 }
5895 break;
5896 case 0x9e: /* sahf */
5897 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5898 goto illegal_op;
5899 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
5900 if (s->cc_op != CC_OP_DYNAMIC)
5901 gen_op_set_cc_op(s->cc_op);
5902 gen_compute_eflags(cpu_cc_src);
5903 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
5904 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
5905 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
5906 s->cc_op = CC_OP_EFLAGS;
5907 break;
5908 case 0x9f: /* lahf */
5909 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
5910 goto illegal_op;
5911 if (s->cc_op != CC_OP_DYNAMIC)
5912 gen_op_set_cc_op(s->cc_op);
5913 gen_compute_eflags(cpu_T[0]);
5914 /* Note: gen_compute_eflags() only gives the condition codes */
5915 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
5916 gen_op_mov_reg_T0(OT_BYTE, R_AH);
5917 break;
5918 case 0xf5: /* cmc */
5919 if (s->cc_op != CC_OP_DYNAMIC)
5920 gen_op_set_cc_op(s->cc_op);
5921 gen_compute_eflags(cpu_cc_src);
5922 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5923 s->cc_op = CC_OP_EFLAGS;
5924 break;
5925 case 0xf8: /* clc */
5926 if (s->cc_op != CC_OP_DYNAMIC)
5927 gen_op_set_cc_op(s->cc_op);
5928 gen_compute_eflags(cpu_cc_src);
5929 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
5930 s->cc_op = CC_OP_EFLAGS;
5931 break;
5932 case 0xf9: /* stc */
5933 if (s->cc_op != CC_OP_DYNAMIC)
5934 gen_op_set_cc_op(s->cc_op);
5935 gen_compute_eflags(cpu_cc_src);
5936 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
5937 s->cc_op = CC_OP_EFLAGS;
5938 break;
5939 case 0xfc: /* cld */
5940 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
5941 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5942 break;
5943 case 0xfd: /* std */
5944 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
5945 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUState, df));
5946 break;
5947
5948 /************************/
5949 /* bit operations */
5950 case 0x1ba: /* bt/bts/btr/btc Gv, im */
5951 ot = dflag + OT_WORD;
5952 modrm = ldub_code(s->pc++);
5953 op = (modrm >> 3) & 7;
5954 mod = (modrm >> 6) & 3;
5955 rm = (modrm & 7) | REX_B(s);
5956 if (mod != 3) {
5957 s->rip_offset = 1;
5958 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5959 gen_op_ld_T0_A0(ot + s->mem_index);
5960 } else {
5961 gen_op_mov_TN_reg(ot, 0, rm);
5962 }
5963 /* load shift */
5964 val = ldub_code(s->pc++);
5965 gen_op_movl_T1_im(val);
5966 if (op < 4)
5967 goto illegal_op;
5968 op -= 4;
5969 goto bt_op;
5970 case 0x1a3: /* bt Gv, Ev */
5971 op = 0;
5972 goto do_btx;
5973 case 0x1ab: /* bts */
5974 op = 1;
5975 goto do_btx;
5976 case 0x1b3: /* btr */
5977 op = 2;
5978 goto do_btx;
5979 case 0x1bb: /* btc */
5980 op = 3;
5981 do_btx:
5982 ot = dflag + OT_WORD;
5983 modrm = ldub_code(s->pc++);
5984 reg = ((modrm >> 3) & 7) | rex_r;
5985 mod = (modrm >> 6) & 3;
5986 rm = (modrm & 7) | REX_B(s);
5987 gen_op_mov_TN_reg(OT_LONG, 1, reg);
5988 if (mod != 3) {
5989 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5990 /* specific case: we need to add a displacement */
5991 gen_exts(ot, cpu_T[1]);
5992 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
5993 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
5994 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
5995 gen_op_ld_T0_A0(ot + s->mem_index);
5996 } else {
5997 gen_op_mov_TN_reg(ot, 0, rm);
5998 }
5999 bt_op:
6000 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6001 switch(op) {
6002 case 0:
6003 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6004 tcg_gen_movi_tl(cpu_cc_dst, 0);
6005 break;
6006 case 1:
6007 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6008 tcg_gen_movi_tl(cpu_tmp0, 1);
6009 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6010 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6011 break;
6012 case 2:
6013 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6014 tcg_gen_movi_tl(cpu_tmp0, 1);
6015 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6016 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6017 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6018 break;
6019 default:
6020 case 3:
6021 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6022 tcg_gen_movi_tl(cpu_tmp0, 1);
6023 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6024 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6025 break;
6026 }
6027 s->cc_op = CC_OP_SARB + ot;
6028 if (op != 0) {
6029 if (mod != 3)
6030 gen_op_st_T0_A0(ot + s->mem_index);
6031 else
6032 gen_op_mov_reg_T0(ot, rm);
6033 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6034 tcg_gen_movi_tl(cpu_cc_dst, 0);
6035 }
6036 break;
6037 case 0x1bc: /* bsf */
6038 case 0x1bd: /* bsr */
6039 {
6040 int label1;
6041 ot = dflag + OT_WORD;
6042 modrm = ldub_code(s->pc++);
6043 reg = ((modrm >> 3) & 7) | rex_r;
6044 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
6045 gen_extu(ot, cpu_T[0]);
6046 label1 = gen_new_label();
6047 tcg_gen_movi_tl(cpu_cc_dst, 0);
6048 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_T[0], tcg_const_tl(0), label1);
6049 if (b & 1) {
6050 tcg_gen_helper_1_1(helper_bsr, cpu_T[0], cpu_T[0]);
6051 } else {
6052 tcg_gen_helper_1_1(helper_bsf, cpu_T[0], cpu_T[0]);
6053 }
6054 gen_op_mov_reg_T0(ot, reg);
6055 tcg_gen_movi_tl(cpu_cc_dst, 1);
6056 gen_set_label(label1);
6057 tcg_gen_discard_tl(cpu_cc_src);
6058 s->cc_op = CC_OP_LOGICB + ot;
6059 }
6060 break;
6061 /************************/
6062 /* bcd */
6063 case 0x27: /* daa */
6064 if (CODE64(s))
6065 goto illegal_op;
6066 if (s->cc_op != CC_OP_DYNAMIC)
6067 gen_op_set_cc_op(s->cc_op);
6068 tcg_gen_helper_0_0(helper_daa);
6069 s->cc_op = CC_OP_EFLAGS;
6070 break;
6071 case 0x2f: /* das */
6072 if (CODE64(s))
6073 goto illegal_op;
6074 if (s->cc_op != CC_OP_DYNAMIC)
6075 gen_op_set_cc_op(s->cc_op);
6076 tcg_gen_helper_0_0(helper_das);
6077 s->cc_op = CC_OP_EFLAGS;
6078 break;
6079 case 0x37: /* aaa */
6080 if (CODE64(s))
6081 goto illegal_op;
6082 if (s->cc_op != CC_OP_DYNAMIC)
6083 gen_op_set_cc_op(s->cc_op);
6084 tcg_gen_helper_0_0(helper_aaa);
6085 s->cc_op = CC_OP_EFLAGS;
6086 break;
6087 case 0x3f: /* aas */
6088 if (CODE64(s))
6089 goto illegal_op;
6090 if (s->cc_op != CC_OP_DYNAMIC)
6091 gen_op_set_cc_op(s->cc_op);
6092 tcg_gen_helper_0_0(helper_aas);
6093 s->cc_op = CC_OP_EFLAGS;
6094 break;
6095 case 0xd4: /* aam */
6096 if (CODE64(s))
6097 goto illegal_op;
6098 val = ldub_code(s->pc++);
6099 if (val == 0) {
6100 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6101 } else {
6102 tcg_gen_helper_0_1(helper_aam, tcg_const_i32(val));
6103 s->cc_op = CC_OP_LOGICB;
6104 }
6105 break;
6106 case 0xd5: /* aad */
6107 if (CODE64(s))
6108 goto illegal_op;
6109 val = ldub_code(s->pc++);
6110 tcg_gen_helper_0_1(helper_aad, tcg_const_i32(val));
6111 s->cc_op = CC_OP_LOGICB;
6112 break;
6113 /************************/
6114 /* misc */
6115 case 0x90: /* nop */
6116 /* XXX: xchg + rex handling */
6117 /* XXX: correct lock test for all insn */
6118 if (prefixes & PREFIX_LOCK)
6119 goto illegal_op;
6120 if (prefixes & PREFIX_REPZ) {
6121 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6122 }
6123 break;
6124 case 0x9b: /* fwait */
6125 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6126 (HF_MP_MASK | HF_TS_MASK)) {
6127 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6128 } else {
6129 if (s->cc_op != CC_OP_DYNAMIC)
6130 gen_op_set_cc_op(s->cc_op);
6131 gen_jmp_im(pc_start - s->cs_base);
6132 tcg_gen_helper_0_0(helper_fwait);
6133 }
6134 break;
6135 case 0xcc: /* int3 */
6136 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6137 break;
6138 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6139 break;
6140 case 0xcd: /* int N */
6141 val = ldub_code(s->pc++);
6142 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6143 break;
6144 if (s->vm86 && s->iopl != 3) {
6145 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6146 } else {
6147 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6148 }
6149 break;
6150 case 0xce: /* into */
6151 if (CODE64(s))
6152 goto illegal_op;
6153 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SWINT))
6154 break;
6155 if (s->cc_op != CC_OP_DYNAMIC)
6156 gen_op_set_cc_op(s->cc_op);
6157 gen_jmp_im(pc_start - s->cs_base);
6158 tcg_gen_helper_0_1(helper_into, tcg_const_i32(s->pc - pc_start));
6159 break;
6160 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6161 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP))
6162 break;
6163 #if 1
6164 gen_debug(s, pc_start - s->cs_base);
6165 #else
6166 /* start debug */
6167 tb_flush(cpu_single_env);
6168 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6169 #endif
6170 break;
6171 case 0xfa: /* cli */
6172 if (!s->vm86) {
6173 if (s->cpl <= s->iopl) {
6174 tcg_gen_helper_0_0(helper_cli);
6175 } else {
6176 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6177 }
6178 } else {
6179 if (s->iopl == 3) {
6180 tcg_gen_helper_0_0(helper_cli);
6181 } else {
6182 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6183 }
6184 }
6185 break;
6186 case 0xfb: /* sti */
6187 if (!s->vm86) {
6188 if (s->cpl <= s->iopl) {
6189 gen_sti:
6190 tcg_gen_helper_0_0(helper_sti);
6191 /* interruptions are enabled only the first insn after sti */
6192 /* If several instructions disable interrupts, only the
6193 _first_ does it */
6194 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6195 tcg_gen_helper_0_0(helper_set_inhibit_irq);
6196 /* give a chance to handle pending irqs */
6197 gen_jmp_im(s->pc - s->cs_base);
6198 gen_eob(s);
6199 } else {
6200 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6201 }
6202 } else {
6203 if (s->iopl == 3) {
6204 goto gen_sti;
6205 } else {
6206 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6207 }
6208 }
6209 break;
6210 case 0x62: /* bound */
6211 if (CODE64(s))
6212 goto illegal_op;
6213 ot = dflag ? OT_LONG : OT_WORD;
6214 modrm = ldub_code(s->pc++);
6215 reg = (modrm >> 3) & 7;
6216 mod = (modrm >> 6) & 3;
6217 if (mod == 3)
6218 goto illegal_op;
6219 gen_op_mov_TN_reg(ot, 0, reg);
6220 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6221 gen_jmp_im(pc_start - s->cs_base);
6222 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6223 if (ot == OT_WORD)
6224 tcg_gen_helper_0_2(helper_boundw, cpu_A0, cpu_tmp2_i32);
6225 else
6226 tcg_gen_helper_0_2(helper_boundl, cpu_A0, cpu_tmp2_i32);
6227 break;
6228 case 0x1c8 ... 0x1cf: /* bswap reg */
6229 reg = (b & 7) | REX_B(s);
6230 #ifdef TARGET_X86_64
6231 if (dflag == 2) {
6232 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6233 tcg_gen_bswap_i64(cpu_T[0], cpu_T[0]);
6234 gen_op_mov_reg_T0(OT_QUAD, reg);
6235 } else
6236 {
6237 TCGv tmp0;
6238 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6239
6240 tmp0 = tcg_temp_new(TCG_TYPE_I32);
6241 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]);
6242 tcg_gen_bswap_i32(tmp0, tmp0);
6243 tcg_gen_extu_i32_i64(cpu_T[0], tmp0);
6244 gen_op_mov_reg_T0(OT_LONG, reg);
6245 }
6246 #else
6247 {
6248 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6249 tcg_gen_bswap_i32(cpu_T[0], cpu_T[0]);
6250 gen_op_mov_reg_T0(OT_LONG, reg);
6251 }
6252 #endif
6253 break;
6254 case 0xd6: /* salc */
6255 if (CODE64(s))
6256 goto illegal_op;
6257 if (s->cc_op != CC_OP_DYNAMIC)
6258 gen_op_set_cc_op(s->cc_op);
6259 gen_compute_eflags_c(cpu_T[0]);
6260 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6261 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6262 break;
6263 case 0xe0: /* loopnz */
6264 case 0xe1: /* loopz */
6265 case 0xe2: /* loop */
6266 case 0xe3: /* jecxz */
6267 {
6268 int l1, l2, l3;
6269
6270 tval = (int8_t)insn_get(s, OT_BYTE);
6271 next_eip = s->pc - s->cs_base;
6272 tval += next_eip;
6273 if (s->dflag == 0)
6274 tval &= 0xffff;
6275
6276 l1 = gen_new_label();
6277 l2 = gen_new_label();
6278 l3 = gen_new_label();
6279 b &= 3;
6280 switch(b) {
6281 case 0: /* loopnz */
6282 case 1: /* loopz */
6283 if (s->cc_op != CC_OP_DYNAMIC)
6284 gen_op_set_cc_op(s->cc_op);
6285 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6286 gen_op_jz_ecx(s->aflag, l3);
6287 gen_compute_eflags(cpu_tmp0);
6288 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6289 if (b == 0) {
6290 tcg_gen_brcond_tl(TCG_COND_EQ,
6291 cpu_tmp0, tcg_const_tl(0), l1);
6292 } else {
6293 tcg_gen_brcond_tl(TCG_COND_NE,
6294 cpu_tmp0, tcg_const_tl(0), l1);
6295 }
6296 break;
6297 case 2: /* loop */
6298 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6299 gen_op_jnz_ecx(s->aflag, l1);
6300 break;
6301 default:
6302 case 3: /* jcxz */
6303 gen_op_jz_ecx(s->aflag, l1);
6304 break;
6305 }
6306
6307 gen_set_label(l3);
6308 gen_jmp_im(next_eip);
6309 tcg_gen_br(l2);
6310
6311 gen_set_label(l1);
6312 gen_jmp_im(tval);
6313 gen_set_label(l2);
6314 gen_eob(s);
6315 }
6316 break;
6317 case 0x130: /* wrmsr */
6318 case 0x132: /* rdmsr */
6319 if (s->cpl != 0) {
6320 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6321 } else {
6322 int retval = 0;
6323 if (b & 2) {
6324 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 0);
6325 tcg_gen_helper_0_0(helper_rdmsr);
6326 } else {
6327 retval = gen_svm_check_intercept_param(s, pc_start, SVM_EXIT_MSR, 1);
6328 tcg_gen_helper_0_0(helper_wrmsr);
6329 }
6330 if(retval)
6331 gen_eob(s);
6332 }
6333 break;
6334 case 0x131: /* rdtsc */
6335 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RDTSC))
6336 break;
6337 gen_jmp_im(pc_start - s->cs_base);
6338 tcg_gen_helper_0_0(helper_rdtsc);
6339 break;
6340 case 0x133: /* rdpmc */
6341 gen_jmp_im(pc_start - s->cs_base);
6342 tcg_gen_helper_0_0(helper_rdpmc);
6343 break;
6344 case 0x134: /* sysenter */
6345 if (CODE64(s))
6346 goto illegal_op;
6347 if (!s->pe) {
6348 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6349 } else {
6350 if (s->cc_op != CC_OP_DYNAMIC) {
6351 gen_op_set_cc_op(s->cc_op);
6352 s->cc_op = CC_OP_DYNAMIC;
6353 }
6354 gen_jmp_im(pc_start - s->cs_base);
6355 tcg_gen_helper_0_0(helper_sysenter);
6356 gen_eob(s);
6357 }
6358 break;
6359 case 0x135: /* sysexit */
6360 if (CODE64(s))
6361 goto illegal_op;
6362 if (!s->pe) {
6363 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6364 } else {
6365 if (s->cc_op != CC_OP_DYNAMIC) {
6366 gen_op_set_cc_op(s->cc_op);
6367 s->cc_op = CC_OP_DYNAMIC;
6368 }
6369 gen_jmp_im(pc_start - s->cs_base);
6370 tcg_gen_helper_0_0(helper_sysexit);
6371 gen_eob(s);
6372 }
6373 break;
6374 #ifdef TARGET_X86_64
6375 case 0x105: /* syscall */
6376 /* XXX: is it usable in real mode ? */
6377 if (s->cc_op != CC_OP_DYNAMIC) {
6378 gen_op_set_cc_op(s->cc_op);
6379 s->cc_op = CC_OP_DYNAMIC;
6380 }
6381 gen_jmp_im(pc_start - s->cs_base);
6382 tcg_gen_helper_0_1(helper_syscall, tcg_const_i32(s->pc - pc_start));
6383 gen_eob(s);
6384 break;
6385 case 0x107: /* sysret */
6386 if (!s->pe) {
6387 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6388 } else {
6389 if (s->cc_op != CC_OP_DYNAMIC) {
6390 gen_op_set_cc_op(s->cc_op);
6391 s->cc_op = CC_OP_DYNAMIC;
6392 }
6393 gen_jmp_im(pc_start - s->cs_base);
6394 tcg_gen_helper_0_1(helper_sysret, tcg_const_i32(s->dflag));
6395 /* condition codes are modified only in long mode */
6396 if (s->lma)
6397 s->cc_op = CC_OP_EFLAGS;
6398 gen_eob(s);
6399 }
6400 break;
6401 #endif
6402 case 0x1a2: /* cpuid */
6403 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CPUID))
6404 break;
6405 tcg_gen_helper_0_0(helper_cpuid);
6406 break;
6407 case 0xf4: /* hlt */
6408 if (s->cpl != 0) {
6409 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6410 } else {
6411 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_HLT))
6412 break;
6413 if (s->cc_op != CC_OP_DYNAMIC)
6414 gen_op_set_cc_op(s->cc_op);
6415 gen_jmp_im(s->pc - s->cs_base);
6416 tcg_gen_helper_0_0(helper_hlt);
6417 s->is_jmp = 3;
6418 }
6419 break;
6420 case 0x100:
6421 modrm = ldub_code(s->pc++);
6422 mod = (modrm >> 6) & 3;
6423 op = (modrm >> 3) & 7;
6424 switch(op) {
6425 case 0: /* sldt */
6426 if (!s->pe || s->vm86)
6427 goto illegal_op;
6428 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ))
6429 break;
6430 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
6431 ot = OT_WORD;
6432 if (mod == 3)
6433 ot += s->dflag;
6434 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6435 break;
6436 case 2: /* lldt */
6437 if (!s->pe || s->vm86)
6438 goto illegal_op;
6439 if (s->cpl != 0) {
6440 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6441 } else {
6442 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE))
6443 break;
6444 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6445 gen_jmp_im(pc_start - s->cs_base);
6446 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6447 tcg_gen_helper_0_1(helper_lldt, cpu_tmp2_i32);
6448 }
6449 break;
6450 case 1: /* str */
6451 if (!s->pe || s->vm86)
6452 goto illegal_op;
6453 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ))
6454 break;
6455 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
6456 ot = OT_WORD;
6457 if (mod == 3)
6458 ot += s->dflag;
6459 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
6460 break;
6461 case 3: /* ltr */
6462 if (!s->pe || s->vm86)
6463 goto illegal_op;
6464 if (s->cpl != 0) {
6465 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6466 } else {
6467 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE))
6468 break;
6469 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6470 gen_jmp_im(pc_start - s->cs_base);
6471 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6472 tcg_gen_helper_0_1(helper_ltr, cpu_tmp2_i32);
6473 }
6474 break;
6475 case 4: /* verr */
6476 case 5: /* verw */
6477 if (!s->pe || s->vm86)
6478 goto illegal_op;
6479 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6480 if (s->cc_op != CC_OP_DYNAMIC)
6481 gen_op_set_cc_op(s->cc_op);
6482 if (op == 4)
6483 tcg_gen_helper_0_1(helper_verr, cpu_T[0]);
6484 else
6485 tcg_gen_helper_0_1(helper_verw, cpu_T[0]);
6486 s->cc_op = CC_OP_EFLAGS;
6487 break;
6488 default:
6489 goto illegal_op;
6490 }
6491 break;
6492 case 0x101:
6493 modrm = ldub_code(s->pc++);
6494 mod = (modrm >> 6) & 3;
6495 op = (modrm >> 3) & 7;
6496 rm = modrm & 7;
6497 switch(op) {
6498 case 0: /* sgdt */
6499 if (mod == 3)
6500 goto illegal_op;
6501 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ))
6502 break;
6503 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6504 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
6505 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6506 gen_add_A0_im(s, 2);
6507 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
6508 if (!s->dflag)
6509 gen_op_andl_T0_im(0xffffff);
6510 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6511 break;
6512 case 1:
6513 if (mod == 3) {
6514 switch (rm) {
6515 case 0: /* monitor */
6516 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6517 s->cpl != 0)
6518 goto illegal_op;
6519 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MONITOR))
6520 break;
6521 gen_jmp_im(pc_start - s->cs_base);
6522 #ifdef TARGET_X86_64
6523 if (s->aflag == 2) {
6524 gen_op_movq_A0_reg(R_EAX);
6525 } else
6526 #endif
6527 {
6528 gen_op_movl_A0_reg(R_EAX);
6529 if (s->aflag == 0)
6530 gen_op_andl_A0_ffff();
6531 }
6532 gen_add_A0_ds_seg(s);
6533 tcg_gen_helper_0_1(helper_monitor, cpu_A0);
6534 break;
6535 case 1: /* mwait */
6536 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
6537 s->cpl != 0)
6538 goto illegal_op;
6539 if (s->cc_op != CC_OP_DYNAMIC) {
6540 gen_op_set_cc_op(s->cc_op);
6541 s->cc_op = CC_OP_DYNAMIC;
6542 }
6543 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_MWAIT))
6544 break;
6545 gen_jmp_im(s->pc - s->cs_base);
6546 tcg_gen_helper_0_0(helper_mwait);
6547 gen_eob(s);
6548 break;
6549 default:
6550 goto illegal_op;
6551 }
6552 } else { /* sidt */
6553 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ))
6554 break;
6555 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6556 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
6557 gen_op_st_T0_A0(OT_WORD + s->mem_index);
6558 gen_add_A0_im(s, 2);
6559 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
6560 if (!s->dflag)
6561 gen_op_andl_T0_im(0xffffff);
6562 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6563 }
6564 break;
6565 case 2: /* lgdt */
6566 case 3: /* lidt */
6567 if (mod == 3) {
6568 switch(rm) {
6569 case 0: /* VMRUN */
6570 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMRUN))
6571 break;
6572 if (s->cc_op != CC_OP_DYNAMIC)
6573 gen_op_set_cc_op(s->cc_op);
6574 gen_jmp_im(s->pc - s->cs_base);
6575 tcg_gen_helper_0_0(helper_vmrun);
6576 s->cc_op = CC_OP_EFLAGS;
6577 gen_eob(s);
6578 break;
6579 case 1: /* VMMCALL */
6580 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMMCALL))
6581 break;
6582 /* FIXME: cause #UD if hflags & SVM */
6583 tcg_gen_helper_0_0(helper_vmmcall);
6584 break;
6585 case 2: /* VMLOAD */
6586 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMLOAD))
6587 break;
6588 tcg_gen_helper_0_0(helper_vmload);
6589 break;
6590 case 3: /* VMSAVE */
6591 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_VMSAVE))
6592 break;
6593 tcg_gen_helper_0_0(helper_vmsave);
6594 break;
6595 case 4: /* STGI */
6596 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_STGI))
6597 break;
6598 tcg_gen_helper_0_0(helper_stgi);
6599 break;
6600 case 5: /* CLGI */
6601 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_CLGI))
6602 break;
6603 tcg_gen_helper_0_0(helper_clgi);
6604 break;
6605 case 6: /* SKINIT */
6606 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_SKINIT))
6607 break;
6608 tcg_gen_helper_0_0(helper_skinit);
6609 break;
6610 case 7: /* INVLPGA */
6611 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPGA))
6612 break;
6613 tcg_gen_helper_0_0(helper_invlpga);
6614 break;
6615 default:
6616 goto illegal_op;
6617 }
6618 } else if (s->cpl != 0) {
6619 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6620 } else {
6621 if (gen_svm_check_intercept(s, pc_start,
6622 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE))
6623 break;
6624 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6625 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
6626 gen_add_A0_im(s, 2);
6627 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
6628 if (!s->dflag)
6629 gen_op_andl_T0_im(0xffffff);
6630 if (op == 2) {
6631 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
6632 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
6633 } else {
6634 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
6635 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
6636 }
6637 }
6638 break;
6639 case 4: /* smsw */
6640 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0))
6641 break;
6642 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
6643 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
6644 break;
6645 case 6: /* lmsw */
6646 if (s->cpl != 0) {
6647 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6648 } else {
6649 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0))
6650 break;
6651 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6652 tcg_gen_helper_0_1(helper_lmsw, cpu_T[0]);
6653 gen_jmp_im(s->pc - s->cs_base);
6654 gen_eob(s);
6655 }
6656 break;
6657 case 7: /* invlpg */
6658 if (s->cpl != 0) {
6659 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6660 } else {
6661 if (mod == 3) {
6662 #ifdef TARGET_X86_64
6663 if (CODE64(s) && rm == 0) {
6664 /* swapgs */
6665 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6666 tcg_gen_ld_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,kernelgsbase));
6667 tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,segs[R_GS].base));
6668 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,kernelgsbase));
6669 } else
6670 #endif
6671 {
6672 goto illegal_op;
6673 }
6674 } else {
6675 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_INVLPG))
6676 break;
6677 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6678 tcg_gen_helper_0_1(helper_invlpg, cpu_A0);
6679 gen_jmp_im(s->pc - s->cs_base);
6680 gen_eob(s);
6681 }
6682 }
6683 break;
6684 default:
6685 goto illegal_op;
6686 }
6687 break;
6688 case 0x108: /* invd */
6689 case 0x109: /* wbinvd */
6690 if (s->cpl != 0) {
6691 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6692 } else {
6693 if (gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD))
6694 break;
6695 /* nothing to do */
6696 }
6697 break;
6698 case 0x63: /* arpl or movslS (x86_64) */
6699 #ifdef TARGET_X86_64
6700 if (CODE64(s)) {
6701 int d_ot;
6702 /* d_ot is the size of destination */
6703 d_ot = dflag + OT_WORD;
6704
6705 modrm = ldub_code(s->pc++);
6706 reg = ((modrm >> 3) & 7) | rex_r;
6707 mod = (modrm >> 6) & 3;
6708 rm = (modrm & 7) | REX_B(s);
6709
6710 if (mod == 3) {
6711 gen_op_mov_TN_reg(OT_LONG, 0, rm);
6712 /* sign extend */
6713 if (d_ot == OT_QUAD)
6714 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
6715 gen_op_mov_reg_T0(d_ot, reg);
6716 } else {
6717 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6718 if (d_ot == OT_QUAD) {
6719 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
6720 } else {
6721 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6722 }
6723 gen_op_mov_reg_T0(d_ot, reg);
6724 }
6725 } else
6726 #endif
6727 {
6728 int label1;
6729 if (!s->pe || s->vm86)
6730 goto illegal_op;
6731 ot = OT_WORD;
6732 modrm = ldub_code(s->pc++);
6733 reg = (modrm >> 3) & 7;
6734 mod = (modrm >> 6) & 3;
6735 rm = modrm & 7;
6736 if (mod != 3) {
6737 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6738 gen_op_ld_T0_A0(ot + s->mem_index);
6739 } else {
6740 gen_op_mov_TN_reg(ot, 0, rm);
6741 }
6742 gen_op_mov_TN_reg(ot, 1, reg);
6743 tcg_gen_andi_tl(cpu_tmp0, cpu_T[0], 3);
6744 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 3);
6745 tcg_gen_movi_tl(cpu_T3, 0);
6746 label1 = gen_new_label();
6747 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, cpu_T[1], label1);
6748 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~3);
6749 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
6750 tcg_gen_movi_tl(cpu_T3, CC_Z);
6751 gen_set_label(label1);
6752 if (mod != 3) {
6753 gen_op_st_T0_A0(ot + s->mem_index);
6754 } else {
6755 gen_op_mov_reg_T0(ot, rm);
6756 }
6757 if (s->cc_op != CC_OP_DYNAMIC)
6758 gen_op_set_cc_op(s->cc_op);
6759 gen_compute_eflags(cpu_cc_src);
6760 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
6761 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T3);
6762 s->cc_op = CC_OP_EFLAGS;
6763 }
6764 break;
6765 case 0x102: /* lar */
6766 case 0x103: /* lsl */
6767 {
6768 int label1;
6769 if (!s->pe || s->vm86)
6770 goto illegal_op;
6771 ot = dflag ? OT_LONG : OT_WORD;
6772 modrm = ldub_code(s->pc++);
6773 reg = ((modrm >> 3) & 7) | rex_r;
6774 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
6775 if (s->cc_op != CC_OP_DYNAMIC)
6776 gen_op_set_cc_op(s->cc_op);
6777 if (b == 0x102)
6778 tcg_gen_helper_1_1(helper_lar, cpu_T[0], cpu_T[0]);
6779 else
6780 tcg_gen_helper_1_1(helper_lsl, cpu_T[0], cpu_T[0]);
6781 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
6782 label1 = gen_new_label();
6783 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), label1);
6784 gen_op_mov_reg_T0(ot, reg);
6785 gen_set_label(label1);
6786 s->cc_op = CC_OP_EFLAGS;
6787 }
6788 break;
6789 case 0x118:
6790 modrm = ldub_code(s->pc++);
6791 mod = (modrm >> 6) & 3;
6792 op = (modrm >> 3) & 7;
6793 switch(op) {
6794 case 0: /* prefetchnta */
6795 case 1: /* prefetchnt0 */
6796 case 2: /* prefetchnt0 */
6797 case 3: /* prefetchnt0 */
6798 if (mod == 3)
6799 goto illegal_op;
6800 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6801 /* nothing more to do */
6802 break;
6803 default: /* nop (multi byte) */
6804 gen_nop_modrm(s, modrm);
6805 break;
6806 }
6807 break;
6808 case 0x119 ... 0x11f: /* nop (multi byte) */
6809 modrm = ldub_code(s->pc++);
6810 gen_nop_modrm(s, modrm);
6811 break;
6812 case 0x120: /* mov reg, crN */
6813 case 0x122: /* mov crN, reg */
6814 if (s->cpl != 0) {
6815 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6816 } else {
6817 modrm = ldub_code(s->pc++);
6818 if ((modrm & 0xc0) != 0xc0)
6819 goto illegal_op;
6820 rm = (modrm & 7) | REX_B(s);
6821 reg = ((modrm >> 3) & 7) | rex_r;
6822 if (CODE64(s))
6823 ot = OT_QUAD;
6824 else
6825 ot = OT_LONG;
6826 switch(reg) {
6827 case 0:
6828 case 2:
6829 case 3:
6830 case 4:
6831 case 8:
6832 if (b & 2) {
6833 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0 + reg);
6834 gen_op_mov_TN_reg(ot, 0, rm);
6835 tcg_gen_helper_0_2(helper_movl_crN_T0,
6836 tcg_const_i32(reg), cpu_T[0]);
6837 gen_jmp_im(s->pc - s->cs_base);
6838 gen_eob(s);
6839 } else {
6840 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0 + reg);
6841 #if !defined(CONFIG_USER_ONLY)
6842 if (reg == 8)
6843 tcg_gen_helper_1_0(helper_movtl_T0_cr8, cpu_T[0]);
6844 else
6845 #endif
6846 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[reg]));
6847 gen_op_mov_reg_T0(ot, rm);
6848 }
6849 break;
6850 default:
6851 goto illegal_op;
6852 }
6853 }
6854 break;
6855 case 0x121: /* mov reg, drN */
6856 case 0x123: /* mov drN, reg */
6857 if (s->cpl != 0) {
6858 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6859 } else {
6860 modrm = ldub_code(s->pc++);
6861 if ((modrm & 0xc0) != 0xc0)
6862 goto illegal_op;
6863 rm = (modrm & 7) | REX_B(s);
6864 reg = ((modrm >> 3) & 7) | rex_r;
6865 if (CODE64(s))
6866 ot = OT_QUAD;
6867 else
6868 ot = OT_LONG;
6869 /* XXX: do it dynamically with CR4.DE bit */
6870 if (reg == 4 || reg == 5 || reg >= 8)
6871 goto illegal_op;
6872 if (b & 2) {
6873 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
6874 gen_op_mov_TN_reg(ot, 0, rm);
6875 tcg_gen_helper_0_2(helper_movl_drN_T0,
6876 tcg_const_i32(reg), cpu_T[0]);
6877 gen_jmp_im(s->pc - s->cs_base);
6878 gen_eob(s);
6879 } else {
6880 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
6881 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
6882 gen_op_mov_reg_T0(ot, rm);
6883 }
6884 }
6885 break;
6886 case 0x106: /* clts */
6887 if (s->cpl != 0) {
6888 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6889 } else {
6890 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
6891 tcg_gen_helper_0_0(helper_clts);
6892 /* abort block because static cpu state changed */
6893 gen_jmp_im(s->pc - s->cs_base);
6894 gen_eob(s);
6895 }
6896 break;
6897 /* MMX/3DNow!/SSE/SSE2/SSE3 support */
6898 case 0x1c3: /* MOVNTI reg, mem */
6899 if (!(s->cpuid_features & CPUID_SSE2))
6900 goto illegal_op;
6901 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
6902 modrm = ldub_code(s->pc++);
6903 mod = (modrm >> 6) & 3;
6904 if (mod == 3)
6905 goto illegal_op;
6906 reg = ((modrm >> 3) & 7) | rex_r;
6907 /* generate a generic store */
6908 gen_ldst_modrm(s, modrm, ot, reg, 1);
6909 break;
6910 case 0x1ae:
6911 modrm = ldub_code(s->pc++);
6912 mod = (modrm >> 6) & 3;
6913 op = (modrm >> 3) & 7;
6914 switch(op) {
6915 case 0: /* fxsave */
6916 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6917 (s->flags & HF_EM_MASK))
6918 goto illegal_op;
6919 if (s->flags & HF_TS_MASK) {
6920 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6921 break;
6922 }
6923 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6924 if (s->cc_op != CC_OP_DYNAMIC)
6925 gen_op_set_cc_op(s->cc_op);
6926 gen_jmp_im(pc_start - s->cs_base);
6927 tcg_gen_helper_0_2(helper_fxsave,
6928 cpu_A0, tcg_const_i32((s->dflag == 2)));
6929 break;
6930 case 1: /* fxrstor */
6931 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
6932 (s->flags & HF_EM_MASK))
6933 goto illegal_op;
6934 if (s->flags & HF_TS_MASK) {
6935 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6936 break;
6937 }
6938 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6939 if (s->cc_op != CC_OP_DYNAMIC)
6940 gen_op_set_cc_op(s->cc_op);
6941 gen_jmp_im(pc_start - s->cs_base);
6942 tcg_gen_helper_0_2(helper_fxrstor,
6943 cpu_A0, tcg_const_i32((s->dflag == 2)));
6944 break;
6945 case 2: /* ldmxcsr */
6946 case 3: /* stmxcsr */
6947 if (s->flags & HF_TS_MASK) {
6948 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6949 break;
6950 }
6951 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
6952 mod == 3)
6953 goto illegal_op;
6954 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6955 if (op == 2) {
6956 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
6957 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
6958 } else {
6959 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
6960 gen_op_st_T0_A0(OT_LONG + s->mem_index);
6961 }
6962 break;
6963 case 5: /* lfence */
6964 case 6: /* mfence */
6965 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE))
6966 goto illegal_op;
6967 break;
6968 case 7: /* sfence / clflush */
6969 if ((modrm & 0xc7) == 0xc0) {
6970 /* sfence */
6971 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
6972 if (!(s->cpuid_features & CPUID_SSE))
6973 goto illegal_op;
6974 } else {
6975 /* clflush */
6976 if (!(s->cpuid_features & CPUID_CLFLUSH))
6977 goto illegal_op;
6978 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6979 }
6980 break;
6981 default:
6982 goto illegal_op;
6983 }
6984 break;
6985 case 0x10d: /* 3DNow! prefetch(w) */
6986 modrm = ldub_code(s->pc++);
6987 mod = (modrm >> 6) & 3;
6988 if (mod == 3)
6989 goto illegal_op;
6990 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6991 /* ignore for now */
6992 break;
6993 case 0x1aa: /* rsm */
6994 if (gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM))
6995 break;
6996 if (!(s->flags & HF_SMM_MASK))
6997 goto illegal_op;
6998 if (s->cc_op != CC_OP_DYNAMIC) {
6999 gen_op_set_cc_op(s->cc_op);
7000 s->cc_op = CC_OP_DYNAMIC;
7001 }
7002 gen_jmp_im(s->pc - s->cs_base);
7003 tcg_gen_helper_0_0(helper_rsm);
7004 gen_eob(s);
7005 break;
7006 case 0x10e ... 0x10f:
7007 /* 3DNow! instructions, ignore prefixes */
7008 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7009 case 0x110 ... 0x117:
7010 case 0x128 ... 0x12f:
7011 case 0x150 ... 0x177:
7012 case 0x17c ... 0x17f:
7013 case 0x1c2:
7014 case 0x1c4 ... 0x1c6:
7015 case 0x1d0 ... 0x1fe:
7016 gen_sse(s, b, pc_start, rex_r);
7017 break;
7018 default:
7019 goto illegal_op;
7020 }
7021 /* lock generation */
7022 if (s->prefix & PREFIX_LOCK)
7023 tcg_gen_helper_0_0(helper_unlock);
7024 return s->pc;
7025 illegal_op:
7026 if (s->prefix & PREFIX_LOCK)
7027 tcg_gen_helper_0_0(helper_unlock);
7028 /* XXX: ensure that no lock was generated */
7029 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7030 return s->pc;
7031 }
7032
7033 static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
7034 {
7035 switch(macro_id) {
7036 #ifdef MACRO_TEST
7037 case MACRO_TEST:
7038 tcg_gen_helper_0_1(helper_divl_EAX_T0, cpu_T[0]);
7039 break;
7040 #endif
7041 }
7042 }
7043
7044 void optimize_flags_init(void)
7045 {
7046 #if TCG_TARGET_REG_BITS == 32
7047 assert(sizeof(CCTable) == (1 << 3));
7048 #else
7049 assert(sizeof(CCTable) == (1 << 4));
7050 #endif
7051 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
7052
7053 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
7054 #if TARGET_LONG_BITS > HOST_LONG_BITS
7055 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
7056 TCG_AREG0, offsetof(CPUState, t0), "T0");
7057 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
7058 TCG_AREG0, offsetof(CPUState, t1), "T1");
7059 cpu_A0 = tcg_global_mem_new(TCG_TYPE_TL,
7060 TCG_AREG0, offsetof(CPUState, t2), "A0");
7061 #else
7062 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
7063 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
7064 cpu_A0 = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "A0");
7065 #endif
7066 cpu_T3 = tcg_global_mem_new(TCG_TYPE_TL,
7067 TCG_AREG0, offsetof(CPUState, t3), "T3");
7068 #if defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS)
7069 /* XXX: must be suppressed once there are less fixed registers */
7070 cpu_tmp1_i64 = tcg_global_reg2_new_hack(TCG_TYPE_I64, TCG_AREG1, TCG_AREG2, "tmp1");
7071 #endif
7072 cpu_cc_op = tcg_global_mem_new(TCG_TYPE_I32,
7073 TCG_AREG0, offsetof(CPUState, cc_op), "cc_op");
7074 cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
7075 TCG_AREG0, offsetof(CPUState, cc_src), "cc_src");
7076 cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
7077 TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst");
7078
7079 /* register helpers */
7080
7081 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
7082 #include "helper.h"
7083 }
7084
7085 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7086 basic block 'tb'. If search_pc is TRUE, also generate PC
7087 information for each intermediate instruction. */
7088 static inline int gen_intermediate_code_internal(CPUState *env,
7089 TranslationBlock *tb,
7090 int search_pc)
7091 {
7092 DisasContext dc1, *dc = &dc1;
7093 target_ulong pc_ptr;
7094 uint16_t *gen_opc_end;
7095 int j, lj, cflags;
7096 uint64_t flags;
7097 target_ulong pc_start;
7098 target_ulong cs_base;
7099
7100 /* generate intermediate code */
7101 pc_start = tb->pc;
7102 cs_base = tb->cs_base;
7103 flags = tb->flags;
7104 cflags = tb->cflags;
7105
7106 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7107 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7108 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7109 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7110 dc->f_st = 0;
7111 dc->vm86 = (flags >> VM_SHIFT) & 1;
7112 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7113 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7114 dc->tf = (flags >> TF_SHIFT) & 1;
7115 dc->singlestep_enabled = env->singlestep_enabled;
7116 dc->cc_op = CC_OP_DYNAMIC;
7117 dc->cs_base = cs_base;
7118 dc->tb = tb;
7119 dc->popl_esp_hack = 0;
7120 /* select memory access functions */
7121 dc->mem_index = 0;
7122 if (flags & HF_SOFTMMU_MASK) {
7123 if (dc->cpl == 3)
7124 dc->mem_index = 2 * 4;
7125 else
7126 dc->mem_index = 1 * 4;
7127 }
7128 dc->cpuid_features = env->cpuid_features;
7129 dc->cpuid_ext_features = env->cpuid_ext_features;
7130 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7131 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7132 #ifdef TARGET_X86_64
7133 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7134 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7135 #endif
7136 dc->flags = flags;
7137 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7138 (flags & HF_INHIBIT_IRQ_MASK)
7139 #ifndef CONFIG_SOFTMMU
7140 || (flags & HF_SOFTMMU_MASK)
7141 #endif
7142 );
7143 #if 0
7144 /* check addseg logic */
7145 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7146 printf("ERROR addseg\n");
7147 #endif
7148
7149 cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
7150 #if !(defined(__i386__) && (TARGET_LONG_BITS <= HOST_LONG_BITS))
7151 cpu_tmp1_i64 = tcg_temp_new(TCG_TYPE_I64);
7152 #endif
7153 cpu_tmp2_i32 = tcg_temp_new(TCG_TYPE_I32);
7154 cpu_tmp3_i32 = tcg_temp_new(TCG_TYPE_I32);
7155 cpu_tmp4 = tcg_temp_new(TCG_TYPE_TL);
7156 cpu_tmp5 = tcg_temp_new(TCG_TYPE_TL);
7157 cpu_tmp6 = tcg_temp_new(TCG_TYPE_TL);
7158 cpu_ptr0 = tcg_temp_new(TCG_TYPE_PTR);
7159 cpu_ptr1 = tcg_temp_new(TCG_TYPE_PTR);
7160
7161 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7162
7163 dc->is_jmp = DISAS_NEXT;
7164 pc_ptr = pc_start;
7165 lj = -1;
7166
7167 for(;;) {
7168 if (env->nb_breakpoints > 0) {
7169 for(j = 0; j < env->nb_breakpoints; j++) {
7170 if (env->breakpoints[j] == pc_ptr) {
7171 gen_debug(dc, pc_ptr - dc->cs_base);
7172 break;
7173 }
7174 }
7175 }
7176 if (search_pc) {
7177 j = gen_opc_ptr - gen_opc_buf;
7178 if (lj < j) {
7179 lj++;
7180 while (lj < j)
7181 gen_opc_instr_start[lj++] = 0;
7182 }
7183 gen_opc_pc[lj] = pc_ptr;
7184 gen_opc_cc_op[lj] = dc->cc_op;
7185 gen_opc_instr_start[lj] = 1;
7186 }
7187 pc_ptr = disas_insn(dc, pc_ptr);
7188 /* stop translation if indicated */
7189 if (dc->is_jmp)
7190 break;
7191 /* if single step mode, we generate only one instruction and
7192 generate an exception */
7193 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7194 the flag and abort the translation to give the irqs a
7195 change to be happen */
7196 if (dc->tf || dc->singlestep_enabled ||
7197 (flags & HF_INHIBIT_IRQ_MASK) ||
7198 (cflags & CF_SINGLE_INSN)) {
7199 gen_jmp_im(pc_ptr - dc->cs_base);
7200 gen_eob(dc);
7201 break;
7202 }
7203 /* if too long translation, stop generation too */
7204 if (gen_opc_ptr >= gen_opc_end ||
7205 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
7206 gen_jmp_im(pc_ptr - dc->cs_base);
7207 gen_eob(dc);
7208 break;
7209 }
7210 }
7211 *gen_opc_ptr = INDEX_op_end;
7212 /* we don't forget to fill the last values */
7213 if (search_pc) {
7214 j = gen_opc_ptr - gen_opc_buf;
7215 lj++;
7216 while (lj <= j)
7217 gen_opc_instr_start[lj++] = 0;
7218 }
7219
7220 #ifdef DEBUG_DISAS
7221 if (loglevel & CPU_LOG_TB_CPU) {
7222 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
7223 }
7224 if (loglevel & CPU_LOG_TB_IN_ASM) {
7225 int disas_flags;
7226 fprintf(logfile, "----------------\n");
7227 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
7228 #ifdef TARGET_X86_64
7229 if (dc->code64)
7230 disas_flags = 2;
7231 else
7232 #endif
7233 disas_flags = !dc->code32;
7234 target_disas(logfile, pc_start, pc_ptr - pc_start, disas_flags);
7235 fprintf(logfile, "\n");
7236 if (loglevel & CPU_LOG_TB_OP_OPT) {
7237 fprintf(logfile, "OP before opt:\n");
7238 tcg_dump_ops(&tcg_ctx, logfile);
7239 fprintf(logfile, "\n");
7240 }
7241 }
7242 #endif
7243
7244 if (!search_pc)
7245 tb->size = pc_ptr - pc_start;
7246 return 0;
7247 }
7248
7249 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
7250 {
7251 return gen_intermediate_code_internal(env, tb, 0);
7252 }
7253
7254 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
7255 {
7256 return gen_intermediate_code_internal(env, tb, 1);
7257 }
7258
7259 void gen_pc_load(CPUState *env, TranslationBlock *tb,
7260 unsigned long searched_pc, int pc_pos, void *puc)
7261 {
7262 int cc_op;
7263 #ifdef DEBUG_DISAS
7264 if (loglevel & CPU_LOG_TB_OP) {
7265 int i;
7266 fprintf(logfile, "RESTORE:\n");
7267 for(i = 0;i <= pc_pos; i++) {
7268 if (gen_opc_instr_start[i]) {
7269 fprintf(logfile, "0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
7270 }
7271 }
7272 fprintf(logfile, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
7273 searched_pc, pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
7274 (uint32_t)tb->cs_base);
7275 }
7276 #endif
7277 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
7278 cc_op = gen_opc_cc_op[pc_pos];
7279 if (cc_op != CC_OP_DYNAMIC)
7280 env->cc_op = cc_op;
7281 }
Qemu copy for testing