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[qemu.git] / target-i386 / translate.c
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <signal.h>
26 #include <assert.h>
27 #include <sys/mman.h>
28
29 #include "cpu.h"
30 #include "exec-all.h"
31 #include "disas.h"
32
33 /* XXX: move that elsewhere */
34 static uint16_t *gen_opc_ptr;
35 static uint32_t *gen_opparam_ptr;
36
37 #define PREFIX_REPZ 0x01
38 #define PREFIX_REPNZ 0x02
39 #define PREFIX_LOCK 0x04
40 #define PREFIX_DATA 0x08
41 #define PREFIX_ADR 0x10
42
43 typedef struct DisasContext {
44 /* current insn context */
45 int override; /* -1 if no override */
46 int prefix;
47 int aflag, dflag;
48 uint8_t *pc; /* pc = eip + cs_base */
49 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
50 static state change (stop translation) */
51 /* current block context */
52 uint8_t *cs_base; /* base of CS segment */
53 int pe; /* protected mode */
54 int code32; /* 32 bit code segment */
55 int ss32; /* 32 bit stack segment */
56 int cc_op; /* current CC operation */
57 int addseg; /* non zero if either DS/ES/SS have a non zero base */
58 int f_st; /* currently unused */
59 int vm86; /* vm86 mode */
60 int cpl;
61 int iopl;
62 int tf; /* TF cpu flag */
63 int singlestep_enabled; /* "hardware" single step enabled */
64 int jmp_opt; /* use direct block chaining for direct jumps */
65 int mem_index; /* select memory access functions */
66 struct TranslationBlock *tb;
67 int popl_esp_hack; /* for correct popl with esp base handling */
68 } DisasContext;
69
70 static void gen_eob(DisasContext *s);
71 static void gen_jmp(DisasContext *s, unsigned int eip);
72
73 /* i386 arith/logic operations */
74 enum {
75 OP_ADDL,
76 OP_ORL,
77 OP_ADCL,
78 OP_SBBL,
79 OP_ANDL,
80 OP_SUBL,
81 OP_XORL,
82 OP_CMPL,
83 };
84
85 /* i386 shift ops */
86 enum {
87 OP_ROL,
88 OP_ROR,
89 OP_RCL,
90 OP_RCR,
91 OP_SHL,
92 OP_SHR,
93 OP_SHL1, /* undocumented */
94 OP_SAR = 7,
95 };
96
97 enum {
98 #define DEF(s, n, copy_size) INDEX_op_ ## s,
99 #include "opc.h"
100 #undef DEF
101 NB_OPS,
102 };
103
104 #include "gen-op.h"
105
106 /* operand size */
107 enum {
108 OT_BYTE = 0,
109 OT_WORD,
110 OT_LONG,
111 OT_QUAD,
112 };
113
114 enum {
115 /* I386 int registers */
116 OR_EAX, /* MUST be even numbered */
117 OR_ECX,
118 OR_EDX,
119 OR_EBX,
120 OR_ESP,
121 OR_EBP,
122 OR_ESI,
123 OR_EDI,
124 OR_TMP0, /* temporary operand register */
125 OR_TMP1,
126 OR_A0, /* temporary register used when doing address evaluation */
127 OR_ZERO, /* fixed zero register */
128 NB_OREGS,
129 };
130
131 typedef void (GenOpFunc)(void);
132 typedef void (GenOpFunc1)(long);
133 typedef void (GenOpFunc2)(long, long);
134 typedef void (GenOpFunc3)(long, long, long);
135
136 static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
137 [OT_BYTE] = {
138 gen_op_movb_EAX_T0,
139 gen_op_movb_ECX_T0,
140 gen_op_movb_EDX_T0,
141 gen_op_movb_EBX_T0,
142 gen_op_movh_EAX_T0,
143 gen_op_movh_ECX_T0,
144 gen_op_movh_EDX_T0,
145 gen_op_movh_EBX_T0,
146 },
147 [OT_WORD] = {
148 gen_op_movw_EAX_T0,
149 gen_op_movw_ECX_T0,
150 gen_op_movw_EDX_T0,
151 gen_op_movw_EBX_T0,
152 gen_op_movw_ESP_T0,
153 gen_op_movw_EBP_T0,
154 gen_op_movw_ESI_T0,
155 gen_op_movw_EDI_T0,
156 },
157 [OT_LONG] = {
158 gen_op_movl_EAX_T0,
159 gen_op_movl_ECX_T0,
160 gen_op_movl_EDX_T0,
161 gen_op_movl_EBX_T0,
162 gen_op_movl_ESP_T0,
163 gen_op_movl_EBP_T0,
164 gen_op_movl_ESI_T0,
165 gen_op_movl_EDI_T0,
166 },
167 };
168
169 static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
170 [OT_BYTE] = {
171 gen_op_movb_EAX_T1,
172 gen_op_movb_ECX_T1,
173 gen_op_movb_EDX_T1,
174 gen_op_movb_EBX_T1,
175 gen_op_movh_EAX_T1,
176 gen_op_movh_ECX_T1,
177 gen_op_movh_EDX_T1,
178 gen_op_movh_EBX_T1,
179 },
180 [OT_WORD] = {
181 gen_op_movw_EAX_T1,
182 gen_op_movw_ECX_T1,
183 gen_op_movw_EDX_T1,
184 gen_op_movw_EBX_T1,
185 gen_op_movw_ESP_T1,
186 gen_op_movw_EBP_T1,
187 gen_op_movw_ESI_T1,
188 gen_op_movw_EDI_T1,
189 },
190 [OT_LONG] = {
191 gen_op_movl_EAX_T1,
192 gen_op_movl_ECX_T1,
193 gen_op_movl_EDX_T1,
194 gen_op_movl_EBX_T1,
195 gen_op_movl_ESP_T1,
196 gen_op_movl_EBP_T1,
197 gen_op_movl_ESI_T1,
198 gen_op_movl_EDI_T1,
199 },
200 };
201
202 static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
203 [0] = {
204 gen_op_movw_EAX_A0,
205 gen_op_movw_ECX_A0,
206 gen_op_movw_EDX_A0,
207 gen_op_movw_EBX_A0,
208 gen_op_movw_ESP_A0,
209 gen_op_movw_EBP_A0,
210 gen_op_movw_ESI_A0,
211 gen_op_movw_EDI_A0,
212 },
213 [1] = {
214 gen_op_movl_EAX_A0,
215 gen_op_movl_ECX_A0,
216 gen_op_movl_EDX_A0,
217 gen_op_movl_EBX_A0,
218 gen_op_movl_ESP_A0,
219 gen_op_movl_EBP_A0,
220 gen_op_movl_ESI_A0,
221 gen_op_movl_EDI_A0,
222 },
223 };
224
225 static GenOpFunc *gen_op_mov_TN_reg[3][2][8] =
226 {
227 [OT_BYTE] = {
228 {
229 gen_op_movl_T0_EAX,
230 gen_op_movl_T0_ECX,
231 gen_op_movl_T0_EDX,
232 gen_op_movl_T0_EBX,
233 gen_op_movh_T0_EAX,
234 gen_op_movh_T0_ECX,
235 gen_op_movh_T0_EDX,
236 gen_op_movh_T0_EBX,
237 },
238 {
239 gen_op_movl_T1_EAX,
240 gen_op_movl_T1_ECX,
241 gen_op_movl_T1_EDX,
242 gen_op_movl_T1_EBX,
243 gen_op_movh_T1_EAX,
244 gen_op_movh_T1_ECX,
245 gen_op_movh_T1_EDX,
246 gen_op_movh_T1_EBX,
247 },
248 },
249 [OT_WORD] = {
250 {
251 gen_op_movl_T0_EAX,
252 gen_op_movl_T0_ECX,
253 gen_op_movl_T0_EDX,
254 gen_op_movl_T0_EBX,
255 gen_op_movl_T0_ESP,
256 gen_op_movl_T0_EBP,
257 gen_op_movl_T0_ESI,
258 gen_op_movl_T0_EDI,
259 },
260 {
261 gen_op_movl_T1_EAX,
262 gen_op_movl_T1_ECX,
263 gen_op_movl_T1_EDX,
264 gen_op_movl_T1_EBX,
265 gen_op_movl_T1_ESP,
266 gen_op_movl_T1_EBP,
267 gen_op_movl_T1_ESI,
268 gen_op_movl_T1_EDI,
269 },
270 },
271 [OT_LONG] = {
272 {
273 gen_op_movl_T0_EAX,
274 gen_op_movl_T0_ECX,
275 gen_op_movl_T0_EDX,
276 gen_op_movl_T0_EBX,
277 gen_op_movl_T0_ESP,
278 gen_op_movl_T0_EBP,
279 gen_op_movl_T0_ESI,
280 gen_op_movl_T0_EDI,
281 },
282 {
283 gen_op_movl_T1_EAX,
284 gen_op_movl_T1_ECX,
285 gen_op_movl_T1_EDX,
286 gen_op_movl_T1_EBX,
287 gen_op_movl_T1_ESP,
288 gen_op_movl_T1_EBP,
289 gen_op_movl_T1_ESI,
290 gen_op_movl_T1_EDI,
291 },
292 },
293 };
294
295 static GenOpFunc *gen_op_movl_A0_reg[8] = {
296 gen_op_movl_A0_EAX,
297 gen_op_movl_A0_ECX,
298 gen_op_movl_A0_EDX,
299 gen_op_movl_A0_EBX,
300 gen_op_movl_A0_ESP,
301 gen_op_movl_A0_EBP,
302 gen_op_movl_A0_ESI,
303 gen_op_movl_A0_EDI,
304 };
305
306 static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
307 [0] = {
308 gen_op_addl_A0_EAX,
309 gen_op_addl_A0_ECX,
310 gen_op_addl_A0_EDX,
311 gen_op_addl_A0_EBX,
312 gen_op_addl_A0_ESP,
313 gen_op_addl_A0_EBP,
314 gen_op_addl_A0_ESI,
315 gen_op_addl_A0_EDI,
316 },
317 [1] = {
318 gen_op_addl_A0_EAX_s1,
319 gen_op_addl_A0_ECX_s1,
320 gen_op_addl_A0_EDX_s1,
321 gen_op_addl_A0_EBX_s1,
322 gen_op_addl_A0_ESP_s1,
323 gen_op_addl_A0_EBP_s1,
324 gen_op_addl_A0_ESI_s1,
325 gen_op_addl_A0_EDI_s1,
326 },
327 [2] = {
328 gen_op_addl_A0_EAX_s2,
329 gen_op_addl_A0_ECX_s2,
330 gen_op_addl_A0_EDX_s2,
331 gen_op_addl_A0_EBX_s2,
332 gen_op_addl_A0_ESP_s2,
333 gen_op_addl_A0_EBP_s2,
334 gen_op_addl_A0_ESI_s2,
335 gen_op_addl_A0_EDI_s2,
336 },
337 [3] = {
338 gen_op_addl_A0_EAX_s3,
339 gen_op_addl_A0_ECX_s3,
340 gen_op_addl_A0_EDX_s3,
341 gen_op_addl_A0_EBX_s3,
342 gen_op_addl_A0_ESP_s3,
343 gen_op_addl_A0_EBP_s3,
344 gen_op_addl_A0_ESI_s3,
345 gen_op_addl_A0_EDI_s3,
346 },
347 };
348
349 static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
350 [0] = {
351 gen_op_cmovw_EAX_T1_T0,
352 gen_op_cmovw_ECX_T1_T0,
353 gen_op_cmovw_EDX_T1_T0,
354 gen_op_cmovw_EBX_T1_T0,
355 gen_op_cmovw_ESP_T1_T0,
356 gen_op_cmovw_EBP_T1_T0,
357 gen_op_cmovw_ESI_T1_T0,
358 gen_op_cmovw_EDI_T1_T0,
359 },
360 [1] = {
361 gen_op_cmovl_EAX_T1_T0,
362 gen_op_cmovl_ECX_T1_T0,
363 gen_op_cmovl_EDX_T1_T0,
364 gen_op_cmovl_EBX_T1_T0,
365 gen_op_cmovl_ESP_T1_T0,
366 gen_op_cmovl_EBP_T1_T0,
367 gen_op_cmovl_ESI_T1_T0,
368 gen_op_cmovl_EDI_T1_T0,
369 },
370 };
371
372 static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
373 NULL,
374 gen_op_orl_T0_T1,
375 NULL,
376 NULL,
377 gen_op_andl_T0_T1,
378 NULL,
379 gen_op_xorl_T0_T1,
380 NULL,
381 };
382
383 static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
384 [OT_BYTE] = {
385 gen_op_adcb_T0_T1_cc,
386 gen_op_sbbb_T0_T1_cc,
387 },
388 [OT_WORD] = {
389 gen_op_adcw_T0_T1_cc,
390 gen_op_sbbw_T0_T1_cc,
391 },
392 [OT_LONG] = {
393 gen_op_adcl_T0_T1_cc,
394 gen_op_sbbl_T0_T1_cc,
395 },
396 };
397
398 static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
399 [OT_BYTE] = {
400 gen_op_adcb_mem_T0_T1_cc,
401 gen_op_sbbb_mem_T0_T1_cc,
402 },
403 [OT_WORD] = {
404 gen_op_adcw_mem_T0_T1_cc,
405 gen_op_sbbw_mem_T0_T1_cc,
406 },
407 [OT_LONG] = {
408 gen_op_adcl_mem_T0_T1_cc,
409 gen_op_sbbl_mem_T0_T1_cc,
410 },
411 };
412
413 static const int cc_op_arithb[8] = {
414 CC_OP_ADDB,
415 CC_OP_LOGICB,
416 CC_OP_ADDB,
417 CC_OP_SUBB,
418 CC_OP_LOGICB,
419 CC_OP_SUBB,
420 CC_OP_LOGICB,
421 CC_OP_SUBB,
422 };
423
424 static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
425 gen_op_cmpxchgb_T0_T1_EAX_cc,
426 gen_op_cmpxchgw_T0_T1_EAX_cc,
427 gen_op_cmpxchgl_T0_T1_EAX_cc,
428 };
429
430 static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
431 gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
432 gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
433 gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
434 };
435
436 static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
437 [OT_BYTE] = {
438 gen_op_rolb_T0_T1_cc,
439 gen_op_rorb_T0_T1_cc,
440 gen_op_rclb_T0_T1_cc,
441 gen_op_rcrb_T0_T1_cc,
442 gen_op_shlb_T0_T1_cc,
443 gen_op_shrb_T0_T1_cc,
444 gen_op_shlb_T0_T1_cc,
445 gen_op_sarb_T0_T1_cc,
446 },
447 [OT_WORD] = {
448 gen_op_rolw_T0_T1_cc,
449 gen_op_rorw_T0_T1_cc,
450 gen_op_rclw_T0_T1_cc,
451 gen_op_rcrw_T0_T1_cc,
452 gen_op_shlw_T0_T1_cc,
453 gen_op_shrw_T0_T1_cc,
454 gen_op_shlw_T0_T1_cc,
455 gen_op_sarw_T0_T1_cc,
456 },
457 [OT_LONG] = {
458 gen_op_roll_T0_T1_cc,
459 gen_op_rorl_T0_T1_cc,
460 gen_op_rcll_T0_T1_cc,
461 gen_op_rcrl_T0_T1_cc,
462 gen_op_shll_T0_T1_cc,
463 gen_op_shrl_T0_T1_cc,
464 gen_op_shll_T0_T1_cc,
465 gen_op_sarl_T0_T1_cc,
466 },
467 };
468
469 static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
470 [OT_BYTE] = {
471 gen_op_rolb_mem_T0_T1_cc,
472 gen_op_rorb_mem_T0_T1_cc,
473 gen_op_rclb_mem_T0_T1_cc,
474 gen_op_rcrb_mem_T0_T1_cc,
475 gen_op_shlb_mem_T0_T1_cc,
476 gen_op_shrb_mem_T0_T1_cc,
477 gen_op_shlb_mem_T0_T1_cc,
478 gen_op_sarb_mem_T0_T1_cc,
479 },
480 [OT_WORD] = {
481 gen_op_rolw_mem_T0_T1_cc,
482 gen_op_rorw_mem_T0_T1_cc,
483 gen_op_rclw_mem_T0_T1_cc,
484 gen_op_rcrw_mem_T0_T1_cc,
485 gen_op_shlw_mem_T0_T1_cc,
486 gen_op_shrw_mem_T0_T1_cc,
487 gen_op_shlw_mem_T0_T1_cc,
488 gen_op_sarw_mem_T0_T1_cc,
489 },
490 [OT_LONG] = {
491 gen_op_roll_mem_T0_T1_cc,
492 gen_op_rorl_mem_T0_T1_cc,
493 gen_op_rcll_mem_T0_T1_cc,
494 gen_op_rcrl_mem_T0_T1_cc,
495 gen_op_shll_mem_T0_T1_cc,
496 gen_op_shrl_mem_T0_T1_cc,
497 gen_op_shll_mem_T0_T1_cc,
498 gen_op_sarl_mem_T0_T1_cc,
499 },
500 };
501
502 static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
503 [0] = {
504 gen_op_shldw_T0_T1_im_cc,
505 gen_op_shrdw_T0_T1_im_cc,
506 },
507 [1] = {
508 gen_op_shldl_T0_T1_im_cc,
509 gen_op_shrdl_T0_T1_im_cc,
510 },
511 };
512
513 static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
514 [0] = {
515 gen_op_shldw_T0_T1_ECX_cc,
516 gen_op_shrdw_T0_T1_ECX_cc,
517 },
518 [1] = {
519 gen_op_shldl_T0_T1_ECX_cc,
520 gen_op_shrdl_T0_T1_ECX_cc,
521 },
522 };
523
524 static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
525 [0] = {
526 gen_op_shldw_mem_T0_T1_im_cc,
527 gen_op_shrdw_mem_T0_T1_im_cc,
528 },
529 [1] = {
530 gen_op_shldl_mem_T0_T1_im_cc,
531 gen_op_shrdl_mem_T0_T1_im_cc,
532 },
533 };
534
535 static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
536 [0] = {
537 gen_op_shldw_mem_T0_T1_ECX_cc,
538 gen_op_shrdw_mem_T0_T1_ECX_cc,
539 },
540 [1] = {
541 gen_op_shldl_mem_T0_T1_ECX_cc,
542 gen_op_shrdl_mem_T0_T1_ECX_cc,
543 },
544 };
545
546 static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
547 [0] = {
548 gen_op_btw_T0_T1_cc,
549 gen_op_btsw_T0_T1_cc,
550 gen_op_btrw_T0_T1_cc,
551 gen_op_btcw_T0_T1_cc,
552 },
553 [1] = {
554 gen_op_btl_T0_T1_cc,
555 gen_op_btsl_T0_T1_cc,
556 gen_op_btrl_T0_T1_cc,
557 gen_op_btcl_T0_T1_cc,
558 },
559 };
560
561 static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
562 [0] = {
563 gen_op_bsfw_T0_cc,
564 gen_op_bsrw_T0_cc,
565 },
566 [1] = {
567 gen_op_bsfl_T0_cc,
568 gen_op_bsrl_T0_cc,
569 },
570 };
571
572 static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
573 gen_op_ldsb_raw_T0_A0,
574 gen_op_ldsw_raw_T0_A0,
575 NULL,
576 #ifndef CONFIG_USER_ONLY
577 gen_op_ldsb_kernel_T0_A0,
578 gen_op_ldsw_kernel_T0_A0,
579 NULL,
580
581 gen_op_ldsb_user_T0_A0,
582 gen_op_ldsw_user_T0_A0,
583 NULL,
584 #endif
585 };
586
587 static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
588 gen_op_ldub_raw_T0_A0,
589 gen_op_lduw_raw_T0_A0,
590 NULL,
591
592 #ifndef CONFIG_USER_ONLY
593 gen_op_ldub_kernel_T0_A0,
594 gen_op_lduw_kernel_T0_A0,
595 NULL,
596
597 gen_op_ldub_user_T0_A0,
598 gen_op_lduw_user_T0_A0,
599 NULL,
600 #endif
601 };
602
603 /* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
604 static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
605 gen_op_ldub_raw_T0_A0,
606 gen_op_lduw_raw_T0_A0,
607 gen_op_ldl_raw_T0_A0,
608
609 #ifndef CONFIG_USER_ONLY
610 gen_op_ldub_kernel_T0_A0,
611 gen_op_lduw_kernel_T0_A0,
612 gen_op_ldl_kernel_T0_A0,
613
614 gen_op_ldub_user_T0_A0,
615 gen_op_lduw_user_T0_A0,
616 gen_op_ldl_user_T0_A0,
617 #endif
618 };
619
620 static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
621 gen_op_ldub_raw_T1_A0,
622 gen_op_lduw_raw_T1_A0,
623 gen_op_ldl_raw_T1_A0,
624
625 #ifndef CONFIG_USER_ONLY
626 gen_op_ldub_kernel_T1_A0,
627 gen_op_lduw_kernel_T1_A0,
628 gen_op_ldl_kernel_T1_A0,
629
630 gen_op_ldub_user_T1_A0,
631 gen_op_lduw_user_T1_A0,
632 gen_op_ldl_user_T1_A0,
633 #endif
634 };
635
636 static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
637 gen_op_stb_raw_T0_A0,
638 gen_op_stw_raw_T0_A0,
639 gen_op_stl_raw_T0_A0,
640
641 #ifndef CONFIG_USER_ONLY
642 gen_op_stb_kernel_T0_A0,
643 gen_op_stw_kernel_T0_A0,
644 gen_op_stl_kernel_T0_A0,
645
646 gen_op_stb_user_T0_A0,
647 gen_op_stw_user_T0_A0,
648 gen_op_stl_user_T0_A0,
649 #endif
650 };
651
652 static inline void gen_string_movl_A0_ESI(DisasContext *s)
653 {
654 int override;
655
656 override = s->override;
657 if (s->aflag) {
658 /* 32 bit address */
659 if (s->addseg && override < 0)
660 override = R_DS;
661 if (override >= 0) {
662 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
663 gen_op_addl_A0_reg_sN[0][R_ESI]();
664 } else {
665 gen_op_movl_A0_reg[R_ESI]();
666 }
667 } else {
668 /* 16 address, always override */
669 if (override < 0)
670 override = R_DS;
671 gen_op_movl_A0_reg[R_ESI]();
672 gen_op_andl_A0_ffff();
673 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
674 }
675 }
676
677 static inline void gen_string_movl_A0_EDI(DisasContext *s)
678 {
679 if (s->aflag) {
680 if (s->addseg) {
681 gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
682 gen_op_addl_A0_reg_sN[0][R_EDI]();
683 } else {
684 gen_op_movl_A0_reg[R_EDI]();
685 }
686 } else {
687 gen_op_movl_A0_reg[R_EDI]();
688 gen_op_andl_A0_ffff();
689 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
690 }
691 }
692
693 static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
694 gen_op_movl_T0_Dshiftb,
695 gen_op_movl_T0_Dshiftw,
696 gen_op_movl_T0_Dshiftl,
697 };
698
699 static GenOpFunc2 *gen_op_jz_ecx[2] = {
700 gen_op_jz_ecxw,
701 gen_op_jz_ecxl,
702 };
703
704 static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
705 gen_op_jz_ecxw_im,
706 gen_op_jz_ecxl_im,
707 };
708
709 static GenOpFunc *gen_op_dec_ECX[2] = {
710 gen_op_decw_ECX,
711 gen_op_decl_ECX,
712 };
713
714 static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
715 {
716 gen_op_string_jnz_subb,
717 gen_op_string_jnz_subw,
718 gen_op_string_jnz_subl,
719 },
720 {
721 gen_op_string_jz_subb,
722 gen_op_string_jz_subw,
723 gen_op_string_jz_subl,
724 },
725 };
726
727 static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
728 {
729 gen_op_string_jnz_subb_im,
730 gen_op_string_jnz_subw_im,
731 gen_op_string_jnz_subl_im,
732 },
733 {
734 gen_op_string_jz_subb_im,
735 gen_op_string_jz_subw_im,
736 gen_op_string_jz_subl_im,
737 },
738 };
739
740 static GenOpFunc *gen_op_in_DX_T0[3] = {
741 gen_op_inb_DX_T0,
742 gen_op_inw_DX_T0,
743 gen_op_inl_DX_T0,
744 };
745
746 static GenOpFunc *gen_op_out_DX_T0[3] = {
747 gen_op_outb_DX_T0,
748 gen_op_outw_DX_T0,
749 gen_op_outl_DX_T0,
750 };
751
752 static GenOpFunc *gen_op_in[3] = {
753 gen_op_inb_T0_T1,
754 gen_op_inw_T0_T1,
755 gen_op_inl_T0_T1,
756 };
757
758 static GenOpFunc *gen_op_out[3] = {
759 gen_op_outb_T0_T1,
760 gen_op_outw_T0_T1,
761 gen_op_outl_T0_T1,
762 };
763
764 static GenOpFunc *gen_check_io_T0[3] = {
765 gen_op_check_iob_T0,
766 gen_op_check_iow_T0,
767 gen_op_check_iol_T0,
768 };
769
770 static GenOpFunc *gen_check_io_DX[3] = {
771 gen_op_check_iob_DX,
772 gen_op_check_iow_DX,
773 gen_op_check_iol_DX,
774 };
775
776 static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
777 {
778 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
779 if (s->cc_op != CC_OP_DYNAMIC)
780 gen_op_set_cc_op(s->cc_op);
781 gen_op_jmp_im(cur_eip);
782 if (use_dx)
783 gen_check_io_DX[ot]();
784 else
785 gen_check_io_T0[ot]();
786 }
787 }
788
789 static inline void gen_movs(DisasContext *s, int ot)
790 {
791 gen_string_movl_A0_ESI(s);
792 gen_op_ld_T0_A0[ot + s->mem_index]();
793 gen_string_movl_A0_EDI(s);
794 gen_op_st_T0_A0[ot + s->mem_index]();
795 gen_op_movl_T0_Dshift[ot]();
796 if (s->aflag) {
797 gen_op_addl_ESI_T0();
798 gen_op_addl_EDI_T0();
799 } else {
800 gen_op_addw_ESI_T0();
801 gen_op_addw_EDI_T0();
802 }
803 }
804
805 static inline void gen_update_cc_op(DisasContext *s)
806 {
807 if (s->cc_op != CC_OP_DYNAMIC) {
808 gen_op_set_cc_op(s->cc_op);
809 s->cc_op = CC_OP_DYNAMIC;
810 }
811 }
812
813 static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
814 {
815 if (s->jmp_opt) {
816 gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
817 } else {
818 /* XXX: does not work with gdbstub "ice" single step - not a
819 serious problem */
820 gen_op_jz_ecx_im[s->aflag](next_eip);
821 }
822 }
823
824 static inline void gen_stos(DisasContext *s, int ot)
825 {
826 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
827 gen_string_movl_A0_EDI(s);
828 gen_op_st_T0_A0[ot + s->mem_index]();
829 gen_op_movl_T0_Dshift[ot]();
830 if (s->aflag) {
831 gen_op_addl_EDI_T0();
832 } else {
833 gen_op_addw_EDI_T0();
834 }
835 }
836
837 static inline void gen_lods(DisasContext *s, int ot)
838 {
839 gen_string_movl_A0_ESI(s);
840 gen_op_ld_T0_A0[ot + s->mem_index]();
841 gen_op_mov_reg_T0[ot][R_EAX]();
842 gen_op_movl_T0_Dshift[ot]();
843 if (s->aflag) {
844 gen_op_addl_ESI_T0();
845 } else {
846 gen_op_addw_ESI_T0();
847 }
848 }
849
850 static inline void gen_scas(DisasContext *s, int ot)
851 {
852 gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
853 gen_string_movl_A0_EDI(s);
854 gen_op_ld_T1_A0[ot + s->mem_index]();
855 gen_op_cmpl_T0_T1_cc();
856 gen_op_movl_T0_Dshift[ot]();
857 if (s->aflag) {
858 gen_op_addl_EDI_T0();
859 } else {
860 gen_op_addw_EDI_T0();
861 }
862 }
863
864 static inline void gen_cmps(DisasContext *s, int ot)
865 {
866 gen_string_movl_A0_ESI(s);
867 gen_op_ld_T0_A0[ot + s->mem_index]();
868 gen_string_movl_A0_EDI(s);
869 gen_op_ld_T1_A0[ot + s->mem_index]();
870 gen_op_cmpl_T0_T1_cc();
871 gen_op_movl_T0_Dshift[ot]();
872 if (s->aflag) {
873 gen_op_addl_ESI_T0();
874 gen_op_addl_EDI_T0();
875 } else {
876 gen_op_addw_ESI_T0();
877 gen_op_addw_EDI_T0();
878 }
879 }
880
881 static inline void gen_ins(DisasContext *s, int ot)
882 {
883 gen_op_in_DX_T0[ot]();
884 gen_string_movl_A0_EDI(s);
885 gen_op_st_T0_A0[ot + s->mem_index]();
886 gen_op_movl_T0_Dshift[ot]();
887 if (s->aflag) {
888 gen_op_addl_EDI_T0();
889 } else {
890 gen_op_addw_EDI_T0();
891 }
892 }
893
894 static inline void gen_outs(DisasContext *s, int ot)
895 {
896 gen_string_movl_A0_ESI(s);
897 gen_op_ld_T0_A0[ot + s->mem_index]();
898 gen_op_out_DX_T0[ot]();
899 gen_op_movl_T0_Dshift[ot]();
900 if (s->aflag) {
901 gen_op_addl_ESI_T0();
902 } else {
903 gen_op_addw_ESI_T0();
904 }
905 }
906
907 /* same method as Valgrind : we generate jumps to current or next
908 instruction */
909 #define GEN_REPZ(op) \
910 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
911 unsigned int cur_eip, unsigned int next_eip) \
912 { \
913 gen_update_cc_op(s); \
914 gen_jz_ecx_string(s, next_eip); \
915 gen_ ## op(s, ot); \
916 gen_op_dec_ECX[s->aflag](); \
917 /* a loop would cause two single step exceptions if ECX = 1 \
918 before rep string_insn */ \
919 if (!s->jmp_opt) \
920 gen_op_jz_ecx_im[s->aflag](next_eip); \
921 gen_jmp(s, cur_eip); \
922 }
923
924 #define GEN_REPZ2(op) \
925 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
926 unsigned int cur_eip, \
927 unsigned int next_eip, \
928 int nz) \
929 { \
930 gen_update_cc_op(s); \
931 gen_jz_ecx_string(s, next_eip); \
932 gen_ ## op(s, ot); \
933 gen_op_dec_ECX[s->aflag](); \
934 gen_op_set_cc_op(CC_OP_SUBB + ot); \
935 if (!s->jmp_opt) \
936 gen_op_string_jnz_sub_im[nz][ot](next_eip); \
937 else \
938 gen_op_string_jnz_sub[nz][ot]((long)s->tb); \
939 if (!s->jmp_opt) \
940 gen_op_jz_ecx_im[s->aflag](next_eip); \
941 gen_jmp(s, cur_eip); \
942 }
943
944 GEN_REPZ(movs)
945 GEN_REPZ(stos)
946 GEN_REPZ(lods)
947 GEN_REPZ(ins)
948 GEN_REPZ(outs)
949 GEN_REPZ2(scas)
950 GEN_REPZ2(cmps)
951
952 enum {
953 JCC_O,
954 JCC_B,
955 JCC_Z,
956 JCC_BE,
957 JCC_S,
958 JCC_P,
959 JCC_L,
960 JCC_LE,
961 };
962
963 static GenOpFunc3 *gen_jcc_sub[3][8] = {
964 [OT_BYTE] = {
965 NULL,
966 gen_op_jb_subb,
967 gen_op_jz_subb,
968 gen_op_jbe_subb,
969 gen_op_js_subb,
970 NULL,
971 gen_op_jl_subb,
972 gen_op_jle_subb,
973 },
974 [OT_WORD] = {
975 NULL,
976 gen_op_jb_subw,
977 gen_op_jz_subw,
978 gen_op_jbe_subw,
979 gen_op_js_subw,
980 NULL,
981 gen_op_jl_subw,
982 gen_op_jle_subw,
983 },
984 [OT_LONG] = {
985 NULL,
986 gen_op_jb_subl,
987 gen_op_jz_subl,
988 gen_op_jbe_subl,
989 gen_op_js_subl,
990 NULL,
991 gen_op_jl_subl,
992 gen_op_jle_subl,
993 },
994 };
995 static GenOpFunc2 *gen_op_loop[2][4] = {
996 [0] = {
997 gen_op_loopnzw,
998 gen_op_loopzw,
999 gen_op_loopw,
1000 gen_op_jecxzw,
1001 },
1002 [1] = {
1003 gen_op_loopnzl,
1004 gen_op_loopzl,
1005 gen_op_loopl,
1006 gen_op_jecxzl,
1007 },
1008 };
1009
1010 static GenOpFunc *gen_setcc_slow[8] = {
1011 gen_op_seto_T0_cc,
1012 gen_op_setb_T0_cc,
1013 gen_op_setz_T0_cc,
1014 gen_op_setbe_T0_cc,
1015 gen_op_sets_T0_cc,
1016 gen_op_setp_T0_cc,
1017 gen_op_setl_T0_cc,
1018 gen_op_setle_T0_cc,
1019 };
1020
1021 static GenOpFunc *gen_setcc_sub[3][8] = {
1022 [OT_BYTE] = {
1023 NULL,
1024 gen_op_setb_T0_subb,
1025 gen_op_setz_T0_subb,
1026 gen_op_setbe_T0_subb,
1027 gen_op_sets_T0_subb,
1028 NULL,
1029 gen_op_setl_T0_subb,
1030 gen_op_setle_T0_subb,
1031 },
1032 [OT_WORD] = {
1033 NULL,
1034 gen_op_setb_T0_subw,
1035 gen_op_setz_T0_subw,
1036 gen_op_setbe_T0_subw,
1037 gen_op_sets_T0_subw,
1038 NULL,
1039 gen_op_setl_T0_subw,
1040 gen_op_setle_T0_subw,
1041 },
1042 [OT_LONG] = {
1043 NULL,
1044 gen_op_setb_T0_subl,
1045 gen_op_setz_T0_subl,
1046 gen_op_setbe_T0_subl,
1047 gen_op_sets_T0_subl,
1048 NULL,
1049 gen_op_setl_T0_subl,
1050 gen_op_setle_T0_subl,
1051 },
1052 };
1053
1054 static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1055 gen_op_fadd_ST0_FT0,
1056 gen_op_fmul_ST0_FT0,
1057 gen_op_fcom_ST0_FT0,
1058 gen_op_fcom_ST0_FT0,
1059 gen_op_fsub_ST0_FT0,
1060 gen_op_fsubr_ST0_FT0,
1061 gen_op_fdiv_ST0_FT0,
1062 gen_op_fdivr_ST0_FT0,
1063 };
1064
1065 /* NOTE the exception in "r" op ordering */
1066 static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1067 gen_op_fadd_STN_ST0,
1068 gen_op_fmul_STN_ST0,
1069 NULL,
1070 NULL,
1071 gen_op_fsubr_STN_ST0,
1072 gen_op_fsub_STN_ST0,
1073 gen_op_fdivr_STN_ST0,
1074 gen_op_fdiv_STN_ST0,
1075 };
1076
1077 /* if d == OR_TMP0, it means memory operand (address in A0) */
1078 static void gen_op(DisasContext *s1, int op, int ot, int d)
1079 {
1080 GenOpFunc *gen_update_cc;
1081
1082 if (d != OR_TMP0) {
1083 gen_op_mov_TN_reg[ot][0][d]();
1084 } else {
1085 gen_op_ld_T0_A0[ot + s1->mem_index]();
1086 }
1087 switch(op) {
1088 case OP_ADCL:
1089 case OP_SBBL:
1090 if (s1->cc_op != CC_OP_DYNAMIC)
1091 gen_op_set_cc_op(s1->cc_op);
1092 if (d != OR_TMP0) {
1093 gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1094 gen_op_mov_reg_T0[ot][d]();
1095 } else {
1096 gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
1097 }
1098 s1->cc_op = CC_OP_DYNAMIC;
1099 goto the_end;
1100 case OP_ADDL:
1101 gen_op_addl_T0_T1();
1102 s1->cc_op = CC_OP_ADDB + ot;
1103 gen_update_cc = gen_op_update2_cc;
1104 break;
1105 case OP_SUBL:
1106 gen_op_subl_T0_T1();
1107 s1->cc_op = CC_OP_SUBB + ot;
1108 gen_update_cc = gen_op_update2_cc;
1109 break;
1110 default:
1111 case OP_ANDL:
1112 case OP_ORL:
1113 case OP_XORL:
1114 gen_op_arith_T0_T1_cc[op]();
1115 s1->cc_op = CC_OP_LOGICB + ot;
1116 gen_update_cc = gen_op_update1_cc;
1117 break;
1118 case OP_CMPL:
1119 gen_op_cmpl_T0_T1_cc();
1120 s1->cc_op = CC_OP_SUBB + ot;
1121 gen_update_cc = NULL;
1122 break;
1123 }
1124 if (op != OP_CMPL) {
1125 if (d != OR_TMP0)
1126 gen_op_mov_reg_T0[ot][d]();
1127 else
1128 gen_op_st_T0_A0[ot + s1->mem_index]();
1129 }
1130 /* the flags update must happen after the memory write (precise
1131 exception support) */
1132 if (gen_update_cc)
1133 gen_update_cc();
1134 the_end: ;
1135 }
1136
1137 /* if d == OR_TMP0, it means memory operand (address in A0) */
1138 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1139 {
1140 if (d != OR_TMP0)
1141 gen_op_mov_TN_reg[ot][0][d]();
1142 else
1143 gen_op_ld_T0_A0[ot + s1->mem_index]();
1144 if (s1->cc_op != CC_OP_DYNAMIC)
1145 gen_op_set_cc_op(s1->cc_op);
1146 if (c > 0) {
1147 gen_op_incl_T0();
1148 s1->cc_op = CC_OP_INCB + ot;
1149 } else {
1150 gen_op_decl_T0();
1151 s1->cc_op = CC_OP_DECB + ot;
1152 }
1153 if (d != OR_TMP0)
1154 gen_op_mov_reg_T0[ot][d]();
1155 else
1156 gen_op_st_T0_A0[ot + s1->mem_index]();
1157 gen_op_update_inc_cc();
1158 }
1159
1160 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1161 {
1162 if (d != OR_TMP0)
1163 gen_op_mov_TN_reg[ot][0][d]();
1164 else
1165 gen_op_ld_T0_A0[ot + s1->mem_index]();
1166 if (s != OR_TMP1)
1167 gen_op_mov_TN_reg[ot][1][s]();
1168 /* for zero counts, flags are not updated, so must do it dynamically */
1169 if (s1->cc_op != CC_OP_DYNAMIC)
1170 gen_op_set_cc_op(s1->cc_op);
1171
1172 if (d != OR_TMP0)
1173 gen_op_shift_T0_T1_cc[ot][op]();
1174 else
1175 gen_op_shift_mem_T0_T1_cc[ot][op]();
1176 if (d != OR_TMP0)
1177 gen_op_mov_reg_T0[ot][d]();
1178 s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1179 }
1180
1181 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1182 {
1183 /* currently not optimized */
1184 gen_op_movl_T1_im(c);
1185 gen_shift(s1, op, ot, d, OR_TMP1);
1186 }
1187
1188 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1189 {
1190 int havesib;
1191 int base, disp;
1192 int index;
1193 int scale;
1194 int opreg;
1195 int mod, rm, code, override, must_add_seg;
1196
1197 override = s->override;
1198 must_add_seg = s->addseg;
1199 if (override >= 0)
1200 must_add_seg = 1;
1201 mod = (modrm >> 6) & 3;
1202 rm = modrm & 7;
1203
1204 if (s->aflag) {
1205
1206 havesib = 0;
1207 base = rm;
1208 index = 0;
1209 scale = 0;
1210
1211 if (base == 4) {
1212 havesib = 1;
1213 code = ldub_code(s->pc++);
1214 scale = (code >> 6) & 3;
1215 index = (code >> 3) & 7;
1216 base = code & 7;
1217 }
1218
1219 switch (mod) {
1220 case 0:
1221 if (base == 5) {
1222 base = -1;
1223 disp = ldl_code(s->pc);
1224 s->pc += 4;
1225 } else {
1226 disp = 0;
1227 }
1228 break;
1229 case 1:
1230 disp = (int8_t)ldub_code(s->pc++);
1231 break;
1232 default:
1233 case 2:
1234 disp = ldl_code(s->pc);
1235 s->pc += 4;
1236 break;
1237 }
1238
1239 if (base >= 0) {
1240 /* for correct popl handling with esp */
1241 if (base == 4 && s->popl_esp_hack)
1242 disp += s->popl_esp_hack;
1243 gen_op_movl_A0_reg[base]();
1244 if (disp != 0)
1245 gen_op_addl_A0_im(disp);
1246 } else {
1247 gen_op_movl_A0_im(disp);
1248 }
1249 /* XXX: index == 4 is always invalid */
1250 if (havesib && (index != 4 || scale != 0)) {
1251 gen_op_addl_A0_reg_sN[scale][index]();
1252 }
1253 if (must_add_seg) {
1254 if (override < 0) {
1255 if (base == R_EBP || base == R_ESP)
1256 override = R_SS;
1257 else
1258 override = R_DS;
1259 }
1260 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1261 }
1262 } else {
1263 switch (mod) {
1264 case 0:
1265 if (rm == 6) {
1266 disp = lduw_code(s->pc);
1267 s->pc += 2;
1268 gen_op_movl_A0_im(disp);
1269 rm = 0; /* avoid SS override */
1270 goto no_rm;
1271 } else {
1272 disp = 0;
1273 }
1274 break;
1275 case 1:
1276 disp = (int8_t)ldub_code(s->pc++);
1277 break;
1278 default:
1279 case 2:
1280 disp = lduw_code(s->pc);
1281 s->pc += 2;
1282 break;
1283 }
1284 switch(rm) {
1285 case 0:
1286 gen_op_movl_A0_reg[R_EBX]();
1287 gen_op_addl_A0_reg_sN[0][R_ESI]();
1288 break;
1289 case 1:
1290 gen_op_movl_A0_reg[R_EBX]();
1291 gen_op_addl_A0_reg_sN[0][R_EDI]();
1292 break;
1293 case 2:
1294 gen_op_movl_A0_reg[R_EBP]();
1295 gen_op_addl_A0_reg_sN[0][R_ESI]();
1296 break;
1297 case 3:
1298 gen_op_movl_A0_reg[R_EBP]();
1299 gen_op_addl_A0_reg_sN[0][R_EDI]();
1300 break;
1301 case 4:
1302 gen_op_movl_A0_reg[R_ESI]();
1303 break;
1304 case 5:
1305 gen_op_movl_A0_reg[R_EDI]();
1306 break;
1307 case 6:
1308 gen_op_movl_A0_reg[R_EBP]();
1309 break;
1310 default:
1311 case 7:
1312 gen_op_movl_A0_reg[R_EBX]();
1313 break;
1314 }
1315 if (disp != 0)
1316 gen_op_addl_A0_im(disp);
1317 gen_op_andl_A0_ffff();
1318 no_rm:
1319 if (must_add_seg) {
1320 if (override < 0) {
1321 if (rm == 2 || rm == 3 || rm == 6)
1322 override = R_SS;
1323 else
1324 override = R_DS;
1325 }
1326 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1327 }
1328 }
1329
1330 opreg = OR_A0;
1331 disp = 0;
1332 *reg_ptr = opreg;
1333 *offset_ptr = disp;
1334 }
1335
1336 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1337 OR_TMP0 */
1338 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1339 {
1340 int mod, rm, opreg, disp;
1341
1342 mod = (modrm >> 6) & 3;
1343 rm = modrm & 7;
1344 if (mod == 3) {
1345 if (is_store) {
1346 if (reg != OR_TMP0)
1347 gen_op_mov_TN_reg[ot][0][reg]();
1348 gen_op_mov_reg_T0[ot][rm]();
1349 } else {
1350 gen_op_mov_TN_reg[ot][0][rm]();
1351 if (reg != OR_TMP0)
1352 gen_op_mov_reg_T0[ot][reg]();
1353 }
1354 } else {
1355 gen_lea_modrm(s, modrm, &opreg, &disp);
1356 if (is_store) {
1357 if (reg != OR_TMP0)
1358 gen_op_mov_TN_reg[ot][0][reg]();
1359 gen_op_st_T0_A0[ot + s->mem_index]();
1360 } else {
1361 gen_op_ld_T0_A0[ot + s->mem_index]();
1362 if (reg != OR_TMP0)
1363 gen_op_mov_reg_T0[ot][reg]();
1364 }
1365 }
1366 }
1367
1368 static inline uint32_t insn_get(DisasContext *s, int ot)
1369 {
1370 uint32_t ret;
1371
1372 switch(ot) {
1373 case OT_BYTE:
1374 ret = ldub_code(s->pc);
1375 s->pc++;
1376 break;
1377 case OT_WORD:
1378 ret = lduw_code(s->pc);
1379 s->pc += 2;
1380 break;
1381 default:
1382 case OT_LONG:
1383 ret = ldl_code(s->pc);
1384 s->pc += 4;
1385 break;
1386 }
1387 return ret;
1388 }
1389
1390 static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1391 {
1392 TranslationBlock *tb;
1393 int inv, jcc_op;
1394 GenOpFunc3 *func;
1395
1396 inv = b & 1;
1397 jcc_op = (b >> 1) & 7;
1398
1399 if (s->jmp_opt) {
1400 switch(s->cc_op) {
1401 /* we optimize the cmp/jcc case */
1402 case CC_OP_SUBB:
1403 case CC_OP_SUBW:
1404 case CC_OP_SUBL:
1405 func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1406 break;
1407
1408 /* some jumps are easy to compute */
1409 case CC_OP_ADDB:
1410 case CC_OP_ADDW:
1411 case CC_OP_ADDL:
1412 case CC_OP_ADCB:
1413 case CC_OP_ADCW:
1414 case CC_OP_ADCL:
1415 case CC_OP_SBBB:
1416 case CC_OP_SBBW:
1417 case CC_OP_SBBL:
1418 case CC_OP_LOGICB:
1419 case CC_OP_LOGICW:
1420 case CC_OP_LOGICL:
1421 case CC_OP_INCB:
1422 case CC_OP_INCW:
1423 case CC_OP_INCL:
1424 case CC_OP_DECB:
1425 case CC_OP_DECW:
1426 case CC_OP_DECL:
1427 case CC_OP_SHLB:
1428 case CC_OP_SHLW:
1429 case CC_OP_SHLL:
1430 case CC_OP_SARB:
1431 case CC_OP_SARW:
1432 case CC_OP_SARL:
1433 switch(jcc_op) {
1434 case JCC_Z:
1435 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1436 break;
1437 case JCC_S:
1438 func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1439 break;
1440 default:
1441 func = NULL;
1442 break;
1443 }
1444 break;
1445 default:
1446 func = NULL;
1447 break;
1448 }
1449
1450 if (s->cc_op != CC_OP_DYNAMIC)
1451 gen_op_set_cc_op(s->cc_op);
1452
1453 if (!func) {
1454 gen_setcc_slow[jcc_op]();
1455 func = gen_op_jcc;
1456 }
1457
1458 tb = s->tb;
1459 if (!inv) {
1460 func((long)tb, val, next_eip);
1461 } else {
1462 func((long)tb, next_eip, val);
1463 }
1464 s->is_jmp = 3;
1465 } else {
1466 if (s->cc_op != CC_OP_DYNAMIC) {
1467 gen_op_set_cc_op(s->cc_op);
1468 s->cc_op = CC_OP_DYNAMIC;
1469 }
1470 gen_setcc_slow[jcc_op]();
1471 if (!inv) {
1472 gen_op_jcc_im(val, next_eip);
1473 } else {
1474 gen_op_jcc_im(next_eip, val);
1475 }
1476 gen_eob(s);
1477 }
1478 }
1479
1480 static void gen_setcc(DisasContext *s, int b)
1481 {
1482 int inv, jcc_op;
1483 GenOpFunc *func;
1484
1485 inv = b & 1;
1486 jcc_op = (b >> 1) & 7;
1487 switch(s->cc_op) {
1488 /* we optimize the cmp/jcc case */
1489 case CC_OP_SUBB:
1490 case CC_OP_SUBW:
1491 case CC_OP_SUBL:
1492 func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1493 if (!func)
1494 goto slow_jcc;
1495 break;
1496
1497 /* some jumps are easy to compute */
1498 case CC_OP_ADDB:
1499 case CC_OP_ADDW:
1500 case CC_OP_ADDL:
1501 case CC_OP_LOGICB:
1502 case CC_OP_LOGICW:
1503 case CC_OP_LOGICL:
1504 case CC_OP_INCB:
1505 case CC_OP_INCW:
1506 case CC_OP_INCL:
1507 case CC_OP_DECB:
1508 case CC_OP_DECW:
1509 case CC_OP_DECL:
1510 case CC_OP_SHLB:
1511 case CC_OP_SHLW:
1512 case CC_OP_SHLL:
1513 switch(jcc_op) {
1514 case JCC_Z:
1515 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1516 break;
1517 case JCC_S:
1518 func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1519 break;
1520 default:
1521 goto slow_jcc;
1522 }
1523 break;
1524 default:
1525 slow_jcc:
1526 if (s->cc_op != CC_OP_DYNAMIC)
1527 gen_op_set_cc_op(s->cc_op);
1528 func = gen_setcc_slow[jcc_op];
1529 break;
1530 }
1531 func();
1532 if (inv) {
1533 gen_op_xor_T0_1();
1534 }
1535 }
1536
1537 /* move T0 to seg_reg and compute if the CPU state may change. Never
1538 call this function with seg_reg == R_CS */
1539 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1540 {
1541 if (s->pe && !s->vm86)
1542 gen_op_movl_seg_T0(seg_reg, cur_eip);
1543 else
1544 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1545 /* abort translation because the register may have a non zero base
1546 or because ss32 may change. For R_SS, translation must always
1547 stop as a special handling must be done to disable hardware
1548 interrupts for the next instruction */
1549 if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1550 s->is_jmp = 3;
1551 }
1552
1553 /* generate a push. It depends on ss32, addseg and dflag */
1554 static void gen_push_T0(DisasContext *s)
1555 {
1556 if (s->ss32) {
1557 if (!s->addseg) {
1558 if (s->dflag)
1559 gen_op_pushl_T0();
1560 else
1561 gen_op_pushw_T0();
1562 } else {
1563 if (s->dflag)
1564 gen_op_pushl_ss32_T0();
1565 else
1566 gen_op_pushw_ss32_T0();
1567 }
1568 } else {
1569 if (s->dflag)
1570 gen_op_pushl_ss16_T0();
1571 else
1572 gen_op_pushw_ss16_T0();
1573 }
1574 }
1575
1576 /* two step pop is necessary for precise exceptions */
1577 static void gen_pop_T0(DisasContext *s)
1578 {
1579 if (s->ss32) {
1580 if (!s->addseg) {
1581 if (s->dflag)
1582 gen_op_popl_T0();
1583 else
1584 gen_op_popw_T0();
1585 } else {
1586 if (s->dflag)
1587 gen_op_popl_ss32_T0();
1588 else
1589 gen_op_popw_ss32_T0();
1590 }
1591 } else {
1592 if (s->dflag)
1593 gen_op_popl_ss16_T0();
1594 else
1595 gen_op_popw_ss16_T0();
1596 }
1597 }
1598
1599 static inline void gen_stack_update(DisasContext *s, int addend)
1600 {
1601 if (s->ss32) {
1602 if (addend == 2)
1603 gen_op_addl_ESP_2();
1604 else if (addend == 4)
1605 gen_op_addl_ESP_4();
1606 else
1607 gen_op_addl_ESP_im(addend);
1608 } else {
1609 if (addend == 2)
1610 gen_op_addw_ESP_2();
1611 else if (addend == 4)
1612 gen_op_addw_ESP_4();
1613 else
1614 gen_op_addw_ESP_im(addend);
1615 }
1616 }
1617
1618 static void gen_pop_update(DisasContext *s)
1619 {
1620 gen_stack_update(s, 2 << s->dflag);
1621 }
1622
1623 static void gen_stack_A0(DisasContext *s)
1624 {
1625 gen_op_movl_A0_ESP();
1626 if (!s->ss32)
1627 gen_op_andl_A0_ffff();
1628 gen_op_movl_T1_A0();
1629 if (s->addseg)
1630 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1631 }
1632
1633 /* NOTE: wrap around in 16 bit not fully handled */
1634 static void gen_pusha(DisasContext *s)
1635 {
1636 int i;
1637 gen_op_movl_A0_ESP();
1638 gen_op_addl_A0_im(-16 << s->dflag);
1639 if (!s->ss32)
1640 gen_op_andl_A0_ffff();
1641 gen_op_movl_T1_A0();
1642 if (s->addseg)
1643 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1644 for(i = 0;i < 8; i++) {
1645 gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1646 gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1647 gen_op_addl_A0_im(2 << s->dflag);
1648 }
1649 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1650 }
1651
1652 /* NOTE: wrap around in 16 bit not fully handled */
1653 static void gen_popa(DisasContext *s)
1654 {
1655 int i;
1656 gen_op_movl_A0_ESP();
1657 if (!s->ss32)
1658 gen_op_andl_A0_ffff();
1659 gen_op_movl_T1_A0();
1660 gen_op_addl_T1_im(16 << s->dflag);
1661 if (s->addseg)
1662 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1663 for(i = 0;i < 8; i++) {
1664 /* ESP is not reloaded */
1665 if (i != 3) {
1666 gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1667 gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1668 }
1669 gen_op_addl_A0_im(2 << s->dflag);
1670 }
1671 gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1672 }
1673
1674 /* NOTE: wrap around in 16 bit not fully handled */
1675 /* XXX: check this */
1676 static void gen_enter(DisasContext *s, int esp_addend, int level)
1677 {
1678 int ot, level1, addend, opsize;
1679
1680 ot = s->dflag + OT_WORD;
1681 level &= 0x1f;
1682 level1 = level;
1683 opsize = 2 << s->dflag;
1684
1685 gen_op_movl_A0_ESP();
1686 gen_op_addl_A0_im(-opsize);
1687 if (!s->ss32)
1688 gen_op_andl_A0_ffff();
1689 gen_op_movl_T1_A0();
1690 if (s->addseg)
1691 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1692 /* push bp */
1693 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1694 gen_op_st_T0_A0[ot + s->mem_index]();
1695 if (level) {
1696 while (level--) {
1697 gen_op_addl_A0_im(-opsize);
1698 gen_op_addl_T0_im(-opsize);
1699 gen_op_st_T0_A0[ot + s->mem_index]();
1700 }
1701 gen_op_addl_A0_im(-opsize);
1702 /* XXX: add st_T1_A0 ? */
1703 gen_op_movl_T0_T1();
1704 gen_op_st_T0_A0[ot + s->mem_index]();
1705 }
1706 gen_op_mov_reg_T1[ot][R_EBP]();
1707 addend = -esp_addend;
1708 if (level1)
1709 addend -= opsize * (level1 + 1);
1710 gen_op_addl_T1_im(addend);
1711 gen_op_mov_reg_T1[ot][R_ESP]();
1712 }
1713
1714 static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1715 {
1716 if (s->cc_op != CC_OP_DYNAMIC)
1717 gen_op_set_cc_op(s->cc_op);
1718 gen_op_jmp_im(cur_eip);
1719 gen_op_raise_exception(trapno);
1720 s->is_jmp = 3;
1721 }
1722
1723 /* an interrupt is different from an exception because of the
1724 priviledge checks */
1725 static void gen_interrupt(DisasContext *s, int intno,
1726 unsigned int cur_eip, unsigned int next_eip)
1727 {
1728 if (s->cc_op != CC_OP_DYNAMIC)
1729 gen_op_set_cc_op(s->cc_op);
1730 gen_op_jmp_im(cur_eip);
1731 gen_op_raise_interrupt(intno, next_eip);
1732 s->is_jmp = 3;
1733 }
1734
1735 static void gen_debug(DisasContext *s, unsigned int cur_eip)
1736 {
1737 if (s->cc_op != CC_OP_DYNAMIC)
1738 gen_op_set_cc_op(s->cc_op);
1739 gen_op_jmp_im(cur_eip);
1740 gen_op_debug();
1741 s->is_jmp = 3;
1742 }
1743
1744 /* generate a generic end of block. Trace exception is also generated
1745 if needed */
1746 static void gen_eob(DisasContext *s)
1747 {
1748 if (s->cc_op != CC_OP_DYNAMIC)
1749 gen_op_set_cc_op(s->cc_op);
1750 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1751 gen_op_reset_inhibit_irq();
1752 }
1753 if (s->singlestep_enabled) {
1754 gen_op_debug();
1755 } else if (s->tf) {
1756 gen_op_raise_exception(EXCP01_SSTP);
1757 } else {
1758 gen_op_movl_T0_0();
1759 gen_op_exit_tb();
1760 }
1761 s->is_jmp = 3;
1762 }
1763
1764 /* generate a jump to eip. No segment change must happen before as a
1765 direct call to the next block may occur */
1766 static void gen_jmp(DisasContext *s, unsigned int eip)
1767 {
1768 TranslationBlock *tb = s->tb;
1769
1770 if (s->jmp_opt) {
1771 if (s->cc_op != CC_OP_DYNAMIC)
1772 gen_op_set_cc_op(s->cc_op);
1773 gen_op_jmp((long)tb, eip);
1774 s->is_jmp = 3;
1775 } else {
1776 gen_op_jmp_im(eip);
1777 gen_eob(s);
1778 }
1779 }
1780
1781 /* convert one instruction. s->is_jmp is set if the translation must
1782 be stopped. Return the next pc value */
1783 static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1784 {
1785 int b, prefixes, aflag, dflag;
1786 int shift, ot;
1787 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1788 unsigned int next_eip;
1789
1790 s->pc = pc_start;
1791 prefixes = 0;
1792 aflag = s->code32;
1793 dflag = s->code32;
1794 s->override = -1;
1795 next_byte:
1796 b = ldub_code(s->pc);
1797 s->pc++;
1798 /* check prefixes */
1799 switch (b) {
1800 case 0xf3:
1801 prefixes |= PREFIX_REPZ;
1802 goto next_byte;
1803 case 0xf2:
1804 prefixes |= PREFIX_REPNZ;
1805 goto next_byte;
1806 case 0xf0:
1807 prefixes |= PREFIX_LOCK;
1808 goto next_byte;
1809 case 0x2e:
1810 s->override = R_CS;
1811 goto next_byte;
1812 case 0x36:
1813 s->override = R_SS;
1814 goto next_byte;
1815 case 0x3e:
1816 s->override = R_DS;
1817 goto next_byte;
1818 case 0x26:
1819 s->override = R_ES;
1820 goto next_byte;
1821 case 0x64:
1822 s->override = R_FS;
1823 goto next_byte;
1824 case 0x65:
1825 s->override = R_GS;
1826 goto next_byte;
1827 case 0x66:
1828 prefixes |= PREFIX_DATA;
1829 goto next_byte;
1830 case 0x67:
1831 prefixes |= PREFIX_ADR;
1832 goto next_byte;
1833 }
1834
1835 if (prefixes & PREFIX_DATA)
1836 dflag ^= 1;
1837 if (prefixes & PREFIX_ADR)
1838 aflag ^= 1;
1839
1840 s->prefix = prefixes;
1841 s->aflag = aflag;
1842 s->dflag = dflag;
1843
1844 /* lock generation */
1845 if (prefixes & PREFIX_LOCK)
1846 gen_op_lock();
1847
1848 /* now check op code */
1849 reswitch:
1850 switch(b) {
1851 case 0x0f:
1852 /**************************/
1853 /* extended op code */
1854 b = ldub_code(s->pc++) | 0x100;
1855 goto reswitch;
1856
1857 /**************************/
1858 /* arith & logic */
1859 case 0x00 ... 0x05:
1860 case 0x08 ... 0x0d:
1861 case 0x10 ... 0x15:
1862 case 0x18 ... 0x1d:
1863 case 0x20 ... 0x25:
1864 case 0x28 ... 0x2d:
1865 case 0x30 ... 0x35:
1866 case 0x38 ... 0x3d:
1867 {
1868 int op, f, val;
1869 op = (b >> 3) & 7;
1870 f = (b >> 1) & 3;
1871
1872 if ((b & 1) == 0)
1873 ot = OT_BYTE;
1874 else
1875 ot = dflag ? OT_LONG : OT_WORD;
1876
1877 switch(f) {
1878 case 0: /* OP Ev, Gv */
1879 modrm = ldub_code(s->pc++);
1880 reg = ((modrm >> 3) & 7);
1881 mod = (modrm >> 6) & 3;
1882 rm = modrm & 7;
1883 if (mod != 3) {
1884 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1885 opreg = OR_TMP0;
1886 } else if (op == OP_XORL && rm == reg) {
1887 xor_zero:
1888 /* xor reg, reg optimisation */
1889 gen_op_movl_T0_0();
1890 s->cc_op = CC_OP_LOGICB + ot;
1891 gen_op_mov_reg_T0[ot][reg]();
1892 gen_op_update1_cc();
1893 break;
1894 } else {
1895 opreg = rm;
1896 }
1897 gen_op_mov_TN_reg[ot][1][reg]();
1898 gen_op(s, op, ot, opreg);
1899 break;
1900 case 1: /* OP Gv, Ev */
1901 modrm = ldub_code(s->pc++);
1902 mod = (modrm >> 6) & 3;
1903 reg = ((modrm >> 3) & 7);
1904 rm = modrm & 7;
1905 if (mod != 3) {
1906 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1907 gen_op_ld_T1_A0[ot + s->mem_index]();
1908 } else if (op == OP_XORL && rm == reg) {
1909 goto xor_zero;
1910 } else {
1911 gen_op_mov_TN_reg[ot][1][rm]();
1912 }
1913 gen_op(s, op, ot, reg);
1914 break;
1915 case 2: /* OP A, Iv */
1916 val = insn_get(s, ot);
1917 gen_op_movl_T1_im(val);
1918 gen_op(s, op, ot, OR_EAX);
1919 break;
1920 }
1921 }
1922 break;
1923
1924 case 0x80: /* GRP1 */
1925 case 0x81:
1926 case 0x83:
1927 {
1928 int val;
1929
1930 if ((b & 1) == 0)
1931 ot = OT_BYTE;
1932 else
1933 ot = dflag ? OT_LONG : OT_WORD;
1934
1935 modrm = ldub_code(s->pc++);
1936 mod = (modrm >> 6) & 3;
1937 rm = modrm & 7;
1938 op = (modrm >> 3) & 7;
1939
1940 if (mod != 3) {
1941 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1942 opreg = OR_TMP0;
1943 } else {
1944 opreg = rm + OR_EAX;
1945 }
1946
1947 switch(b) {
1948 default:
1949 case 0x80:
1950 case 0x81:
1951 val = insn_get(s, ot);
1952 break;
1953 case 0x83:
1954 val = (int8_t)insn_get(s, OT_BYTE);
1955 break;
1956 }
1957 gen_op_movl_T1_im(val);
1958 gen_op(s, op, ot, opreg);
1959 }
1960 break;
1961
1962 /**************************/
1963 /* inc, dec, and other misc arith */
1964 case 0x40 ... 0x47: /* inc Gv */
1965 ot = dflag ? OT_LONG : OT_WORD;
1966 gen_inc(s, ot, OR_EAX + (b & 7), 1);
1967 break;
1968 case 0x48 ... 0x4f: /* dec Gv */
1969 ot = dflag ? OT_LONG : OT_WORD;
1970 gen_inc(s, ot, OR_EAX + (b & 7), -1);
1971 break;
1972 case 0xf6: /* GRP3 */
1973 case 0xf7:
1974 if ((b & 1) == 0)
1975 ot = OT_BYTE;
1976 else
1977 ot = dflag ? OT_LONG : OT_WORD;
1978
1979 modrm = ldub_code(s->pc++);
1980 mod = (modrm >> 6) & 3;
1981 rm = modrm & 7;
1982 op = (modrm >> 3) & 7;
1983 if (mod != 3) {
1984 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1985 gen_op_ld_T0_A0[ot + s->mem_index]();
1986 } else {
1987 gen_op_mov_TN_reg[ot][0][rm]();
1988 }
1989
1990 switch(op) {
1991 case 0: /* test */
1992 val = insn_get(s, ot);
1993 gen_op_movl_T1_im(val);
1994 gen_op_testl_T0_T1_cc();
1995 s->cc_op = CC_OP_LOGICB + ot;
1996 break;
1997 case 2: /* not */
1998 gen_op_notl_T0();
1999 if (mod != 3) {
2000 gen_op_st_T0_A0[ot + s->mem_index]();
2001 } else {
2002 gen_op_mov_reg_T0[ot][rm]();
2003 }
2004 break;
2005 case 3: /* neg */
2006 gen_op_negl_T0();
2007 if (mod != 3) {
2008 gen_op_st_T0_A0[ot + s->mem_index]();
2009 } else {
2010 gen_op_mov_reg_T0[ot][rm]();
2011 }
2012 gen_op_update_neg_cc();
2013 s->cc_op = CC_OP_SUBB + ot;
2014 break;
2015 case 4: /* mul */
2016 switch(ot) {
2017 case OT_BYTE:
2018 gen_op_mulb_AL_T0();
2019 break;
2020 case OT_WORD:
2021 gen_op_mulw_AX_T0();
2022 break;
2023 default:
2024 case OT_LONG:
2025 gen_op_mull_EAX_T0();
2026 break;
2027 }
2028 s->cc_op = CC_OP_MUL;
2029 break;
2030 case 5: /* imul */
2031 switch(ot) {
2032 case OT_BYTE:
2033 gen_op_imulb_AL_T0();
2034 break;
2035 case OT_WORD:
2036 gen_op_imulw_AX_T0();
2037 break;
2038 default:
2039 case OT_LONG:
2040 gen_op_imull_EAX_T0();
2041 break;
2042 }
2043 s->cc_op = CC_OP_MUL;
2044 break;
2045 case 6: /* div */
2046 switch(ot) {
2047 case OT_BYTE:
2048 gen_op_divb_AL_T0(pc_start - s->cs_base);
2049 break;
2050 case OT_WORD:
2051 gen_op_divw_AX_T0(pc_start - s->cs_base);
2052 break;
2053 default:
2054 case OT_LONG:
2055 gen_op_divl_EAX_T0(pc_start - s->cs_base);
2056 break;
2057 }
2058 break;
2059 case 7: /* idiv */
2060 switch(ot) {
2061 case OT_BYTE:
2062 gen_op_idivb_AL_T0(pc_start - s->cs_base);
2063 break;
2064 case OT_WORD:
2065 gen_op_idivw_AX_T0(pc_start - s->cs_base);
2066 break;
2067 default:
2068 case OT_LONG:
2069 gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2070 break;
2071 }
2072 break;
2073 default:
2074 goto illegal_op;
2075 }
2076 break;
2077
2078 case 0xfe: /* GRP4 */
2079 case 0xff: /* GRP5 */
2080 if ((b & 1) == 0)
2081 ot = OT_BYTE;
2082 else
2083 ot = dflag ? OT_LONG : OT_WORD;
2084
2085 modrm = ldub_code(s->pc++);
2086 mod = (modrm >> 6) & 3;
2087 rm = modrm & 7;
2088 op = (modrm >> 3) & 7;
2089 if (op >= 2 && b == 0xfe) {
2090 goto illegal_op;
2091 }
2092 if (mod != 3) {
2093 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2094 if (op >= 2 && op != 3 && op != 5)
2095 gen_op_ld_T0_A0[ot + s->mem_index]();
2096 } else {
2097 gen_op_mov_TN_reg[ot][0][rm]();
2098 }
2099
2100 switch(op) {
2101 case 0: /* inc Ev */
2102 if (mod != 3)
2103 opreg = OR_TMP0;
2104 else
2105 opreg = rm;
2106 gen_inc(s, ot, opreg, 1);
2107 break;
2108 case 1: /* dec Ev */
2109 if (mod != 3)
2110 opreg = OR_TMP0;
2111 else
2112 opreg = rm;
2113 gen_inc(s, ot, opreg, -1);
2114 break;
2115 case 2: /* call Ev */
2116 /* XXX: optimize if memory (no and is necessary) */
2117 if (s->dflag == 0)
2118 gen_op_andl_T0_ffff();
2119 gen_op_jmp_T0();
2120 next_eip = s->pc - s->cs_base;
2121 gen_op_movl_T0_im(next_eip);
2122 gen_push_T0(s);
2123 gen_eob(s);
2124 break;
2125 case 3: /* lcall Ev */
2126 gen_op_ld_T1_A0[ot + s->mem_index]();
2127 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2128 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2129 do_lcall:
2130 if (s->pe && !s->vm86) {
2131 if (s->cc_op != CC_OP_DYNAMIC)
2132 gen_op_set_cc_op(s->cc_op);
2133 gen_op_jmp_im(pc_start - s->cs_base);
2134 gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2135 } else {
2136 gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2137 }
2138 gen_eob(s);
2139 break;
2140 case 4: /* jmp Ev */
2141 if (s->dflag == 0)
2142 gen_op_andl_T0_ffff();
2143 gen_op_jmp_T0();
2144 gen_eob(s);
2145 break;
2146 case 5: /* ljmp Ev */
2147 gen_op_ld_T1_A0[ot + s->mem_index]();
2148 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2149 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2150 do_ljmp:
2151 if (s->pe && !s->vm86) {
2152 if (s->cc_op != CC_OP_DYNAMIC)
2153 gen_op_set_cc_op(s->cc_op);
2154 gen_op_jmp_im(pc_start - s->cs_base);
2155 gen_op_ljmp_protected_T0_T1();
2156 } else {
2157 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2158 gen_op_movl_T0_T1();
2159 gen_op_jmp_T0();
2160 }
2161 gen_eob(s);
2162 break;
2163 case 6: /* push Ev */
2164 gen_push_T0(s);
2165 break;
2166 default:
2167 goto illegal_op;
2168 }
2169 break;
2170
2171 case 0x84: /* test Ev, Gv */
2172 case 0x85:
2173 if ((b & 1) == 0)
2174 ot = OT_BYTE;
2175 else
2176 ot = dflag ? OT_LONG : OT_WORD;
2177
2178 modrm = ldub_code(s->pc++);
2179 mod = (modrm >> 6) & 3;
2180 rm = modrm & 7;
2181 reg = (modrm >> 3) & 7;
2182
2183 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2184 gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2185 gen_op_testl_T0_T1_cc();
2186 s->cc_op = CC_OP_LOGICB + ot;
2187 break;
2188
2189 case 0xa8: /* test eAX, Iv */
2190 case 0xa9:
2191 if ((b & 1) == 0)
2192 ot = OT_BYTE;
2193 else
2194 ot = dflag ? OT_LONG : OT_WORD;
2195 val = insn_get(s, ot);
2196
2197 gen_op_mov_TN_reg[ot][0][OR_EAX]();
2198 gen_op_movl_T1_im(val);
2199 gen_op_testl_T0_T1_cc();
2200 s->cc_op = CC_OP_LOGICB + ot;
2201 break;
2202
2203 case 0x98: /* CWDE/CBW */
2204 if (dflag)
2205 gen_op_movswl_EAX_AX();
2206 else
2207 gen_op_movsbw_AX_AL();
2208 break;
2209 case 0x99: /* CDQ/CWD */
2210 if (dflag)
2211 gen_op_movslq_EDX_EAX();
2212 else
2213 gen_op_movswl_DX_AX();
2214 break;
2215 case 0x1af: /* imul Gv, Ev */
2216 case 0x69: /* imul Gv, Ev, I */
2217 case 0x6b:
2218 ot = dflag ? OT_LONG : OT_WORD;
2219 modrm = ldub_code(s->pc++);
2220 reg = ((modrm >> 3) & 7) + OR_EAX;
2221 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2222 if (b == 0x69) {
2223 val = insn_get(s, ot);
2224 gen_op_movl_T1_im(val);
2225 } else if (b == 0x6b) {
2226 val = insn_get(s, OT_BYTE);
2227 gen_op_movl_T1_im(val);
2228 } else {
2229 gen_op_mov_TN_reg[ot][1][reg]();
2230 }
2231
2232 if (ot == OT_LONG) {
2233 gen_op_imull_T0_T1();
2234 } else {
2235 gen_op_imulw_T0_T1();
2236 }
2237 gen_op_mov_reg_T0[ot][reg]();
2238 s->cc_op = CC_OP_MUL;
2239 break;
2240 case 0x1c0:
2241 case 0x1c1: /* xadd Ev, Gv */
2242 if ((b & 1) == 0)
2243 ot = OT_BYTE;
2244 else
2245 ot = dflag ? OT_LONG : OT_WORD;
2246 modrm = ldub_code(s->pc++);
2247 reg = (modrm >> 3) & 7;
2248 mod = (modrm >> 6) & 3;
2249 if (mod == 3) {
2250 rm = modrm & 7;
2251 gen_op_mov_TN_reg[ot][0][reg]();
2252 gen_op_mov_TN_reg[ot][1][rm]();
2253 gen_op_addl_T0_T1();
2254 gen_op_mov_reg_T0[ot][rm]();
2255 gen_op_mov_reg_T1[ot][reg]();
2256 } else {
2257 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2258 gen_op_mov_TN_reg[ot][0][reg]();
2259 gen_op_ld_T1_A0[ot + s->mem_index]();
2260 gen_op_addl_T0_T1();
2261 gen_op_st_T0_A0[ot + s->mem_index]();
2262 gen_op_mov_reg_T1[ot][reg]();
2263 }
2264 gen_op_update2_cc();
2265 s->cc_op = CC_OP_ADDB + ot;
2266 break;
2267 case 0x1b0:
2268 case 0x1b1: /* cmpxchg Ev, Gv */
2269 if ((b & 1) == 0)
2270 ot = OT_BYTE;
2271 else
2272 ot = dflag ? OT_LONG : OT_WORD;
2273 modrm = ldub_code(s->pc++);
2274 reg = (modrm >> 3) & 7;
2275 mod = (modrm >> 6) & 3;
2276 gen_op_mov_TN_reg[ot][1][reg]();
2277 if (mod == 3) {
2278 rm = modrm & 7;
2279 gen_op_mov_TN_reg[ot][0][rm]();
2280 gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2281 gen_op_mov_reg_T0[ot][rm]();
2282 } else {
2283 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2284 gen_op_ld_T0_A0[ot + s->mem_index]();
2285 gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
2286 }
2287 s->cc_op = CC_OP_SUBB + ot;
2288 break;
2289 case 0x1c7: /* cmpxchg8b */
2290 modrm = ldub_code(s->pc++);
2291 mod = (modrm >> 6) & 3;
2292 if (mod == 3)
2293 goto illegal_op;
2294 if (s->cc_op != CC_OP_DYNAMIC)
2295 gen_op_set_cc_op(s->cc_op);
2296 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2297 gen_op_cmpxchg8b();
2298 s->cc_op = CC_OP_EFLAGS;
2299 break;
2300
2301 /**************************/
2302 /* push/pop */
2303 case 0x50 ... 0x57: /* push */
2304 gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2305 gen_push_T0(s);
2306 break;
2307 case 0x58 ... 0x5f: /* pop */
2308 ot = dflag ? OT_LONG : OT_WORD;
2309 gen_pop_T0(s);
2310 /* NOTE: order is important for pop %sp */
2311 gen_pop_update(s);
2312 gen_op_mov_reg_T0[ot][b & 7]();
2313 break;
2314 case 0x60: /* pusha */
2315 gen_pusha(s);
2316 break;
2317 case 0x61: /* popa */
2318 gen_popa(s);
2319 break;
2320 case 0x68: /* push Iv */
2321 case 0x6a:
2322 ot = dflag ? OT_LONG : OT_WORD;
2323 if (b == 0x68)
2324 val = insn_get(s, ot);
2325 else
2326 val = (int8_t)insn_get(s, OT_BYTE);
2327 gen_op_movl_T0_im(val);
2328 gen_push_T0(s);
2329 break;
2330 case 0x8f: /* pop Ev */
2331 ot = dflag ? OT_LONG : OT_WORD;
2332 modrm = ldub_code(s->pc++);
2333 mod = (modrm >> 6) & 3;
2334 gen_pop_T0(s);
2335 if (mod == 3) {
2336 /* NOTE: order is important for pop %sp */
2337 gen_pop_update(s);
2338 rm = modrm & 7;
2339 gen_op_mov_reg_T0[ot][rm]();
2340 } else {
2341 /* NOTE: order is important too for MMU exceptions */
2342 s->popl_esp_hack = 2 << dflag;
2343 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2344 s->popl_esp_hack = 0;
2345 gen_pop_update(s);
2346 }
2347 break;
2348 case 0xc8: /* enter */
2349 {
2350 int level;
2351 val = lduw_code(s->pc);
2352 s->pc += 2;
2353 level = ldub_code(s->pc++);
2354 gen_enter(s, val, level);
2355 }
2356 break;
2357 case 0xc9: /* leave */
2358 /* XXX: exception not precise (ESP is updated before potential exception) */
2359 if (s->ss32) {
2360 gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2361 gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2362 } else {
2363 gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2364 gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2365 }
2366 gen_pop_T0(s);
2367 ot = dflag ? OT_LONG : OT_WORD;
2368 gen_op_mov_reg_T0[ot][R_EBP]();
2369 gen_pop_update(s);
2370 break;
2371 case 0x06: /* push es */
2372 case 0x0e: /* push cs */
2373 case 0x16: /* push ss */
2374 case 0x1e: /* push ds */
2375 gen_op_movl_T0_seg(b >> 3);
2376 gen_push_T0(s);
2377 break;
2378 case 0x1a0: /* push fs */
2379 case 0x1a8: /* push gs */
2380 gen_op_movl_T0_seg((b >> 3) & 7);
2381 gen_push_T0(s);
2382 break;
2383 case 0x07: /* pop es */
2384 case 0x17: /* pop ss */
2385 case 0x1f: /* pop ds */
2386 reg = b >> 3;
2387 gen_pop_T0(s);
2388 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2389 gen_pop_update(s);
2390 if (reg == R_SS) {
2391 /* if reg == SS, inhibit interrupts/trace. */
2392 /* If several instructions disable interrupts, only the
2393 _first_ does it */
2394 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2395 gen_op_set_inhibit_irq();
2396 s->tf = 0;
2397 }
2398 if (s->is_jmp) {
2399 gen_op_jmp_im(s->pc - s->cs_base);
2400 gen_eob(s);
2401 }
2402 break;
2403 case 0x1a1: /* pop fs */
2404 case 0x1a9: /* pop gs */
2405 gen_pop_T0(s);
2406 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2407 gen_pop_update(s);
2408 if (s->is_jmp) {
2409 gen_op_jmp_im(s->pc - s->cs_base);
2410 gen_eob(s);
2411 }
2412 break;
2413
2414 /**************************/
2415 /* mov */
2416 case 0x88:
2417 case 0x89: /* mov Gv, Ev */
2418 if ((b & 1) == 0)
2419 ot = OT_BYTE;
2420 else
2421 ot = dflag ? OT_LONG : OT_WORD;
2422 modrm = ldub_code(s->pc++);
2423 reg = (modrm >> 3) & 7;
2424
2425 /* generate a generic store */
2426 gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2427 break;
2428 case 0xc6:
2429 case 0xc7: /* mov Ev, Iv */
2430 if ((b & 1) == 0)
2431 ot = OT_BYTE;
2432 else
2433 ot = dflag ? OT_LONG : OT_WORD;
2434 modrm = ldub_code(s->pc++);
2435 mod = (modrm >> 6) & 3;
2436 if (mod != 3)
2437 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2438 val = insn_get(s, ot);
2439 gen_op_movl_T0_im(val);
2440 if (mod != 3)
2441 gen_op_st_T0_A0[ot + s->mem_index]();
2442 else
2443 gen_op_mov_reg_T0[ot][modrm & 7]();
2444 break;
2445 case 0x8a:
2446 case 0x8b: /* mov Ev, Gv */
2447 if ((b & 1) == 0)
2448 ot = OT_BYTE;
2449 else
2450 ot = dflag ? OT_LONG : OT_WORD;
2451 modrm = ldub_code(s->pc++);
2452 reg = (modrm >> 3) & 7;
2453
2454 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2455 gen_op_mov_reg_T0[ot][reg]();
2456 break;
2457 case 0x8e: /* mov seg, Gv */
2458 modrm = ldub_code(s->pc++);
2459 reg = (modrm >> 3) & 7;
2460 if (reg >= 6 || reg == R_CS)
2461 goto illegal_op;
2462 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2463 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2464 if (reg == R_SS) {
2465 /* if reg == SS, inhibit interrupts/trace */
2466 /* If several instructions disable interrupts, only the
2467 _first_ does it */
2468 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2469 gen_op_set_inhibit_irq();
2470 s->tf = 0;
2471 }
2472 if (s->is_jmp) {
2473 gen_op_jmp_im(s->pc - s->cs_base);
2474 gen_eob(s);
2475 }
2476 break;
2477 case 0x8c: /* mov Gv, seg */
2478 modrm = ldub_code(s->pc++);
2479 reg = (modrm >> 3) & 7;
2480 mod = (modrm >> 6) & 3;
2481 if (reg >= 6)
2482 goto illegal_op;
2483 gen_op_movl_T0_seg(reg);
2484 ot = OT_WORD;
2485 if (mod == 3 && dflag)
2486 ot = OT_LONG;
2487 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2488 break;
2489
2490 case 0x1b6: /* movzbS Gv, Eb */
2491 case 0x1b7: /* movzwS Gv, Eb */
2492 case 0x1be: /* movsbS Gv, Eb */
2493 case 0x1bf: /* movswS Gv, Eb */
2494 {
2495 int d_ot;
2496 /* d_ot is the size of destination */
2497 d_ot = dflag + OT_WORD;
2498 /* ot is the size of source */
2499 ot = (b & 1) + OT_BYTE;
2500 modrm = ldub_code(s->pc++);
2501 reg = ((modrm >> 3) & 7) + OR_EAX;
2502 mod = (modrm >> 6) & 3;
2503 rm = modrm & 7;
2504
2505 if (mod == 3) {
2506 gen_op_mov_TN_reg[ot][0][rm]();
2507 switch(ot | (b & 8)) {
2508 case OT_BYTE:
2509 gen_op_movzbl_T0_T0();
2510 break;
2511 case OT_BYTE | 8:
2512 gen_op_movsbl_T0_T0();
2513 break;
2514 case OT_WORD:
2515 gen_op_movzwl_T0_T0();
2516 break;
2517 default:
2518 case OT_WORD | 8:
2519 gen_op_movswl_T0_T0();
2520 break;
2521 }
2522 gen_op_mov_reg_T0[d_ot][reg]();
2523 } else {
2524 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2525 if (b & 8) {
2526 gen_op_lds_T0_A0[ot + s->mem_index]();
2527 } else {
2528 gen_op_ldu_T0_A0[ot + s->mem_index]();
2529 }
2530 gen_op_mov_reg_T0[d_ot][reg]();
2531 }
2532 }
2533 break;
2534
2535 case 0x8d: /* lea */
2536 ot = dflag ? OT_LONG : OT_WORD;
2537 modrm = ldub_code(s->pc++);
2538 reg = (modrm >> 3) & 7;
2539 /* we must ensure that no segment is added */
2540 s->override = -1;
2541 val = s->addseg;
2542 s->addseg = 0;
2543 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2544 s->addseg = val;
2545 gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2546 break;
2547
2548 case 0xa0: /* mov EAX, Ov */
2549 case 0xa1:
2550 case 0xa2: /* mov Ov, EAX */
2551 case 0xa3:
2552 if ((b & 1) == 0)
2553 ot = OT_BYTE;
2554 else
2555 ot = dflag ? OT_LONG : OT_WORD;
2556 if (s->aflag)
2557 offset_addr = insn_get(s, OT_LONG);
2558 else
2559 offset_addr = insn_get(s, OT_WORD);
2560 gen_op_movl_A0_im(offset_addr);
2561 /* handle override */
2562 {
2563 int override, must_add_seg;
2564 must_add_seg = s->addseg;
2565 if (s->override >= 0) {
2566 override = s->override;
2567 must_add_seg = 1;
2568 } else {
2569 override = R_DS;
2570 }
2571 if (must_add_seg) {
2572 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2573 }
2574 }
2575 if ((b & 2) == 0) {
2576 gen_op_ld_T0_A0[ot + s->mem_index]();
2577 gen_op_mov_reg_T0[ot][R_EAX]();
2578 } else {
2579 gen_op_mov_TN_reg[ot][0][R_EAX]();
2580 gen_op_st_T0_A0[ot + s->mem_index]();
2581 }
2582 break;
2583 case 0xd7: /* xlat */
2584 gen_op_movl_A0_reg[R_EBX]();
2585 gen_op_addl_A0_AL();
2586 if (s->aflag == 0)
2587 gen_op_andl_A0_ffff();
2588 /* handle override */
2589 {
2590 int override, must_add_seg;
2591 must_add_seg = s->addseg;
2592 override = R_DS;
2593 if (s->override >= 0) {
2594 override = s->override;
2595 must_add_seg = 1;
2596 } else {
2597 override = R_DS;
2598 }
2599 if (must_add_seg) {
2600 gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2601 }
2602 }
2603 gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2604 gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2605 break;
2606 case 0xb0 ... 0xb7: /* mov R, Ib */
2607 val = insn_get(s, OT_BYTE);
2608 gen_op_movl_T0_im(val);
2609 gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2610 break;
2611 case 0xb8 ... 0xbf: /* mov R, Iv */
2612 ot = dflag ? OT_LONG : OT_WORD;
2613 val = insn_get(s, ot);
2614 reg = OR_EAX + (b & 7);
2615 gen_op_movl_T0_im(val);
2616 gen_op_mov_reg_T0[ot][reg]();
2617 break;
2618
2619 case 0x91 ... 0x97: /* xchg R, EAX */
2620 ot = dflag ? OT_LONG : OT_WORD;
2621 reg = b & 7;
2622 rm = R_EAX;
2623 goto do_xchg_reg;
2624 case 0x86:
2625 case 0x87: /* xchg Ev, Gv */
2626 if ((b & 1) == 0)
2627 ot = OT_BYTE;
2628 else
2629 ot = dflag ? OT_LONG : OT_WORD;
2630 modrm = ldub_code(s->pc++);
2631 reg = (modrm >> 3) & 7;
2632 mod = (modrm >> 6) & 3;
2633 if (mod == 3) {
2634 rm = modrm & 7;
2635 do_xchg_reg:
2636 gen_op_mov_TN_reg[ot][0][reg]();
2637 gen_op_mov_TN_reg[ot][1][rm]();
2638 gen_op_mov_reg_T0[ot][rm]();
2639 gen_op_mov_reg_T1[ot][reg]();
2640 } else {
2641 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2642 gen_op_mov_TN_reg[ot][0][reg]();
2643 /* for xchg, lock is implicit */
2644 if (!(prefixes & PREFIX_LOCK))
2645 gen_op_lock();
2646 gen_op_ld_T1_A0[ot + s->mem_index]();
2647 gen_op_st_T0_A0[ot + s->mem_index]();
2648 if (!(prefixes & PREFIX_LOCK))
2649 gen_op_unlock();
2650 gen_op_mov_reg_T1[ot][reg]();
2651 }
2652 break;
2653 case 0xc4: /* les Gv */
2654 op = R_ES;
2655 goto do_lxx;
2656 case 0xc5: /* lds Gv */
2657 op = R_DS;
2658 goto do_lxx;
2659 case 0x1b2: /* lss Gv */
2660 op = R_SS;
2661 goto do_lxx;
2662 case 0x1b4: /* lfs Gv */
2663 op = R_FS;
2664 goto do_lxx;
2665 case 0x1b5: /* lgs Gv */
2666 op = R_GS;
2667 do_lxx:
2668 ot = dflag ? OT_LONG : OT_WORD;
2669 modrm = ldub_code(s->pc++);
2670 reg = (modrm >> 3) & 7;
2671 mod = (modrm >> 6) & 3;
2672 if (mod == 3)
2673 goto illegal_op;
2674 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2675 gen_op_ld_T1_A0[ot + s->mem_index]();
2676 gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2677 /* load the segment first to handle exceptions properly */
2678 gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2679 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2680 /* then put the data */
2681 gen_op_mov_reg_T1[ot][reg]();
2682 if (s->is_jmp) {
2683 gen_op_jmp_im(s->pc - s->cs_base);
2684 gen_eob(s);
2685 }
2686 break;
2687
2688 /************************/
2689 /* shifts */
2690 case 0xc0:
2691 case 0xc1:
2692 /* shift Ev,Ib */
2693 shift = 2;
2694 grp2:
2695 {
2696 if ((b & 1) == 0)
2697 ot = OT_BYTE;
2698 else
2699 ot = dflag ? OT_LONG : OT_WORD;
2700
2701 modrm = ldub_code(s->pc++);
2702 mod = (modrm >> 6) & 3;
2703 rm = modrm & 7;
2704 op = (modrm >> 3) & 7;
2705
2706 if (mod != 3) {
2707 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2708 opreg = OR_TMP0;
2709 } else {
2710 opreg = rm + OR_EAX;
2711 }
2712
2713 /* simpler op */
2714 if (shift == 0) {
2715 gen_shift(s, op, ot, opreg, OR_ECX);
2716 } else {
2717 if (shift == 2) {
2718 shift = ldub_code(s->pc++);
2719 }
2720 gen_shifti(s, op, ot, opreg, shift);
2721 }
2722 }
2723 break;
2724 case 0xd0:
2725 case 0xd1:
2726 /* shift Ev,1 */
2727 shift = 1;
2728 goto grp2;
2729 case 0xd2:
2730 case 0xd3:
2731 /* shift Ev,cl */
2732 shift = 0;
2733 goto grp2;
2734
2735 case 0x1a4: /* shld imm */
2736 op = 0;
2737 shift = 1;
2738 goto do_shiftd;
2739 case 0x1a5: /* shld cl */
2740 op = 0;
2741 shift = 0;
2742 goto do_shiftd;
2743 case 0x1ac: /* shrd imm */
2744 op = 1;
2745 shift = 1;
2746 goto do_shiftd;
2747 case 0x1ad: /* shrd cl */
2748 op = 1;
2749 shift = 0;
2750 do_shiftd:
2751 ot = dflag ? OT_LONG : OT_WORD;
2752 modrm = ldub_code(s->pc++);
2753 mod = (modrm >> 6) & 3;
2754 rm = modrm & 7;
2755 reg = (modrm >> 3) & 7;
2756
2757 if (mod != 3) {
2758 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2759 gen_op_ld_T0_A0[ot + s->mem_index]();
2760 } else {
2761 gen_op_mov_TN_reg[ot][0][rm]();
2762 }
2763 gen_op_mov_TN_reg[ot][1][reg]();
2764
2765 if (shift) {
2766 val = ldub_code(s->pc++);
2767 val &= 0x1f;
2768 if (val) {
2769 if (mod == 3)
2770 gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2771 else
2772 gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
2773 if (op == 0 && ot != OT_WORD)
2774 s->cc_op = CC_OP_SHLB + ot;
2775 else
2776 s->cc_op = CC_OP_SARB + ot;
2777 }
2778 } else {
2779 if (s->cc_op != CC_OP_DYNAMIC)
2780 gen_op_set_cc_op(s->cc_op);
2781 if (mod == 3)
2782 gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2783 else
2784 gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
2785 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2786 }
2787 if (mod == 3) {
2788 gen_op_mov_reg_T0[ot][rm]();
2789 }
2790 break;
2791
2792 /************************/
2793 /* floats */
2794 case 0xd8 ... 0xdf:
2795 modrm = ldub_code(s->pc++);
2796 mod = (modrm >> 6) & 3;
2797 rm = modrm & 7;
2798 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2799
2800 if (mod != 3) {
2801 /* memory op */
2802 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2803 switch(op) {
2804 case 0x00 ... 0x07: /* fxxxs */
2805 case 0x10 ... 0x17: /* fixxxl */
2806 case 0x20 ... 0x27: /* fxxxl */
2807 case 0x30 ... 0x37: /* fixxx */
2808 {
2809 int op1;
2810 op1 = op & 7;
2811
2812 switch(op >> 4) {
2813 case 0:
2814 gen_op_flds_FT0_A0();
2815 break;
2816 case 1:
2817 gen_op_fildl_FT0_A0();
2818 break;
2819 case 2:
2820 gen_op_fldl_FT0_A0();
2821 break;
2822 case 3:
2823 default:
2824 gen_op_fild_FT0_A0();
2825 break;
2826 }
2827
2828 gen_op_fp_arith_ST0_FT0[op1]();
2829 if (op1 == 3) {
2830 /* fcomp needs pop */
2831 gen_op_fpop();
2832 }
2833 }
2834 break;
2835 case 0x08: /* flds */
2836 case 0x0a: /* fsts */
2837 case 0x0b: /* fstps */
2838 case 0x18: /* fildl */
2839 case 0x1a: /* fistl */
2840 case 0x1b: /* fistpl */
2841 case 0x28: /* fldl */
2842 case 0x2a: /* fstl */
2843 case 0x2b: /* fstpl */
2844 case 0x38: /* filds */
2845 case 0x3a: /* fists */
2846 case 0x3b: /* fistps */
2847
2848 switch(op & 7) {
2849 case 0:
2850 switch(op >> 4) {
2851 case 0:
2852 gen_op_flds_ST0_A0();
2853 break;
2854 case 1:
2855 gen_op_fildl_ST0_A0();
2856 break;
2857 case 2:
2858 gen_op_fldl_ST0_A0();
2859 break;
2860 case 3:
2861 default:
2862 gen_op_fild_ST0_A0();
2863 break;
2864 }
2865 break;
2866 default:
2867 switch(op >> 4) {
2868 case 0:
2869 gen_op_fsts_ST0_A0();
2870 break;
2871 case 1:
2872 gen_op_fistl_ST0_A0();
2873 break;
2874 case 2:
2875 gen_op_fstl_ST0_A0();
2876 break;
2877 case 3:
2878 default:
2879 gen_op_fist_ST0_A0();
2880 break;
2881 }
2882 if ((op & 7) == 3)
2883 gen_op_fpop();
2884 break;
2885 }
2886 break;
2887 case 0x0c: /* fldenv mem */
2888 gen_op_fldenv_A0(s->dflag);
2889 break;
2890 case 0x0d: /* fldcw mem */
2891 gen_op_fldcw_A0();
2892 break;
2893 case 0x0e: /* fnstenv mem */
2894 gen_op_fnstenv_A0(s->dflag);
2895 break;
2896 case 0x0f: /* fnstcw mem */
2897 gen_op_fnstcw_A0();
2898 break;
2899 case 0x1d: /* fldt mem */
2900 gen_op_fldt_ST0_A0();
2901 break;
2902 case 0x1f: /* fstpt mem */
2903 gen_op_fstt_ST0_A0();
2904 gen_op_fpop();
2905 break;
2906 case 0x2c: /* frstor mem */
2907 gen_op_frstor_A0(s->dflag);
2908 break;
2909 case 0x2e: /* fnsave mem */
2910 gen_op_fnsave_A0(s->dflag);
2911 break;
2912 case 0x2f: /* fnstsw mem */
2913 gen_op_fnstsw_A0();
2914 break;
2915 case 0x3c: /* fbld */
2916 gen_op_fbld_ST0_A0();
2917 break;
2918 case 0x3e: /* fbstp */
2919 gen_op_fbst_ST0_A0();
2920 gen_op_fpop();
2921 break;
2922 case 0x3d: /* fildll */
2923 gen_op_fildll_ST0_A0();
2924 break;
2925 case 0x3f: /* fistpll */
2926 gen_op_fistll_ST0_A0();
2927 gen_op_fpop();
2928 break;
2929 default:
2930 goto illegal_op;
2931 }
2932 } else {
2933 /* register float ops */
2934 opreg = rm;
2935
2936 switch(op) {
2937 case 0x08: /* fld sti */
2938 gen_op_fpush();
2939 gen_op_fmov_ST0_STN((opreg + 1) & 7);
2940 break;
2941 case 0x09: /* fxchg sti */
2942 gen_op_fxchg_ST0_STN(opreg);
2943 break;
2944 case 0x0a: /* grp d9/2 */
2945 switch(rm) {
2946 case 0: /* fnop */
2947 break;
2948 default:
2949 goto illegal_op;
2950 }
2951 break;
2952 case 0x0c: /* grp d9/4 */
2953 switch(rm) {
2954 case 0: /* fchs */
2955 gen_op_fchs_ST0();
2956 break;
2957 case 1: /* fabs */
2958 gen_op_fabs_ST0();
2959 break;
2960 case 4: /* ftst */
2961 gen_op_fldz_FT0();
2962 gen_op_fcom_ST0_FT0();
2963 break;
2964 case 5: /* fxam */
2965 gen_op_fxam_ST0();
2966 break;
2967 default:
2968 goto illegal_op;
2969 }
2970 break;
2971 case 0x0d: /* grp d9/5 */
2972 {
2973 switch(rm) {
2974 case 0:
2975 gen_op_fpush();
2976 gen_op_fld1_ST0();
2977 break;
2978 case 1:
2979 gen_op_fpush();
2980 gen_op_fldl2t_ST0();
2981 break;
2982 case 2:
2983 gen_op_fpush();
2984 gen_op_fldl2e_ST0();
2985 break;
2986 case 3:
2987 gen_op_fpush();
2988 gen_op_fldpi_ST0();
2989 break;
2990 case 4:
2991 gen_op_fpush();
2992 gen_op_fldlg2_ST0();
2993 break;
2994 case 5:
2995 gen_op_fpush();
2996 gen_op_fldln2_ST0();
2997 break;
2998 case 6:
2999 gen_op_fpush();
3000 gen_op_fldz_ST0();
3001 break;
3002 default:
3003 goto illegal_op;
3004 }
3005 }
3006 break;
3007 case 0x0e: /* grp d9/6 */
3008 switch(rm) {
3009 case 0: /* f2xm1 */
3010 gen_op_f2xm1();
3011 break;
3012 case 1: /* fyl2x */
3013 gen_op_fyl2x();
3014 break;
3015 case 2: /* fptan */
3016 gen_op_fptan();
3017 break;
3018 case 3: /* fpatan */
3019 gen_op_fpatan();
3020 break;
3021 case 4: /* fxtract */
3022 gen_op_fxtract();
3023 break;
3024 case 5: /* fprem1 */
3025 gen_op_fprem1();
3026 break;
3027 case 6: /* fdecstp */
3028 gen_op_fdecstp();
3029 break;
3030 default:
3031 case 7: /* fincstp */
3032 gen_op_fincstp();
3033 break;
3034 }
3035 break;
3036 case 0x0f: /* grp d9/7 */
3037 switch(rm) {
3038 case 0: /* fprem */
3039 gen_op_fprem();
3040 break;
3041 case 1: /* fyl2xp1 */
3042 gen_op_fyl2xp1();
3043 break;
3044 case 2: /* fsqrt */
3045 gen_op_fsqrt();
3046 break;
3047 case 3: /* fsincos */
3048 gen_op_fsincos();
3049 break;
3050 case 5: /* fscale */
3051 gen_op_fscale();
3052 break;
3053 case 4: /* frndint */
3054 gen_op_frndint();
3055 break;
3056 case 6: /* fsin */
3057 gen_op_fsin();
3058 break;
3059 default:
3060 case 7: /* fcos */
3061 gen_op_fcos();
3062 break;
3063 }
3064 break;
3065 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3066 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3067 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3068 {
3069 int op1;
3070
3071 op1 = op & 7;
3072 if (op >= 0x20) {
3073 gen_op_fp_arith_STN_ST0[op1](opreg);
3074 if (op >= 0x30)
3075 gen_op_fpop();
3076 } else {
3077 gen_op_fmov_FT0_STN(opreg);
3078 gen_op_fp_arith_ST0_FT0[op1]();
3079 }
3080 }
3081 break;
3082 case 0x02: /* fcom */
3083 gen_op_fmov_FT0_STN(opreg);
3084 gen_op_fcom_ST0_FT0();
3085 break;
3086 case 0x03: /* fcomp */
3087 gen_op_fmov_FT0_STN(opreg);
3088 gen_op_fcom_ST0_FT0();
3089 gen_op_fpop();
3090 break;
3091 case 0x15: /* da/5 */
3092 switch(rm) {
3093 case 1: /* fucompp */
3094 gen_op_fmov_FT0_STN(1);
3095 gen_op_fucom_ST0_FT0();
3096 gen_op_fpop();
3097 gen_op_fpop();
3098 break;
3099 default:
3100 goto illegal_op;
3101 }
3102 break;
3103 case 0x1c:
3104 switch(rm) {
3105 case 0: /* feni (287 only, just do nop here) */
3106 break;
3107 case 1: /* fdisi (287 only, just do nop here) */
3108 break;
3109 case 2: /* fclex */
3110 gen_op_fclex();
3111 break;
3112 case 3: /* fninit */
3113 gen_op_fninit();
3114 break;
3115 case 4: /* fsetpm (287 only, just do nop here) */
3116 break;
3117 default:
3118 goto illegal_op;
3119 }
3120 break;
3121 case 0x1d: /* fucomi */
3122 if (s->cc_op != CC_OP_DYNAMIC)
3123 gen_op_set_cc_op(s->cc_op);
3124 gen_op_fmov_FT0_STN(opreg);
3125 gen_op_fucomi_ST0_FT0();
3126 s->cc_op = CC_OP_EFLAGS;
3127 break;
3128 case 0x1e: /* fcomi */
3129 if (s->cc_op != CC_OP_DYNAMIC)
3130 gen_op_set_cc_op(s->cc_op);
3131 gen_op_fmov_FT0_STN(opreg);
3132 gen_op_fcomi_ST0_FT0();
3133 s->cc_op = CC_OP_EFLAGS;
3134 break;
3135 case 0x2a: /* fst sti */
3136 gen_op_fmov_STN_ST0(opreg);
3137 break;
3138 case 0x2b: /* fstp sti */
3139 gen_op_fmov_STN_ST0(opreg);
3140 gen_op_fpop();
3141 break;
3142 case 0x2c: /* fucom st(i) */
3143 gen_op_fmov_FT0_STN(opreg);
3144 gen_op_fucom_ST0_FT0();
3145 break;
3146 case 0x2d: /* fucomp st(i) */
3147 gen_op_fmov_FT0_STN(opreg);
3148 gen_op_fucom_ST0_FT0();
3149 gen_op_fpop();
3150 break;
3151 case 0x33: /* de/3 */
3152 switch(rm) {
3153 case 1: /* fcompp */
3154 gen_op_fmov_FT0_STN(1);
3155 gen_op_fcom_ST0_FT0();
3156 gen_op_fpop();
3157 gen_op_fpop();
3158 break;
3159 default:
3160 goto illegal_op;
3161 }
3162 break;
3163 case 0x3c: /* df/4 */
3164 switch(rm) {
3165 case 0:
3166 gen_op_fnstsw_EAX();
3167 break;
3168 default:
3169 goto illegal_op;
3170 }
3171 break;
3172 case 0x3d: /* fucomip */
3173 if (s->cc_op != CC_OP_DYNAMIC)
3174 gen_op_set_cc_op(s->cc_op);
3175 gen_op_fmov_FT0_STN(opreg);
3176 gen_op_fucomi_ST0_FT0();
3177 gen_op_fpop();
3178 s->cc_op = CC_OP_EFLAGS;
3179 break;
3180 case 0x3e: /* fcomip */
3181 if (s->cc_op != CC_OP_DYNAMIC)
3182 gen_op_set_cc_op(s->cc_op);
3183 gen_op_fmov_FT0_STN(opreg);
3184 gen_op_fcomi_ST0_FT0();
3185 gen_op_fpop();
3186 s->cc_op = CC_OP_EFLAGS;
3187 break;
3188 case 0x10 ... 0x13: /* fcmovxx */
3189 case 0x18 ... 0x1b:
3190 {
3191 int op1;
3192 const static uint8_t fcmov_cc[8] = {
3193 (JCC_B << 1),
3194 (JCC_Z << 1),
3195 (JCC_BE << 1),
3196 (JCC_P << 1),
3197 };
3198 op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
3199 gen_setcc(s, op1);
3200 gen_op_fcmov_ST0_STN_T0(opreg);
3201 }
3202 break;
3203 default:
3204 goto illegal_op;
3205 }
3206 }
3207 break;
3208 /************************/
3209 /* string ops */
3210
3211 case 0xa4: /* movsS */
3212 case 0xa5:
3213 if ((b & 1) == 0)
3214 ot = OT_BYTE;
3215 else
3216 ot = dflag ? OT_LONG : OT_WORD;
3217
3218 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3219 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3220 } else {
3221 gen_movs(s, ot);
3222 }
3223 break;
3224
3225 case 0xaa: /* stosS */
3226 case 0xab:
3227 if ((b & 1) == 0)
3228 ot = OT_BYTE;
3229 else
3230 ot = dflag ? OT_LONG : OT_WORD;
3231
3232 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3233 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3234 } else {
3235 gen_stos(s, ot);
3236 }
3237 break;
3238 case 0xac: /* lodsS */
3239 case 0xad:
3240 if ((b & 1) == 0)
3241 ot = OT_BYTE;
3242 else
3243 ot = dflag ? OT_LONG : OT_WORD;
3244 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3245 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3246 } else {
3247 gen_lods(s, ot);
3248 }
3249 break;
3250 case 0xae: /* scasS */
3251 case 0xaf:
3252 if ((b & 1) == 0)
3253 ot = OT_BYTE;
3254 else
3255 ot = dflag ? OT_LONG : OT_WORD;
3256 if (prefixes & PREFIX_REPNZ) {
3257 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3258 } else if (prefixes & PREFIX_REPZ) {
3259 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3260 } else {
3261 gen_scas(s, ot);
3262 s->cc_op = CC_OP_SUBB + ot;
3263 }
3264 break;
3265
3266 case 0xa6: /* cmpsS */
3267 case 0xa7:
3268 if ((b & 1) == 0)
3269 ot = OT_BYTE;
3270 else
3271 ot = dflag ? OT_LONG : OT_WORD;
3272 if (prefixes & PREFIX_REPNZ) {
3273 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3274 } else if (prefixes & PREFIX_REPZ) {
3275 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3276 } else {
3277 gen_cmps(s, ot);
3278 s->cc_op = CC_OP_SUBB + ot;
3279 }
3280 break;
3281 case 0x6c: /* insS */
3282 case 0x6d:
3283 if ((b & 1) == 0)
3284 ot = OT_BYTE;
3285 else
3286 ot = dflag ? OT_LONG : OT_WORD;
3287 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3288 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3289 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3290 } else {
3291 gen_ins(s, ot);
3292 }
3293 break;
3294 case 0x6e: /* outsS */
3295 case 0x6f:
3296 if ((b & 1) == 0)
3297 ot = OT_BYTE;
3298 else
3299 ot = dflag ? OT_LONG : OT_WORD;
3300 gen_check_io(s, ot, 1, pc_start - s->cs_base);
3301 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3302 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3303 } else {
3304 gen_outs(s, ot);
3305 }
3306 break;
3307
3308 /************************/
3309 /* port I/O */
3310 case 0xe4:
3311 case 0xe5:
3312 if ((b & 1) == 0)
3313 ot = OT_BYTE;
3314 else
3315 ot = dflag ? OT_LONG : OT_WORD;
3316 val = ldub_code(s->pc++);
3317 gen_op_movl_T0_im(val);
3318 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3319 gen_op_in[ot]();
3320 gen_op_mov_reg_T1[ot][R_EAX]();
3321 break;
3322 case 0xe6:
3323 case 0xe7:
3324 if ((b & 1) == 0)
3325 ot = OT_BYTE;
3326 else
3327 ot = dflag ? OT_LONG : OT_WORD;
3328 val = ldub_code(s->pc++);
3329 gen_op_movl_T0_im(val);
3330 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3331 gen_op_mov_TN_reg[ot][1][R_EAX]();
3332 gen_op_out[ot]();
3333 break;
3334 case 0xec:
3335 case 0xed:
3336 if ((b & 1) == 0)
3337 ot = OT_BYTE;
3338 else
3339 ot = dflag ? OT_LONG : OT_WORD;
3340 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3341 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3342 gen_op_in[ot]();
3343 gen_op_mov_reg_T1[ot][R_EAX]();
3344 break;
3345 case 0xee:
3346 case 0xef:
3347 if ((b & 1) == 0)
3348 ot = OT_BYTE;
3349 else
3350 ot = dflag ? OT_LONG : OT_WORD;
3351 gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3352 gen_check_io(s, ot, 0, pc_start - s->cs_base);
3353 gen_op_mov_TN_reg[ot][1][R_EAX]();
3354 gen_op_out[ot]();
3355 break;
3356
3357 /************************/
3358 /* control */
3359 case 0xc2: /* ret im */
3360 val = ldsw_code(s->pc);
3361 s->pc += 2;
3362 gen_pop_T0(s);
3363 gen_stack_update(s, val + (2 << s->dflag));
3364 if (s->dflag == 0)
3365 gen_op_andl_T0_ffff();
3366 gen_op_jmp_T0();
3367 gen_eob(s);
3368 break;
3369 case 0xc3: /* ret */
3370 gen_pop_T0(s);
3371 gen_pop_update(s);
3372 if (s->dflag == 0)
3373 gen_op_andl_T0_ffff();
3374 gen_op_jmp_T0();
3375 gen_eob(s);
3376 break;
3377 case 0xca: /* lret im */
3378 val = ldsw_code(s->pc);
3379 s->pc += 2;
3380 do_lret:
3381 if (s->pe && !s->vm86) {
3382 if (s->cc_op != CC_OP_DYNAMIC)
3383 gen_op_set_cc_op(s->cc_op);
3384 gen_op_jmp_im(pc_start - s->cs_base);
3385 gen_op_lret_protected(s->dflag, val);
3386 } else {
3387 gen_stack_A0(s);
3388 /* pop offset */
3389 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3390 if (s->dflag == 0)
3391 gen_op_andl_T0_ffff();
3392 /* NOTE: keeping EIP updated is not a problem in case of
3393 exception */
3394 gen_op_jmp_T0();
3395 /* pop selector */
3396 gen_op_addl_A0_im(2 << s->dflag);
3397 gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3398 gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3399 /* add stack offset */
3400 gen_stack_update(s, val + (4 << s->dflag));
3401 }
3402 gen_eob(s);
3403 break;
3404 case 0xcb: /* lret */
3405 val = 0;
3406 goto do_lret;
3407 case 0xcf: /* iret */
3408 if (!s->pe) {
3409 /* real mode */
3410 gen_op_iret_real(s->dflag);
3411 s->cc_op = CC_OP_EFLAGS;
3412 } else if (s->vm86) {
3413 if (s->iopl != 3) {
3414 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3415 } else {
3416 gen_op_iret_real(s->dflag);
3417 s->cc_op = CC_OP_EFLAGS;
3418 }
3419 } else {
3420 if (s->cc_op != CC_OP_DYNAMIC)
3421 gen_op_set_cc_op(s->cc_op);
3422 gen_op_jmp_im(pc_start - s->cs_base);
3423 gen_op_iret_protected(s->dflag);
3424 s->cc_op = CC_OP_EFLAGS;
3425 }
3426 gen_eob(s);
3427 break;
3428 case 0xe8: /* call im */
3429 {
3430 unsigned int next_eip;
3431 ot = dflag ? OT_LONG : OT_WORD;
3432 val = insn_get(s, ot);
3433 next_eip = s->pc - s->cs_base;
3434 val += next_eip;
3435 if (s->dflag == 0)
3436 val &= 0xffff;
3437 gen_op_movl_T0_im(next_eip);
3438 gen_push_T0(s);
3439 gen_jmp(s, val);
3440 }
3441 break;
3442 case 0x9a: /* lcall im */
3443 {
3444 unsigned int selector, offset;
3445
3446 ot = dflag ? OT_LONG : OT_WORD;
3447 offset = insn_get(s, ot);
3448 selector = insn_get(s, OT_WORD);
3449
3450 gen_op_movl_T0_im(selector);
3451 gen_op_movl_T1_im(offset);
3452 }
3453 goto do_lcall;
3454 case 0xe9: /* jmp */
3455 ot = dflag ? OT_LONG : OT_WORD;
3456 val = insn_get(s, ot);
3457 val += s->pc - s->cs_base;
3458 if (s->dflag == 0)
3459 val = val & 0xffff;
3460 gen_jmp(s, val);
3461 break;
3462 case 0xea: /* ljmp im */
3463 {
3464 unsigned int selector, offset;
3465
3466 ot = dflag ? OT_LONG : OT_WORD;
3467 offset = insn_get(s, ot);
3468 selector = insn_get(s, OT_WORD);
3469
3470 gen_op_movl_T0_im(selector);
3471 gen_op_movl_T1_im(offset);
3472 }
3473 goto do_ljmp;
3474 case 0xeb: /* jmp Jb */
3475 val = (int8_t)insn_get(s, OT_BYTE);
3476 val += s->pc - s->cs_base;
3477 if (s->dflag == 0)
3478 val = val & 0xffff;
3479 gen_jmp(s, val);
3480 break;
3481 case 0x70 ... 0x7f: /* jcc Jb */
3482 val = (int8_t)insn_get(s, OT_BYTE);
3483 goto do_jcc;
3484 case 0x180 ... 0x18f: /* jcc Jv */
3485 if (dflag) {
3486 val = insn_get(s, OT_LONG);
3487 } else {
3488 val = (int16_t)insn_get(s, OT_WORD);
3489 }
3490 do_jcc:
3491 next_eip = s->pc - s->cs_base;
3492 val += next_eip;
3493 if (s->dflag == 0)
3494 val &= 0xffff;
3495 gen_jcc(s, b, val, next_eip);
3496 break;
3497
3498 case 0x190 ... 0x19f: /* setcc Gv */
3499 modrm = ldub_code(s->pc++);
3500 gen_setcc(s, b);
3501 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3502 break;
3503 case 0x140 ... 0x14f: /* cmov Gv, Ev */
3504 ot = dflag ? OT_LONG : OT_WORD;
3505 modrm = ldub_code(s->pc++);
3506 reg = (modrm >> 3) & 7;
3507 mod = (modrm >> 6) & 3;
3508 gen_setcc(s, b);
3509 if (mod != 3) {
3510 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3511 gen_op_ld_T1_A0[ot + s->mem_index]();
3512 } else {
3513 rm = modrm & 7;
3514 gen_op_mov_TN_reg[ot][1][rm]();
3515 }
3516 gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3517 break;
3518
3519 /************************/
3520 /* flags */
3521 case 0x9c: /* pushf */
3522 if (s->vm86 && s->iopl != 3) {
3523 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3524 } else {
3525 if (s->cc_op != CC_OP_DYNAMIC)
3526 gen_op_set_cc_op(s->cc_op);
3527 gen_op_movl_T0_eflags();
3528 gen_push_T0(s);
3529 }
3530 break;
3531 case 0x9d: /* popf */
3532 if (s->vm86 && s->iopl != 3) {
3533 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3534 } else {
3535 gen_pop_T0(s);
3536 if (s->cpl == 0) {
3537 if (s->dflag) {
3538 gen_op_movl_eflags_T0_cpl0();
3539 } else {
3540 gen_op_movw_eflags_T0_cpl0();
3541 }
3542 } else {
3543 if (s->dflag) {
3544 gen_op_movl_eflags_T0();
3545 } else {
3546 gen_op_movw_eflags_T0();
3547 }
3548 }
3549 gen_pop_update(s);
3550 s->cc_op = CC_OP_EFLAGS;
3551 /* abort translation because TF flag may change */
3552 gen_op_jmp_im(s->pc - s->cs_base);
3553 gen_eob(s);
3554 }
3555 break;
3556 case 0x9e: /* sahf */
3557 gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3558 if (s->cc_op != CC_OP_DYNAMIC)
3559 gen_op_set_cc_op(s->cc_op);
3560 gen_op_movb_eflags_T0();
3561 s->cc_op = CC_OP_EFLAGS;
3562 break;
3563 case 0x9f: /* lahf */
3564 if (s->cc_op != CC_OP_DYNAMIC)
3565 gen_op_set_cc_op(s->cc_op);
3566 gen_op_movl_T0_eflags();
3567 gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3568 break;
3569 case 0xf5: /* cmc */
3570 if (s->cc_op != CC_OP_DYNAMIC)
3571 gen_op_set_cc_op(s->cc_op);
3572 gen_op_cmc();
3573 s->cc_op = CC_OP_EFLAGS;
3574 break;
3575 case 0xf8: /* clc */
3576 if (s->cc_op != CC_OP_DYNAMIC)
3577 gen_op_set_cc_op(s->cc_op);
3578 gen_op_clc();
3579 s->cc_op = CC_OP_EFLAGS;
3580 break;
3581 case 0xf9: /* stc */
3582 if (s->cc_op != CC_OP_DYNAMIC)
3583 gen_op_set_cc_op(s->cc_op);
3584 gen_op_stc();
3585 s->cc_op = CC_OP_EFLAGS;
3586 break;
3587 case 0xfc: /* cld */
3588 gen_op_cld();
3589 break;
3590 case 0xfd: /* std */
3591 gen_op_std();
3592 break;
3593
3594 /************************/
3595 /* bit operations */
3596 case 0x1ba: /* bt/bts/btr/btc Gv, im */
3597 ot = dflag ? OT_LONG : OT_WORD;
3598 modrm = ldub_code(s->pc++);
3599 op = (modrm >> 3) & 7;
3600 mod = (modrm >> 6) & 3;
3601 rm = modrm & 7;
3602 if (mod != 3) {
3603 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3604 gen_op_ld_T0_A0[ot + s->mem_index]();
3605 } else {
3606 gen_op_mov_TN_reg[ot][0][rm]();
3607 }
3608 /* load shift */
3609 val = ldub_code(s->pc++);
3610 gen_op_movl_T1_im(val);
3611 if (op < 4)
3612 goto illegal_op;
3613 op -= 4;
3614 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3615 s->cc_op = CC_OP_SARB + ot;
3616 if (op != 0) {
3617 if (mod != 3)
3618 gen_op_st_T0_A0[ot + s->mem_index]();
3619 else
3620 gen_op_mov_reg_T0[ot][rm]();
3621 gen_op_update_bt_cc();
3622 }
3623 break;
3624 case 0x1a3: /* bt Gv, Ev */
3625 op = 0;
3626 goto do_btx;
3627 case 0x1ab: /* bts */
3628 op = 1;
3629 goto do_btx;
3630 case 0x1b3: /* btr */
3631 op = 2;
3632 goto do_btx;
3633 case 0x1bb: /* btc */
3634 op = 3;
3635 do_btx:
3636 ot = dflag ? OT_LONG : OT_WORD;
3637 modrm = ldub_code(s->pc++);
3638 reg = (modrm >> 3) & 7;
3639 mod = (modrm >> 6) & 3;
3640 rm = modrm & 7;
3641 gen_op_mov_TN_reg[OT_LONG][1][reg]();
3642 if (mod != 3) {
3643 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3644 /* specific case: we need to add a displacement */
3645 if (ot == OT_WORD)
3646 gen_op_add_bitw_A0_T1();
3647 else
3648 gen_op_add_bitl_A0_T1();
3649 gen_op_ld_T0_A0[ot + s->mem_index]();
3650 } else {
3651 gen_op_mov_TN_reg[ot][0][rm]();
3652 }
3653 gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3654 s->cc_op = CC_OP_SARB + ot;
3655 if (op != 0) {
3656 if (mod != 3)
3657 gen_op_st_T0_A0[ot + s->mem_index]();
3658 else
3659 gen_op_mov_reg_T0[ot][rm]();
3660 gen_op_update_bt_cc();
3661 }
3662 break;
3663 case 0x1bc: /* bsf */
3664 case 0x1bd: /* bsr */
3665 ot = dflag ? OT_LONG : OT_WORD;
3666 modrm = ldub_code(s->pc++);
3667 reg = (modrm >> 3) & 7;
3668 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3669 gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3670 /* NOTE: we always write back the result. Intel doc says it is
3671 undefined if T0 == 0 */
3672 gen_op_mov_reg_T0[ot][reg]();
3673 s->cc_op = CC_OP_LOGICB + ot;
3674 break;
3675 /************************/
3676 /* bcd */
3677 case 0x27: /* daa */
3678 if (s->cc_op != CC_OP_DYNAMIC)
3679 gen_op_set_cc_op(s->cc_op);
3680 gen_op_daa();
3681 s->cc_op = CC_OP_EFLAGS;
3682 break;
3683 case 0x2f: /* das */
3684 if (s->cc_op != CC_OP_DYNAMIC)
3685 gen_op_set_cc_op(s->cc_op);
3686 gen_op_das();
3687 s->cc_op = CC_OP_EFLAGS;
3688 break;
3689 case 0x37: /* aaa */
3690 if (s->cc_op != CC_OP_DYNAMIC)
3691 gen_op_set_cc_op(s->cc_op);
3692 gen_op_aaa();
3693 s->cc_op = CC_OP_EFLAGS;
3694 break;
3695 case 0x3f: /* aas */
3696 if (s->cc_op != CC_OP_DYNAMIC)
3697 gen_op_set_cc_op(s->cc_op);
3698 gen_op_aas();
3699 s->cc_op = CC_OP_EFLAGS;
3700 break;
3701 case 0xd4: /* aam */
3702 val = ldub_code(s->pc++);
3703 gen_op_aam(val);
3704 s->cc_op = CC_OP_LOGICB;
3705 break;
3706 case 0xd5: /* aad */
3707 val = ldub_code(s->pc++);
3708 gen_op_aad(val);
3709 s->cc_op = CC_OP_LOGICB;
3710 break;
3711 /************************/
3712 /* misc */
3713 case 0x90: /* nop */
3714 break;
3715 case 0x9b: /* fwait */
3716 break;
3717 case 0xcc: /* int3 */
3718 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3719 break;
3720 case 0xcd: /* int N */
3721 val = ldub_code(s->pc++);
3722 if (s->vm86 && s->iopl != 3) {
3723 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3724 } else {
3725 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3726 }
3727 break;
3728 case 0xce: /* into */
3729 if (s->cc_op != CC_OP_DYNAMIC)
3730 gen_op_set_cc_op(s->cc_op);
3731 gen_op_into(s->pc - s->cs_base);
3732 break;
3733 case 0xf1: /* icebp (undocumented, exits to external debugger) */
3734 gen_debug(s, pc_start - s->cs_base);
3735 break;
3736 case 0xfa: /* cli */
3737 if (!s->vm86) {
3738 if (s->cpl <= s->iopl) {
3739 gen_op_cli();
3740 } else {
3741 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3742 }
3743 } else {
3744 if (s->iopl == 3) {
3745 gen_op_cli();
3746 } else {
3747 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3748 }
3749 }
3750 break;
3751 case 0xfb: /* sti */
3752 if (!s->vm86) {
3753 if (s->cpl <= s->iopl) {
3754 gen_sti:
3755 gen_op_sti();
3756 /* interruptions are enabled only the first insn after sti */
3757 /* If several instructions disable interrupts, only the
3758 _first_ does it */
3759 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3760 gen_op_set_inhibit_irq();
3761 /* give a chance to handle pending irqs */
3762 gen_op_jmp_im(s->pc - s->cs_base);
3763 gen_eob(s);
3764 } else {
3765 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3766 }
3767 } else {
3768 if (s->iopl == 3) {
3769 goto gen_sti;
3770 } else {
3771 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3772 }
3773 }
3774 break;
3775 case 0x62: /* bound */
3776 ot = dflag ? OT_LONG : OT_WORD;
3777 modrm = ldub_code(s->pc++);
3778 reg = (modrm >> 3) & 7;
3779 mod = (modrm >> 6) & 3;
3780 if (mod == 3)
3781 goto illegal_op;
3782 gen_op_mov_reg_T0[ot][reg]();
3783 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3784 if (ot == OT_WORD)
3785 gen_op_boundw(pc_start - s->cs_base);
3786 else
3787 gen_op_boundl(pc_start - s->cs_base);
3788 break;
3789 case 0x1c8 ... 0x1cf: /* bswap reg */
3790 reg = b & 7;
3791 gen_op_mov_TN_reg[OT_LONG][0][reg]();
3792 gen_op_bswapl_T0();
3793 gen_op_mov_reg_T0[OT_LONG][reg]();
3794 break;
3795 case 0xd6: /* salc */
3796 if (s->cc_op != CC_OP_DYNAMIC)
3797 gen_op_set_cc_op(s->cc_op);
3798 gen_op_salc();
3799 break;
3800 case 0xe0: /* loopnz */
3801 case 0xe1: /* loopz */
3802 if (s->cc_op != CC_OP_DYNAMIC)
3803 gen_op_set_cc_op(s->cc_op);
3804 /* FALL THRU */
3805 case 0xe2: /* loop */
3806 case 0xe3: /* jecxz */
3807 val = (int8_t)insn_get(s, OT_BYTE);
3808 next_eip = s->pc - s->cs_base;
3809 val += next_eip;
3810 if (s->dflag == 0)
3811 val &= 0xffff;
3812 gen_op_loop[s->aflag][b & 3](val, next_eip);
3813 gen_eob(s);
3814 break;
3815 case 0x130: /* wrmsr */
3816 case 0x132: /* rdmsr */
3817 if (s->cpl != 0) {
3818 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3819 } else {
3820 if (b & 2)
3821 gen_op_rdmsr();
3822 else
3823 gen_op_wrmsr();
3824 }
3825 break;
3826 case 0x131: /* rdtsc */
3827 gen_op_rdtsc();
3828 break;
3829 case 0x1a2: /* cpuid */
3830 gen_op_cpuid();
3831 break;
3832 case 0xf4: /* hlt */
3833 if (s->cpl != 0) {
3834 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3835 } else {
3836 if (s->cc_op != CC_OP_DYNAMIC)
3837 gen_op_set_cc_op(s->cc_op);
3838 gen_op_jmp_im(s->pc - s->cs_base);
3839 gen_op_hlt();
3840 s->is_jmp = 3;
3841 }
3842 break;
3843 case 0x100:
3844 modrm = ldub_code(s->pc++);
3845 mod = (modrm >> 6) & 3;
3846 op = (modrm >> 3) & 7;
3847 switch(op) {
3848 case 0: /* sldt */
3849 if (!s->pe || s->vm86)
3850 goto illegal_op;
3851 gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3852 ot = OT_WORD;
3853 if (mod == 3)
3854 ot += s->dflag;
3855 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3856 break;
3857 case 2: /* lldt */
3858 if (!s->pe || s->vm86)
3859 goto illegal_op;
3860 if (s->cpl != 0) {
3861 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3862 } else {
3863 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3864 gen_op_jmp_im(pc_start - s->cs_base);
3865 gen_op_lldt_T0();
3866 }
3867 break;
3868 case 1: /* str */
3869 if (!s->pe || s->vm86)
3870 goto illegal_op;
3871 gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3872 ot = OT_WORD;
3873 if (mod == 3)
3874 ot += s->dflag;
3875 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3876 break;
3877 case 3: /* ltr */
3878 if (!s->pe || s->vm86)
3879 goto illegal_op;
3880 if (s->cpl != 0) {
3881 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3882 } else {
3883 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3884 gen_op_jmp_im(pc_start - s->cs_base);
3885 gen_op_ltr_T0();
3886 }
3887 break;
3888 case 4: /* verr */
3889 case 5: /* verw */
3890 if (!s->pe || s->vm86)
3891 goto illegal_op;
3892 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3893 if (s->cc_op != CC_OP_DYNAMIC)
3894 gen_op_set_cc_op(s->cc_op);
3895 if (op == 4)
3896 gen_op_verr();
3897 else
3898 gen_op_verw();
3899 s->cc_op = CC_OP_EFLAGS;
3900 break;
3901 default:
3902 goto illegal_op;
3903 }
3904 break;
3905 case 0x101:
3906 modrm = ldub_code(s->pc++);
3907 mod = (modrm >> 6) & 3;
3908 op = (modrm >> 3) & 7;
3909 switch(op) {
3910 case 0: /* sgdt */
3911 case 1: /* sidt */
3912 if (mod == 3)
3913 goto illegal_op;
3914 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3915 if (op == 0)
3916 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3917 else
3918 gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
3919 gen_op_st_T0_A0[OT_WORD + s->mem_index]();
3920 gen_op_addl_A0_im(2);
3921 if (op == 0)
3922 gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3923 else
3924 gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3925 if (!s->dflag)
3926 gen_op_andl_T0_im(0xffffff);
3927 gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3928 break;
3929 case 2: /* lgdt */
3930 case 3: /* lidt */
3931 if (mod == 3)
3932 goto illegal_op;
3933 if (s->cpl != 0) {
3934 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3935 } else {
3936 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3937 gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
3938 gen_op_addl_A0_im(2);
3939 gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3940 if (!s->dflag)
3941 gen_op_andl_T0_im(0xffffff);
3942 if (op == 2) {
3943 gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3944 gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3945 } else {
3946 gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3947 gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3948 }
3949 }
3950 break;
3951 case 4: /* smsw */
3952 gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
3953 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
3954 break;
3955 case 6: /* lmsw */
3956 if (s->cpl != 0) {
3957 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3958 } else {
3959 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3960 gen_op_lmsw_T0();
3961 gen_op_jmp_im(s->pc - s->cs_base);
3962 gen_eob(s);
3963 }
3964 break;
3965 case 7: /* invlpg */
3966 if (s->cpl != 0) {
3967 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3968 } else {
3969 if (mod == 3)
3970 goto illegal_op;
3971 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3972 gen_op_invlpg_A0();
3973 }
3974 break;
3975 default:
3976 goto illegal_op;
3977 }
3978 break;
3979 case 0x63: /* arpl */
3980 if (!s->pe || s->vm86)
3981 goto illegal_op;
3982 ot = dflag ? OT_LONG : OT_WORD;
3983 modrm = ldub_code(s->pc++);
3984 reg = (modrm >> 3) & 7;
3985 mod = (modrm >> 6) & 3;
3986 rm = modrm & 7;
3987 if (mod != 3) {
3988 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3989 gen_op_ld_T0_A0[ot + s->mem_index]();
3990 } else {
3991 gen_op_mov_TN_reg[ot][0][rm]();
3992 }
3993 if (s->cc_op != CC_OP_DYNAMIC)
3994 gen_op_set_cc_op(s->cc_op);
3995 gen_op_arpl();
3996 s->cc_op = CC_OP_EFLAGS;
3997 if (mod != 3) {
3998 gen_op_st_T0_A0[ot + s->mem_index]();
3999 } else {
4000 gen_op_mov_reg_T0[ot][rm]();
4001 }
4002 gen_op_arpl_update();
4003 break;
4004 case 0x102: /* lar */
4005 case 0x103: /* lsl */
4006 if (!s->pe || s->vm86)
4007 goto illegal_op;
4008 ot = dflag ? OT_LONG : OT_WORD;
4009 modrm = ldub_code(s->pc++);
4010 reg = (modrm >> 3) & 7;
4011 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4012 gen_op_mov_TN_reg[ot][1][reg]();
4013 if (s->cc_op != CC_OP_DYNAMIC)
4014 gen_op_set_cc_op(s->cc_op);
4015 if (b == 0x102)
4016 gen_op_lar();
4017 else
4018 gen_op_lsl();
4019 s->cc_op = CC_OP_EFLAGS;
4020 gen_op_mov_reg_T1[ot][reg]();
4021 break;
4022 case 0x118:
4023 modrm = ldub_code(s->pc++);
4024 mod = (modrm >> 6) & 3;
4025 op = (modrm >> 3) & 7;
4026 switch(op) {
4027 case 0: /* prefetchnta */
4028 case 1: /* prefetchnt0 */
4029 case 2: /* prefetchnt0 */
4030 case 3: /* prefetchnt0 */
4031 if (mod == 3)
4032 goto illegal_op;
4033 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4034 /* nothing more to do */
4035 break;
4036 default:
4037 goto illegal_op;
4038 }
4039 break;
4040 case 0x120: /* mov reg, crN */
4041 case 0x122: /* mov crN, reg */
4042 if (s->cpl != 0) {
4043 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4044 } else {
4045 modrm = ldub_code(s->pc++);
4046 if ((modrm & 0xc0) != 0xc0)
4047 goto illegal_op;
4048 rm = modrm & 7;
4049 reg = (modrm >> 3) & 7;
4050 switch(reg) {
4051 case 0:
4052 case 2:
4053 case 3:
4054 case 4:
4055 if (b & 2) {
4056 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4057 gen_op_movl_crN_T0(reg);
4058 gen_op_jmp_im(s->pc - s->cs_base);
4059 gen_eob(s);
4060 } else {
4061 gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4062 gen_op_mov_reg_T0[OT_LONG][rm]();
4063 }
4064 break;
4065 default:
4066 goto illegal_op;
4067 }
4068 }
4069 break;
4070 case 0x121: /* mov reg, drN */
4071 case 0x123: /* mov drN, reg */
4072 if (s->cpl != 0) {
4073 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4074 } else {
4075 modrm = ldub_code(s->pc++);
4076 if ((modrm & 0xc0) != 0xc0)
4077 goto illegal_op;
4078 rm = modrm & 7;
4079 reg = (modrm >> 3) & 7;
4080 /* XXX: do it dynamically with CR4.DE bit */
4081 if (reg == 4 || reg == 5)
4082 goto illegal_op;
4083 if (b & 2) {
4084 gen_op_mov_TN_reg[OT_LONG][0][rm]();
4085 gen_op_movl_drN_T0(reg);
4086 gen_op_jmp_im(s->pc - s->cs_base);
4087 gen_eob(s);
4088 } else {
4089 gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4090 gen_op_mov_reg_T0[OT_LONG][rm]();
4091 }
4092 }
4093 break;
4094 case 0x106: /* clts */
4095 if (s->cpl != 0) {
4096 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4097 } else {
4098 gen_op_clts();
4099 }
4100 break;
4101 default:
4102 goto illegal_op;
4103 }
4104 /* lock generation */
4105 if (s->prefix & PREFIX_LOCK)
4106 gen_op_unlock();
4107 return s->pc;
4108 illegal_op:
4109 /* XXX: ensure that no lock was generated */
4110 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4111 return s->pc;
4112 }
4113
4114 #define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4115 #define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4116
4117 /* flags read by an operation */
4118 static uint16_t opc_read_flags[NB_OPS] = {
4119 [INDEX_op_aas] = CC_A,
4120 [INDEX_op_aaa] = CC_A,
4121 [INDEX_op_das] = CC_A | CC_C,
4122 [INDEX_op_daa] = CC_A | CC_C,
4123
4124 [INDEX_op_adcb_T0_T1_cc] = CC_C,
4125 [INDEX_op_adcw_T0_T1_cc] = CC_C,
4126 [INDEX_op_adcl_T0_T1_cc] = CC_C,
4127 [INDEX_op_sbbb_T0_T1_cc] = CC_C,
4128 [INDEX_op_sbbw_T0_T1_cc] = CC_C,
4129 [INDEX_op_sbbl_T0_T1_cc] = CC_C,
4130
4131 [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
4132 [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
4133 [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
4134 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
4135 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
4136 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
4137
4138 /* subtle: due to the incl/decl implementation, C is used */
4139 [INDEX_op_update_inc_cc] = CC_C,
4140
4141 [INDEX_op_into] = CC_O,
4142
4143 [INDEX_op_jb_subb] = CC_C,
4144 [INDEX_op_jb_subw] = CC_C,
4145 [INDEX_op_jb_subl] = CC_C,
4146
4147 [INDEX_op_jz_subb] = CC_Z,
4148 [INDEX_op_jz_subw] = CC_Z,
4149 [INDEX_op_jz_subl] = CC_Z,
4150
4151 [INDEX_op_jbe_subb] = CC_Z | CC_C,
4152 [INDEX_op_jbe_subw] = CC_Z | CC_C,
4153 [INDEX_op_jbe_subl] = CC_Z | CC_C,
4154
4155 [INDEX_op_js_subb] = CC_S,
4156 [INDEX_op_js_subw] = CC_S,
4157 [INDEX_op_js_subl] = CC_S,
4158
4159 [INDEX_op_jl_subb] = CC_O | CC_S,
4160 [INDEX_op_jl_subw] = CC_O | CC_S,
4161 [INDEX_op_jl_subl] = CC_O | CC_S,
4162
4163 [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4164 [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4165 [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4166
4167 [INDEX_op_loopnzw] = CC_Z,
4168 [INDEX_op_loopnzl] = CC_Z,
4169 [INDEX_op_loopzw] = CC_Z,
4170 [INDEX_op_loopzl] = CC_Z,
4171
4172 [INDEX_op_seto_T0_cc] = CC_O,
4173 [INDEX_op_setb_T0_cc] = CC_C,
4174 [INDEX_op_setz_T0_cc] = CC_Z,
4175 [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4176 [INDEX_op_sets_T0_cc] = CC_S,
4177 [INDEX_op_setp_T0_cc] = CC_P,
4178 [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4179 [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4180
4181 [INDEX_op_setb_T0_subb] = CC_C,
4182 [INDEX_op_setb_T0_subw] = CC_C,
4183 [INDEX_op_setb_T0_subl] = CC_C,
4184
4185 [INDEX_op_setz_T0_subb] = CC_Z,
4186 [INDEX_op_setz_T0_subw] = CC_Z,
4187 [INDEX_op_setz_T0_subl] = CC_Z,
4188
4189 [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4190 [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4191 [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4192
4193 [INDEX_op_sets_T0_subb] = CC_S,
4194 [INDEX_op_sets_T0_subw] = CC_S,
4195 [INDEX_op_sets_T0_subl] = CC_S,
4196
4197 [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4198 [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4199 [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4200
4201 [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4202 [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4203 [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4204
4205 [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4206 [INDEX_op_cmc] = CC_C,
4207 [INDEX_op_salc] = CC_C,
4208
4209 [INDEX_op_rclb_T0_T1_cc] = CC_C,
4210 [INDEX_op_rclw_T0_T1_cc] = CC_C,
4211 [INDEX_op_rcll_T0_T1_cc] = CC_C,
4212 [INDEX_op_rcrb_T0_T1_cc] = CC_C,
4213 [INDEX_op_rcrw_T0_T1_cc] = CC_C,
4214 [INDEX_op_rcrl_T0_T1_cc] = CC_C,
4215
4216 [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
4217 [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
4218 [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
4219 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
4220 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
4221 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
4222 };
4223
4224 /* flags written by an operation */
4225 static uint16_t opc_write_flags[NB_OPS] = {
4226 [INDEX_op_update2_cc] = CC_OSZAPC,
4227 [INDEX_op_update1_cc] = CC_OSZAPC,
4228 [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4229 [INDEX_op_update_neg_cc] = CC_OSZAPC,
4230 /* subtle: due to the incl/decl implementation, C is used */
4231 [INDEX_op_update_inc_cc] = CC_OSZAPC,
4232 [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4233
4234 [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
4235 [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
4236 [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
4237 [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
4238 [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
4239 [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
4240
4241 [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
4242 [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
4243 [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
4244 [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
4245 [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
4246 [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
4247
4248 [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4249 [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4250 [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4251 [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4252 [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4253 [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4254 [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4255 [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4256
4257 /* bcd */
4258 [INDEX_op_aam] = CC_OSZAPC,
4259 [INDEX_op_aad] = CC_OSZAPC,
4260 [INDEX_op_aas] = CC_OSZAPC,
4261 [INDEX_op_aaa] = CC_OSZAPC,
4262 [INDEX_op_das] = CC_OSZAPC,
4263 [INDEX_op_daa] = CC_OSZAPC,
4264
4265 [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4266 [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4267 [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4268 [INDEX_op_clc] = CC_C,
4269 [INDEX_op_stc] = CC_C,
4270 [INDEX_op_cmc] = CC_C,
4271
4272 [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
4273 [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
4274 [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
4275 [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
4276 [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
4277 [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
4278
4279 [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
4280 [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
4281 [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
4282 [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
4283 [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
4284 [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
4285
4286 [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
4287 [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
4288 [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
4289
4290 [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
4291 [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
4292 [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
4293
4294 [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
4295 [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
4296 [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
4297
4298 [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
4299 [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
4300 [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
4301 [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
4302
4303 [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
4304 [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
4305 [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
4306 [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
4307
4308 [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
4309 [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
4310 [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
4311 [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
4312 [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
4313 [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
4314
4315 [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
4316 [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
4317 [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
4318 [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
4319 [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
4320 [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
4321
4322 [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
4323 [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
4324 [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
4325
4326 [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
4327 [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
4328 [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
4329
4330 [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
4331 [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
4332 [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
4333
4334 [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4335 [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4336 [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
4337 [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
4338
4339 [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4340 [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4341 [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
4342 [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
4343
4344 [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4345 [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4346 [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4347 [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4348 [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4349 [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4350 [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4351 [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4352
4353 [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4354 [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4355 [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4356 [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4357
4358 [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4359 [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4360 [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4361
4362 [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4363 [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4364 [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4365
4366 [INDEX_op_cmpxchg8b] = CC_Z,
4367 [INDEX_op_lar] = CC_Z,
4368 [INDEX_op_lsl] = CC_Z,
4369 [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4370 [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4371 };
4372
4373 /* simpler form of an operation if no flags need to be generated */
4374 static uint16_t opc_simpler[NB_OPS] = {
4375 [INDEX_op_update2_cc] = INDEX_op_nop,
4376 [INDEX_op_update1_cc] = INDEX_op_nop,
4377 [INDEX_op_update_neg_cc] = INDEX_op_nop,
4378 #if 0
4379 /* broken: CC_OP logic must be rewritten */
4380 [INDEX_op_update_inc_cc] = INDEX_op_nop,
4381 #endif
4382 [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
4383 [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
4384 [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
4385
4386 [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
4387 [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4388 [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4389
4390 [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4391 [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4392 [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4393
4394 [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4395 [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4396 [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4397
4398 [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4399 [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4400 [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4401
4402 [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4403 [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4404 [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4405
4406 [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4407 [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4408 [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4409 };
4410
4411 void optimize_flags_init(void)
4412 {
4413 int i;
4414 /* put default values in arrays */
4415 for(i = 0; i < NB_OPS; i++) {
4416 if (opc_simpler[i] == 0)
4417 opc_simpler[i] = i;
4418 }
4419 }
4420
4421 /* CPU flags computation optimization: we move backward thru the
4422 generated code to see which flags are needed. The operation is
4423 modified if suitable */
4424 static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4425 {
4426 uint16_t *opc_ptr;
4427 int live_flags, write_flags, op;
4428
4429 opc_ptr = opc_buf + opc_buf_len;
4430 /* live_flags contains the flags needed by the next instructions
4431 in the code. At the end of the bloc, we consider that all the
4432 flags are live. */
4433 live_flags = CC_OSZAPC;
4434 while (opc_ptr > opc_buf) {
4435 op = *--opc_ptr;
4436 /* if none of the flags written by the instruction is used,
4437 then we can try to find a simpler instruction */
4438 write_flags = opc_write_flags[op];
4439 if ((live_flags & write_flags) == 0) {
4440 *opc_ptr = opc_simpler[op];
4441 }
4442 /* compute the live flags before the instruction */
4443 live_flags &= ~write_flags;
4444 live_flags |= opc_read_flags[op];
4445 }
4446 }
4447
4448 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4449 basic block 'tb'. If search_pc is TRUE, also generate PC
4450 information for each intermediate instruction. */
4451 static inline int gen_intermediate_code_internal(CPUState *env,
4452 TranslationBlock *tb,
4453 int search_pc)
4454 {
4455 DisasContext dc1, *dc = &dc1;
4456 uint8_t *pc_ptr;
4457 uint16_t *gen_opc_end;
4458 int flags, j, lj;
4459 uint8_t *pc_start;
4460 uint8_t *cs_base;
4461
4462 /* generate intermediate code */
4463 pc_start = (uint8_t *)tb->pc;
4464 cs_base = (uint8_t *)tb->cs_base;
4465 flags = tb->flags;
4466
4467 dc->pe = env->cr[0] & CR0_PE_MASK;
4468 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4469 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4470 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4471 dc->f_st = 0;
4472 dc->vm86 = (flags >> VM_SHIFT) & 1;
4473 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4474 dc->iopl = (flags >> IOPL_SHIFT) & 3;
4475 dc->tf = (flags >> TF_SHIFT) & 1;
4476 dc->singlestep_enabled = env->singlestep_enabled;
4477 dc->cc_op = CC_OP_DYNAMIC;
4478 dc->cs_base = cs_base;
4479 dc->tb = tb;
4480 dc->popl_esp_hack = 0;
4481 /* select memory access functions */
4482 dc->mem_index = 0;
4483 if (flags & HF_SOFTMMU_MASK) {
4484 if (dc->cpl == 3)
4485 dc->mem_index = 6;
4486 else
4487 dc->mem_index = 3;
4488 }
4489 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
4490 (flags & HF_INHIBIT_IRQ_MASK)
4491 #ifndef CONFIG_SOFTMMU
4492 || (flags & HF_SOFTMMU_MASK)
4493 #endif
4494 );
4495 gen_opc_ptr = gen_opc_buf;
4496 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4497 gen_opparam_ptr = gen_opparam_buf;
4498
4499 dc->is_jmp = DISAS_NEXT;
4500 pc_ptr = pc_start;
4501 lj = -1;
4502
4503 for(;;) {
4504 if (env->nb_breakpoints > 0) {
4505 for(j = 0; j < env->nb_breakpoints; j++) {
4506 if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4507 gen_debug(dc, pc_ptr - dc->cs_base);
4508 break;
4509 }
4510 }
4511 }
4512 if (search_pc) {
4513 j = gen_opc_ptr - gen_opc_buf;
4514 if (lj < j) {
4515 lj++;
4516 while (lj < j)
4517 gen_opc_instr_start[lj++] = 0;
4518 }
4519 gen_opc_pc[lj] = (uint32_t)pc_ptr;
4520 gen_opc_cc_op[lj] = dc->cc_op;
4521 gen_opc_instr_start[lj] = 1;
4522 }
4523 pc_ptr = disas_insn(dc, pc_ptr);
4524 /* stop translation if indicated */
4525 if (dc->is_jmp)
4526 break;
4527 /* if single step mode, we generate only one instruction and
4528 generate an exception */
4529 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4530 the flag and abort the translation to give the irqs a
4531 change to be happen */
4532 if (dc->tf || dc->singlestep_enabled ||
4533 (flags & HF_INHIBIT_IRQ_MASK)) {
4534 gen_op_jmp_im(pc_ptr - dc->cs_base);
4535 gen_eob(dc);
4536 break;
4537 }
4538 /* if too long translation, stop generation too */
4539 if (gen_opc_ptr >= gen_opc_end ||
4540 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4541 gen_op_jmp_im(pc_ptr - dc->cs_base);
4542 gen_eob(dc);
4543 break;
4544 }
4545 }
4546 *gen_opc_ptr = INDEX_op_end;
4547 /* we don't forget to fill the last values */
4548 if (search_pc) {
4549 j = gen_opc_ptr - gen_opc_buf;
4550 lj++;
4551 while (lj <= j)
4552 gen_opc_instr_start[lj++] = 0;
4553 }
4554
4555 #ifdef DEBUG_DISAS
4556 if (loglevel) {
4557 fprintf(logfile, "----------------\n");
4558 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4559 disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4560 fprintf(logfile, "\n");
4561
4562 fprintf(logfile, "OP:\n");
4563 dump_ops(gen_opc_buf, gen_opparam_buf);
4564 fprintf(logfile, "\n");
4565 }
4566 #endif
4567
4568 /* optimize flag computations */
4569 optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4570
4571 #ifdef DEBUG_DISAS
4572 if (loglevel) {
4573 fprintf(logfile, "AFTER FLAGS OPT:\n");
4574 dump_ops(gen_opc_buf, gen_opparam_buf);
4575 fprintf(logfile, "\n");
4576 }
4577 #endif
4578 if (!search_pc)
4579 tb->size = pc_ptr - pc_start;
4580 return 0;
4581 }
4582
4583 int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4584 {
4585 return gen_intermediate_code_internal(env, tb, 0);
4586 }
4587
4588 int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4589 {
4590 return gen_intermediate_code_internal(env, tb, 1);
4591 }
4592
Qemu copy for testing