4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
63 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
;
64 static TCGv_i32 cpu_cc_op
;
65 static TCGv cpu_regs
[CPU_NB_REGS
];
67 static TCGv cpu_T
[2], cpu_T3
;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0
, cpu_tmp4
;
70 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
71 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
72 static TCGv_i64 cpu_tmp1_i64
;
75 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
77 #include "exec/gen-icount.h"
80 static int x86_64_hregs
;
83 typedef struct DisasContext
{
84 /* current insn context */
85 int override
; /* -1 if no override */
88 target_ulong pc
; /* pc = eip + cs_base */
89 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
90 static state change (stop translation) */
91 /* current block context */
92 target_ulong cs_base
; /* base of CS segment */
93 int pe
; /* protected mode */
94 int code32
; /* 32 bit code segment */
96 int lma
; /* long mode active */
97 int code64
; /* 64 bit code segment */
100 int ss32
; /* 32 bit stack segment */
101 CCOp cc_op
; /* current CC operation */
103 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
104 int f_st
; /* currently unused */
105 int vm86
; /* vm86 mode */
108 int tf
; /* TF cpu flag */
109 int singlestep_enabled
; /* "hardware" single step enabled */
110 int jmp_opt
; /* use direct block chaining for direct jumps */
111 int mem_index
; /* select memory access functions */
112 uint64_t flags
; /* all execution flags */
113 struct TranslationBlock
*tb
;
114 int popl_esp_hack
; /* for correct popl with esp base handling */
115 int rip_offset
; /* only used in x86_64, but left for simplicity */
117 int cpuid_ext_features
;
118 int cpuid_ext2_features
;
119 int cpuid_ext3_features
;
120 int cpuid_7_0_ebx_features
;
123 static void gen_eob(DisasContext
*s
);
124 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
125 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
127 /* i386 arith/logic operations */
147 OP_SHL1
, /* undocumented */
171 /* I386 int registers */
172 OR_EAX
, /* MUST be even numbered */
181 OR_TMP0
= 16, /* temporary operand register */
183 OR_A0
, /* temporary register used when doing address evaluation */
191 /* Bit set if the global variable is live after setting CC_OP to X. */
192 static const uint8_t cc_op_live
[CC_OP_NB
] = {
193 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
,
194 [CC_OP_EFLAGS
] = USES_CC_SRC
,
195 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
196 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
197 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
,
198 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
,
199 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
201 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
207 static void set_cc_op(DisasContext
*s
, CCOp op
)
211 if (s
->cc_op
== op
) {
215 /* Discard CC computation that will no longer be used. */
216 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
217 if (dead
& USES_CC_DST
) {
218 tcg_gen_discard_tl(cpu_cc_dst
);
220 if (dead
& USES_CC_SRC
) {
221 tcg_gen_discard_tl(cpu_cc_src
);
225 /* The DYNAMIC setting is translator only, and should never be
226 stored. Thus we always consider it clean. */
227 s
->cc_op_dirty
= (op
!= CC_OP_DYNAMIC
);
230 static void gen_update_cc_op(DisasContext
*s
)
232 if (s
->cc_op_dirty
) {
233 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
234 s
->cc_op_dirty
= false;
238 static inline void gen_op_movl_T0_0(void)
240 tcg_gen_movi_tl(cpu_T
[0], 0);
243 static inline void gen_op_movl_T0_im(int32_t val
)
245 tcg_gen_movi_tl(cpu_T
[0], val
);
248 static inline void gen_op_movl_T0_imu(uint32_t val
)
250 tcg_gen_movi_tl(cpu_T
[0], val
);
253 static inline void gen_op_movl_T1_im(int32_t val
)
255 tcg_gen_movi_tl(cpu_T
[1], val
);
258 static inline void gen_op_movl_T1_imu(uint32_t val
)
260 tcg_gen_movi_tl(cpu_T
[1], val
);
263 static inline void gen_op_movl_A0_im(uint32_t val
)
265 tcg_gen_movi_tl(cpu_A0
, val
);
269 static inline void gen_op_movq_A0_im(int64_t val
)
271 tcg_gen_movi_tl(cpu_A0
, val
);
275 static inline void gen_movtl_T0_im(target_ulong val
)
277 tcg_gen_movi_tl(cpu_T
[0], val
);
280 static inline void gen_movtl_T1_im(target_ulong val
)
282 tcg_gen_movi_tl(cpu_T
[1], val
);
285 static inline void gen_op_andl_T0_ffff(void)
287 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
290 static inline void gen_op_andl_T0_im(uint32_t val
)
292 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
295 static inline void gen_op_movl_T0_T1(void)
297 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
300 static inline void gen_op_andl_A0_ffff(void)
302 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
307 #define NB_OP_SIZES 4
309 #else /* !TARGET_X86_64 */
311 #define NB_OP_SIZES 3
313 #endif /* !TARGET_X86_64 */
315 #if defined(HOST_WORDS_BIGENDIAN)
316 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
317 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
318 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
319 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
320 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
322 #define REG_B_OFFSET 0
323 #define REG_H_OFFSET 1
324 #define REG_W_OFFSET 0
325 #define REG_L_OFFSET 0
326 #define REG_LH_OFFSET 4
329 /* In instruction encodings for byte register accesses the
330 * register number usually indicates "low 8 bits of register N";
331 * however there are some special cases where N 4..7 indicates
332 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
333 * true for this special case, false otherwise.
335 static inline bool byte_reg_is_xH(int reg
)
341 if (reg
>= 8 || x86_64_hregs
) {
348 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
352 if (!byte_reg_is_xH(reg
)) {
353 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
355 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
359 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
361 default: /* XXX this shouldn't be reached; abort? */
363 /* For x86_64, this sets the higher half of register to zero.
364 For i386, this is equivalent to a mov. */
365 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
369 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
375 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
377 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
380 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
382 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
385 static inline void gen_op_mov_reg_A0(int size
, int reg
)
389 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
391 default: /* XXX this shouldn't be reached; abort? */
393 /* For x86_64, this sets the higher half of register to zero.
394 For i386, this is equivalent to a mov. */
395 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
399 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
405 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
407 if (ot
== OT_BYTE
&& byte_reg_is_xH(reg
)) {
408 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
409 tcg_gen_ext8u_tl(t0
, t0
);
411 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
415 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
417 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
420 static inline void gen_op_movl_A0_reg(int reg
)
422 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
425 static inline void gen_op_addl_A0_im(int32_t val
)
427 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
429 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
434 static inline void gen_op_addq_A0_im(int64_t val
)
436 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
440 static void gen_add_A0_im(DisasContext
*s
, int val
)
444 gen_op_addq_A0_im(val
);
447 gen_op_addl_A0_im(val
);
450 static inline void gen_op_addl_T0_T1(void)
452 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
455 static inline void gen_op_jmp_T0(void)
457 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
460 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
464 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
465 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
468 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
469 /* For x86_64, this sets the higher half of register to zero.
470 For i386, this is equivalent to a nop. */
471 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
472 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
476 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
482 static inline void gen_op_add_reg_T0(int size
, int reg
)
486 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
487 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
490 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
491 /* For x86_64, this sets the higher half of register to zero.
492 For i386, this is equivalent to a nop. */
493 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
494 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
498 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
504 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
506 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
508 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
509 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
510 /* For x86_64, this sets the higher half of register to zero.
511 For i386, this is equivalent to a nop. */
512 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
515 static inline void gen_op_movl_A0_seg(int reg
)
517 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
520 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
522 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
525 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
526 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
528 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
529 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
532 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
537 static inline void gen_op_movq_A0_seg(int reg
)
539 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
542 static inline void gen_op_addq_A0_seg(int reg
)
544 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
545 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
548 static inline void gen_op_movq_A0_reg(int reg
)
550 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
553 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
555 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
557 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
558 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
562 static inline void gen_op_lds_T0_A0(int idx
)
564 int mem_index
= (idx
>> 2) - 1;
567 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
570 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
574 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
579 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
581 int mem_index
= (idx
>> 2) - 1;
584 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
587 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
590 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
594 /* Should never happen on 32-bit targets. */
596 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
602 /* XXX: always use ldu or lds */
603 static inline void gen_op_ld_T0_A0(int idx
)
605 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
608 static inline void gen_op_ldu_T0_A0(int idx
)
610 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
613 static inline void gen_op_ld_T1_A0(int idx
)
615 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
618 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
620 int mem_index
= (idx
>> 2) - 1;
623 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
626 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
629 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
633 /* Should never happen on 32-bit targets. */
635 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
641 static inline void gen_op_st_T0_A0(int idx
)
643 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
646 static inline void gen_op_st_T1_A0(int idx
)
648 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
651 static inline void gen_jmp_im(target_ulong pc
)
653 tcg_gen_movi_tl(cpu_tmp0
, pc
);
654 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
657 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
661 override
= s
->override
;
665 gen_op_movq_A0_seg(override
);
666 gen_op_addq_A0_reg_sN(0, R_ESI
);
668 gen_op_movq_A0_reg(R_ESI
);
674 if (s
->addseg
&& override
< 0)
677 gen_op_movl_A0_seg(override
);
678 gen_op_addl_A0_reg_sN(0, R_ESI
);
680 gen_op_movl_A0_reg(R_ESI
);
683 /* 16 address, always override */
686 gen_op_movl_A0_reg(R_ESI
);
687 gen_op_andl_A0_ffff();
688 gen_op_addl_A0_seg(s
, override
);
692 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
696 gen_op_movq_A0_reg(R_EDI
);
701 gen_op_movl_A0_seg(R_ES
);
702 gen_op_addl_A0_reg_sN(0, R_EDI
);
704 gen_op_movl_A0_reg(R_EDI
);
707 gen_op_movl_A0_reg(R_EDI
);
708 gen_op_andl_A0_ffff();
709 gen_op_addl_A0_seg(s
, R_ES
);
713 static inline void gen_op_movl_T0_Dshift(int ot
)
715 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
716 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
719 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
724 tcg_gen_ext8s_tl(dst
, src
);
726 tcg_gen_ext8u_tl(dst
, src
);
731 tcg_gen_ext16s_tl(dst
, src
);
733 tcg_gen_ext16u_tl(dst
, src
);
739 tcg_gen_ext32s_tl(dst
, src
);
741 tcg_gen_ext32u_tl(dst
, src
);
750 static void gen_extu(int ot
, TCGv reg
)
752 gen_ext_tl(reg
, reg
, ot
, false);
755 static void gen_exts(int ot
, TCGv reg
)
757 gen_ext_tl(reg
, reg
, ot
, true);
760 static inline void gen_op_jnz_ecx(int size
, int label1
)
762 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
763 gen_extu(size
+ 1, cpu_tmp0
);
764 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
767 static inline void gen_op_jz_ecx(int size
, int label1
)
769 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
770 gen_extu(size
+ 1, cpu_tmp0
);
771 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
774 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
778 gen_helper_inb(v
, n
);
781 gen_helper_inw(v
, n
);
784 gen_helper_inl(v
, n
);
789 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
793 gen_helper_outb(v
, n
);
796 gen_helper_outw(v
, n
);
799 gen_helper_outl(v
, n
);
804 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
808 target_ulong next_eip
;
811 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
815 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
818 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
821 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
824 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
828 if(s
->flags
& HF_SVMI_MASK
) {
833 svm_flags
|= (1 << (4 + ot
));
834 next_eip
= s
->pc
- s
->cs_base
;
835 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
836 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
837 tcg_const_i32(svm_flags
),
838 tcg_const_i32(next_eip
- cur_eip
));
842 static inline void gen_movs(DisasContext
*s
, int ot
)
844 gen_string_movl_A0_ESI(s
);
845 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
846 gen_string_movl_A0_EDI(s
);
847 gen_op_st_T0_A0(ot
+ s
->mem_index
);
848 gen_op_movl_T0_Dshift(ot
);
849 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
850 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
853 static void gen_op_update1_cc(void)
855 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
858 static void gen_op_update2_cc(void)
860 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
861 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
864 static inline void gen_op_cmpl_T0_T1_cc(void)
866 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
867 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
870 static inline void gen_op_testl_T0_T1_cc(void)
872 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
875 static void gen_op_update_neg_cc(void)
877 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
878 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
881 /* compute all eflags to cc_src */
882 static void gen_compute_eflags(DisasContext
*s
)
884 if (s
->cc_op
== CC_OP_EFLAGS
) {
888 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
889 set_cc_op(s
, CC_OP_EFLAGS
);
890 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
893 typedef struct CCPrepare
{
903 /* compute eflags.C to reg */
904 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
910 case CC_OP_SUBB
... CC_OP_SUBQ
:
911 /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
912 size
= s
->cc_op
- CC_OP_SUBB
;
913 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
914 /* If no temporary was used, be careful not to alias t1 and t0. */
915 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
916 tcg_gen_add_tl(t0
, cpu_cc_dst
, cpu_cc_src
);
920 case CC_OP_ADDB
... CC_OP_ADDQ
:
921 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
922 size
= s
->cc_op
- CC_OP_ADDB
;
923 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
924 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
926 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
927 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
929 case CC_OP_SBBB
... CC_OP_SBBQ
:
930 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
931 size
= s
->cc_op
- CC_OP_SBBB
;
932 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
933 if (TCGV_EQUAL(t1
, reg
) && TCGV_EQUAL(reg
, cpu_cc_src
)) {
934 tcg_gen_mov_tl(cpu_tmp0
, cpu_cc_src
);
938 tcg_gen_add_tl(reg
, cpu_cc_dst
, cpu_cc_src
);
939 tcg_gen_addi_tl(reg
, reg
, 1);
944 case CC_OP_ADCB
... CC_OP_ADCQ
:
945 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
946 size
= s
->cc_op
- CC_OP_ADCB
;
947 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
948 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
950 return (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= t0
,
951 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
953 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
954 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
956 case CC_OP_INCB
... CC_OP_INCQ
:
957 case CC_OP_DECB
... CC_OP_DECQ
:
958 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
959 .mask
= -1, .no_setcond
= true };
961 case CC_OP_SHLB
... CC_OP_SHLQ
:
962 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
963 size
= s
->cc_op
- CC_OP_SHLB
;
964 shift
= (8 << size
) - 1;
965 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
966 .mask
= (target_ulong
)1 << shift
};
968 case CC_OP_MULB
... CC_OP_MULQ
:
969 return (CCPrepare
) { .cond
= TCG_COND_NE
,
970 .reg
= cpu_cc_src
, .mask
= -1 };
973 case CC_OP_SARB
... CC_OP_SARQ
:
975 return (CCPrepare
) { .cond
= TCG_COND_NE
,
976 .reg
= cpu_cc_src
, .mask
= CC_C
};
979 /* The need to compute only C from CC_OP_DYNAMIC is important
980 in efficiently implementing e.g. INC at the start of a TB. */
982 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
983 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
984 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
985 .mask
= -1, .no_setcond
= true };
989 /* compute eflags.P to reg */
990 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
992 gen_compute_eflags(s
);
993 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
997 /* compute eflags.S to reg */
998 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
1002 gen_compute_eflags(s
);
1005 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1009 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1010 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
1011 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
1016 /* compute eflags.O to reg */
1017 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
1019 gen_compute_eflags(s
);
1020 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1024 /* compute eflags.Z to reg */
1025 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
1029 gen_compute_eflags(s
);
1032 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1036 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1037 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1038 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
1043 #define gen_compute_eflags_c(s, reg, inv) \
1044 gen_do_setcc(reg, gen_prepare_eflags_c(s, reg), inv)
1045 #define gen_compute_eflags_p(s, reg) \
1046 gen_do_setcc(reg, gen_prepare_eflags_p(s, reg), false)
1047 #define gen_compute_eflags_s(s, reg, inv) \
1048 gen_do_setcc(reg, gen_prepare_eflags_s(s, reg), inv)
1049 #define gen_compute_eflags_o(s, reg) \
1050 gen_do_setcc(reg, gen_prepare_eflags_o(s, reg), false)
1051 #define gen_compute_eflags_z(s, reg, inv) \
1052 gen_do_setcc(reg, gen_prepare_eflags_z(s, reg), inv)
1054 static void gen_do_setcc(TCGv reg
, struct CCPrepare cc
, bool inv
)
1057 cc
.cond
= tcg_invert_cond(cc
.cond
);
1060 if (cc
.no_setcond
) {
1061 if (cc
.cond
== TCG_COND_EQ
) {
1062 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1064 tcg_gen_mov_tl(reg
, cc
.reg
);
1069 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1070 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1071 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1072 tcg_gen_andi_tl(reg
, reg
, 1);
1075 if (cc
.mask
!= -1) {
1076 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1079 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1081 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1085 static void gen_setcc_slow(DisasContext
*s
, int jcc_op
, TCGv reg
, bool inv
)
1089 gen_compute_eflags_o(s
, reg
);
1092 gen_compute_eflags_c(s
, reg
, inv
);
1096 gen_compute_eflags_z(s
, reg
, inv
);
1100 gen_compute_eflags(s
);
1101 tcg_gen_andi_tl(reg
, cpu_cc_src
, CC_Z
| CC_C
);
1102 tcg_gen_setcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, reg
, reg
, 0);
1105 gen_compute_eflags_s(s
, reg
, inv
);
1109 gen_compute_eflags_p(s
, reg
);
1112 gen_compute_eflags(s
);
1113 tcg_gen_shri_tl(cpu_tmp0
, cpu_cc_src
, 11); /* CC_O */
1114 tcg_gen_shri_tl(reg
, cpu_cc_src
, 7); /* CC_S */
1115 tcg_gen_xor_tl(reg
, reg
, cpu_tmp0
);
1116 tcg_gen_andi_tl(reg
, reg
, 1);
1120 gen_compute_eflags(s
);
1121 tcg_gen_shri_tl(cpu_tmp0
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1122 tcg_gen_xor_tl(reg
, cpu_tmp0
, cpu_cc_src
);
1123 tcg_gen_andi_tl(reg
, reg
, CC_S
| CC_Z
);
1124 tcg_gen_setcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, reg
, reg
, 0);
1128 tcg_gen_xori_tl(reg
, reg
, 1);
1132 /* perform a conditional store into register 'reg' according to jump opcode
1133 value 'b'. In the fast case, T0 is guaranted not to be used. */
1134 static inline void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1136 int inv
, jcc_op
, size
, cond
;
1140 jcc_op
= (b
>> 1) & 7;
1143 /* we optimize relational operators for the cmp/jcc case */
1148 size
= s
->cc_op
- CC_OP_SUBB
;
1151 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1152 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1153 gen_extu(size
, cpu_tmp4
);
1154 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1155 tcg_gen_setcond_tl(cond
, reg
, cpu_tmp4
, t0
);
1159 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1162 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1164 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1165 gen_exts(size
, cpu_tmp4
);
1166 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1167 tcg_gen_setcond_tl(cond
, reg
, cpu_tmp4
, t0
);
1177 /* gen_setcc_slow actually generates good code for JC, JZ and JS */
1178 gen_setcc_slow(s
, jcc_op
, reg
, inv
);
1183 /* generate a conditional jump to label 'l1' according to jump opcode
1184 value 'b'. In the fast case, T0 is guaranted not to be used. */
1185 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1187 int inv
, jcc_op
, size
, cond
;
1191 jcc_op
= (b
>> 1) & 7;
1194 /* we optimize the cmp/jcc case */
1200 size
= s
->cc_op
- CC_OP_SUBB
;
1204 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_dst
, size
, false);
1205 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
1209 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_dst
, size
, true);
1210 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, t0
, 0, l1
);
1214 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1217 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1219 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1220 gen_extu(size
, cpu_tmp4
);
1221 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1222 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1226 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1229 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1231 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1232 gen_exts(size
, cpu_tmp4
);
1233 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1234 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1242 /* some jumps are easy to compute */
1284 size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1287 size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1295 gen_setcc_slow(s
, jcc_op
, cpu_T
[0], false);
1296 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1302 /* XXX: does not work with gdbstub "ice" single step - not a
1304 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1308 l1
= gen_new_label();
1309 l2
= gen_new_label();
1310 gen_op_jnz_ecx(s
->aflag
, l1
);
1312 gen_jmp_tb(s
, next_eip
, 1);
1317 static inline void gen_stos(DisasContext
*s
, int ot
)
1319 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1320 gen_string_movl_A0_EDI(s
);
1321 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1322 gen_op_movl_T0_Dshift(ot
);
1323 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1326 static inline void gen_lods(DisasContext
*s
, int ot
)
1328 gen_string_movl_A0_ESI(s
);
1329 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1330 gen_op_mov_reg_T0(ot
, R_EAX
);
1331 gen_op_movl_T0_Dshift(ot
);
1332 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1335 static inline void gen_scas(DisasContext
*s
, int ot
)
1337 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1338 gen_string_movl_A0_EDI(s
);
1339 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1340 gen_op_cmpl_T0_T1_cc();
1341 gen_op_movl_T0_Dshift(ot
);
1342 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1343 set_cc_op(s
, CC_OP_SUBB
+ ot
);
1346 static inline void gen_cmps(DisasContext
*s
, int ot
)
1348 gen_string_movl_A0_ESI(s
);
1349 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1350 gen_string_movl_A0_EDI(s
);
1351 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1352 gen_op_cmpl_T0_T1_cc();
1353 gen_op_movl_T0_Dshift(ot
);
1354 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1355 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1356 set_cc_op(s
, CC_OP_SUBB
+ ot
);
1359 static inline void gen_ins(DisasContext
*s
, int ot
)
1363 gen_string_movl_A0_EDI(s
);
1364 /* Note: we must do this dummy write first to be restartable in
1365 case of page fault. */
1367 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1368 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1369 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1370 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1371 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1372 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1373 gen_op_movl_T0_Dshift(ot
);
1374 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1379 static inline void gen_outs(DisasContext
*s
, int ot
)
1383 gen_string_movl_A0_ESI(s
);
1384 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1386 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1387 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1388 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1389 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1390 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1392 gen_op_movl_T0_Dshift(ot
);
1393 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1398 /* same method as Valgrind : we generate jumps to current or next
1400 #define GEN_REPZ(op) \
1401 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1402 target_ulong cur_eip, target_ulong next_eip) \
1405 gen_update_cc_op(s); \
1406 l2 = gen_jz_ecx_string(s, next_eip); \
1407 gen_ ## op(s, ot); \
1408 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1409 /* a loop would cause two single step exceptions if ECX = 1 \
1410 before rep string_insn */ \
1412 gen_op_jz_ecx(s->aflag, l2); \
1413 gen_jmp(s, cur_eip); \
1416 #define GEN_REPZ2(op) \
1417 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1418 target_ulong cur_eip, \
1419 target_ulong next_eip, \
1423 gen_update_cc_op(s); \
1424 l2 = gen_jz_ecx_string(s, next_eip); \
1425 gen_ ## op(s, ot); \
1426 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1427 gen_update_cc_op(s); \
1428 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1430 gen_op_jz_ecx(s->aflag, l2); \
1431 gen_jmp(s, cur_eip); \
1432 set_cc_op(s, CC_OP_DYNAMIC); \
1443 static void gen_helper_fp_arith_ST0_FT0(int op
)
1447 gen_helper_fadd_ST0_FT0(cpu_env
);
1450 gen_helper_fmul_ST0_FT0(cpu_env
);
1453 gen_helper_fcom_ST0_FT0(cpu_env
);
1456 gen_helper_fcom_ST0_FT0(cpu_env
);
1459 gen_helper_fsub_ST0_FT0(cpu_env
);
1462 gen_helper_fsubr_ST0_FT0(cpu_env
);
1465 gen_helper_fdiv_ST0_FT0(cpu_env
);
1468 gen_helper_fdivr_ST0_FT0(cpu_env
);
1473 /* NOTE the exception in "r" op ordering */
1474 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1476 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1479 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1482 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1485 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1488 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1491 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1494 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1499 /* if d == OR_TMP0, it means memory operand (address in A0) */
1500 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1503 gen_op_mov_TN_reg(ot
, 0, d
);
1505 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1509 gen_compute_eflags_c(s1
, cpu_tmp4
, false);
1510 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1511 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1513 gen_op_mov_reg_T0(ot
, d
);
1515 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1516 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1517 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1518 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1519 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1520 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1521 set_cc_op(s1
, CC_OP_DYNAMIC
);
1524 gen_compute_eflags_c(s1
, cpu_tmp4
, false);
1525 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1526 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1528 gen_op_mov_reg_T0(ot
, d
);
1530 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1531 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1532 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1533 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1534 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1535 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1536 set_cc_op(s1
, CC_OP_DYNAMIC
);
1539 gen_op_addl_T0_T1();
1541 gen_op_mov_reg_T0(ot
, d
);
1543 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1544 gen_op_update2_cc();
1545 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1548 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1550 gen_op_mov_reg_T0(ot
, d
);
1552 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1553 gen_op_update2_cc();
1554 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1558 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1560 gen_op_mov_reg_T0(ot
, d
);
1562 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1563 gen_op_update1_cc();
1564 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1567 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1569 gen_op_mov_reg_T0(ot
, d
);
1571 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1572 gen_op_update1_cc();
1573 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1576 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1578 gen_op_mov_reg_T0(ot
, d
);
1580 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1581 gen_op_update1_cc();
1582 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1585 gen_op_cmpl_T0_T1_cc();
1586 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1591 /* if d == OR_TMP0, it means memory operand (address in A0) */
1592 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1595 gen_op_mov_TN_reg(ot
, 0, d
);
1597 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1598 gen_compute_eflags_c(s1
, cpu_cc_src
, false);
1600 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1601 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1603 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1604 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1607 gen_op_mov_reg_T0(ot
, d
);
1609 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1610 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1613 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1614 int is_right
, int is_arith
)
1620 if (ot
== OT_QUAD
) {
1627 if (op1
== OR_TMP0
) {
1628 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1630 gen_op_mov_TN_reg(ot
, 0, op1
);
1633 t0
= tcg_temp_local_new();
1634 t1
= tcg_temp_local_new();
1635 t2
= tcg_temp_local_new();
1637 tcg_gen_andi_tl(t2
, cpu_T
[1], mask
);
1641 gen_exts(ot
, cpu_T
[0]);
1642 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1643 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], t2
);
1645 gen_extu(ot
, cpu_T
[0]);
1646 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1647 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], t2
);
1650 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1651 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], t2
);
1655 if (op1
== OR_TMP0
) {
1656 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1658 gen_op_mov_reg_T0(ot
, op1
);
1662 gen_update_cc_op(s
);
1664 tcg_gen_mov_tl(t1
, cpu_T
[0]);
1666 shift_label
= gen_new_label();
1667 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, shift_label
);
1669 tcg_gen_addi_tl(t2
, t2
, -1);
1670 tcg_gen_mov_tl(cpu_cc_dst
, t1
);
1674 tcg_gen_sar_tl(cpu_cc_src
, t0
, t2
);
1676 tcg_gen_shr_tl(cpu_cc_src
, t0
, t2
);
1679 tcg_gen_shl_tl(cpu_cc_src
, t0
, t2
);
1683 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1685 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1688 gen_set_label(shift_label
);
1689 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
1696 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1697 int is_right
, int is_arith
)
1708 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1710 gen_op_mov_TN_reg(ot
, 0, op1
);
1716 gen_exts(ot
, cpu_T
[0]);
1717 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1718 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1720 gen_extu(ot
, cpu_T
[0]);
1721 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1722 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1725 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1726 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1732 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1734 gen_op_mov_reg_T0(ot
, op1
);
1736 /* update eflags if non zero shift */
1738 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1739 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1740 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1744 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1747 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1749 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1752 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1756 int label1
, label2
, data_bits
;
1757 TCGv t0
, t1
, t2
, a0
;
1759 /* XXX: inefficient, but we must use local temps */
1760 t0
= tcg_temp_local_new();
1761 t1
= tcg_temp_local_new();
1762 t2
= tcg_temp_local_new();
1763 a0
= tcg_temp_local_new();
1771 if (op1
== OR_TMP0
) {
1772 tcg_gen_mov_tl(a0
, cpu_A0
);
1773 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1775 gen_op_mov_v_reg(ot
, t0
, op1
);
1778 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1780 tcg_gen_andi_tl(t1
, t1
, mask
);
1782 /* Must test zero case to avoid using undefined behaviour in TCG
1784 label1
= gen_new_label();
1785 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1788 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1790 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1793 tcg_gen_mov_tl(t2
, t0
);
1795 data_bits
= 8 << ot
;
1796 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1797 fix TCG definition) */
1799 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1800 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1801 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1803 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1804 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1805 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1807 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1809 gen_set_label(label1
);
1811 if (op1
== OR_TMP0
) {
1812 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1814 gen_op_mov_reg_v(ot
, op1
, t0
);
1817 /* update eflags. It is needed anyway most of the time, do it always. */
1818 gen_compute_eflags(s
);
1819 assert(s
->cc_op
== CC_OP_EFLAGS
);
1821 label2
= gen_new_label();
1822 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1824 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1825 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1826 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1827 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1828 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1830 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1832 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1833 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1835 gen_set_label(label2
);
1843 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1850 /* XXX: inefficient, but we must use local temps */
1851 t0
= tcg_temp_local_new();
1852 t1
= tcg_temp_local_new();
1853 a0
= tcg_temp_local_new();
1861 if (op1
== OR_TMP0
) {
1862 tcg_gen_mov_tl(a0
, cpu_A0
);
1863 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1865 gen_op_mov_v_reg(ot
, t0
, op1
);
1869 tcg_gen_mov_tl(t1
, t0
);
1872 data_bits
= 8 << ot
;
1874 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1876 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1877 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1880 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1881 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1883 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1887 if (op1
== OR_TMP0
) {
1888 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1890 gen_op_mov_reg_v(ot
, op1
, t0
);
1895 gen_compute_eflags(s
);
1896 assert(s
->cc_op
== CC_OP_EFLAGS
);
1898 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1899 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1900 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1901 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1902 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1904 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1906 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1907 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1915 /* XXX: add faster immediate = 1 case */
1916 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1919 gen_compute_eflags(s
);
1920 assert(s
->cc_op
== CC_OP_EFLAGS
);
1924 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1926 gen_op_mov_TN_reg(ot
, 0, op1
);
1931 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1934 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1937 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1939 #ifdef TARGET_X86_64
1941 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1948 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1951 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1954 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1956 #ifdef TARGET_X86_64
1958 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1965 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1967 gen_op_mov_reg_T0(ot
, op1
);
1970 /* XXX: add faster immediate case */
1971 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1974 int label1
, label2
, data_bits
;
1976 TCGv t0
, t1
, t2
, a0
;
1978 t0
= tcg_temp_local_new();
1979 t1
= tcg_temp_local_new();
1980 t2
= tcg_temp_local_new();
1981 a0
= tcg_temp_local_new();
1989 if (op1
== OR_TMP0
) {
1990 tcg_gen_mov_tl(a0
, cpu_A0
);
1991 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1993 gen_op_mov_v_reg(ot
, t0
, op1
);
1996 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1998 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1999 tcg_gen_mov_tl(t2
, cpu_T3
);
2001 /* Must test zero case to avoid using undefined behaviour in TCG
2003 label1
= gen_new_label();
2004 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
2006 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
2007 if (ot
== OT_WORD
) {
2008 /* Note: we implement the Intel behaviour for shift count > 16 */
2010 tcg_gen_andi_tl(t0
, t0
, 0xffff);
2011 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
2012 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
2013 tcg_gen_ext32u_tl(t0
, t0
);
2015 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2017 /* only needed if count > 16, but a test would complicate */
2018 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
2019 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
2021 tcg_gen_shr_tl(t0
, t0
, t2
);
2023 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
2025 /* XXX: not optimal */
2026 tcg_gen_andi_tl(t0
, t0
, 0xffff);
2027 tcg_gen_shli_tl(t1
, t1
, 16);
2028 tcg_gen_or_tl(t1
, t1
, t0
);
2029 tcg_gen_ext32u_tl(t1
, t1
);
2031 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2032 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
2033 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
2034 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
2036 tcg_gen_shl_tl(t0
, t0
, t2
);
2037 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
2038 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
2039 tcg_gen_or_tl(t0
, t0
, t1
);
2042 data_bits
= 8 << ot
;
2045 tcg_gen_ext32u_tl(t0
, t0
);
2047 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2049 tcg_gen_shr_tl(t0
, t0
, t2
);
2050 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
2051 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
2052 tcg_gen_or_tl(t0
, t0
, t1
);
2056 tcg_gen_ext32u_tl(t1
, t1
);
2058 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
2060 tcg_gen_shl_tl(t0
, t0
, t2
);
2061 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
2062 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
2063 tcg_gen_or_tl(t0
, t0
, t1
);
2066 tcg_gen_mov_tl(t1
, cpu_tmp4
);
2068 gen_set_label(label1
);
2070 if (op1
== OR_TMP0
) {
2071 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
2073 gen_op_mov_reg_v(ot
, op1
, t0
);
2077 gen_update_cc_op(s
);
2079 label2
= gen_new_label();
2080 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
2082 tcg_gen_mov_tl(cpu_cc_src
, t1
);
2083 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
2085 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
2087 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
2089 gen_set_label(label2
);
2090 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
2098 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
2101 gen_op_mov_TN_reg(ot
, 1, s
);
2104 gen_rot_rm_T1(s1
, ot
, d
, 0);
2107 gen_rot_rm_T1(s1
, ot
, d
, 1);
2111 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
2114 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
2117 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
2120 gen_rotc_rm_T1(s1
, ot
, d
, 0);
2123 gen_rotc_rm_T1(s1
, ot
, d
, 1);
2128 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
2132 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
2135 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
2139 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
2142 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
2145 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
2148 /* currently not optimized */
2149 gen_op_movl_T1_im(c
);
2150 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
2155 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2156 int *reg_ptr
, int *offset_ptr
)
2164 int mod
, rm
, code
, override
, must_add_seg
;
2166 override
= s
->override
;
2167 must_add_seg
= s
->addseg
;
2170 mod
= (modrm
>> 6) & 3;
2182 code
= cpu_ldub_code(env
, s
->pc
++);
2183 scale
= (code
>> 6) & 3;
2184 index
= ((code
>> 3) & 7) | REX_X(s
);
2191 if ((base
& 7) == 5) {
2193 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2195 if (CODE64(s
) && !havesib
) {
2196 disp
+= s
->pc
+ s
->rip_offset
;
2203 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2207 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2213 /* for correct popl handling with esp */
2214 if (base
== 4 && s
->popl_esp_hack
)
2215 disp
+= s
->popl_esp_hack
;
2216 #ifdef TARGET_X86_64
2217 if (s
->aflag
== 2) {
2218 gen_op_movq_A0_reg(base
);
2220 gen_op_addq_A0_im(disp
);
2225 gen_op_movl_A0_reg(base
);
2227 gen_op_addl_A0_im(disp
);
2230 #ifdef TARGET_X86_64
2231 if (s
->aflag
== 2) {
2232 gen_op_movq_A0_im(disp
);
2236 gen_op_movl_A0_im(disp
);
2239 /* index == 4 means no index */
2240 if (havesib
&& (index
!= 4)) {
2241 #ifdef TARGET_X86_64
2242 if (s
->aflag
== 2) {
2243 gen_op_addq_A0_reg_sN(scale
, index
);
2247 gen_op_addl_A0_reg_sN(scale
, index
);
2252 if (base
== R_EBP
|| base
== R_ESP
)
2257 #ifdef TARGET_X86_64
2258 if (s
->aflag
== 2) {
2259 gen_op_addq_A0_seg(override
);
2263 gen_op_addl_A0_seg(s
, override
);
2270 disp
= cpu_lduw_code(env
, s
->pc
);
2272 gen_op_movl_A0_im(disp
);
2273 rm
= 0; /* avoid SS override */
2280 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2284 disp
= cpu_lduw_code(env
, s
->pc
);
2290 gen_op_movl_A0_reg(R_EBX
);
2291 gen_op_addl_A0_reg_sN(0, R_ESI
);
2294 gen_op_movl_A0_reg(R_EBX
);
2295 gen_op_addl_A0_reg_sN(0, R_EDI
);
2298 gen_op_movl_A0_reg(R_EBP
);
2299 gen_op_addl_A0_reg_sN(0, R_ESI
);
2302 gen_op_movl_A0_reg(R_EBP
);
2303 gen_op_addl_A0_reg_sN(0, R_EDI
);
2306 gen_op_movl_A0_reg(R_ESI
);
2309 gen_op_movl_A0_reg(R_EDI
);
2312 gen_op_movl_A0_reg(R_EBP
);
2316 gen_op_movl_A0_reg(R_EBX
);
2320 gen_op_addl_A0_im(disp
);
2321 gen_op_andl_A0_ffff();
2325 if (rm
== 2 || rm
== 3 || rm
== 6)
2330 gen_op_addl_A0_seg(s
, override
);
2340 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2342 int mod
, rm
, base
, code
;
2344 mod
= (modrm
>> 6) & 3;
2354 code
= cpu_ldub_code(env
, s
->pc
++);
2390 /* used for LEA and MOV AX, mem */
2391 static void gen_add_A0_ds_seg(DisasContext
*s
)
2393 int override
, must_add_seg
;
2394 must_add_seg
= s
->addseg
;
2396 if (s
->override
>= 0) {
2397 override
= s
->override
;
2401 #ifdef TARGET_X86_64
2403 gen_op_addq_A0_seg(override
);
2407 gen_op_addl_A0_seg(s
, override
);
2412 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2414 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2415 int ot
, int reg
, int is_store
)
2417 int mod
, rm
, opreg
, disp
;
2419 mod
= (modrm
>> 6) & 3;
2420 rm
= (modrm
& 7) | REX_B(s
);
2424 gen_op_mov_TN_reg(ot
, 0, reg
);
2425 gen_op_mov_reg_T0(ot
, rm
);
2427 gen_op_mov_TN_reg(ot
, 0, rm
);
2429 gen_op_mov_reg_T0(ot
, reg
);
2432 gen_lea_modrm(env
, s
, modrm
, &opreg
, &disp
);
2435 gen_op_mov_TN_reg(ot
, 0, reg
);
2436 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2438 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2440 gen_op_mov_reg_T0(ot
, reg
);
2445 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2451 ret
= cpu_ldub_code(env
, s
->pc
);
2455 ret
= cpu_lduw_code(env
, s
->pc
);
2460 ret
= cpu_ldl_code(env
, s
->pc
);
2467 static inline int insn_const_size(unsigned int ot
)
2475 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2477 TranslationBlock
*tb
;
2480 pc
= s
->cs_base
+ eip
;
2482 /* NOTE: we handle the case where the TB spans two pages here */
2483 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2484 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2485 /* jump to same page: we can use a direct jump */
2486 tcg_gen_goto_tb(tb_num
);
2488 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
2490 /* jump to another page: currently not optimized */
2496 static inline void gen_jcc(DisasContext
*s
, int b
,
2497 target_ulong val
, target_ulong next_eip
)
2502 gen_update_cc_op(s
);
2503 l1
= gen_new_label();
2505 set_cc_op(s
, CC_OP_DYNAMIC
);
2507 gen_goto_tb(s
, 0, next_eip
);
2510 gen_goto_tb(s
, 1, val
);
2511 s
->is_jmp
= DISAS_TB_JUMP
;
2513 l1
= gen_new_label();
2514 l2
= gen_new_label();
2517 gen_jmp_im(next_eip
);
2527 static void gen_setcc(DisasContext
*s
, int b
)
2529 gen_setcc1(s
, b
, cpu_T
[0]);
2532 static inline void gen_op_movl_T0_seg(int seg_reg
)
2534 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2535 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2538 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2540 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2541 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2542 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2543 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2544 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2545 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2548 /* move T0 to seg_reg and compute if the CPU state may change. Never
2549 call this function with seg_reg == R_CS */
2550 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2552 if (s
->pe
&& !s
->vm86
) {
2553 /* XXX: optimize by finding processor state dynamically */
2554 gen_update_cc_op(s
);
2555 gen_jmp_im(cur_eip
);
2556 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2557 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2558 /* abort translation because the addseg value may change or
2559 because ss32 may change. For R_SS, translation must always
2560 stop as a special handling must be done to disable hardware
2561 interrupts for the next instruction */
2562 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2563 s
->is_jmp
= DISAS_TB_JUMP
;
2565 gen_op_movl_seg_T0_vm(seg_reg
);
2566 if (seg_reg
== R_SS
)
2567 s
->is_jmp
= DISAS_TB_JUMP
;
2571 static inline int svm_is_rep(int prefixes
)
2573 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2577 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2578 uint32_t type
, uint64_t param
)
2580 /* no SVM activated; fast case */
2581 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2583 gen_update_cc_op(s
);
2584 gen_jmp_im(pc_start
- s
->cs_base
);
2585 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2586 tcg_const_i64(param
));
2590 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2592 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2595 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2597 #ifdef TARGET_X86_64
2599 gen_op_add_reg_im(2, R_ESP
, addend
);
2603 gen_op_add_reg_im(1, R_ESP
, addend
);
2605 gen_op_add_reg_im(0, R_ESP
, addend
);
2609 /* generate a push. It depends on ss32, addseg and dflag */
2610 static void gen_push_T0(DisasContext
*s
)
2612 #ifdef TARGET_X86_64
2614 gen_op_movq_A0_reg(R_ESP
);
2616 gen_op_addq_A0_im(-8);
2617 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2619 gen_op_addq_A0_im(-2);
2620 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2622 gen_op_mov_reg_A0(2, R_ESP
);
2626 gen_op_movl_A0_reg(R_ESP
);
2628 gen_op_addl_A0_im(-2);
2630 gen_op_addl_A0_im(-4);
2633 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2634 gen_op_addl_A0_seg(s
, R_SS
);
2637 gen_op_andl_A0_ffff();
2638 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2639 gen_op_addl_A0_seg(s
, R_SS
);
2641 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2642 if (s
->ss32
&& !s
->addseg
)
2643 gen_op_mov_reg_A0(1, R_ESP
);
2645 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2649 /* generate a push. It depends on ss32, addseg and dflag */
2650 /* slower version for T1, only used for call Ev */
2651 static void gen_push_T1(DisasContext
*s
)
2653 #ifdef TARGET_X86_64
2655 gen_op_movq_A0_reg(R_ESP
);
2657 gen_op_addq_A0_im(-8);
2658 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2660 gen_op_addq_A0_im(-2);
2661 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2663 gen_op_mov_reg_A0(2, R_ESP
);
2667 gen_op_movl_A0_reg(R_ESP
);
2669 gen_op_addl_A0_im(-2);
2671 gen_op_addl_A0_im(-4);
2674 gen_op_addl_A0_seg(s
, R_SS
);
2677 gen_op_andl_A0_ffff();
2678 gen_op_addl_A0_seg(s
, R_SS
);
2680 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2682 if (s
->ss32
&& !s
->addseg
)
2683 gen_op_mov_reg_A0(1, R_ESP
);
2685 gen_stack_update(s
, (-2) << s
->dflag
);
2689 /* two step pop is necessary for precise exceptions */
2690 static void gen_pop_T0(DisasContext
*s
)
2692 #ifdef TARGET_X86_64
2694 gen_op_movq_A0_reg(R_ESP
);
2695 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2699 gen_op_movl_A0_reg(R_ESP
);
2702 gen_op_addl_A0_seg(s
, R_SS
);
2704 gen_op_andl_A0_ffff();
2705 gen_op_addl_A0_seg(s
, R_SS
);
2707 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2711 static void gen_pop_update(DisasContext
*s
)
2713 #ifdef TARGET_X86_64
2714 if (CODE64(s
) && s
->dflag
) {
2715 gen_stack_update(s
, 8);
2719 gen_stack_update(s
, 2 << s
->dflag
);
2723 static void gen_stack_A0(DisasContext
*s
)
2725 gen_op_movl_A0_reg(R_ESP
);
2727 gen_op_andl_A0_ffff();
2728 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2730 gen_op_addl_A0_seg(s
, R_SS
);
2733 /* NOTE: wrap around in 16 bit not fully handled */
2734 static void gen_pusha(DisasContext
*s
)
2737 gen_op_movl_A0_reg(R_ESP
);
2738 gen_op_addl_A0_im(-16 << s
->dflag
);
2740 gen_op_andl_A0_ffff();
2741 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2743 gen_op_addl_A0_seg(s
, R_SS
);
2744 for(i
= 0;i
< 8; i
++) {
2745 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2746 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2747 gen_op_addl_A0_im(2 << s
->dflag
);
2749 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2752 /* NOTE: wrap around in 16 bit not fully handled */
2753 static void gen_popa(DisasContext
*s
)
2756 gen_op_movl_A0_reg(R_ESP
);
2758 gen_op_andl_A0_ffff();
2759 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2760 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2762 gen_op_addl_A0_seg(s
, R_SS
);
2763 for(i
= 0;i
< 8; i
++) {
2764 /* ESP is not reloaded */
2766 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2767 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2769 gen_op_addl_A0_im(2 << s
->dflag
);
2771 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2774 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2779 #ifdef TARGET_X86_64
2781 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2784 gen_op_movl_A0_reg(R_ESP
);
2785 gen_op_addq_A0_im(-opsize
);
2786 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2789 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2790 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2792 /* XXX: must save state */
2793 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2794 tcg_const_i32((ot
== OT_QUAD
)),
2797 gen_op_mov_reg_T1(ot
, R_EBP
);
2798 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2799 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2803 ot
= s
->dflag
+ OT_WORD
;
2804 opsize
= 2 << s
->dflag
;
2806 gen_op_movl_A0_reg(R_ESP
);
2807 gen_op_addl_A0_im(-opsize
);
2809 gen_op_andl_A0_ffff();
2810 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2812 gen_op_addl_A0_seg(s
, R_SS
);
2814 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2815 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2817 /* XXX: must save state */
2818 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2819 tcg_const_i32(s
->dflag
),
2822 gen_op_mov_reg_T1(ot
, R_EBP
);
2823 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2824 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2828 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2830 gen_update_cc_op(s
);
2831 gen_jmp_im(cur_eip
);
2832 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2833 s
->is_jmp
= DISAS_TB_JUMP
;
2836 /* an interrupt is different from an exception because of the
2838 static void gen_interrupt(DisasContext
*s
, int intno
,
2839 target_ulong cur_eip
, target_ulong next_eip
)
2841 gen_update_cc_op(s
);
2842 gen_jmp_im(cur_eip
);
2843 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2844 tcg_const_i32(next_eip
- cur_eip
));
2845 s
->is_jmp
= DISAS_TB_JUMP
;
2848 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2850 gen_update_cc_op(s
);
2851 gen_jmp_im(cur_eip
);
2852 gen_helper_debug(cpu_env
);
2853 s
->is_jmp
= DISAS_TB_JUMP
;
2856 /* generate a generic end of block. Trace exception is also generated
2858 static void gen_eob(DisasContext
*s
)
2860 gen_update_cc_op(s
);
2861 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2862 gen_helper_reset_inhibit_irq(cpu_env
);
2864 if (s
->tb
->flags
& HF_RF_MASK
) {
2865 gen_helper_reset_rf(cpu_env
);
2867 if (s
->singlestep_enabled
) {
2868 gen_helper_debug(cpu_env
);
2870 gen_helper_single_step(cpu_env
);
2874 s
->is_jmp
= DISAS_TB_JUMP
;
2877 /* generate a jump to eip. No segment change must happen before as a
2878 direct call to the next block may occur */
2879 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2882 gen_update_cc_op(s
);
2883 gen_goto_tb(s
, tb_num
, eip
);
2884 s
->is_jmp
= DISAS_TB_JUMP
;
2891 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2893 gen_jmp_tb(s
, eip
, 0);
2896 static inline void gen_ldq_env_A0(int idx
, int offset
)
2898 int mem_index
= (idx
>> 2) - 1;
2899 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2900 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2903 static inline void gen_stq_env_A0(int idx
, int offset
)
2905 int mem_index
= (idx
>> 2) - 1;
2906 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2907 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2910 static inline void gen_ldo_env_A0(int idx
, int offset
)
2912 int mem_index
= (idx
>> 2) - 1;
2913 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2914 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2915 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2916 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2917 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2920 static inline void gen_sto_env_A0(int idx
, int offset
)
2922 int mem_index
= (idx
>> 2) - 1;
2923 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2924 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2925 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2926 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2927 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2930 static inline void gen_op_movo(int d_offset
, int s_offset
)
2932 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2933 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2934 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2935 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2938 static inline void gen_op_movq(int d_offset
, int s_offset
)
2940 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2941 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2944 static inline void gen_op_movl(int d_offset
, int s_offset
)
2946 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2947 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2950 static inline void gen_op_movq_env_0(int d_offset
)
2952 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2953 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2956 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2957 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2958 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2959 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2960 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2961 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2963 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2964 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2967 #define SSE_SPECIAL ((void *)1)
2968 #define SSE_DUMMY ((void *)2)
2970 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2971 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2972 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2974 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2975 /* 3DNow! extensions */
2976 [0x0e] = { SSE_DUMMY
}, /* femms */
2977 [0x0f] = { SSE_DUMMY
}, /* pf... */
2978 /* pure SSE operations */
2979 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2980 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2981 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2982 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2983 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2984 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2985 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2986 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2988 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2989 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2990 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2991 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2992 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2993 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2994 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2995 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2996 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2997 [0x51] = SSE_FOP(sqrt
),
2998 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2999 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
3000 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
3001 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
3002 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
3003 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
3004 [0x58] = SSE_FOP(add
),
3005 [0x59] = SSE_FOP(mul
),
3006 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
3007 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
3008 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
3009 [0x5c] = SSE_FOP(sub
),
3010 [0x5d] = SSE_FOP(min
),
3011 [0x5e] = SSE_FOP(div
),
3012 [0x5f] = SSE_FOP(max
),
3014 [0xc2] = SSE_FOP(cmpeq
),
3015 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
3016 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
3018 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
3019 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
3021 /* MMX ops and their SSE extensions */
3022 [0x60] = MMX_OP2(punpcklbw
),
3023 [0x61] = MMX_OP2(punpcklwd
),
3024 [0x62] = MMX_OP2(punpckldq
),
3025 [0x63] = MMX_OP2(packsswb
),
3026 [0x64] = MMX_OP2(pcmpgtb
),
3027 [0x65] = MMX_OP2(pcmpgtw
),
3028 [0x66] = MMX_OP2(pcmpgtl
),
3029 [0x67] = MMX_OP2(packuswb
),
3030 [0x68] = MMX_OP2(punpckhbw
),
3031 [0x69] = MMX_OP2(punpckhwd
),
3032 [0x6a] = MMX_OP2(punpckhdq
),
3033 [0x6b] = MMX_OP2(packssdw
),
3034 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
3035 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
3036 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
3037 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
3038 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
3039 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
3040 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
3041 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
3042 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
3043 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
3044 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
3045 [0x74] = MMX_OP2(pcmpeqb
),
3046 [0x75] = MMX_OP2(pcmpeqw
),
3047 [0x76] = MMX_OP2(pcmpeql
),
3048 [0x77] = { SSE_DUMMY
}, /* emms */
3049 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
3050 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
3051 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
3052 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
3053 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
3054 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
3055 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
3056 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
3057 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
3058 [0xd1] = MMX_OP2(psrlw
),
3059 [0xd2] = MMX_OP2(psrld
),
3060 [0xd3] = MMX_OP2(psrlq
),
3061 [0xd4] = MMX_OP2(paddq
),
3062 [0xd5] = MMX_OP2(pmullw
),
3063 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
3064 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
3065 [0xd8] = MMX_OP2(psubusb
),
3066 [0xd9] = MMX_OP2(psubusw
),
3067 [0xda] = MMX_OP2(pminub
),
3068 [0xdb] = MMX_OP2(pand
),
3069 [0xdc] = MMX_OP2(paddusb
),
3070 [0xdd] = MMX_OP2(paddusw
),
3071 [0xde] = MMX_OP2(pmaxub
),
3072 [0xdf] = MMX_OP2(pandn
),
3073 [0xe0] = MMX_OP2(pavgb
),
3074 [0xe1] = MMX_OP2(psraw
),
3075 [0xe2] = MMX_OP2(psrad
),
3076 [0xe3] = MMX_OP2(pavgw
),
3077 [0xe4] = MMX_OP2(pmulhuw
),
3078 [0xe5] = MMX_OP2(pmulhw
),
3079 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
3080 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
3081 [0xe8] = MMX_OP2(psubsb
),
3082 [0xe9] = MMX_OP2(psubsw
),
3083 [0xea] = MMX_OP2(pminsw
),
3084 [0xeb] = MMX_OP2(por
),
3085 [0xec] = MMX_OP2(paddsb
),
3086 [0xed] = MMX_OP2(paddsw
),
3087 [0xee] = MMX_OP2(pmaxsw
),
3088 [0xef] = MMX_OP2(pxor
),
3089 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
3090 [0xf1] = MMX_OP2(psllw
),
3091 [0xf2] = MMX_OP2(pslld
),
3092 [0xf3] = MMX_OP2(psllq
),
3093 [0xf4] = MMX_OP2(pmuludq
),
3094 [0xf5] = MMX_OP2(pmaddwd
),
3095 [0xf6] = MMX_OP2(psadbw
),
3096 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
3097 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
3098 [0xf8] = MMX_OP2(psubb
),
3099 [0xf9] = MMX_OP2(psubw
),
3100 [0xfa] = MMX_OP2(psubl
),
3101 [0xfb] = MMX_OP2(psubq
),
3102 [0xfc] = MMX_OP2(paddb
),
3103 [0xfd] = MMX_OP2(paddw
),
3104 [0xfe] = MMX_OP2(paddl
),
3107 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
3108 [0 + 2] = MMX_OP2(psrlw
),
3109 [0 + 4] = MMX_OP2(psraw
),
3110 [0 + 6] = MMX_OP2(psllw
),
3111 [8 + 2] = MMX_OP2(psrld
),
3112 [8 + 4] = MMX_OP2(psrad
),
3113 [8 + 6] = MMX_OP2(pslld
),
3114 [16 + 2] = MMX_OP2(psrlq
),
3115 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
3116 [16 + 6] = MMX_OP2(psllq
),
3117 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
3120 static const SSEFunc_0_epi sse_op_table3ai
[] = {
3121 gen_helper_cvtsi2ss
,
3125 #ifdef TARGET_X86_64
3126 static const SSEFunc_0_epl sse_op_table3aq
[] = {
3127 gen_helper_cvtsq2ss
,
3132 static const SSEFunc_i_ep sse_op_table3bi
[] = {
3133 gen_helper_cvttss2si
,
3134 gen_helper_cvtss2si
,
3135 gen_helper_cvttsd2si
,
3139 #ifdef TARGET_X86_64
3140 static const SSEFunc_l_ep sse_op_table3bq
[] = {
3141 gen_helper_cvttss2sq
,
3142 gen_helper_cvtss2sq
,
3143 gen_helper_cvttsd2sq
,
3148 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
3159 static const SSEFunc_0_epp sse_op_table5
[256] = {
3160 [0x0c] = gen_helper_pi2fw
,
3161 [0x0d] = gen_helper_pi2fd
,
3162 [0x1c] = gen_helper_pf2iw
,
3163 [0x1d] = gen_helper_pf2id
,
3164 [0x8a] = gen_helper_pfnacc
,
3165 [0x8e] = gen_helper_pfpnacc
,
3166 [0x90] = gen_helper_pfcmpge
,
3167 [0x94] = gen_helper_pfmin
,
3168 [0x96] = gen_helper_pfrcp
,
3169 [0x97] = gen_helper_pfrsqrt
,
3170 [0x9a] = gen_helper_pfsub
,
3171 [0x9e] = gen_helper_pfadd
,
3172 [0xa0] = gen_helper_pfcmpgt
,
3173 [0xa4] = gen_helper_pfmax
,
3174 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
3175 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
3176 [0xaa] = gen_helper_pfsubr
,
3177 [0xae] = gen_helper_pfacc
,
3178 [0xb0] = gen_helper_pfcmpeq
,
3179 [0xb4] = gen_helper_pfmul
,
3180 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3181 [0xb7] = gen_helper_pmulhrw_mmx
,
3182 [0xbb] = gen_helper_pswapd
,
3183 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3186 struct SSEOpHelper_epp
{
3187 SSEFunc_0_epp op
[2];
3191 struct SSEOpHelper_eppi
{
3192 SSEFunc_0_eppi op
[2];
3196 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3197 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3198 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3199 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3201 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3202 [0x00] = SSSE3_OP(pshufb
),
3203 [0x01] = SSSE3_OP(phaddw
),
3204 [0x02] = SSSE3_OP(phaddd
),
3205 [0x03] = SSSE3_OP(phaddsw
),
3206 [0x04] = SSSE3_OP(pmaddubsw
),
3207 [0x05] = SSSE3_OP(phsubw
),
3208 [0x06] = SSSE3_OP(phsubd
),
3209 [0x07] = SSSE3_OP(phsubsw
),
3210 [0x08] = SSSE3_OP(psignb
),
3211 [0x09] = SSSE3_OP(psignw
),
3212 [0x0a] = SSSE3_OP(psignd
),
3213 [0x0b] = SSSE3_OP(pmulhrsw
),
3214 [0x10] = SSE41_OP(pblendvb
),
3215 [0x14] = SSE41_OP(blendvps
),
3216 [0x15] = SSE41_OP(blendvpd
),
3217 [0x17] = SSE41_OP(ptest
),
3218 [0x1c] = SSSE3_OP(pabsb
),
3219 [0x1d] = SSSE3_OP(pabsw
),
3220 [0x1e] = SSSE3_OP(pabsd
),
3221 [0x20] = SSE41_OP(pmovsxbw
),
3222 [0x21] = SSE41_OP(pmovsxbd
),
3223 [0x22] = SSE41_OP(pmovsxbq
),
3224 [0x23] = SSE41_OP(pmovsxwd
),
3225 [0x24] = SSE41_OP(pmovsxwq
),
3226 [0x25] = SSE41_OP(pmovsxdq
),
3227 [0x28] = SSE41_OP(pmuldq
),
3228 [0x29] = SSE41_OP(pcmpeqq
),
3229 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3230 [0x2b] = SSE41_OP(packusdw
),
3231 [0x30] = SSE41_OP(pmovzxbw
),
3232 [0x31] = SSE41_OP(pmovzxbd
),
3233 [0x32] = SSE41_OP(pmovzxbq
),
3234 [0x33] = SSE41_OP(pmovzxwd
),
3235 [0x34] = SSE41_OP(pmovzxwq
),
3236 [0x35] = SSE41_OP(pmovzxdq
),
3237 [0x37] = SSE42_OP(pcmpgtq
),
3238 [0x38] = SSE41_OP(pminsb
),
3239 [0x39] = SSE41_OP(pminsd
),
3240 [0x3a] = SSE41_OP(pminuw
),
3241 [0x3b] = SSE41_OP(pminud
),
3242 [0x3c] = SSE41_OP(pmaxsb
),
3243 [0x3d] = SSE41_OP(pmaxsd
),
3244 [0x3e] = SSE41_OP(pmaxuw
),
3245 [0x3f] = SSE41_OP(pmaxud
),
3246 [0x40] = SSE41_OP(pmulld
),
3247 [0x41] = SSE41_OP(phminposuw
),
3250 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3251 [0x08] = SSE41_OP(roundps
),
3252 [0x09] = SSE41_OP(roundpd
),
3253 [0x0a] = SSE41_OP(roundss
),
3254 [0x0b] = SSE41_OP(roundsd
),
3255 [0x0c] = SSE41_OP(blendps
),
3256 [0x0d] = SSE41_OP(blendpd
),
3257 [0x0e] = SSE41_OP(pblendw
),
3258 [0x0f] = SSSE3_OP(palignr
),
3259 [0x14] = SSE41_SPECIAL
, /* pextrb */
3260 [0x15] = SSE41_SPECIAL
, /* pextrw */
3261 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3262 [0x17] = SSE41_SPECIAL
, /* extractps */
3263 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3264 [0x21] = SSE41_SPECIAL
, /* insertps */
3265 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3266 [0x40] = SSE41_OP(dpps
),
3267 [0x41] = SSE41_OP(dppd
),
3268 [0x42] = SSE41_OP(mpsadbw
),
3269 [0x60] = SSE42_OP(pcmpestrm
),
3270 [0x61] = SSE42_OP(pcmpestri
),
3271 [0x62] = SSE42_OP(pcmpistrm
),
3272 [0x63] = SSE42_OP(pcmpistri
),
3275 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3276 target_ulong pc_start
, int rex_r
)
3278 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3279 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3280 SSEFunc_0_epp sse_fn_epp
;
3281 SSEFunc_0_eppi sse_fn_eppi
;
3282 SSEFunc_0_ppi sse_fn_ppi
;
3283 SSEFunc_0_eppt sse_fn_eppt
;
3286 if (s
->prefix
& PREFIX_DATA
)
3288 else if (s
->prefix
& PREFIX_REPZ
)
3290 else if (s
->prefix
& PREFIX_REPNZ
)
3294 sse_fn_epp
= sse_op_table1
[b
][b1
];
3298 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3308 /* simple MMX/SSE operation */
3309 if (s
->flags
& HF_TS_MASK
) {
3310 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3313 if (s
->flags
& HF_EM_MASK
) {
3315 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3318 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3319 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3322 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3325 gen_helper_emms(cpu_env
);
3330 gen_helper_emms(cpu_env
);
3333 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3334 the static cpu state) */
3336 gen_helper_enter_mmx(cpu_env
);
3339 modrm
= cpu_ldub_code(env
, s
->pc
++);
3340 reg
= ((modrm
>> 3) & 7);
3343 mod
= (modrm
>> 6) & 3;
3344 if (sse_fn_epp
== SSE_SPECIAL
) {
3347 case 0x0e7: /* movntq */
3350 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3351 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3353 case 0x1e7: /* movntdq */
3354 case 0x02b: /* movntps */
3355 case 0x12b: /* movntps */
3358 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3359 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3361 case 0x3f0: /* lddqu */
3364 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3365 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3367 case 0x22b: /* movntss */
3368 case 0x32b: /* movntsd */
3371 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3373 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3376 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3377 xmm_regs
[reg
].XMM_L(0)));
3378 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3381 case 0x6e: /* movd mm, ea */
3382 #ifdef TARGET_X86_64
3383 if (s
->dflag
== 2) {
3384 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3385 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3389 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3390 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3391 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3392 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3393 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3396 case 0x16e: /* movd xmm, ea */
3397 #ifdef TARGET_X86_64
3398 if (s
->dflag
== 2) {
3399 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3400 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3401 offsetof(CPUX86State
,xmm_regs
[reg
]));
3402 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3406 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3407 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3408 offsetof(CPUX86State
,xmm_regs
[reg
]));
3409 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3410 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3413 case 0x6f: /* movq mm, ea */
3415 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3416 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3419 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3420 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3421 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3422 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3425 case 0x010: /* movups */
3426 case 0x110: /* movupd */
3427 case 0x028: /* movaps */
3428 case 0x128: /* movapd */
3429 case 0x16f: /* movdqa xmm, ea */
3430 case 0x26f: /* movdqu xmm, ea */
3432 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3433 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3435 rm
= (modrm
& 7) | REX_B(s
);
3436 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3437 offsetof(CPUX86State
,xmm_regs
[rm
]));
3440 case 0x210: /* movss xmm, ea */
3442 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3443 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3444 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3446 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3447 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3448 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3450 rm
= (modrm
& 7) | REX_B(s
);
3451 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3452 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3455 case 0x310: /* movsd xmm, ea */
3457 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3458 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3460 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3461 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3463 rm
= (modrm
& 7) | REX_B(s
);
3464 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3465 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3468 case 0x012: /* movlps */
3469 case 0x112: /* movlpd */
3471 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3472 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3475 rm
= (modrm
& 7) | REX_B(s
);
3476 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3477 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3480 case 0x212: /* movsldup */
3482 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3483 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3485 rm
= (modrm
& 7) | REX_B(s
);
3486 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3487 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3488 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3489 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3491 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3492 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3493 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3494 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3496 case 0x312: /* movddup */
3498 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3499 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3501 rm
= (modrm
& 7) | REX_B(s
);
3502 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3503 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3505 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3506 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3508 case 0x016: /* movhps */
3509 case 0x116: /* movhpd */
3511 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3512 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3515 rm
= (modrm
& 7) | REX_B(s
);
3516 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3517 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3520 case 0x216: /* movshdup */
3522 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3523 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3525 rm
= (modrm
& 7) | REX_B(s
);
3526 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3527 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3528 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3529 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3531 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3532 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3533 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3534 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3539 int bit_index
, field_length
;
3541 if (b1
== 1 && reg
!= 0)
3543 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3544 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3545 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3546 offsetof(CPUX86State
,xmm_regs
[reg
]));
3548 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3549 tcg_const_i32(bit_index
),
3550 tcg_const_i32(field_length
));
3552 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3553 tcg_const_i32(bit_index
),
3554 tcg_const_i32(field_length
));
3557 case 0x7e: /* movd ea, mm */
3558 #ifdef TARGET_X86_64
3559 if (s
->dflag
== 2) {
3560 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3561 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3562 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3566 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3567 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3568 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3571 case 0x17e: /* movd ea, xmm */
3572 #ifdef TARGET_X86_64
3573 if (s
->dflag
== 2) {
3574 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3575 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3576 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3580 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3581 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3582 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3585 case 0x27e: /* movq xmm, ea */
3587 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3588 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3590 rm
= (modrm
& 7) | REX_B(s
);
3591 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3592 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3594 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3596 case 0x7f: /* movq ea, mm */
3598 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3599 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3602 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3603 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3606 case 0x011: /* movups */
3607 case 0x111: /* movupd */
3608 case 0x029: /* movaps */
3609 case 0x129: /* movapd */
3610 case 0x17f: /* movdqa ea, xmm */
3611 case 0x27f: /* movdqu ea, xmm */
3613 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3614 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3616 rm
= (modrm
& 7) | REX_B(s
);
3617 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3618 offsetof(CPUX86State
,xmm_regs
[reg
]));
3621 case 0x211: /* movss ea, xmm */
3623 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3624 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3625 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3627 rm
= (modrm
& 7) | REX_B(s
);
3628 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3629 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3632 case 0x311: /* movsd ea, xmm */
3634 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3635 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3637 rm
= (modrm
& 7) | REX_B(s
);
3638 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3639 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3642 case 0x013: /* movlps */
3643 case 0x113: /* movlpd */
3645 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3646 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3651 case 0x017: /* movhps */
3652 case 0x117: /* movhpd */
3654 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3655 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3660 case 0x71: /* shift mm, im */
3663 case 0x171: /* shift xmm, im */
3669 val
= cpu_ldub_code(env
, s
->pc
++);
3671 gen_op_movl_T0_im(val
);
3672 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3674 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3675 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3677 gen_op_movl_T0_im(val
);
3678 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3680 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3681 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3683 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3684 (((modrm
>> 3)) & 7)][b1
];
3689 rm
= (modrm
& 7) | REX_B(s
);
3690 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3693 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3695 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3696 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3697 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3699 case 0x050: /* movmskps */
3700 rm
= (modrm
& 7) | REX_B(s
);
3701 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3702 offsetof(CPUX86State
,xmm_regs
[rm
]));
3703 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3704 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3705 gen_op_mov_reg_T0(OT_LONG
, reg
);
3707 case 0x150: /* movmskpd */
3708 rm
= (modrm
& 7) | REX_B(s
);
3709 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3710 offsetof(CPUX86State
,xmm_regs
[rm
]));
3711 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3712 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3713 gen_op_mov_reg_T0(OT_LONG
, reg
);
3715 case 0x02a: /* cvtpi2ps */
3716 case 0x12a: /* cvtpi2pd */
3717 gen_helper_enter_mmx(cpu_env
);
3719 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3720 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3721 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3724 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3726 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3727 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3728 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3731 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3735 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3739 case 0x22a: /* cvtsi2ss */
3740 case 0x32a: /* cvtsi2sd */
3741 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3742 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3743 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3744 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3745 if (ot
== OT_LONG
) {
3746 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3748 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3750 #ifdef TARGET_X86_64
3751 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3752 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3758 case 0x02c: /* cvttps2pi */
3759 case 0x12c: /* cvttpd2pi */
3760 case 0x02d: /* cvtps2pi */
3761 case 0x12d: /* cvtpd2pi */
3762 gen_helper_enter_mmx(cpu_env
);
3764 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3765 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3766 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3768 rm
= (modrm
& 7) | REX_B(s
);
3769 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3771 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3772 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3773 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3776 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3779 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3782 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3785 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3789 case 0x22c: /* cvttss2si */
3790 case 0x32c: /* cvttsd2si */
3791 case 0x22d: /* cvtss2si */
3792 case 0x32d: /* cvtsd2si */
3793 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3795 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3797 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3799 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3800 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3802 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3804 rm
= (modrm
& 7) | REX_B(s
);
3805 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3807 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3808 if (ot
== OT_LONG
) {
3809 SSEFunc_i_ep sse_fn_i_ep
=
3810 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3811 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3812 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3814 #ifdef TARGET_X86_64
3815 SSEFunc_l_ep sse_fn_l_ep
=
3816 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3817 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3822 gen_op_mov_reg_T0(ot
, reg
);
3824 case 0xc4: /* pinsrw */
3827 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3828 val
= cpu_ldub_code(env
, s
->pc
++);
3831 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3832 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3835 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3836 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3839 case 0xc5: /* pextrw */
3843 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3844 val
= cpu_ldub_code(env
, s
->pc
++);
3847 rm
= (modrm
& 7) | REX_B(s
);
3848 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3849 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3853 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3854 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3856 reg
= ((modrm
>> 3) & 7) | rex_r
;
3857 gen_op_mov_reg_T0(ot
, reg
);
3859 case 0x1d6: /* movq ea, xmm */
3861 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3862 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3864 rm
= (modrm
& 7) | REX_B(s
);
3865 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3866 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3867 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3870 case 0x2d6: /* movq2dq */
3871 gen_helper_enter_mmx(cpu_env
);
3873 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3874 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3875 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3877 case 0x3d6: /* movdq2q */
3878 gen_helper_enter_mmx(cpu_env
);
3879 rm
= (modrm
& 7) | REX_B(s
);
3880 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3881 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3883 case 0xd7: /* pmovmskb */
3888 rm
= (modrm
& 7) | REX_B(s
);
3889 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3890 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3893 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3894 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3896 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3897 reg
= ((modrm
>> 3) & 7) | rex_r
;
3898 gen_op_mov_reg_T0(OT_LONG
, reg
);
3901 if (s
->prefix
& PREFIX_REPNZ
)
3905 modrm
= cpu_ldub_code(env
, s
->pc
++);
3907 reg
= ((modrm
>> 3) & 7) | rex_r
;
3908 mod
= (modrm
>> 6) & 3;
3913 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3917 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3921 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3923 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3925 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3926 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3928 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3929 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3930 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3931 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3932 offsetof(XMMReg
, XMM_Q(0)));
3934 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3935 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3936 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3937 (s
->mem_index
>> 2) - 1);
3938 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3939 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3940 offsetof(XMMReg
, XMM_L(0)));
3942 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3943 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3944 (s
->mem_index
>> 2) - 1);
3945 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3946 offsetof(XMMReg
, XMM_W(0)));
3948 case 0x2a: /* movntqda */
3949 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3952 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3956 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3958 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3960 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3961 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3962 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3965 if (sse_fn_epp
== SSE_SPECIAL
) {
3969 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3970 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3971 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3974 set_cc_op(s
, CC_OP_EFLAGS
);
3977 case 0x338: /* crc32 */
3980 modrm
= cpu_ldub_code(env
, s
->pc
++);
3981 reg
= ((modrm
>> 3) & 7) | rex_r
;
3983 if (b
!= 0xf0 && b
!= 0xf1)
3985 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3990 else if (b
== 0xf1 && s
->dflag
!= 2)
3991 if (s
->prefix
& PREFIX_DATA
)
3998 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3999 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4000 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4001 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
4002 cpu_T
[0], tcg_const_i32(8 << ot
));
4004 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
4005 gen_op_mov_reg_T0(ot
, reg
);
4010 modrm
= cpu_ldub_code(env
, s
->pc
++);
4012 reg
= ((modrm
>> 3) & 7) | rex_r
;
4013 mod
= (modrm
>> 6) & 3;
4018 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4022 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4025 if (sse_fn_eppi
== SSE_SPECIAL
) {
4026 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
4027 rm
= (modrm
& 7) | REX_B(s
);
4029 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4030 reg
= ((modrm
>> 3) & 7) | rex_r
;
4031 val
= cpu_ldub_code(env
, s
->pc
++);
4033 case 0x14: /* pextrb */
4034 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4035 xmm_regs
[reg
].XMM_B(val
& 15)));
4037 gen_op_mov_reg_T0(ot
, rm
);
4039 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
4040 (s
->mem_index
>> 2) - 1);
4042 case 0x15: /* pextrw */
4043 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4044 xmm_regs
[reg
].XMM_W(val
& 7)));
4046 gen_op_mov_reg_T0(ot
, rm
);
4048 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
4049 (s
->mem_index
>> 2) - 1);
4052 if (ot
== OT_LONG
) { /* pextrd */
4053 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4054 offsetof(CPUX86State
,
4055 xmm_regs
[reg
].XMM_L(val
& 3)));
4056 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4058 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4060 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4061 (s
->mem_index
>> 2) - 1);
4062 } else { /* pextrq */
4063 #ifdef TARGET_X86_64
4064 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4065 offsetof(CPUX86State
,
4066 xmm_regs
[reg
].XMM_Q(val
& 1)));
4068 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
4070 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
4071 (s
->mem_index
>> 2) - 1);
4077 case 0x17: /* extractps */
4078 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4079 xmm_regs
[reg
].XMM_L(val
& 3)));
4081 gen_op_mov_reg_T0(ot
, rm
);
4083 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4084 (s
->mem_index
>> 2) - 1);
4086 case 0x20: /* pinsrb */
4088 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
4090 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
4091 (s
->mem_index
>> 2) - 1);
4092 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
4093 xmm_regs
[reg
].XMM_B(val
& 15)));
4095 case 0x21: /* insertps */
4097 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4098 offsetof(CPUX86State
,xmm_regs
[rm
]
4099 .XMM_L((val
>> 6) & 3)));
4101 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4102 (s
->mem_index
>> 2) - 1);
4103 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4105 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4106 offsetof(CPUX86State
,xmm_regs
[reg
]
4107 .XMM_L((val
>> 4) & 3)));
4109 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4110 cpu_env
, offsetof(CPUX86State
,
4111 xmm_regs
[reg
].XMM_L(0)));
4113 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4114 cpu_env
, offsetof(CPUX86State
,
4115 xmm_regs
[reg
].XMM_L(1)));
4117 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4118 cpu_env
, offsetof(CPUX86State
,
4119 xmm_regs
[reg
].XMM_L(2)));
4121 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4122 cpu_env
, offsetof(CPUX86State
,
4123 xmm_regs
[reg
].XMM_L(3)));
4126 if (ot
== OT_LONG
) { /* pinsrd */
4128 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4130 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4131 (s
->mem_index
>> 2) - 1);
4132 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4133 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4134 offsetof(CPUX86State
,
4135 xmm_regs
[reg
].XMM_L(val
& 3)));
4136 } else { /* pinsrq */
4137 #ifdef TARGET_X86_64
4139 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4141 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
4142 (s
->mem_index
>> 2) - 1);
4143 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4144 offsetof(CPUX86State
,
4145 xmm_regs
[reg
].XMM_Q(val
& 1)));
4156 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4158 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4160 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4161 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4162 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4165 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4167 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4169 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4170 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4171 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4174 val
= cpu_ldub_code(env
, s
->pc
++);
4176 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4177 set_cc_op(s
, CC_OP_EFLAGS
);
4180 /* The helper must use entire 64-bit gp registers */
4184 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4185 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4186 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4192 /* generic MMX or SSE operation */
4194 case 0x70: /* pshufx insn */
4195 case 0xc6: /* pshufx insn */
4196 case 0xc2: /* compare insns */
4203 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4205 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4206 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4207 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4209 /* specific case for SSE single instructions */
4212 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
4213 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4216 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4219 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4222 rm
= (modrm
& 7) | REX_B(s
);
4223 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4226 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4228 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4229 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4230 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4233 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4237 case 0x0f: /* 3DNow! data insns */
4238 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4240 val
= cpu_ldub_code(env
, s
->pc
++);
4241 sse_fn_epp
= sse_op_table5
[val
];
4245 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4246 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4247 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4249 case 0x70: /* pshufx insn */
4250 case 0xc6: /* pshufx insn */
4251 val
= cpu_ldub_code(env
, s
->pc
++);
4252 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4253 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4254 /* XXX: introduce a new table? */
4255 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4256 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4260 val
= cpu_ldub_code(env
, s
->pc
++);
4263 sse_fn_epp
= sse_op_table4
[val
][b1
];
4265 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4266 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4267 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4270 /* maskmov : we must prepare A0 */
4273 #ifdef TARGET_X86_64
4274 if (s
->aflag
== 2) {
4275 gen_op_movq_A0_reg(R_EDI
);
4279 gen_op_movl_A0_reg(R_EDI
);
4281 gen_op_andl_A0_ffff();
4283 gen_add_A0_ds_seg(s
);
4285 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4286 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4287 /* XXX: introduce a new table? */
4288 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4289 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4292 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4293 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4294 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4297 if (b
== 0x2e || b
== 0x2f) {
4298 set_cc_op(s
, CC_OP_EFLAGS
);
4303 /* convert one instruction. s->is_jmp is set if the translation must
4304 be stopped. Return the next pc value */
4305 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4306 target_ulong pc_start
)
4308 int b
, prefixes
, aflag
, dflag
;
4310 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4311 target_ulong next_eip
, tval
;
4314 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4315 tcg_gen_debug_insn_start(pc_start
);
4324 #ifdef TARGET_X86_64
4329 s
->rip_offset
= 0; /* for relative ip address */
4331 b
= cpu_ldub_code(env
, s
->pc
);
4333 /* check prefixes */
4334 #ifdef TARGET_X86_64
4338 prefixes
|= PREFIX_REPZ
;
4341 prefixes
|= PREFIX_REPNZ
;
4344 prefixes
|= PREFIX_LOCK
;
4365 prefixes
|= PREFIX_DATA
;
4368 prefixes
|= PREFIX_ADR
;
4372 rex_w
= (b
>> 3) & 1;
4373 rex_r
= (b
& 0x4) << 1;
4374 s
->rex_x
= (b
& 0x2) << 2;
4375 REX_B(s
) = (b
& 0x1) << 3;
4376 x86_64_hregs
= 1; /* select uniform byte register addressing */
4380 /* 0x66 is ignored if rex.w is set */
4383 if (prefixes
& PREFIX_DATA
)
4386 if (!(prefixes
& PREFIX_ADR
))
4393 prefixes
|= PREFIX_REPZ
;
4396 prefixes
|= PREFIX_REPNZ
;
4399 prefixes
|= PREFIX_LOCK
;
4420 prefixes
|= PREFIX_DATA
;
4423 prefixes
|= PREFIX_ADR
;
4426 if (prefixes
& PREFIX_DATA
)
4428 if (prefixes
& PREFIX_ADR
)
4432 s
->prefix
= prefixes
;
4436 /* lock generation */
4437 if (prefixes
& PREFIX_LOCK
)
4440 /* now check op code */
4444 /**************************/
4445 /* extended op code */
4446 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4449 /**************************/
4467 ot
= dflag
+ OT_WORD
;
4470 case 0: /* OP Ev, Gv */
4471 modrm
= cpu_ldub_code(env
, s
->pc
++);
4472 reg
= ((modrm
>> 3) & 7) | rex_r
;
4473 mod
= (modrm
>> 6) & 3;
4474 rm
= (modrm
& 7) | REX_B(s
);
4476 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4478 } else if (op
== OP_XORL
&& rm
== reg
) {
4480 /* xor reg, reg optimisation */
4482 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4483 gen_op_mov_reg_T0(ot
, reg
);
4484 gen_op_update1_cc();
4489 gen_op_mov_TN_reg(ot
, 1, reg
);
4490 gen_op(s
, op
, ot
, opreg
);
4492 case 1: /* OP Gv, Ev */
4493 modrm
= cpu_ldub_code(env
, s
->pc
++);
4494 mod
= (modrm
>> 6) & 3;
4495 reg
= ((modrm
>> 3) & 7) | rex_r
;
4496 rm
= (modrm
& 7) | REX_B(s
);
4498 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4499 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4500 } else if (op
== OP_XORL
&& rm
== reg
) {
4503 gen_op_mov_TN_reg(ot
, 1, rm
);
4505 gen_op(s
, op
, ot
, reg
);
4507 case 2: /* OP A, Iv */
4508 val
= insn_get(env
, s
, ot
);
4509 gen_op_movl_T1_im(val
);
4510 gen_op(s
, op
, ot
, OR_EAX
);
4519 case 0x80: /* GRP1 */
4528 ot
= dflag
+ OT_WORD
;
4530 modrm
= cpu_ldub_code(env
, s
->pc
++);
4531 mod
= (modrm
>> 6) & 3;
4532 rm
= (modrm
& 7) | REX_B(s
);
4533 op
= (modrm
>> 3) & 7;
4539 s
->rip_offset
= insn_const_size(ot
);
4540 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4551 val
= insn_get(env
, s
, ot
);
4554 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4557 gen_op_movl_T1_im(val
);
4558 gen_op(s
, op
, ot
, opreg
);
4562 /**************************/
4563 /* inc, dec, and other misc arith */
4564 case 0x40 ... 0x47: /* inc Gv */
4565 ot
= dflag
? OT_LONG
: OT_WORD
;
4566 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4568 case 0x48 ... 0x4f: /* dec Gv */
4569 ot
= dflag
? OT_LONG
: OT_WORD
;
4570 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4572 case 0xf6: /* GRP3 */
4577 ot
= dflag
+ OT_WORD
;
4579 modrm
= cpu_ldub_code(env
, s
->pc
++);
4580 mod
= (modrm
>> 6) & 3;
4581 rm
= (modrm
& 7) | REX_B(s
);
4582 op
= (modrm
>> 3) & 7;
4585 s
->rip_offset
= insn_const_size(ot
);
4586 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4587 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4589 gen_op_mov_TN_reg(ot
, 0, rm
);
4594 val
= insn_get(env
, s
, ot
);
4595 gen_op_movl_T1_im(val
);
4596 gen_op_testl_T0_T1_cc();
4597 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4600 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4602 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4604 gen_op_mov_reg_T0(ot
, rm
);
4608 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4610 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4612 gen_op_mov_reg_T0(ot
, rm
);
4614 gen_op_update_neg_cc();
4615 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4620 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4621 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4622 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4623 /* XXX: use 32 bit mul which could be faster */
4624 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4625 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4626 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4627 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4628 set_cc_op(s
, CC_OP_MULB
);
4631 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4632 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4633 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4634 /* XXX: use 32 bit mul which could be faster */
4635 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4636 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4637 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4638 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4639 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4640 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4641 set_cc_op(s
, CC_OP_MULW
);
4645 #ifdef TARGET_X86_64
4646 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4647 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4648 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4649 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4650 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4651 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4652 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4653 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4654 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4658 t0
= tcg_temp_new_i64();
4659 t1
= tcg_temp_new_i64();
4660 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4661 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4662 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4663 tcg_gen_mul_i64(t0
, t0
, t1
);
4664 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4665 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4666 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4667 tcg_gen_shri_i64(t0
, t0
, 32);
4668 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4669 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4670 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4673 set_cc_op(s
, CC_OP_MULL
);
4675 #ifdef TARGET_X86_64
4677 gen_helper_mulq_EAX_T0(cpu_env
, cpu_T
[0]);
4678 set_cc_op(s
, CC_OP_MULQ
);
4686 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4687 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4688 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4689 /* XXX: use 32 bit mul which could be faster */
4690 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4691 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4692 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4693 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4694 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4695 set_cc_op(s
, CC_OP_MULB
);
4698 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4699 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4700 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4701 /* XXX: use 32 bit mul which could be faster */
4702 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4703 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4704 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4705 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4706 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4707 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4708 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4709 set_cc_op(s
, CC_OP_MULW
);
4713 #ifdef TARGET_X86_64
4714 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4715 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4716 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4717 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4718 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4719 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4720 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4721 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4722 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4723 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4727 t0
= tcg_temp_new_i64();
4728 t1
= tcg_temp_new_i64();
4729 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4730 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4731 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4732 tcg_gen_mul_i64(t0
, t0
, t1
);
4733 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4734 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4735 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4736 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4737 tcg_gen_shri_i64(t0
, t0
, 32);
4738 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4739 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4740 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4743 set_cc_op(s
, CC_OP_MULL
);
4745 #ifdef TARGET_X86_64
4747 gen_helper_imulq_EAX_T0(cpu_env
, cpu_T
[0]);
4748 set_cc_op(s
, CC_OP_MULQ
);
4756 gen_jmp_im(pc_start
- s
->cs_base
);
4757 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4760 gen_jmp_im(pc_start
- s
->cs_base
);
4761 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4765 gen_jmp_im(pc_start
- s
->cs_base
);
4766 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4768 #ifdef TARGET_X86_64
4770 gen_jmp_im(pc_start
- s
->cs_base
);
4771 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4779 gen_jmp_im(pc_start
- s
->cs_base
);
4780 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4783 gen_jmp_im(pc_start
- s
->cs_base
);
4784 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4788 gen_jmp_im(pc_start
- s
->cs_base
);
4789 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4791 #ifdef TARGET_X86_64
4793 gen_jmp_im(pc_start
- s
->cs_base
);
4794 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4804 case 0xfe: /* GRP4 */
4805 case 0xff: /* GRP5 */
4809 ot
= dflag
+ OT_WORD
;
4811 modrm
= cpu_ldub_code(env
, s
->pc
++);
4812 mod
= (modrm
>> 6) & 3;
4813 rm
= (modrm
& 7) | REX_B(s
);
4814 op
= (modrm
>> 3) & 7;
4815 if (op
>= 2 && b
== 0xfe) {
4819 if (op
== 2 || op
== 4) {
4820 /* operand size for jumps is 64 bit */
4822 } else if (op
== 3 || op
== 5) {
4823 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4824 } else if (op
== 6) {
4825 /* default push size is 64 bit */
4826 ot
= dflag
? OT_QUAD
: OT_WORD
;
4830 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4831 if (op
>= 2 && op
!= 3 && op
!= 5)
4832 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4834 gen_op_mov_TN_reg(ot
, 0, rm
);
4838 case 0: /* inc Ev */
4843 gen_inc(s
, ot
, opreg
, 1);
4845 case 1: /* dec Ev */
4850 gen_inc(s
, ot
, opreg
, -1);
4852 case 2: /* call Ev */
4853 /* XXX: optimize if memory (no 'and' is necessary) */
4855 gen_op_andl_T0_ffff();
4856 next_eip
= s
->pc
- s
->cs_base
;
4857 gen_movtl_T1_im(next_eip
);
4862 case 3: /* lcall Ev */
4863 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4864 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4865 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4867 if (s
->pe
&& !s
->vm86
) {
4868 gen_update_cc_op(s
);
4869 gen_jmp_im(pc_start
- s
->cs_base
);
4870 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4871 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4872 tcg_const_i32(dflag
),
4873 tcg_const_i32(s
->pc
- pc_start
));
4875 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4876 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4877 tcg_const_i32(dflag
),
4878 tcg_const_i32(s
->pc
- s
->cs_base
));
4882 case 4: /* jmp Ev */
4884 gen_op_andl_T0_ffff();
4888 case 5: /* ljmp Ev */
4889 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4890 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4891 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4893 if (s
->pe
&& !s
->vm86
) {
4894 gen_update_cc_op(s
);
4895 gen_jmp_im(pc_start
- s
->cs_base
);
4896 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4897 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4898 tcg_const_i32(s
->pc
- pc_start
));
4900 gen_op_movl_seg_T0_vm(R_CS
);
4901 gen_op_movl_T0_T1();
4906 case 6: /* push Ev */
4914 case 0x84: /* test Ev, Gv */
4919 ot
= dflag
+ OT_WORD
;
4921 modrm
= cpu_ldub_code(env
, s
->pc
++);
4922 reg
= ((modrm
>> 3) & 7) | rex_r
;
4924 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4925 gen_op_mov_TN_reg(ot
, 1, reg
);
4926 gen_op_testl_T0_T1_cc();
4927 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4930 case 0xa8: /* test eAX, Iv */
4935 ot
= dflag
+ OT_WORD
;
4936 val
= insn_get(env
, s
, ot
);
4938 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4939 gen_op_movl_T1_im(val
);
4940 gen_op_testl_T0_T1_cc();
4941 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4944 case 0x98: /* CWDE/CBW */
4945 #ifdef TARGET_X86_64
4947 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4948 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4949 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4953 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4954 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4955 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4957 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4958 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4959 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4962 case 0x99: /* CDQ/CWD */
4963 #ifdef TARGET_X86_64
4965 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4966 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4967 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4971 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4972 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4973 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4974 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4976 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4977 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4978 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4979 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4982 case 0x1af: /* imul Gv, Ev */
4983 case 0x69: /* imul Gv, Ev, I */
4985 ot
= dflag
+ OT_WORD
;
4986 modrm
= cpu_ldub_code(env
, s
->pc
++);
4987 reg
= ((modrm
>> 3) & 7) | rex_r
;
4989 s
->rip_offset
= insn_const_size(ot
);
4992 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4994 val
= insn_get(env
, s
, ot
);
4995 gen_op_movl_T1_im(val
);
4996 } else if (b
== 0x6b) {
4997 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4998 gen_op_movl_T1_im(val
);
5000 gen_op_mov_TN_reg(ot
, 1, reg
);
5003 #ifdef TARGET_X86_64
5004 if (ot
== OT_QUAD
) {
5005 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
5008 if (ot
== OT_LONG
) {
5009 #ifdef TARGET_X86_64
5010 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5011 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
5012 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5013 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5014 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
5015 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5019 t0
= tcg_temp_new_i64();
5020 t1
= tcg_temp_new_i64();
5021 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
5022 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
5023 tcg_gen_mul_i64(t0
, t0
, t1
);
5024 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
5025 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5026 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
5027 tcg_gen_shri_i64(t0
, t0
, 32);
5028 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
5029 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
5033 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5034 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5035 /* XXX: use 32 bit mul which could be faster */
5036 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5037 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5038 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5039 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5041 gen_op_mov_reg_T0(ot
, reg
);
5042 set_cc_op(s
, CC_OP_MULB
+ ot
);
5045 case 0x1c1: /* xadd Ev, Gv */
5049 ot
= dflag
+ OT_WORD
;
5050 modrm
= cpu_ldub_code(env
, s
->pc
++);
5051 reg
= ((modrm
>> 3) & 7) | rex_r
;
5052 mod
= (modrm
>> 6) & 3;
5054 rm
= (modrm
& 7) | REX_B(s
);
5055 gen_op_mov_TN_reg(ot
, 0, reg
);
5056 gen_op_mov_TN_reg(ot
, 1, rm
);
5057 gen_op_addl_T0_T1();
5058 gen_op_mov_reg_T1(ot
, reg
);
5059 gen_op_mov_reg_T0(ot
, rm
);
5061 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5062 gen_op_mov_TN_reg(ot
, 0, reg
);
5063 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5064 gen_op_addl_T0_T1();
5065 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5066 gen_op_mov_reg_T1(ot
, reg
);
5068 gen_op_update2_cc();
5069 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5072 case 0x1b1: /* cmpxchg Ev, Gv */
5075 TCGv t0
, t1
, t2
, a0
;
5080 ot
= dflag
+ OT_WORD
;
5081 modrm
= cpu_ldub_code(env
, s
->pc
++);
5082 reg
= ((modrm
>> 3) & 7) | rex_r
;
5083 mod
= (modrm
>> 6) & 3;
5084 t0
= tcg_temp_local_new();
5085 t1
= tcg_temp_local_new();
5086 t2
= tcg_temp_local_new();
5087 a0
= tcg_temp_local_new();
5088 gen_op_mov_v_reg(ot
, t1
, reg
);
5090 rm
= (modrm
& 7) | REX_B(s
);
5091 gen_op_mov_v_reg(ot
, t0
, rm
);
5093 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5094 tcg_gen_mov_tl(a0
, cpu_A0
);
5095 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
5096 rm
= 0; /* avoid warning */
5098 label1
= gen_new_label();
5099 tcg_gen_sub_tl(t2
, cpu_regs
[R_EAX
], t0
);
5101 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
5102 label2
= gen_new_label();
5104 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5106 gen_set_label(label1
);
5107 gen_op_mov_reg_v(ot
, rm
, t1
);
5109 /* perform no-op store cycle like physical cpu; must be
5110 before changing accumulator to ensure idempotency if
5111 the store faults and the instruction is restarted */
5112 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
5113 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5115 gen_set_label(label1
);
5116 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
5118 gen_set_label(label2
);
5119 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5120 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
5121 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5128 case 0x1c7: /* cmpxchg8b */
5129 modrm
= cpu_ldub_code(env
, s
->pc
++);
5130 mod
= (modrm
>> 6) & 3;
5131 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5133 #ifdef TARGET_X86_64
5135 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5137 gen_jmp_im(pc_start
- s
->cs_base
);
5138 gen_update_cc_op(s
);
5139 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5140 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5144 if (!(s
->cpuid_features
& CPUID_CX8
))
5146 gen_jmp_im(pc_start
- s
->cs_base
);
5147 gen_update_cc_op(s
);
5148 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5149 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5151 set_cc_op(s
, CC_OP_EFLAGS
);
5154 /**************************/
5156 case 0x50 ... 0x57: /* push */
5157 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
5160 case 0x58 ... 0x5f: /* pop */
5162 ot
= dflag
? OT_QUAD
: OT_WORD
;
5164 ot
= dflag
+ OT_WORD
;
5167 /* NOTE: order is important for pop %sp */
5169 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5171 case 0x60: /* pusha */
5176 case 0x61: /* popa */
5181 case 0x68: /* push Iv */
5184 ot
= dflag
? OT_QUAD
: OT_WORD
;
5186 ot
= dflag
+ OT_WORD
;
5189 val
= insn_get(env
, s
, ot
);
5191 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
5192 gen_op_movl_T0_im(val
);
5195 case 0x8f: /* pop Ev */
5197 ot
= dflag
? OT_QUAD
: OT_WORD
;
5199 ot
= dflag
+ OT_WORD
;
5201 modrm
= cpu_ldub_code(env
, s
->pc
++);
5202 mod
= (modrm
>> 6) & 3;
5205 /* NOTE: order is important for pop %sp */
5207 rm
= (modrm
& 7) | REX_B(s
);
5208 gen_op_mov_reg_T0(ot
, rm
);
5210 /* NOTE: order is important too for MMU exceptions */
5211 s
->popl_esp_hack
= 1 << ot
;
5212 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5213 s
->popl_esp_hack
= 0;
5217 case 0xc8: /* enter */
5220 val
= cpu_lduw_code(env
, s
->pc
);
5222 level
= cpu_ldub_code(env
, s
->pc
++);
5223 gen_enter(s
, val
, level
);
5226 case 0xc9: /* leave */
5227 /* XXX: exception not precise (ESP is updated before potential exception) */
5229 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5230 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5231 } else if (s
->ss32
) {
5232 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5233 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5235 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5236 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5240 ot
= dflag
? OT_QUAD
: OT_WORD
;
5242 ot
= dflag
+ OT_WORD
;
5244 gen_op_mov_reg_T0(ot
, R_EBP
);
5247 case 0x06: /* push es */
5248 case 0x0e: /* push cs */
5249 case 0x16: /* push ss */
5250 case 0x1e: /* push ds */
5253 gen_op_movl_T0_seg(b
>> 3);
5256 case 0x1a0: /* push fs */
5257 case 0x1a8: /* push gs */
5258 gen_op_movl_T0_seg((b
>> 3) & 7);
5261 case 0x07: /* pop es */
5262 case 0x17: /* pop ss */
5263 case 0x1f: /* pop ds */
5268 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5271 /* if reg == SS, inhibit interrupts/trace. */
5272 /* If several instructions disable interrupts, only the
5274 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5275 gen_helper_set_inhibit_irq(cpu_env
);
5279 gen_jmp_im(s
->pc
- s
->cs_base
);
5283 case 0x1a1: /* pop fs */
5284 case 0x1a9: /* pop gs */
5286 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5289 gen_jmp_im(s
->pc
- s
->cs_base
);
5294 /**************************/
5297 case 0x89: /* mov Gv, Ev */
5301 ot
= dflag
+ OT_WORD
;
5302 modrm
= cpu_ldub_code(env
, s
->pc
++);
5303 reg
= ((modrm
>> 3) & 7) | rex_r
;
5305 /* generate a generic store */
5306 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5309 case 0xc7: /* mov Ev, Iv */
5313 ot
= dflag
+ OT_WORD
;
5314 modrm
= cpu_ldub_code(env
, s
->pc
++);
5315 mod
= (modrm
>> 6) & 3;
5317 s
->rip_offset
= insn_const_size(ot
);
5318 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5320 val
= insn_get(env
, s
, ot
);
5321 gen_op_movl_T0_im(val
);
5323 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5325 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5328 case 0x8b: /* mov Ev, Gv */
5332 ot
= OT_WORD
+ dflag
;
5333 modrm
= cpu_ldub_code(env
, s
->pc
++);
5334 reg
= ((modrm
>> 3) & 7) | rex_r
;
5336 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5337 gen_op_mov_reg_T0(ot
, reg
);
5339 case 0x8e: /* mov seg, Gv */
5340 modrm
= cpu_ldub_code(env
, s
->pc
++);
5341 reg
= (modrm
>> 3) & 7;
5342 if (reg
>= 6 || reg
== R_CS
)
5344 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5345 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5347 /* if reg == SS, inhibit interrupts/trace */
5348 /* If several instructions disable interrupts, only the
5350 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5351 gen_helper_set_inhibit_irq(cpu_env
);
5355 gen_jmp_im(s
->pc
- s
->cs_base
);
5359 case 0x8c: /* mov Gv, seg */
5360 modrm
= cpu_ldub_code(env
, s
->pc
++);
5361 reg
= (modrm
>> 3) & 7;
5362 mod
= (modrm
>> 6) & 3;
5365 gen_op_movl_T0_seg(reg
);
5367 ot
= OT_WORD
+ dflag
;
5370 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5373 case 0x1b6: /* movzbS Gv, Eb */
5374 case 0x1b7: /* movzwS Gv, Eb */
5375 case 0x1be: /* movsbS Gv, Eb */
5376 case 0x1bf: /* movswS Gv, Eb */
5379 /* d_ot is the size of destination */
5380 d_ot
= dflag
+ OT_WORD
;
5381 /* ot is the size of source */
5382 ot
= (b
& 1) + OT_BYTE
;
5383 modrm
= cpu_ldub_code(env
, s
->pc
++);
5384 reg
= ((modrm
>> 3) & 7) | rex_r
;
5385 mod
= (modrm
>> 6) & 3;
5386 rm
= (modrm
& 7) | REX_B(s
);
5389 gen_op_mov_TN_reg(ot
, 0, rm
);
5390 switch(ot
| (b
& 8)) {
5392 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5395 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5398 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5402 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5405 gen_op_mov_reg_T0(d_ot
, reg
);
5407 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5409 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5411 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5413 gen_op_mov_reg_T0(d_ot
, reg
);
5418 case 0x8d: /* lea */
5419 ot
= dflag
+ OT_WORD
;
5420 modrm
= cpu_ldub_code(env
, s
->pc
++);
5421 mod
= (modrm
>> 6) & 3;
5424 reg
= ((modrm
>> 3) & 7) | rex_r
;
5425 /* we must ensure that no segment is added */
5429 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5431 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5434 case 0xa0: /* mov EAX, Ov */
5436 case 0xa2: /* mov Ov, EAX */
5439 target_ulong offset_addr
;
5444 ot
= dflag
+ OT_WORD
;
5445 #ifdef TARGET_X86_64
5446 if (s
->aflag
== 2) {
5447 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5449 gen_op_movq_A0_im(offset_addr
);
5454 offset_addr
= insn_get(env
, s
, OT_LONG
);
5456 offset_addr
= insn_get(env
, s
, OT_WORD
);
5458 gen_op_movl_A0_im(offset_addr
);
5460 gen_add_A0_ds_seg(s
);
5462 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5463 gen_op_mov_reg_T0(ot
, R_EAX
);
5465 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5466 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5470 case 0xd7: /* xlat */
5471 #ifdef TARGET_X86_64
5472 if (s
->aflag
== 2) {
5473 gen_op_movq_A0_reg(R_EBX
);
5474 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5475 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5476 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5480 gen_op_movl_A0_reg(R_EBX
);
5481 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5482 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5483 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5485 gen_op_andl_A0_ffff();
5487 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5489 gen_add_A0_ds_seg(s
);
5490 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5491 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5493 case 0xb0 ... 0xb7: /* mov R, Ib */
5494 val
= insn_get(env
, s
, OT_BYTE
);
5495 gen_op_movl_T0_im(val
);
5496 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5498 case 0xb8 ... 0xbf: /* mov R, Iv */
5499 #ifdef TARGET_X86_64
5503 tmp
= cpu_ldq_code(env
, s
->pc
);
5505 reg
= (b
& 7) | REX_B(s
);
5506 gen_movtl_T0_im(tmp
);
5507 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5511 ot
= dflag
? OT_LONG
: OT_WORD
;
5512 val
= insn_get(env
, s
, ot
);
5513 reg
= (b
& 7) | REX_B(s
);
5514 gen_op_movl_T0_im(val
);
5515 gen_op_mov_reg_T0(ot
, reg
);
5519 case 0x91 ... 0x97: /* xchg R, EAX */
5521 ot
= dflag
+ OT_WORD
;
5522 reg
= (b
& 7) | REX_B(s
);
5526 case 0x87: /* xchg Ev, Gv */
5530 ot
= dflag
+ OT_WORD
;
5531 modrm
= cpu_ldub_code(env
, s
->pc
++);
5532 reg
= ((modrm
>> 3) & 7) | rex_r
;
5533 mod
= (modrm
>> 6) & 3;
5535 rm
= (modrm
& 7) | REX_B(s
);
5537 gen_op_mov_TN_reg(ot
, 0, reg
);
5538 gen_op_mov_TN_reg(ot
, 1, rm
);
5539 gen_op_mov_reg_T0(ot
, rm
);
5540 gen_op_mov_reg_T1(ot
, reg
);
5542 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5543 gen_op_mov_TN_reg(ot
, 0, reg
);
5544 /* for xchg, lock is implicit */
5545 if (!(prefixes
& PREFIX_LOCK
))
5547 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5548 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5549 if (!(prefixes
& PREFIX_LOCK
))
5550 gen_helper_unlock();
5551 gen_op_mov_reg_T1(ot
, reg
);
5554 case 0xc4: /* les Gv */
5559 case 0xc5: /* lds Gv */
5564 case 0x1b2: /* lss Gv */
5567 case 0x1b4: /* lfs Gv */
5570 case 0x1b5: /* lgs Gv */
5573 ot
= dflag
? OT_LONG
: OT_WORD
;
5574 modrm
= cpu_ldub_code(env
, s
->pc
++);
5575 reg
= ((modrm
>> 3) & 7) | rex_r
;
5576 mod
= (modrm
>> 6) & 3;
5579 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5580 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5581 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5582 /* load the segment first to handle exceptions properly */
5583 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5584 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5585 /* then put the data */
5586 gen_op_mov_reg_T1(ot
, reg
);
5588 gen_jmp_im(s
->pc
- s
->cs_base
);
5593 /************************/
5604 ot
= dflag
+ OT_WORD
;
5606 modrm
= cpu_ldub_code(env
, s
->pc
++);
5607 mod
= (modrm
>> 6) & 3;
5608 op
= (modrm
>> 3) & 7;
5614 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5617 opreg
= (modrm
& 7) | REX_B(s
);
5622 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5625 shift
= cpu_ldub_code(env
, s
->pc
++);
5627 gen_shifti(s
, op
, ot
, opreg
, shift
);
5642 case 0x1a4: /* shld imm */
5646 case 0x1a5: /* shld cl */
5650 case 0x1ac: /* shrd imm */
5654 case 0x1ad: /* shrd cl */
5658 ot
= dflag
+ OT_WORD
;
5659 modrm
= cpu_ldub_code(env
, s
->pc
++);
5660 mod
= (modrm
>> 6) & 3;
5661 rm
= (modrm
& 7) | REX_B(s
);
5662 reg
= ((modrm
>> 3) & 7) | rex_r
;
5664 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5669 gen_op_mov_TN_reg(ot
, 1, reg
);
5672 val
= cpu_ldub_code(env
, s
->pc
++);
5673 tcg_gen_movi_tl(cpu_T3
, val
);
5675 tcg_gen_mov_tl(cpu_T3
, cpu_regs
[R_ECX
]);
5677 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
5680 /************************/
5683 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5684 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5685 /* XXX: what to do if illegal op ? */
5686 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5689 modrm
= cpu_ldub_code(env
, s
->pc
++);
5690 mod
= (modrm
>> 6) & 3;
5692 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5695 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5697 case 0x00 ... 0x07: /* fxxxs */
5698 case 0x10 ... 0x17: /* fixxxl */
5699 case 0x20 ... 0x27: /* fxxxl */
5700 case 0x30 ... 0x37: /* fixxx */
5707 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5708 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5709 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5712 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5713 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5714 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5717 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5718 (s
->mem_index
>> 2) - 1);
5719 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5723 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5724 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5725 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5729 gen_helper_fp_arith_ST0_FT0(op1
);
5731 /* fcomp needs pop */
5732 gen_helper_fpop(cpu_env
);
5736 case 0x08: /* flds */
5737 case 0x0a: /* fsts */
5738 case 0x0b: /* fstps */
5739 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5740 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5741 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5746 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5748 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5751 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5752 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5753 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5756 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5757 (s
->mem_index
>> 2) - 1);
5758 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5762 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5763 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5764 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5769 /* XXX: the corresponding CPUID bit must be tested ! */
5772 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5773 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5774 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5777 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5778 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5779 (s
->mem_index
>> 2) - 1);
5783 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5784 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5785 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5788 gen_helper_fpop(cpu_env
);
5793 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5794 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5795 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5798 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5799 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5800 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5803 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5804 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5805 (s
->mem_index
>> 2) - 1);
5809 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5810 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5811 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5815 gen_helper_fpop(cpu_env
);
5819 case 0x0c: /* fldenv mem */
5820 gen_update_cc_op(s
);
5821 gen_jmp_im(pc_start
- s
->cs_base
);
5822 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5824 case 0x0d: /* fldcw mem */
5825 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5826 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5827 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5829 case 0x0e: /* fnstenv mem */
5830 gen_update_cc_op(s
);
5831 gen_jmp_im(pc_start
- s
->cs_base
);
5832 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5834 case 0x0f: /* fnstcw mem */
5835 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5836 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5837 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5839 case 0x1d: /* fldt mem */
5840 gen_update_cc_op(s
);
5841 gen_jmp_im(pc_start
- s
->cs_base
);
5842 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5844 case 0x1f: /* fstpt mem */
5845 gen_update_cc_op(s
);
5846 gen_jmp_im(pc_start
- s
->cs_base
);
5847 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5848 gen_helper_fpop(cpu_env
);
5850 case 0x2c: /* frstor mem */
5851 gen_update_cc_op(s
);
5852 gen_jmp_im(pc_start
- s
->cs_base
);
5853 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5855 case 0x2e: /* fnsave mem */
5856 gen_update_cc_op(s
);
5857 gen_jmp_im(pc_start
- s
->cs_base
);
5858 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5860 case 0x2f: /* fnstsw mem */
5861 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5862 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5863 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5865 case 0x3c: /* fbld */
5866 gen_update_cc_op(s
);
5867 gen_jmp_im(pc_start
- s
->cs_base
);
5868 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5870 case 0x3e: /* fbstp */
5871 gen_update_cc_op(s
);
5872 gen_jmp_im(pc_start
- s
->cs_base
);
5873 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5874 gen_helper_fpop(cpu_env
);
5876 case 0x3d: /* fildll */
5877 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5878 (s
->mem_index
>> 2) - 1);
5879 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5881 case 0x3f: /* fistpll */
5882 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5883 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5884 (s
->mem_index
>> 2) - 1);
5885 gen_helper_fpop(cpu_env
);
5891 /* register float ops */
5895 case 0x08: /* fld sti */
5896 gen_helper_fpush(cpu_env
);
5897 gen_helper_fmov_ST0_STN(cpu_env
,
5898 tcg_const_i32((opreg
+ 1) & 7));
5900 case 0x09: /* fxchg sti */
5901 case 0x29: /* fxchg4 sti, undocumented op */
5902 case 0x39: /* fxchg7 sti, undocumented op */
5903 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5905 case 0x0a: /* grp d9/2 */
5908 /* check exceptions (FreeBSD FPU probe) */
5909 gen_update_cc_op(s
);
5910 gen_jmp_im(pc_start
- s
->cs_base
);
5911 gen_helper_fwait(cpu_env
);
5917 case 0x0c: /* grp d9/4 */
5920 gen_helper_fchs_ST0(cpu_env
);
5923 gen_helper_fabs_ST0(cpu_env
);
5926 gen_helper_fldz_FT0(cpu_env
);
5927 gen_helper_fcom_ST0_FT0(cpu_env
);
5930 gen_helper_fxam_ST0(cpu_env
);
5936 case 0x0d: /* grp d9/5 */
5940 gen_helper_fpush(cpu_env
);
5941 gen_helper_fld1_ST0(cpu_env
);
5944 gen_helper_fpush(cpu_env
);
5945 gen_helper_fldl2t_ST0(cpu_env
);
5948 gen_helper_fpush(cpu_env
);
5949 gen_helper_fldl2e_ST0(cpu_env
);
5952 gen_helper_fpush(cpu_env
);
5953 gen_helper_fldpi_ST0(cpu_env
);
5956 gen_helper_fpush(cpu_env
);
5957 gen_helper_fldlg2_ST0(cpu_env
);
5960 gen_helper_fpush(cpu_env
);
5961 gen_helper_fldln2_ST0(cpu_env
);
5964 gen_helper_fpush(cpu_env
);
5965 gen_helper_fldz_ST0(cpu_env
);
5972 case 0x0e: /* grp d9/6 */
5975 gen_helper_f2xm1(cpu_env
);
5978 gen_helper_fyl2x(cpu_env
);
5981 gen_helper_fptan(cpu_env
);
5983 case 3: /* fpatan */
5984 gen_helper_fpatan(cpu_env
);
5986 case 4: /* fxtract */
5987 gen_helper_fxtract(cpu_env
);
5989 case 5: /* fprem1 */
5990 gen_helper_fprem1(cpu_env
);
5992 case 6: /* fdecstp */
5993 gen_helper_fdecstp(cpu_env
);
5996 case 7: /* fincstp */
5997 gen_helper_fincstp(cpu_env
);
6001 case 0x0f: /* grp d9/7 */
6004 gen_helper_fprem(cpu_env
);
6006 case 1: /* fyl2xp1 */
6007 gen_helper_fyl2xp1(cpu_env
);
6010 gen_helper_fsqrt(cpu_env
);
6012 case 3: /* fsincos */
6013 gen_helper_fsincos(cpu_env
);
6015 case 5: /* fscale */
6016 gen_helper_fscale(cpu_env
);
6018 case 4: /* frndint */
6019 gen_helper_frndint(cpu_env
);
6022 gen_helper_fsin(cpu_env
);
6026 gen_helper_fcos(cpu_env
);
6030 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6031 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6032 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6038 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6040 gen_helper_fpop(cpu_env
);
6042 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6043 gen_helper_fp_arith_ST0_FT0(op1
);
6047 case 0x02: /* fcom */
6048 case 0x22: /* fcom2, undocumented op */
6049 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6050 gen_helper_fcom_ST0_FT0(cpu_env
);
6052 case 0x03: /* fcomp */
6053 case 0x23: /* fcomp3, undocumented op */
6054 case 0x32: /* fcomp5, undocumented op */
6055 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6056 gen_helper_fcom_ST0_FT0(cpu_env
);
6057 gen_helper_fpop(cpu_env
);
6059 case 0x15: /* da/5 */
6061 case 1: /* fucompp */
6062 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6063 gen_helper_fucom_ST0_FT0(cpu_env
);
6064 gen_helper_fpop(cpu_env
);
6065 gen_helper_fpop(cpu_env
);
6073 case 0: /* feni (287 only, just do nop here) */
6075 case 1: /* fdisi (287 only, just do nop here) */
6078 gen_helper_fclex(cpu_env
);
6080 case 3: /* fninit */
6081 gen_helper_fninit(cpu_env
);
6083 case 4: /* fsetpm (287 only, just do nop here) */
6089 case 0x1d: /* fucomi */
6090 gen_update_cc_op(s
);
6091 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6092 gen_helper_fucomi_ST0_FT0(cpu_env
);
6093 set_cc_op(s
, CC_OP_EFLAGS
);
6095 case 0x1e: /* fcomi */
6096 gen_update_cc_op(s
);
6097 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6098 gen_helper_fcomi_ST0_FT0(cpu_env
);
6099 set_cc_op(s
, CC_OP_EFLAGS
);
6101 case 0x28: /* ffree sti */
6102 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6104 case 0x2a: /* fst sti */
6105 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6107 case 0x2b: /* fstp sti */
6108 case 0x0b: /* fstp1 sti, undocumented op */
6109 case 0x3a: /* fstp8 sti, undocumented op */
6110 case 0x3b: /* fstp9 sti, undocumented op */
6111 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6112 gen_helper_fpop(cpu_env
);
6114 case 0x2c: /* fucom st(i) */
6115 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6116 gen_helper_fucom_ST0_FT0(cpu_env
);
6118 case 0x2d: /* fucomp st(i) */
6119 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6120 gen_helper_fucom_ST0_FT0(cpu_env
);
6121 gen_helper_fpop(cpu_env
);
6123 case 0x33: /* de/3 */
6125 case 1: /* fcompp */
6126 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6127 gen_helper_fcom_ST0_FT0(cpu_env
);
6128 gen_helper_fpop(cpu_env
);
6129 gen_helper_fpop(cpu_env
);
6135 case 0x38: /* ffreep sti, undocumented op */
6136 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6137 gen_helper_fpop(cpu_env
);
6139 case 0x3c: /* df/4 */
6142 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6143 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6144 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
6150 case 0x3d: /* fucomip */
6151 gen_update_cc_op(s
);
6152 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6153 gen_helper_fucomi_ST0_FT0(cpu_env
);
6154 gen_helper_fpop(cpu_env
);
6155 set_cc_op(s
, CC_OP_EFLAGS
);
6157 case 0x3e: /* fcomip */
6158 gen_update_cc_op(s
);
6159 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6160 gen_helper_fcomi_ST0_FT0(cpu_env
);
6161 gen_helper_fpop(cpu_env
);
6162 set_cc_op(s
, CC_OP_EFLAGS
);
6164 case 0x10 ... 0x13: /* fcmovxx */
6168 static const uint8_t fcmov_cc
[8] = {
6174 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6175 l1
= gen_new_label();
6176 gen_jcc1(s
, op1
, l1
);
6177 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6186 /************************/
6189 case 0xa4: /* movsS */
6194 ot
= dflag
+ OT_WORD
;
6196 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6197 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6203 case 0xaa: /* stosS */
6208 ot
= dflag
+ OT_WORD
;
6210 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6211 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6216 case 0xac: /* lodsS */
6221 ot
= dflag
+ OT_WORD
;
6222 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6223 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6228 case 0xae: /* scasS */
6233 ot
= dflag
+ OT_WORD
;
6234 if (prefixes
& PREFIX_REPNZ
) {
6235 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6236 } else if (prefixes
& PREFIX_REPZ
) {
6237 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6243 case 0xa6: /* cmpsS */
6248 ot
= dflag
+ OT_WORD
;
6249 if (prefixes
& PREFIX_REPNZ
) {
6250 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6251 } else if (prefixes
& PREFIX_REPZ
) {
6252 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6257 case 0x6c: /* insS */
6262 ot
= dflag
? OT_LONG
: OT_WORD
;
6263 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6264 gen_op_andl_T0_ffff();
6265 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6266 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6267 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6268 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6272 gen_jmp(s
, s
->pc
- s
->cs_base
);
6276 case 0x6e: /* outsS */
6281 ot
= dflag
? OT_LONG
: OT_WORD
;
6282 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6283 gen_op_andl_T0_ffff();
6284 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6285 svm_is_rep(prefixes
) | 4);
6286 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6287 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6291 gen_jmp(s
, s
->pc
- s
->cs_base
);
6296 /************************/
6304 ot
= dflag
? OT_LONG
: OT_WORD
;
6305 val
= cpu_ldub_code(env
, s
->pc
++);
6306 gen_op_movl_T0_im(val
);
6307 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6308 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6311 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6312 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6313 gen_op_mov_reg_T1(ot
, R_EAX
);
6316 gen_jmp(s
, s
->pc
- s
->cs_base
);
6324 ot
= dflag
? OT_LONG
: OT_WORD
;
6325 val
= cpu_ldub_code(env
, s
->pc
++);
6326 gen_op_movl_T0_im(val
);
6327 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6328 svm_is_rep(prefixes
));
6329 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6334 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6335 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6338 gen_jmp(s
, s
->pc
- s
->cs_base
);
6346 ot
= dflag
? OT_LONG
: OT_WORD
;
6347 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6348 gen_op_andl_T0_ffff();
6349 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6350 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6353 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6354 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6355 gen_op_mov_reg_T1(ot
, R_EAX
);
6358 gen_jmp(s
, s
->pc
- s
->cs_base
);
6366 ot
= dflag
? OT_LONG
: OT_WORD
;
6367 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6368 gen_op_andl_T0_ffff();
6369 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6370 svm_is_rep(prefixes
));
6371 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6375 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6376 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6377 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6380 gen_jmp(s
, s
->pc
- s
->cs_base
);
6384 /************************/
6386 case 0xc2: /* ret im */
6387 val
= cpu_ldsw_code(env
, s
->pc
);
6390 if (CODE64(s
) && s
->dflag
)
6392 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6394 gen_op_andl_T0_ffff();
6398 case 0xc3: /* ret */
6402 gen_op_andl_T0_ffff();
6406 case 0xca: /* lret im */
6407 val
= cpu_ldsw_code(env
, s
->pc
);
6410 if (s
->pe
&& !s
->vm86
) {
6411 gen_update_cc_op(s
);
6412 gen_jmp_im(pc_start
- s
->cs_base
);
6413 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6414 tcg_const_i32(val
));
6418 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6420 gen_op_andl_T0_ffff();
6421 /* NOTE: keeping EIP updated is not a problem in case of
6425 gen_op_addl_A0_im(2 << s
->dflag
);
6426 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6427 gen_op_movl_seg_T0_vm(R_CS
);
6428 /* add stack offset */
6429 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6433 case 0xcb: /* lret */
6436 case 0xcf: /* iret */
6437 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6440 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6441 set_cc_op(s
, CC_OP_EFLAGS
);
6442 } else if (s
->vm86
) {
6444 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6446 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6447 set_cc_op(s
, CC_OP_EFLAGS
);
6450 gen_update_cc_op(s
);
6451 gen_jmp_im(pc_start
- s
->cs_base
);
6452 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6453 tcg_const_i32(s
->pc
- s
->cs_base
));
6454 set_cc_op(s
, CC_OP_EFLAGS
);
6458 case 0xe8: /* call im */
6461 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6463 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6464 next_eip
= s
->pc
- s
->cs_base
;
6470 gen_movtl_T0_im(next_eip
);
6475 case 0x9a: /* lcall im */
6477 unsigned int selector
, offset
;
6481 ot
= dflag
? OT_LONG
: OT_WORD
;
6482 offset
= insn_get(env
, s
, ot
);
6483 selector
= insn_get(env
, s
, OT_WORD
);
6485 gen_op_movl_T0_im(selector
);
6486 gen_op_movl_T1_imu(offset
);
6489 case 0xe9: /* jmp im */
6491 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6493 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6494 tval
+= s
->pc
- s
->cs_base
;
6501 case 0xea: /* ljmp im */
6503 unsigned int selector
, offset
;
6507 ot
= dflag
? OT_LONG
: OT_WORD
;
6508 offset
= insn_get(env
, s
, ot
);
6509 selector
= insn_get(env
, s
, OT_WORD
);
6511 gen_op_movl_T0_im(selector
);
6512 gen_op_movl_T1_imu(offset
);
6515 case 0xeb: /* jmp Jb */
6516 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6517 tval
+= s
->pc
- s
->cs_base
;
6522 case 0x70 ... 0x7f: /* jcc Jb */
6523 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6525 case 0x180 ... 0x18f: /* jcc Jv */
6527 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6529 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6532 next_eip
= s
->pc
- s
->cs_base
;
6536 gen_jcc(s
, b
, tval
, next_eip
);
6539 case 0x190 ... 0x19f: /* setcc Gv */
6540 modrm
= cpu_ldub_code(env
, s
->pc
++);
6542 gen_ldst_modrm(env
, s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6544 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6549 ot
= dflag
+ OT_WORD
;
6550 modrm
= cpu_ldub_code(env
, s
->pc
++);
6551 reg
= ((modrm
>> 3) & 7) | rex_r
;
6552 mod
= (modrm
>> 6) & 3;
6553 t0
= tcg_temp_local_new();
6555 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6556 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6558 rm
= (modrm
& 7) | REX_B(s
);
6559 gen_op_mov_v_reg(ot
, t0
, rm
);
6561 #ifdef TARGET_X86_64
6562 if (ot
== OT_LONG
) {
6563 /* XXX: specific Intel behaviour ? */
6564 l1
= gen_new_label();
6565 gen_jcc1(s
, b
^ 1, l1
);
6566 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
6568 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_regs
[reg
]);
6572 l1
= gen_new_label();
6573 gen_jcc1(s
, b
^ 1, l1
);
6574 gen_op_mov_reg_v(ot
, reg
, t0
);
6581 /************************/
6583 case 0x9c: /* pushf */
6584 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6585 if (s
->vm86
&& s
->iopl
!= 3) {
6586 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6588 gen_update_cc_op(s
);
6589 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6593 case 0x9d: /* popf */
6594 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6595 if (s
->vm86
&& s
->iopl
!= 3) {
6596 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6601 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6602 tcg_const_i32((TF_MASK
| AC_MASK
|
6607 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6608 tcg_const_i32((TF_MASK
| AC_MASK
|
6610 IF_MASK
| IOPL_MASK
)
6614 if (s
->cpl
<= s
->iopl
) {
6616 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6617 tcg_const_i32((TF_MASK
|
6623 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6624 tcg_const_i32((TF_MASK
|
6633 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6634 tcg_const_i32((TF_MASK
| AC_MASK
|
6635 ID_MASK
| NT_MASK
)));
6637 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6638 tcg_const_i32((TF_MASK
| AC_MASK
|
6645 set_cc_op(s
, CC_OP_EFLAGS
);
6646 /* abort translation because TF/AC flag may change */
6647 gen_jmp_im(s
->pc
- s
->cs_base
);
6651 case 0x9e: /* sahf */
6652 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6654 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6655 gen_compute_eflags(s
);
6656 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6657 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6658 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6660 case 0x9f: /* lahf */
6661 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6663 gen_compute_eflags(s
);
6664 /* Note: gen_compute_eflags() only gives the condition codes */
6665 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6666 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6668 case 0xf5: /* cmc */
6669 gen_compute_eflags(s
);
6670 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6672 case 0xf8: /* clc */
6673 gen_compute_eflags(s
);
6674 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6676 case 0xf9: /* stc */
6677 gen_compute_eflags(s
);
6678 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6680 case 0xfc: /* cld */
6681 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6682 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6684 case 0xfd: /* std */
6685 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6686 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6689 /************************/
6690 /* bit operations */
6691 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6692 ot
= dflag
+ OT_WORD
;
6693 modrm
= cpu_ldub_code(env
, s
->pc
++);
6694 op
= (modrm
>> 3) & 7;
6695 mod
= (modrm
>> 6) & 3;
6696 rm
= (modrm
& 7) | REX_B(s
);
6699 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6700 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6702 gen_op_mov_TN_reg(ot
, 0, rm
);
6705 val
= cpu_ldub_code(env
, s
->pc
++);
6706 gen_op_movl_T1_im(val
);
6711 case 0x1a3: /* bt Gv, Ev */
6714 case 0x1ab: /* bts */
6717 case 0x1b3: /* btr */
6720 case 0x1bb: /* btc */
6723 ot
= dflag
+ OT_WORD
;
6724 modrm
= cpu_ldub_code(env
, s
->pc
++);
6725 reg
= ((modrm
>> 3) & 7) | rex_r
;
6726 mod
= (modrm
>> 6) & 3;
6727 rm
= (modrm
& 7) | REX_B(s
);
6728 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6730 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6731 /* specific case: we need to add a displacement */
6732 gen_exts(ot
, cpu_T
[1]);
6733 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6734 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6735 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6736 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6738 gen_op_mov_TN_reg(ot
, 0, rm
);
6741 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6744 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6745 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6748 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6749 tcg_gen_movi_tl(cpu_tmp0
, 1);
6750 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6751 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6754 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6755 tcg_gen_movi_tl(cpu_tmp0
, 1);
6756 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6757 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6758 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6762 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6763 tcg_gen_movi_tl(cpu_tmp0
, 1);
6764 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6765 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6768 set_cc_op(s
, CC_OP_SARB
+ ot
);
6771 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6773 gen_op_mov_reg_T0(ot
, rm
);
6774 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6775 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6778 case 0x1bc: /* bsf */
6779 case 0x1bd: /* bsr */
6784 ot
= dflag
+ OT_WORD
;
6785 modrm
= cpu_ldub_code(env
, s
->pc
++);
6786 reg
= ((modrm
>> 3) & 7) | rex_r
;
6787 gen_ldst_modrm(env
, s
,modrm
, ot
, OR_TMP0
, 0);
6788 gen_extu(ot
, cpu_T
[0]);
6789 t0
= tcg_temp_local_new();
6790 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6791 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6792 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6794 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6795 tcg_const_i32(16)); break;
6796 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6797 tcg_const_i32(32)); break;
6798 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6799 tcg_const_i32(64)); break;
6801 gen_op_mov_reg_T0(ot
, reg
);
6803 label1
= gen_new_label();
6804 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6805 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6807 gen_helper_bsr(cpu_T
[0], t0
);
6809 gen_helper_bsf(cpu_T
[0], t0
);
6811 gen_op_mov_reg_T0(ot
, reg
);
6812 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6813 gen_set_label(label1
);
6814 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6819 /************************/
6821 case 0x27: /* daa */
6824 gen_update_cc_op(s
);
6825 gen_helper_daa(cpu_env
);
6826 set_cc_op(s
, CC_OP_EFLAGS
);
6828 case 0x2f: /* das */
6831 gen_update_cc_op(s
);
6832 gen_helper_das(cpu_env
);
6833 set_cc_op(s
, CC_OP_EFLAGS
);
6835 case 0x37: /* aaa */
6838 gen_update_cc_op(s
);
6839 gen_helper_aaa(cpu_env
);
6840 set_cc_op(s
, CC_OP_EFLAGS
);
6842 case 0x3f: /* aas */
6845 gen_update_cc_op(s
);
6846 gen_helper_aas(cpu_env
);
6847 set_cc_op(s
, CC_OP_EFLAGS
);
6849 case 0xd4: /* aam */
6852 val
= cpu_ldub_code(env
, s
->pc
++);
6854 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6856 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6857 set_cc_op(s
, CC_OP_LOGICB
);
6860 case 0xd5: /* aad */
6863 val
= cpu_ldub_code(env
, s
->pc
++);
6864 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6865 set_cc_op(s
, CC_OP_LOGICB
);
6867 /************************/
6869 case 0x90: /* nop */
6870 /* XXX: correct lock test for all insn */
6871 if (prefixes
& PREFIX_LOCK
) {
6874 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6876 goto do_xchg_reg_eax
;
6878 if (prefixes
& PREFIX_REPZ
) {
6879 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6882 case 0x9b: /* fwait */
6883 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6884 (HF_MP_MASK
| HF_TS_MASK
)) {
6885 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6887 gen_update_cc_op(s
);
6888 gen_jmp_im(pc_start
- s
->cs_base
);
6889 gen_helper_fwait(cpu_env
);
6892 case 0xcc: /* int3 */
6893 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6895 case 0xcd: /* int N */
6896 val
= cpu_ldub_code(env
, s
->pc
++);
6897 if (s
->vm86
&& s
->iopl
!= 3) {
6898 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6900 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6903 case 0xce: /* into */
6906 gen_update_cc_op(s
);
6907 gen_jmp_im(pc_start
- s
->cs_base
);
6908 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6911 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6912 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6914 gen_debug(s
, pc_start
- s
->cs_base
);
6918 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6922 case 0xfa: /* cli */
6924 if (s
->cpl
<= s
->iopl
) {
6925 gen_helper_cli(cpu_env
);
6927 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6931 gen_helper_cli(cpu_env
);
6933 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6937 case 0xfb: /* sti */
6939 if (s
->cpl
<= s
->iopl
) {
6941 gen_helper_sti(cpu_env
);
6942 /* interruptions are enabled only the first insn after sti */
6943 /* If several instructions disable interrupts, only the
6945 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6946 gen_helper_set_inhibit_irq(cpu_env
);
6947 /* give a chance to handle pending irqs */
6948 gen_jmp_im(s
->pc
- s
->cs_base
);
6951 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6957 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6961 case 0x62: /* bound */
6964 ot
= dflag
? OT_LONG
: OT_WORD
;
6965 modrm
= cpu_ldub_code(env
, s
->pc
++);
6966 reg
= (modrm
>> 3) & 7;
6967 mod
= (modrm
>> 6) & 3;
6970 gen_op_mov_TN_reg(ot
, 0, reg
);
6971 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6972 gen_jmp_im(pc_start
- s
->cs_base
);
6973 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6974 if (ot
== OT_WORD
) {
6975 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6977 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6980 case 0x1c8 ... 0x1cf: /* bswap reg */
6981 reg
= (b
& 7) | REX_B(s
);
6982 #ifdef TARGET_X86_64
6984 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6985 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6986 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6990 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6991 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6992 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6993 gen_op_mov_reg_T0(OT_LONG
, reg
);
6996 case 0xd6: /* salc */
6999 gen_compute_eflags_c(s
, cpu_T
[0], false);
7000 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7001 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
7003 case 0xe0: /* loopnz */
7004 case 0xe1: /* loopz */
7005 case 0xe2: /* loop */
7006 case 0xe3: /* jecxz */
7010 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
7011 next_eip
= s
->pc
- s
->cs_base
;
7016 l1
= gen_new_label();
7017 l2
= gen_new_label();
7018 l3
= gen_new_label();
7021 case 0: /* loopnz */
7023 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7024 gen_op_jz_ecx(s
->aflag
, l3
);
7025 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7028 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7029 gen_op_jnz_ecx(s
->aflag
, l1
);
7033 gen_op_jz_ecx(s
->aflag
, l1
);
7038 gen_jmp_im(next_eip
);
7047 case 0x130: /* wrmsr */
7048 case 0x132: /* rdmsr */
7050 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7052 gen_update_cc_op(s
);
7053 gen_jmp_im(pc_start
- s
->cs_base
);
7055 gen_helper_rdmsr(cpu_env
);
7057 gen_helper_wrmsr(cpu_env
);
7061 case 0x131: /* rdtsc */
7062 gen_update_cc_op(s
);
7063 gen_jmp_im(pc_start
- s
->cs_base
);
7066 gen_helper_rdtsc(cpu_env
);
7069 gen_jmp(s
, s
->pc
- s
->cs_base
);
7072 case 0x133: /* rdpmc */
7073 gen_update_cc_op(s
);
7074 gen_jmp_im(pc_start
- s
->cs_base
);
7075 gen_helper_rdpmc(cpu_env
);
7077 case 0x134: /* sysenter */
7078 /* For Intel SYSENTER is valid on 64-bit */
7079 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7082 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7084 gen_update_cc_op(s
);
7085 gen_jmp_im(pc_start
- s
->cs_base
);
7086 gen_helper_sysenter(cpu_env
);
7090 case 0x135: /* sysexit */
7091 /* For Intel SYSEXIT is valid on 64-bit */
7092 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7095 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7097 gen_update_cc_op(s
);
7098 gen_jmp_im(pc_start
- s
->cs_base
);
7099 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7103 #ifdef TARGET_X86_64
7104 case 0x105: /* syscall */
7105 /* XXX: is it usable in real mode ? */
7106 gen_update_cc_op(s
);
7107 gen_jmp_im(pc_start
- s
->cs_base
);
7108 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7111 case 0x107: /* sysret */
7113 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7115 gen_update_cc_op(s
);
7116 gen_jmp_im(pc_start
- s
->cs_base
);
7117 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7118 /* condition codes are modified only in long mode */
7120 set_cc_op(s
, CC_OP_EFLAGS
);
7126 case 0x1a2: /* cpuid */
7127 gen_update_cc_op(s
);
7128 gen_jmp_im(pc_start
- s
->cs_base
);
7129 gen_helper_cpuid(cpu_env
);
7131 case 0xf4: /* hlt */
7133 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7135 gen_update_cc_op(s
);
7136 gen_jmp_im(pc_start
- s
->cs_base
);
7137 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7138 s
->is_jmp
= DISAS_TB_JUMP
;
7142 modrm
= cpu_ldub_code(env
, s
->pc
++);
7143 mod
= (modrm
>> 6) & 3;
7144 op
= (modrm
>> 3) & 7;
7147 if (!s
->pe
|| s
->vm86
)
7149 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7150 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7154 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7157 if (!s
->pe
|| s
->vm86
)
7160 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7162 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7163 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7164 gen_jmp_im(pc_start
- s
->cs_base
);
7165 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7166 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7170 if (!s
->pe
|| s
->vm86
)
7172 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7173 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7177 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7180 if (!s
->pe
|| s
->vm86
)
7183 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7185 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7186 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7187 gen_jmp_im(pc_start
- s
->cs_base
);
7188 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7189 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7194 if (!s
->pe
|| s
->vm86
)
7196 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7197 gen_update_cc_op(s
);
7199 gen_helper_verr(cpu_env
, cpu_T
[0]);
7201 gen_helper_verw(cpu_env
, cpu_T
[0]);
7203 set_cc_op(s
, CC_OP_EFLAGS
);
7210 modrm
= cpu_ldub_code(env
, s
->pc
++);
7211 mod
= (modrm
>> 6) & 3;
7212 op
= (modrm
>> 3) & 7;
7218 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7219 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7220 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7221 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7222 gen_add_A0_im(s
, 2);
7223 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7225 gen_op_andl_T0_im(0xffffff);
7226 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7231 case 0: /* monitor */
7232 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7235 gen_update_cc_op(s
);
7236 gen_jmp_im(pc_start
- s
->cs_base
);
7237 #ifdef TARGET_X86_64
7238 if (s
->aflag
== 2) {
7239 gen_op_movq_A0_reg(R_EAX
);
7243 gen_op_movl_A0_reg(R_EAX
);
7245 gen_op_andl_A0_ffff();
7247 gen_add_A0_ds_seg(s
);
7248 gen_helper_monitor(cpu_env
, cpu_A0
);
7251 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7254 gen_update_cc_op(s
);
7255 gen_jmp_im(pc_start
- s
->cs_base
);
7256 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7260 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7264 gen_helper_clac(cpu_env
);
7265 gen_jmp_im(s
->pc
- s
->cs_base
);
7269 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7273 gen_helper_stac(cpu_env
);
7274 gen_jmp_im(s
->pc
- s
->cs_base
);
7281 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7282 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7283 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7284 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7285 gen_add_A0_im(s
, 2);
7286 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7288 gen_op_andl_T0_im(0xffffff);
7289 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7295 gen_update_cc_op(s
);
7296 gen_jmp_im(pc_start
- s
->cs_base
);
7299 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7302 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7305 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7306 tcg_const_i32(s
->pc
- pc_start
));
7308 s
->is_jmp
= DISAS_TB_JUMP
;
7311 case 1: /* VMMCALL */
7312 if (!(s
->flags
& HF_SVME_MASK
))
7314 gen_helper_vmmcall(cpu_env
);
7316 case 2: /* VMLOAD */
7317 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7320 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7323 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7326 case 3: /* VMSAVE */
7327 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7330 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7333 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7337 if ((!(s
->flags
& HF_SVME_MASK
) &&
7338 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7342 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7345 gen_helper_stgi(cpu_env
);
7349 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7352 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7355 gen_helper_clgi(cpu_env
);
7358 case 6: /* SKINIT */
7359 if ((!(s
->flags
& HF_SVME_MASK
) &&
7360 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7363 gen_helper_skinit(cpu_env
);
7365 case 7: /* INVLPGA */
7366 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7369 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7372 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7378 } else if (s
->cpl
!= 0) {
7379 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7381 gen_svm_check_intercept(s
, pc_start
,
7382 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7383 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7384 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7385 gen_add_A0_im(s
, 2);
7386 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7388 gen_op_andl_T0_im(0xffffff);
7390 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7391 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7393 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7394 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7399 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7400 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7401 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7403 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7405 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7409 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7411 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7412 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7413 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7414 gen_jmp_im(s
->pc
- s
->cs_base
);
7419 if (mod
!= 3) { /* invlpg */
7421 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7423 gen_update_cc_op(s
);
7424 gen_jmp_im(pc_start
- s
->cs_base
);
7425 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7426 gen_helper_invlpg(cpu_env
, cpu_A0
);
7427 gen_jmp_im(s
->pc
- s
->cs_base
);
7432 case 0: /* swapgs */
7433 #ifdef TARGET_X86_64
7436 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7438 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7439 offsetof(CPUX86State
,segs
[R_GS
].base
));
7440 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7441 offsetof(CPUX86State
,kernelgsbase
));
7442 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7443 offsetof(CPUX86State
,segs
[R_GS
].base
));
7444 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7445 offsetof(CPUX86State
,kernelgsbase
));
7453 case 1: /* rdtscp */
7454 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7456 gen_update_cc_op(s
);
7457 gen_jmp_im(pc_start
- s
->cs_base
);
7460 gen_helper_rdtscp(cpu_env
);
7463 gen_jmp(s
, s
->pc
- s
->cs_base
);
7475 case 0x108: /* invd */
7476 case 0x109: /* wbinvd */
7478 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7480 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7484 case 0x63: /* arpl or movslS (x86_64) */
7485 #ifdef TARGET_X86_64
7488 /* d_ot is the size of destination */
7489 d_ot
= dflag
+ OT_WORD
;
7491 modrm
= cpu_ldub_code(env
, s
->pc
++);
7492 reg
= ((modrm
>> 3) & 7) | rex_r
;
7493 mod
= (modrm
>> 6) & 3;
7494 rm
= (modrm
& 7) | REX_B(s
);
7497 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7499 if (d_ot
== OT_QUAD
)
7500 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7501 gen_op_mov_reg_T0(d_ot
, reg
);
7503 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7504 if (d_ot
== OT_QUAD
) {
7505 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7507 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7509 gen_op_mov_reg_T0(d_ot
, reg
);
7515 TCGv t0
, t1
, t2
, a0
;
7517 if (!s
->pe
|| s
->vm86
)
7519 t0
= tcg_temp_local_new();
7520 t1
= tcg_temp_local_new();
7521 t2
= tcg_temp_local_new();
7523 modrm
= cpu_ldub_code(env
, s
->pc
++);
7524 reg
= (modrm
>> 3) & 7;
7525 mod
= (modrm
>> 6) & 3;
7528 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7529 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7530 a0
= tcg_temp_local_new();
7531 tcg_gen_mov_tl(a0
, cpu_A0
);
7533 gen_op_mov_v_reg(ot
, t0
, rm
);
7536 gen_op_mov_v_reg(ot
, t1
, reg
);
7537 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7538 tcg_gen_andi_tl(t1
, t1
, 3);
7539 tcg_gen_movi_tl(t2
, 0);
7540 label1
= gen_new_label();
7541 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7542 tcg_gen_andi_tl(t0
, t0
, ~3);
7543 tcg_gen_or_tl(t0
, t0
, t1
);
7544 tcg_gen_movi_tl(t2
, CC_Z
);
7545 gen_set_label(label1
);
7547 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7550 gen_op_mov_reg_v(ot
, rm
, t0
);
7552 gen_compute_eflags(s
);
7553 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7554 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7560 case 0x102: /* lar */
7561 case 0x103: /* lsl */
7565 if (!s
->pe
|| s
->vm86
)
7567 ot
= dflag
? OT_LONG
: OT_WORD
;
7568 modrm
= cpu_ldub_code(env
, s
->pc
++);
7569 reg
= ((modrm
>> 3) & 7) | rex_r
;
7570 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7571 t0
= tcg_temp_local_new();
7572 gen_update_cc_op(s
);
7574 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7576 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7578 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7579 label1
= gen_new_label();
7580 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7581 gen_op_mov_reg_v(ot
, reg
, t0
);
7582 gen_set_label(label1
);
7583 set_cc_op(s
, CC_OP_EFLAGS
);
7588 modrm
= cpu_ldub_code(env
, s
->pc
++);
7589 mod
= (modrm
>> 6) & 3;
7590 op
= (modrm
>> 3) & 7;
7592 case 0: /* prefetchnta */
7593 case 1: /* prefetchnt0 */
7594 case 2: /* prefetchnt0 */
7595 case 3: /* prefetchnt0 */
7598 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7599 /* nothing more to do */
7601 default: /* nop (multi byte) */
7602 gen_nop_modrm(env
, s
, modrm
);
7606 case 0x119 ... 0x11f: /* nop (multi byte) */
7607 modrm
= cpu_ldub_code(env
, s
->pc
++);
7608 gen_nop_modrm(env
, s
, modrm
);
7610 case 0x120: /* mov reg, crN */
7611 case 0x122: /* mov crN, reg */
7613 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7615 modrm
= cpu_ldub_code(env
, s
->pc
++);
7616 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7617 * AMD documentation (24594.pdf) and testing of
7618 * intel 386 and 486 processors all show that the mod bits
7619 * are assumed to be 1's, regardless of actual values.
7621 rm
= (modrm
& 7) | REX_B(s
);
7622 reg
= ((modrm
>> 3) & 7) | rex_r
;
7627 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7628 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7637 gen_update_cc_op(s
);
7638 gen_jmp_im(pc_start
- s
->cs_base
);
7640 gen_op_mov_TN_reg(ot
, 0, rm
);
7641 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7643 gen_jmp_im(s
->pc
- s
->cs_base
);
7646 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7647 gen_op_mov_reg_T0(ot
, rm
);
7655 case 0x121: /* mov reg, drN */
7656 case 0x123: /* mov drN, reg */
7658 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7660 modrm
= cpu_ldub_code(env
, s
->pc
++);
7661 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7662 * AMD documentation (24594.pdf) and testing of
7663 * intel 386 and 486 processors all show that the mod bits
7664 * are assumed to be 1's, regardless of actual values.
7666 rm
= (modrm
& 7) | REX_B(s
);
7667 reg
= ((modrm
>> 3) & 7) | rex_r
;
7672 /* XXX: do it dynamically with CR4.DE bit */
7673 if (reg
== 4 || reg
== 5 || reg
>= 8)
7676 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7677 gen_op_mov_TN_reg(ot
, 0, rm
);
7678 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7679 gen_jmp_im(s
->pc
- s
->cs_base
);
7682 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7683 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7684 gen_op_mov_reg_T0(ot
, rm
);
7688 case 0x106: /* clts */
7690 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7692 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7693 gen_helper_clts(cpu_env
);
7694 /* abort block because static cpu state changed */
7695 gen_jmp_im(s
->pc
- s
->cs_base
);
7699 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7700 case 0x1c3: /* MOVNTI reg, mem */
7701 if (!(s
->cpuid_features
& CPUID_SSE2
))
7703 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7704 modrm
= cpu_ldub_code(env
, s
->pc
++);
7705 mod
= (modrm
>> 6) & 3;
7708 reg
= ((modrm
>> 3) & 7) | rex_r
;
7709 /* generate a generic store */
7710 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7713 modrm
= cpu_ldub_code(env
, s
->pc
++);
7714 mod
= (modrm
>> 6) & 3;
7715 op
= (modrm
>> 3) & 7;
7717 case 0: /* fxsave */
7718 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7719 (s
->prefix
& PREFIX_LOCK
))
7721 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7722 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7725 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7726 gen_update_cc_op(s
);
7727 gen_jmp_im(pc_start
- s
->cs_base
);
7728 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7730 case 1: /* fxrstor */
7731 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7732 (s
->prefix
& PREFIX_LOCK
))
7734 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7735 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7738 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7739 gen_update_cc_op(s
);
7740 gen_jmp_im(pc_start
- s
->cs_base
);
7741 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7742 tcg_const_i32((s
->dflag
== 2)));
7744 case 2: /* ldmxcsr */
7745 case 3: /* stmxcsr */
7746 if (s
->flags
& HF_TS_MASK
) {
7747 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7750 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7753 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7755 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7756 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7757 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7759 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7760 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7763 case 5: /* lfence */
7764 case 6: /* mfence */
7765 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7768 case 7: /* sfence / clflush */
7769 if ((modrm
& 0xc7) == 0xc0) {
7771 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7772 if (!(s
->cpuid_features
& CPUID_SSE
))
7776 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7778 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7785 case 0x10d: /* 3DNow! prefetch(w) */
7786 modrm
= cpu_ldub_code(env
, s
->pc
++);
7787 mod
= (modrm
>> 6) & 3;
7790 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7791 /* ignore for now */
7793 case 0x1aa: /* rsm */
7794 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7795 if (!(s
->flags
& HF_SMM_MASK
))
7797 gen_update_cc_op(s
);
7798 gen_jmp_im(s
->pc
- s
->cs_base
);
7799 gen_helper_rsm(cpu_env
);
7802 case 0x1b8: /* SSE4.2 popcnt */
7803 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7806 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7809 modrm
= cpu_ldub_code(env
, s
->pc
++);
7810 reg
= ((modrm
>> 3) & 7) | rex_r
;
7812 if (s
->prefix
& PREFIX_DATA
)
7814 else if (s
->dflag
!= 2)
7819 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7820 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7821 gen_op_mov_reg_T0(ot
, reg
);
7823 set_cc_op(s
, CC_OP_EFLAGS
);
7825 case 0x10e ... 0x10f:
7826 /* 3DNow! instructions, ignore prefixes */
7827 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7828 case 0x110 ... 0x117:
7829 case 0x128 ... 0x12f:
7830 case 0x138 ... 0x13a:
7831 case 0x150 ... 0x179:
7832 case 0x17c ... 0x17f:
7834 case 0x1c4 ... 0x1c6:
7835 case 0x1d0 ... 0x1fe:
7836 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7841 /* lock generation */
7842 if (s
->prefix
& PREFIX_LOCK
)
7843 gen_helper_unlock();
7846 if (s
->prefix
& PREFIX_LOCK
)
7847 gen_helper_unlock();
7848 /* XXX: ensure that no lock was generated */
7849 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7853 void optimize_flags_init(void)
7855 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7856 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7857 offsetof(CPUX86State
, cc_op
), "cc_op");
7858 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7860 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7863 #ifdef TARGET_X86_64
7864 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7865 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7866 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7867 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7868 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7869 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7870 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7871 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7872 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7873 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7874 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7875 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7876 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7877 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7878 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7879 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7880 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7881 offsetof(CPUX86State
, regs
[8]), "r8");
7882 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7883 offsetof(CPUX86State
, regs
[9]), "r9");
7884 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7885 offsetof(CPUX86State
, regs
[10]), "r10");
7886 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7887 offsetof(CPUX86State
, regs
[11]), "r11");
7888 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7889 offsetof(CPUX86State
, regs
[12]), "r12");
7890 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7891 offsetof(CPUX86State
, regs
[13]), "r13");
7892 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7893 offsetof(CPUX86State
, regs
[14]), "r14");
7894 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7895 offsetof(CPUX86State
, regs
[15]), "r15");
7897 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7898 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7899 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7900 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7901 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7902 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7903 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7904 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7905 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7906 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7907 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7908 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7909 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7910 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7911 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7912 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7915 /* register helpers */
7916 #define GEN_HELPER 2
7920 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7921 basic block 'tb'. If search_pc is TRUE, also generate PC
7922 information for each intermediate instruction. */
7923 static inline void gen_intermediate_code_internal(CPUX86State
*env
,
7924 TranslationBlock
*tb
,
7927 DisasContext dc1
, *dc
= &dc1
;
7928 target_ulong pc_ptr
;
7929 uint16_t *gen_opc_end
;
7933 target_ulong pc_start
;
7934 target_ulong cs_base
;
7938 /* generate intermediate code */
7940 cs_base
= tb
->cs_base
;
7943 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7944 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7945 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7946 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7948 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7949 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7950 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7951 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7952 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7953 dc
->cc_op
= CC_OP_DYNAMIC
;
7954 dc
->cc_op_dirty
= false;
7955 dc
->cs_base
= cs_base
;
7957 dc
->popl_esp_hack
= 0;
7958 /* select memory access functions */
7960 if (flags
& HF_SOFTMMU_MASK
) {
7961 dc
->mem_index
= (cpu_mmu_index(env
) + 1) << 2;
7963 dc
->cpuid_features
= env
->cpuid_features
;
7964 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7965 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7966 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7967 dc
->cpuid_7_0_ebx_features
= env
->cpuid_7_0_ebx_features
;
7968 #ifdef TARGET_X86_64
7969 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7970 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7973 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7974 (flags
& HF_INHIBIT_IRQ_MASK
)
7975 #ifndef CONFIG_SOFTMMU
7976 || (flags
& HF_SOFTMMU_MASK
)
7980 /* check addseg logic */
7981 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7982 printf("ERROR addseg\n");
7985 cpu_T
[0] = tcg_temp_new();
7986 cpu_T
[1] = tcg_temp_new();
7987 cpu_A0
= tcg_temp_new();
7988 cpu_T3
= tcg_temp_new();
7990 cpu_tmp0
= tcg_temp_new();
7991 cpu_tmp1_i64
= tcg_temp_new_i64();
7992 cpu_tmp2_i32
= tcg_temp_new_i32();
7993 cpu_tmp3_i32
= tcg_temp_new_i32();
7994 cpu_tmp4
= tcg_temp_new();
7995 cpu_tmp5
= tcg_temp_new();
7996 cpu_ptr0
= tcg_temp_new_ptr();
7997 cpu_ptr1
= tcg_temp_new_ptr();
7999 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
8001 dc
->is_jmp
= DISAS_NEXT
;
8005 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8007 max_insns
= CF_COUNT_MASK
;
8011 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8012 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8013 if (bp
->pc
== pc_ptr
&&
8014 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8015 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8021 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8025 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8027 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8028 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8029 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8030 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8032 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8035 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8037 /* stop translation if indicated */
8040 /* if single step mode, we generate only one instruction and
8041 generate an exception */
8042 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8043 the flag and abort the translation to give the irqs a
8044 change to be happen */
8045 if (dc
->tf
|| dc
->singlestep_enabled
||
8046 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8047 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8051 /* if too long translation, stop generation too */
8052 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8053 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8054 num_insns
>= max_insns
) {
8055 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8060 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8065 if (tb
->cflags
& CF_LAST_IO
)
8067 gen_icount_end(tb
, num_insns
);
8068 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8069 /* we don't forget to fill the last values */
8071 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8074 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8078 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8080 qemu_log("----------------\n");
8081 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8082 #ifdef TARGET_X86_64
8087 disas_flags
= !dc
->code32
;
8088 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8094 tb
->size
= pc_ptr
- pc_start
;
8095 tb
->icount
= num_insns
;
8099 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8101 gen_intermediate_code_internal(env
, tb
, 0);
8104 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8106 gen_intermediate_code_internal(env
, tb
, 1);
8109 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8113 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8115 qemu_log("RESTORE:\n");
8116 for(i
= 0;i
<= pc_pos
; i
++) {
8117 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8118 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8119 tcg_ctx
.gen_opc_pc
[i
]);
8122 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8123 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8124 (uint32_t)tb
->cs_base
);
8127 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8128 cc_op
= gen_opc_cc_op
[pc_pos
];
8129 if (cc_op
!= CC_OP_DYNAMIC
)