4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define X86_64_ONLY(x) x
43 #define X86_64_DEF(...) __VA_ARGS__
44 #define CODE64(s) ((s)->code64)
45 #define REX_X(s) ((s)->rex_x)
46 #define REX_B(s) ((s)->rex_b)
47 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
49 #define BUGGY_64(x) NULL
52 #define X86_64_ONLY(x) NULL
53 #define X86_64_DEF(...)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
63 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
, cpu_cc_tmp
;
64 static TCGv_i32 cpu_cc_op
;
65 static TCGv cpu_regs
[CPU_NB_REGS
];
67 static TCGv cpu_T
[2], cpu_T3
;
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0
, cpu_tmp4
;
70 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
71 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
72 static TCGv_i64 cpu_tmp1_i64
;
75 #include "gen-icount.h"
78 static int x86_64_hregs
;
81 typedef struct DisasContext
{
82 /* current insn context */
83 int override
; /* -1 if no override */
86 target_ulong pc
; /* pc = eip + cs_base */
87 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
88 static state change (stop translation) */
89 /* current block context */
90 target_ulong cs_base
; /* base of CS segment */
91 int pe
; /* protected mode */
92 int code32
; /* 32 bit code segment */
94 int lma
; /* long mode active */
95 int code64
; /* 64 bit code segment */
98 int ss32
; /* 32 bit stack segment */
99 int cc_op
; /* current CC operation */
100 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
101 int f_st
; /* currently unused */
102 int vm86
; /* vm86 mode */
105 int tf
; /* TF cpu flag */
106 int singlestep_enabled
; /* "hardware" single step enabled */
107 int jmp_opt
; /* use direct block chaining for direct jumps */
108 int mem_index
; /* select memory access functions */
109 uint64_t flags
; /* all execution flags */
110 struct TranslationBlock
*tb
;
111 int popl_esp_hack
; /* for correct popl with esp base handling */
112 int rip_offset
; /* only used in x86_64, but left for simplicity */
114 int cpuid_ext_features
;
115 int cpuid_ext2_features
;
116 int cpuid_ext3_features
;
119 static void gen_eob(DisasContext
*s
);
120 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
121 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
123 /* i386 arith/logic operations */
143 OP_SHL1
, /* undocumented */
167 /* I386 int registers */
168 OR_EAX
, /* MUST be even numbered */
177 OR_TMP0
= 16, /* temporary operand register */
179 OR_A0
, /* temporary register used when doing address evaluation */
182 static inline void gen_op_movl_T0_0(void)
184 tcg_gen_movi_tl(cpu_T
[0], 0);
187 static inline void gen_op_movl_T0_im(int32_t val
)
189 tcg_gen_movi_tl(cpu_T
[0], val
);
192 static inline void gen_op_movl_T0_imu(uint32_t val
)
194 tcg_gen_movi_tl(cpu_T
[0], val
);
197 static inline void gen_op_movl_T1_im(int32_t val
)
199 tcg_gen_movi_tl(cpu_T
[1], val
);
202 static inline void gen_op_movl_T1_imu(uint32_t val
)
204 tcg_gen_movi_tl(cpu_T
[1], val
);
207 static inline void gen_op_movl_A0_im(uint32_t val
)
209 tcg_gen_movi_tl(cpu_A0
, val
);
213 static inline void gen_op_movq_A0_im(int64_t val
)
215 tcg_gen_movi_tl(cpu_A0
, val
);
219 static inline void gen_movtl_T0_im(target_ulong val
)
221 tcg_gen_movi_tl(cpu_T
[0], val
);
224 static inline void gen_movtl_T1_im(target_ulong val
)
226 tcg_gen_movi_tl(cpu_T
[1], val
);
229 static inline void gen_op_andl_T0_ffff(void)
231 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
234 static inline void gen_op_andl_T0_im(uint32_t val
)
236 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
239 static inline void gen_op_movl_T0_T1(void)
241 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
244 static inline void gen_op_andl_A0_ffff(void)
246 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
251 #define NB_OP_SIZES 4
253 #else /* !TARGET_X86_64 */
255 #define NB_OP_SIZES 3
257 #endif /* !TARGET_X86_64 */
259 #if defined(HOST_WORDS_BIGENDIAN)
260 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
261 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
262 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
263 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
264 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
266 #define REG_B_OFFSET 0
267 #define REG_H_OFFSET 1
268 #define REG_W_OFFSET 0
269 #define REG_L_OFFSET 0
270 #define REG_LH_OFFSET 4
273 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
279 tmp
= tcg_temp_new();
280 tcg_gen_ext8u_tl(tmp
, t0
);
281 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
282 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xff);
283 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
285 tcg_gen_shli_tl(tmp
, tmp
, 8);
286 tcg_gen_andi_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], ~0xff00);
287 tcg_gen_or_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], tmp
);
292 tmp
= tcg_temp_new();
293 tcg_gen_ext16u_tl(tmp
, t0
);
294 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
295 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
298 default: /* XXX this shouldn't be reached; abort? */
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
306 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
312 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
314 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
317 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
319 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
322 static inline void gen_op_mov_reg_A0(int size
, int reg
)
328 tmp
= tcg_temp_new();
329 tcg_gen_ext16u_tl(tmp
, cpu_A0
);
330 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
331 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], tmp
);
334 default: /* XXX this shouldn't be reached; abort? */
336 /* For x86_64, this sets the higher half of register to zero.
337 For i386, this is equivalent to a mov. */
338 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
342 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
348 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
352 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
355 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
356 tcg_gen_ext8u_tl(t0
, t0
);
361 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
366 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
368 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
371 static inline void gen_op_movl_A0_reg(int reg
)
373 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
376 static inline void gen_op_addl_A0_im(int32_t val
)
378 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
380 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
385 static inline void gen_op_addq_A0_im(int64_t val
)
387 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
391 static void gen_add_A0_im(DisasContext
*s
, int val
)
395 gen_op_addq_A0_im(val
);
398 gen_op_addl_A0_im(val
);
401 static inline void gen_op_addl_T0_T1(void)
403 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
406 static inline void gen_op_jmp_T0(void)
408 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, eip
));
411 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
415 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
416 tcg_gen_ext16u_tl(cpu_tmp0
, cpu_tmp0
);
417 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
418 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
);
421 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
422 /* For x86_64, this sets the higher half of register to zero.
423 For i386, this is equivalent to a nop. */
424 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
425 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
429 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
435 static inline void gen_op_add_reg_T0(int size
, int reg
)
439 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
440 tcg_gen_ext16u_tl(cpu_tmp0
, cpu_tmp0
);
441 tcg_gen_andi_tl(cpu_regs
[reg
], cpu_regs
[reg
], ~0xffff);
442 tcg_gen_or_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
);
445 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
446 /* For x86_64, this sets the higher half of register to zero.
447 For i386, this is equivalent to a nop. */
448 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
449 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
453 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
459 static inline void gen_op_set_cc_op(int32_t val
)
461 tcg_gen_movi_i32(cpu_cc_op
, val
);
464 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
466 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
468 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
469 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
470 /* For x86_64, this sets the higher half of register to zero.
471 For i386, this is equivalent to a nop. */
472 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
475 static inline void gen_op_movl_A0_seg(int reg
)
477 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
) + REG_L_OFFSET
);
480 static inline void gen_op_addl_A0_seg(int reg
)
482 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
483 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
485 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
490 static inline void gen_op_movq_A0_seg(int reg
)
492 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
495 static inline void gen_op_addq_A0_seg(int reg
)
497 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
498 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
501 static inline void gen_op_movq_A0_reg(int reg
)
503 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
506 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
508 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
510 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
511 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
515 static inline void gen_op_lds_T0_A0(int idx
)
517 int mem_index
= (idx
>> 2) - 1;
520 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
523 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
527 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
532 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
534 int mem_index
= (idx
>> 2) - 1;
537 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
540 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
543 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
547 /* Should never happen on 32-bit targets. */
549 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
555 /* XXX: always use ldu or lds */
556 static inline void gen_op_ld_T0_A0(int idx
)
558 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
561 static inline void gen_op_ldu_T0_A0(int idx
)
563 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
566 static inline void gen_op_ld_T1_A0(int idx
)
568 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
571 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
573 int mem_index
= (idx
>> 2) - 1;
576 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
579 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
582 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
586 /* Should never happen on 32-bit targets. */
588 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
594 static inline void gen_op_st_T0_A0(int idx
)
596 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
599 static inline void gen_op_st_T1_A0(int idx
)
601 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
604 static inline void gen_jmp_im(target_ulong pc
)
606 tcg_gen_movi_tl(cpu_tmp0
, pc
);
607 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, eip
));
610 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
614 override
= s
->override
;
618 gen_op_movq_A0_seg(override
);
619 gen_op_addq_A0_reg_sN(0, R_ESI
);
621 gen_op_movq_A0_reg(R_ESI
);
627 if (s
->addseg
&& override
< 0)
630 gen_op_movl_A0_seg(override
);
631 gen_op_addl_A0_reg_sN(0, R_ESI
);
633 gen_op_movl_A0_reg(R_ESI
);
636 /* 16 address, always override */
639 gen_op_movl_A0_reg(R_ESI
);
640 gen_op_andl_A0_ffff();
641 gen_op_addl_A0_seg(override
);
645 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
649 gen_op_movq_A0_reg(R_EDI
);
654 gen_op_movl_A0_seg(R_ES
);
655 gen_op_addl_A0_reg_sN(0, R_EDI
);
657 gen_op_movl_A0_reg(R_EDI
);
660 gen_op_movl_A0_reg(R_EDI
);
661 gen_op_andl_A0_ffff();
662 gen_op_addl_A0_seg(R_ES
);
666 static inline void gen_op_movl_T0_Dshift(int ot
)
668 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, df
));
669 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
672 static void gen_extu(int ot
, TCGv reg
)
676 tcg_gen_ext8u_tl(reg
, reg
);
679 tcg_gen_ext16u_tl(reg
, reg
);
682 tcg_gen_ext32u_tl(reg
, reg
);
689 static void gen_exts(int ot
, TCGv reg
)
693 tcg_gen_ext8s_tl(reg
, reg
);
696 tcg_gen_ext16s_tl(reg
, reg
);
699 tcg_gen_ext32s_tl(reg
, reg
);
706 static inline void gen_op_jnz_ecx(int size
, int label1
)
708 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
709 gen_extu(size
+ 1, cpu_tmp0
);
710 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
713 static inline void gen_op_jz_ecx(int size
, int label1
)
715 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
716 gen_extu(size
+ 1, cpu_tmp0
);
717 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
720 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
723 case 0: gen_helper_inb(v
, n
); break;
724 case 1: gen_helper_inw(v
, n
); break;
725 case 2: gen_helper_inl(v
, n
); break;
730 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
733 case 0: gen_helper_outb(v
, n
); break;
734 case 1: gen_helper_outw(v
, n
); break;
735 case 2: gen_helper_outl(v
, n
); break;
740 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
744 target_ulong next_eip
;
747 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
748 if (s
->cc_op
!= CC_OP_DYNAMIC
)
749 gen_op_set_cc_op(s
->cc_op
);
752 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
754 case 0: gen_helper_check_iob(cpu_tmp2_i32
); break;
755 case 1: gen_helper_check_iow(cpu_tmp2_i32
); break;
756 case 2: gen_helper_check_iol(cpu_tmp2_i32
); break;
759 if(s
->flags
& HF_SVMI_MASK
) {
761 if (s
->cc_op
!= CC_OP_DYNAMIC
)
762 gen_op_set_cc_op(s
->cc_op
);
766 svm_flags
|= (1 << (4 + ot
));
767 next_eip
= s
->pc
- s
->cs_base
;
768 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
769 gen_helper_svm_check_io(cpu_tmp2_i32
, tcg_const_i32(svm_flags
),
770 tcg_const_i32(next_eip
- cur_eip
));
774 static inline void gen_movs(DisasContext
*s
, int ot
)
776 gen_string_movl_A0_ESI(s
);
777 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
778 gen_string_movl_A0_EDI(s
);
779 gen_op_st_T0_A0(ot
+ s
->mem_index
);
780 gen_op_movl_T0_Dshift(ot
);
781 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
782 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
785 static inline void gen_update_cc_op(DisasContext
*s
)
787 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
788 gen_op_set_cc_op(s
->cc_op
);
789 s
->cc_op
= CC_OP_DYNAMIC
;
793 static void gen_op_update1_cc(void)
795 tcg_gen_discard_tl(cpu_cc_src
);
796 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
799 static void gen_op_update2_cc(void)
801 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
802 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
805 static inline void gen_op_cmpl_T0_T1_cc(void)
807 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
808 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
811 static inline void gen_op_testl_T0_T1_cc(void)
813 tcg_gen_discard_tl(cpu_cc_src
);
814 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
817 static void gen_op_update_neg_cc(void)
819 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
820 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
823 /* compute eflags.C to reg */
824 static void gen_compute_eflags_c(TCGv reg
)
826 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_cc_op
);
827 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
830 /* compute all eflags to cc_src */
831 static void gen_compute_eflags(TCGv reg
)
833 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_cc_op
);
834 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
837 static inline void gen_setcc_slow_T0(DisasContext
*s
, int jcc_op
)
839 if (s
->cc_op
!= CC_OP_DYNAMIC
)
840 gen_op_set_cc_op(s
->cc_op
);
843 gen_compute_eflags(cpu_T
[0]);
844 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 11);
845 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
848 gen_compute_eflags_c(cpu_T
[0]);
851 gen_compute_eflags(cpu_T
[0]);
852 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 6);
853 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
856 gen_compute_eflags(cpu_tmp0
);
857 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 6);
858 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
859 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
862 gen_compute_eflags(cpu_T
[0]);
863 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 7);
864 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
867 gen_compute_eflags(cpu_T
[0]);
868 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 2);
869 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
872 gen_compute_eflags(cpu_tmp0
);
873 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
874 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 7); /* CC_S */
875 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
876 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
880 gen_compute_eflags(cpu_tmp0
);
881 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
882 tcg_gen_shri_tl(cpu_tmp4
, cpu_tmp0
, 7); /* CC_S */
883 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 6); /* CC_Z */
884 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
885 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
886 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
891 /* return true if setcc_slow is not needed (WARNING: must be kept in
892 sync with gen_jcc1) */
893 static int is_fast_jcc_case(DisasContext
*s
, int b
)
896 jcc_op
= (b
>> 1) & 7;
898 /* we optimize the cmp/jcc case */
903 if (jcc_op
== JCC_O
|| jcc_op
== JCC_P
)
907 /* some jumps are easy to compute */
932 if (jcc_op
!= JCC_Z
&& jcc_op
!= JCC_S
)
942 /* generate a conditional jump to label 'l1' according to jump opcode
943 value 'b'. In the fast case, T0 is guaranted not to be used. */
944 static inline void gen_jcc1(DisasContext
*s
, int cc_op
, int b
, int l1
)
946 int inv
, jcc_op
, size
, cond
;
950 jcc_op
= (b
>> 1) & 7;
953 /* we optimize the cmp/jcc case */
959 size
= cc_op
- CC_OP_SUBB
;
965 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xff);
969 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffff);
974 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffffffff);
982 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
988 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80);
989 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
993 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x8000);
994 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
999 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80000000);
1000 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1005 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, cpu_cc_dst
,
1012 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1015 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1017 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1021 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xff);
1022 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xff);
1026 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffff);
1027 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffff);
1029 #ifdef TARGET_X86_64
1032 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffffffff);
1033 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffffffff);
1040 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1044 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1047 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1049 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1053 tcg_gen_ext8s_tl(cpu_tmp4
, cpu_tmp4
);
1054 tcg_gen_ext8s_tl(t0
, cpu_cc_src
);
1058 tcg_gen_ext16s_tl(cpu_tmp4
, cpu_tmp4
);
1059 tcg_gen_ext16s_tl(t0
, cpu_cc_src
);
1061 #ifdef TARGET_X86_64
1064 tcg_gen_ext32s_tl(cpu_tmp4
, cpu_tmp4
);
1065 tcg_gen_ext32s_tl(t0
, cpu_cc_src
);
1072 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1080 /* some jumps are easy to compute */
1122 size
= (cc_op
- CC_OP_ADDB
) & 3;
1125 size
= (cc_op
- CC_OP_ADDB
) & 3;
1133 gen_setcc_slow_T0(s
, jcc_op
);
1134 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1140 /* XXX: does not work with gdbstub "ice" single step - not a
1142 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1146 l1
= gen_new_label();
1147 l2
= gen_new_label();
1148 gen_op_jnz_ecx(s
->aflag
, l1
);
1150 gen_jmp_tb(s
, next_eip
, 1);
1155 static inline void gen_stos(DisasContext
*s
, int ot
)
1157 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1158 gen_string_movl_A0_EDI(s
);
1159 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1160 gen_op_movl_T0_Dshift(ot
);
1161 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1164 static inline void gen_lods(DisasContext
*s
, int ot
)
1166 gen_string_movl_A0_ESI(s
);
1167 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1168 gen_op_mov_reg_T0(ot
, R_EAX
);
1169 gen_op_movl_T0_Dshift(ot
);
1170 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1173 static inline void gen_scas(DisasContext
*s
, int ot
)
1175 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1176 gen_string_movl_A0_EDI(s
);
1177 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1178 gen_op_cmpl_T0_T1_cc();
1179 gen_op_movl_T0_Dshift(ot
);
1180 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1183 static inline void gen_cmps(DisasContext
*s
, int ot
)
1185 gen_string_movl_A0_ESI(s
);
1186 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1187 gen_string_movl_A0_EDI(s
);
1188 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot
);
1191 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1192 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1195 static inline void gen_ins(DisasContext
*s
, int ot
)
1199 gen_string_movl_A0_EDI(s
);
1200 /* Note: we must do this dummy write first to be restartable in
1201 case of page fault. */
1203 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1204 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1205 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1206 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1207 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1208 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1209 gen_op_movl_T0_Dshift(ot
);
1210 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1215 static inline void gen_outs(DisasContext
*s
, int ot
)
1219 gen_string_movl_A0_ESI(s
);
1220 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1222 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1224 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1225 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1226 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1228 gen_op_movl_T0_Dshift(ot
);
1229 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1234 /* same method as Valgrind : we generate jumps to current or next
1236 #define GEN_REPZ(op) \
1237 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1238 target_ulong cur_eip, target_ulong next_eip) \
1241 gen_update_cc_op(s); \
1242 l2 = gen_jz_ecx_string(s, next_eip); \
1243 gen_ ## op(s, ot); \
1244 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1245 /* a loop would cause two single step exceptions if ECX = 1 \
1246 before rep string_insn */ \
1248 gen_op_jz_ecx(s->aflag, l2); \
1249 gen_jmp(s, cur_eip); \
1252 #define GEN_REPZ2(op) \
1253 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1254 target_ulong cur_eip, \
1255 target_ulong next_eip, \
1259 gen_update_cc_op(s); \
1260 l2 = gen_jz_ecx_string(s, next_eip); \
1261 gen_ ## op(s, ot); \
1262 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1263 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1264 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1266 gen_op_jz_ecx(s->aflag, l2); \
1267 gen_jmp(s, cur_eip); \
1278 static void gen_helper_fp_arith_ST0_FT0(int op
)
1281 case 0: gen_helper_fadd_ST0_FT0(); break;
1282 case 1: gen_helper_fmul_ST0_FT0(); break;
1283 case 2: gen_helper_fcom_ST0_FT0(); break;
1284 case 3: gen_helper_fcom_ST0_FT0(); break;
1285 case 4: gen_helper_fsub_ST0_FT0(); break;
1286 case 5: gen_helper_fsubr_ST0_FT0(); break;
1287 case 6: gen_helper_fdiv_ST0_FT0(); break;
1288 case 7: gen_helper_fdivr_ST0_FT0(); break;
1292 /* NOTE the exception in "r" op ordering */
1293 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1295 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1297 case 0: gen_helper_fadd_STN_ST0(tmp
); break;
1298 case 1: gen_helper_fmul_STN_ST0(tmp
); break;
1299 case 4: gen_helper_fsubr_STN_ST0(tmp
); break;
1300 case 5: gen_helper_fsub_STN_ST0(tmp
); break;
1301 case 6: gen_helper_fdivr_STN_ST0(tmp
); break;
1302 case 7: gen_helper_fdiv_STN_ST0(tmp
); break;
1306 /* if d == OR_TMP0, it means memory operand (address in A0) */
1307 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1310 gen_op_mov_TN_reg(ot
, 0, d
);
1312 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1316 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1317 gen_op_set_cc_op(s1
->cc_op
);
1318 gen_compute_eflags_c(cpu_tmp4
);
1319 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1320 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1322 gen_op_mov_reg_T0(ot
, d
);
1324 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1325 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1326 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1327 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1328 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1329 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1330 s1
->cc_op
= CC_OP_DYNAMIC
;
1333 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1334 gen_op_set_cc_op(s1
->cc_op
);
1335 gen_compute_eflags_c(cpu_tmp4
);
1336 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1337 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1339 gen_op_mov_reg_T0(ot
, d
);
1341 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1342 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1343 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1344 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1345 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1346 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1347 s1
->cc_op
= CC_OP_DYNAMIC
;
1350 gen_op_addl_T0_T1();
1352 gen_op_mov_reg_T0(ot
, d
);
1354 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1355 gen_op_update2_cc();
1356 s1
->cc_op
= CC_OP_ADDB
+ ot
;
1359 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1361 gen_op_mov_reg_T0(ot
, d
);
1363 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1364 gen_op_update2_cc();
1365 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1369 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1371 gen_op_mov_reg_T0(ot
, d
);
1373 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1374 gen_op_update1_cc();
1375 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1378 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1380 gen_op_mov_reg_T0(ot
, d
);
1382 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1383 gen_op_update1_cc();
1384 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1387 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1389 gen_op_mov_reg_T0(ot
, d
);
1391 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1392 gen_op_update1_cc();
1393 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1396 gen_op_cmpl_T0_T1_cc();
1397 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1402 /* if d == OR_TMP0, it means memory operand (address in A0) */
1403 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1406 gen_op_mov_TN_reg(ot
, 0, d
);
1408 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1409 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1410 gen_op_set_cc_op(s1
->cc_op
);
1412 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1413 s1
->cc_op
= CC_OP_INCB
+ ot
;
1415 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1416 s1
->cc_op
= CC_OP_DECB
+ ot
;
1419 gen_op_mov_reg_T0(ot
, d
);
1421 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1422 gen_compute_eflags_c(cpu_cc_src
);
1423 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1426 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1427 int is_right
, int is_arith
)
1440 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1442 gen_op_mov_TN_reg(ot
, 0, op1
);
1444 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1446 tcg_gen_addi_tl(cpu_tmp5
, cpu_T
[1], -1);
1450 gen_exts(ot
, cpu_T
[0]);
1451 tcg_gen_sar_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1452 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1454 gen_extu(ot
, cpu_T
[0]);
1455 tcg_gen_shr_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1456 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1459 tcg_gen_shl_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1460 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1465 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1467 gen_op_mov_reg_T0(ot
, op1
);
1469 /* update eflags if non zero shift */
1470 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1471 gen_op_set_cc_op(s
->cc_op
);
1473 /* XXX: inefficient */
1474 t0
= tcg_temp_local_new();
1475 t1
= tcg_temp_local_new();
1477 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1478 tcg_gen_mov_tl(t1
, cpu_T3
);
1480 shift_label
= gen_new_label();
1481 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_T
[1], 0, shift_label
);
1483 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1484 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1486 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1488 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1490 gen_set_label(shift_label
);
1491 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1497 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1498 int is_right
, int is_arith
)
1509 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1511 gen_op_mov_TN_reg(ot
, 0, op1
);
1517 gen_exts(ot
, cpu_T
[0]);
1518 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1519 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1521 gen_extu(ot
, cpu_T
[0]);
1522 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1523 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1526 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1527 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1533 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1535 gen_op_mov_reg_T0(ot
, op1
);
1537 /* update eflags if non zero shift */
1539 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1540 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1542 s
->cc_op
= CC_OP_SARB
+ ot
;
1544 s
->cc_op
= CC_OP_SHLB
+ ot
;
1548 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1551 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1553 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1556 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1560 int label1
, label2
, data_bits
;
1561 TCGv t0
, t1
, t2
, a0
;
1563 /* XXX: inefficient, but we must use local temps */
1564 t0
= tcg_temp_local_new();
1565 t1
= tcg_temp_local_new();
1566 t2
= tcg_temp_local_new();
1567 a0
= tcg_temp_local_new();
1575 if (op1
== OR_TMP0
) {
1576 tcg_gen_mov_tl(a0
, cpu_A0
);
1577 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1579 gen_op_mov_v_reg(ot
, t0
, op1
);
1582 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1584 tcg_gen_andi_tl(t1
, t1
, mask
);
1586 /* Must test zero case to avoid using undefined behaviour in TCG
1588 label1
= gen_new_label();
1589 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1592 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1594 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1597 tcg_gen_mov_tl(t2
, t0
);
1599 data_bits
= 8 << ot
;
1600 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1601 fix TCG definition) */
1603 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1604 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1605 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1607 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1608 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1609 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1611 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1613 gen_set_label(label1
);
1615 if (op1
== OR_TMP0
) {
1616 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1618 gen_op_mov_reg_v(ot
, op1
, t0
);
1622 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1623 gen_op_set_cc_op(s
->cc_op
);
1625 label2
= gen_new_label();
1626 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1628 gen_compute_eflags(cpu_cc_src
);
1629 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1630 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1631 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1632 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1633 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1635 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1637 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1638 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1640 tcg_gen_discard_tl(cpu_cc_dst
);
1641 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1643 gen_set_label(label2
);
1644 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1652 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1659 /* XXX: inefficient, but we must use local temps */
1660 t0
= tcg_temp_local_new();
1661 t1
= tcg_temp_local_new();
1662 a0
= tcg_temp_local_new();
1670 if (op1
== OR_TMP0
) {
1671 tcg_gen_mov_tl(a0
, cpu_A0
);
1672 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1674 gen_op_mov_v_reg(ot
, t0
, op1
);
1678 tcg_gen_mov_tl(t1
, t0
);
1681 data_bits
= 8 << ot
;
1683 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1685 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1686 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1689 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1690 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1692 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1696 if (op1
== OR_TMP0
) {
1697 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1699 gen_op_mov_reg_v(ot
, op1
, t0
);
1704 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1705 gen_op_set_cc_op(s
->cc_op
);
1707 gen_compute_eflags(cpu_cc_src
);
1708 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1709 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1710 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1711 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1712 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1714 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1716 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1717 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1719 tcg_gen_discard_tl(cpu_cc_dst
);
1720 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1721 s
->cc_op
= CC_OP_EFLAGS
;
1729 /* XXX: add faster immediate = 1 case */
1730 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1735 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1736 gen_op_set_cc_op(s
->cc_op
);
1740 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1742 gen_op_mov_TN_reg(ot
, 0, op1
);
1746 case 0: gen_helper_rcrb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1747 case 1: gen_helper_rcrw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1748 case 2: gen_helper_rcrl(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1749 #ifdef TARGET_X86_64
1750 case 3: gen_helper_rcrq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1755 case 0: gen_helper_rclb(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1756 case 1: gen_helper_rclw(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1757 case 2: gen_helper_rcll(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1758 #ifdef TARGET_X86_64
1759 case 3: gen_helper_rclq(cpu_T
[0], cpu_T
[0], cpu_T
[1]); break;
1765 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1767 gen_op_mov_reg_T0(ot
, op1
);
1770 label1
= gen_new_label();
1771 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cc_tmp
, -1, label1
);
1773 tcg_gen_mov_tl(cpu_cc_src
, cpu_cc_tmp
);
1774 tcg_gen_discard_tl(cpu_cc_dst
);
1775 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1777 gen_set_label(label1
);
1778 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1781 /* XXX: add faster immediate case */
1782 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1785 int label1
, label2
, data_bits
;
1787 TCGv t0
, t1
, t2
, a0
;
1789 t0
= tcg_temp_local_new();
1790 t1
= tcg_temp_local_new();
1791 t2
= tcg_temp_local_new();
1792 a0
= tcg_temp_local_new();
1800 if (op1
== OR_TMP0
) {
1801 tcg_gen_mov_tl(a0
, cpu_A0
);
1802 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1804 gen_op_mov_v_reg(ot
, t0
, op1
);
1807 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1809 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1810 tcg_gen_mov_tl(t2
, cpu_T3
);
1812 /* Must test zero case to avoid using undefined behaviour in TCG
1814 label1
= gen_new_label();
1815 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1817 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1818 if (ot
== OT_WORD
) {
1819 /* Note: we implement the Intel behaviour for shift count > 16 */
1821 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1822 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1823 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1824 tcg_gen_ext32u_tl(t0
, t0
);
1826 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1828 /* only needed if count > 16, but a test would complicate */
1829 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1830 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1832 tcg_gen_shr_tl(t0
, t0
, t2
);
1834 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1836 /* XXX: not optimal */
1837 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1838 tcg_gen_shli_tl(t1
, t1
, 16);
1839 tcg_gen_or_tl(t1
, t1
, t0
);
1840 tcg_gen_ext32u_tl(t1
, t1
);
1842 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1843 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1844 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1845 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
1847 tcg_gen_shl_tl(t0
, t0
, t2
);
1848 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1849 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1850 tcg_gen_or_tl(t0
, t0
, t1
);
1853 data_bits
= 8 << ot
;
1856 tcg_gen_ext32u_tl(t0
, t0
);
1858 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1860 tcg_gen_shr_tl(t0
, t0
, t2
);
1861 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1862 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1863 tcg_gen_or_tl(t0
, t0
, t1
);
1867 tcg_gen_ext32u_tl(t1
, t1
);
1869 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1871 tcg_gen_shl_tl(t0
, t0
, t2
);
1872 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1873 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1874 tcg_gen_or_tl(t0
, t0
, t1
);
1877 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1879 gen_set_label(label1
);
1881 if (op1
== OR_TMP0
) {
1882 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1884 gen_op_mov_reg_v(ot
, op1
, t0
);
1888 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1889 gen_op_set_cc_op(s
->cc_op
);
1891 label2
= gen_new_label();
1892 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1894 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1895 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1897 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1899 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1901 gen_set_label(label2
);
1902 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1910 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1913 gen_op_mov_TN_reg(ot
, 1, s
);
1916 gen_rot_rm_T1(s1
, ot
, d
, 0);
1919 gen_rot_rm_T1(s1
, ot
, d
, 1);
1923 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1926 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1929 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1932 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1935 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1940 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1944 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1947 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1951 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1954 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1957 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1960 /* currently not optimized */
1961 gen_op_movl_T1_im(c
);
1962 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1967 static void gen_lea_modrm(DisasContext
*s
, int modrm
, int *reg_ptr
, int *offset_ptr
)
1975 int mod
, rm
, code
, override
, must_add_seg
;
1977 override
= s
->override
;
1978 must_add_seg
= s
->addseg
;
1981 mod
= (modrm
>> 6) & 3;
1993 code
= ldub_code(s
->pc
++);
1994 scale
= (code
>> 6) & 3;
1995 index
= ((code
>> 3) & 7) | REX_X(s
);
2002 if ((base
& 7) == 5) {
2004 disp
= (int32_t)ldl_code(s
->pc
);
2006 if (CODE64(s
) && !havesib
) {
2007 disp
+= s
->pc
+ s
->rip_offset
;
2014 disp
= (int8_t)ldub_code(s
->pc
++);
2018 disp
= ldl_code(s
->pc
);
2024 /* for correct popl handling with esp */
2025 if (base
== 4 && s
->popl_esp_hack
)
2026 disp
+= s
->popl_esp_hack
;
2027 #ifdef TARGET_X86_64
2028 if (s
->aflag
== 2) {
2029 gen_op_movq_A0_reg(base
);
2031 gen_op_addq_A0_im(disp
);
2036 gen_op_movl_A0_reg(base
);
2038 gen_op_addl_A0_im(disp
);
2041 #ifdef TARGET_X86_64
2042 if (s
->aflag
== 2) {
2043 gen_op_movq_A0_im(disp
);
2047 gen_op_movl_A0_im(disp
);
2050 /* XXX: index == 4 is always invalid */
2051 if (havesib
&& (index
!= 4 || scale
!= 0)) {
2052 #ifdef TARGET_X86_64
2053 if (s
->aflag
== 2) {
2054 gen_op_addq_A0_reg_sN(scale
, index
);
2058 gen_op_addl_A0_reg_sN(scale
, index
);
2063 if (base
== R_EBP
|| base
== R_ESP
)
2068 #ifdef TARGET_X86_64
2069 if (s
->aflag
== 2) {
2070 gen_op_addq_A0_seg(override
);
2074 gen_op_addl_A0_seg(override
);
2081 disp
= lduw_code(s
->pc
);
2083 gen_op_movl_A0_im(disp
);
2084 rm
= 0; /* avoid SS override */
2091 disp
= (int8_t)ldub_code(s
->pc
++);
2095 disp
= lduw_code(s
->pc
);
2101 gen_op_movl_A0_reg(R_EBX
);
2102 gen_op_addl_A0_reg_sN(0, R_ESI
);
2105 gen_op_movl_A0_reg(R_EBX
);
2106 gen_op_addl_A0_reg_sN(0, R_EDI
);
2109 gen_op_movl_A0_reg(R_EBP
);
2110 gen_op_addl_A0_reg_sN(0, R_ESI
);
2113 gen_op_movl_A0_reg(R_EBP
);
2114 gen_op_addl_A0_reg_sN(0, R_EDI
);
2117 gen_op_movl_A0_reg(R_ESI
);
2120 gen_op_movl_A0_reg(R_EDI
);
2123 gen_op_movl_A0_reg(R_EBP
);
2127 gen_op_movl_A0_reg(R_EBX
);
2131 gen_op_addl_A0_im(disp
);
2132 gen_op_andl_A0_ffff();
2136 if (rm
== 2 || rm
== 3 || rm
== 6)
2141 gen_op_addl_A0_seg(override
);
2151 static void gen_nop_modrm(DisasContext
*s
, int modrm
)
2153 int mod
, rm
, base
, code
;
2155 mod
= (modrm
>> 6) & 3;
2165 code
= ldub_code(s
->pc
++);
2201 /* used for LEA and MOV AX, mem */
2202 static void gen_add_A0_ds_seg(DisasContext
*s
)
2204 int override
, must_add_seg
;
2205 must_add_seg
= s
->addseg
;
2207 if (s
->override
>= 0) {
2208 override
= s
->override
;
2214 #ifdef TARGET_X86_64
2216 gen_op_addq_A0_seg(override
);
2220 gen_op_addl_A0_seg(override
);
2225 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2227 static void gen_ldst_modrm(DisasContext
*s
, int modrm
, int ot
, int reg
, int is_store
)
2229 int mod
, rm
, opreg
, disp
;
2231 mod
= (modrm
>> 6) & 3;
2232 rm
= (modrm
& 7) | REX_B(s
);
2236 gen_op_mov_TN_reg(ot
, 0, reg
);
2237 gen_op_mov_reg_T0(ot
, rm
);
2239 gen_op_mov_TN_reg(ot
, 0, rm
);
2241 gen_op_mov_reg_T0(ot
, reg
);
2244 gen_lea_modrm(s
, modrm
, &opreg
, &disp
);
2247 gen_op_mov_TN_reg(ot
, 0, reg
);
2248 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2250 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2252 gen_op_mov_reg_T0(ot
, reg
);
2257 static inline uint32_t insn_get(DisasContext
*s
, int ot
)
2263 ret
= ldub_code(s
->pc
);
2267 ret
= lduw_code(s
->pc
);
2272 ret
= ldl_code(s
->pc
);
2279 static inline int insn_const_size(unsigned int ot
)
2287 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2289 TranslationBlock
*tb
;
2292 pc
= s
->cs_base
+ eip
;
2294 /* NOTE: we handle the case where the TB spans two pages here */
2295 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2296 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2297 /* jump to same page: we can use a direct jump */
2298 tcg_gen_goto_tb(tb_num
);
2300 tcg_gen_exit_tb((long)tb
+ tb_num
);
2302 /* jump to another page: currently not optimized */
2308 static inline void gen_jcc(DisasContext
*s
, int b
,
2309 target_ulong val
, target_ulong next_eip
)
2314 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2315 gen_op_set_cc_op(s
->cc_op
);
2316 s
->cc_op
= CC_OP_DYNAMIC
;
2319 l1
= gen_new_label();
2320 gen_jcc1(s
, cc_op
, b
, l1
);
2322 gen_goto_tb(s
, 0, next_eip
);
2325 gen_goto_tb(s
, 1, val
);
2329 l1
= gen_new_label();
2330 l2
= gen_new_label();
2331 gen_jcc1(s
, cc_op
, b
, l1
);
2333 gen_jmp_im(next_eip
);
2343 static void gen_setcc(DisasContext
*s
, int b
)
2345 int inv
, jcc_op
, l1
;
2348 if (is_fast_jcc_case(s
, b
)) {
2349 /* nominal case: we use a jump */
2350 /* XXX: make it faster by adding new instructions in TCG */
2351 t0
= tcg_temp_local_new();
2352 tcg_gen_movi_tl(t0
, 0);
2353 l1
= gen_new_label();
2354 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
2355 tcg_gen_movi_tl(t0
, 1);
2357 tcg_gen_mov_tl(cpu_T
[0], t0
);
2360 /* slow case: it is more efficient not to generate a jump,
2361 although it is questionnable whether this optimization is
2364 jcc_op
= (b
>> 1) & 7;
2365 gen_setcc_slow_T0(s
, jcc_op
);
2367 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], 1);
2372 static inline void gen_op_movl_T0_seg(int seg_reg
)
2374 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2375 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2378 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2380 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2381 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2382 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2383 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2384 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2385 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2388 /* move T0 to seg_reg and compute if the CPU state may change. Never
2389 call this function with seg_reg == R_CS */
2390 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2392 if (s
->pe
&& !s
->vm86
) {
2393 /* XXX: optimize by finding processor state dynamically */
2394 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2395 gen_op_set_cc_op(s
->cc_op
);
2396 gen_jmp_im(cur_eip
);
2397 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2398 gen_helper_load_seg(tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2399 /* abort translation because the addseg value may change or
2400 because ss32 may change. For R_SS, translation must always
2401 stop as a special handling must be done to disable hardware
2402 interrupts for the next instruction */
2403 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2406 gen_op_movl_seg_T0_vm(seg_reg
);
2407 if (seg_reg
== R_SS
)
2412 static inline int svm_is_rep(int prefixes
)
2414 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2418 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2419 uint32_t type
, uint64_t param
)
2421 /* no SVM activated; fast case */
2422 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2424 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2425 gen_op_set_cc_op(s
->cc_op
);
2426 gen_jmp_im(pc_start
- s
->cs_base
);
2427 gen_helper_svm_check_intercept_param(tcg_const_i32(type
),
2428 tcg_const_i64(param
));
2432 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2434 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2437 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2439 #ifdef TARGET_X86_64
2441 gen_op_add_reg_im(2, R_ESP
, addend
);
2445 gen_op_add_reg_im(1, R_ESP
, addend
);
2447 gen_op_add_reg_im(0, R_ESP
, addend
);
2451 /* generate a push. It depends on ss32, addseg and dflag */
2452 static void gen_push_T0(DisasContext
*s
)
2454 #ifdef TARGET_X86_64
2456 gen_op_movq_A0_reg(R_ESP
);
2458 gen_op_addq_A0_im(-8);
2459 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2461 gen_op_addq_A0_im(-2);
2462 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2464 gen_op_mov_reg_A0(2, R_ESP
);
2468 gen_op_movl_A0_reg(R_ESP
);
2470 gen_op_addl_A0_im(-2);
2472 gen_op_addl_A0_im(-4);
2475 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2476 gen_op_addl_A0_seg(R_SS
);
2479 gen_op_andl_A0_ffff();
2480 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2481 gen_op_addl_A0_seg(R_SS
);
2483 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2484 if (s
->ss32
&& !s
->addseg
)
2485 gen_op_mov_reg_A0(1, R_ESP
);
2487 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2491 /* generate a push. It depends on ss32, addseg and dflag */
2492 /* slower version for T1, only used for call Ev */
2493 static void gen_push_T1(DisasContext
*s
)
2495 #ifdef TARGET_X86_64
2497 gen_op_movq_A0_reg(R_ESP
);
2499 gen_op_addq_A0_im(-8);
2500 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2502 gen_op_addq_A0_im(-2);
2503 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2505 gen_op_mov_reg_A0(2, R_ESP
);
2509 gen_op_movl_A0_reg(R_ESP
);
2511 gen_op_addl_A0_im(-2);
2513 gen_op_addl_A0_im(-4);
2516 gen_op_addl_A0_seg(R_SS
);
2519 gen_op_andl_A0_ffff();
2520 gen_op_addl_A0_seg(R_SS
);
2522 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2524 if (s
->ss32
&& !s
->addseg
)
2525 gen_op_mov_reg_A0(1, R_ESP
);
2527 gen_stack_update(s
, (-2) << s
->dflag
);
2531 /* two step pop is necessary for precise exceptions */
2532 static void gen_pop_T0(DisasContext
*s
)
2534 #ifdef TARGET_X86_64
2536 gen_op_movq_A0_reg(R_ESP
);
2537 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2541 gen_op_movl_A0_reg(R_ESP
);
2544 gen_op_addl_A0_seg(R_SS
);
2546 gen_op_andl_A0_ffff();
2547 gen_op_addl_A0_seg(R_SS
);
2549 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2553 static void gen_pop_update(DisasContext
*s
)
2555 #ifdef TARGET_X86_64
2556 if (CODE64(s
) && s
->dflag
) {
2557 gen_stack_update(s
, 8);
2561 gen_stack_update(s
, 2 << s
->dflag
);
2565 static void gen_stack_A0(DisasContext
*s
)
2567 gen_op_movl_A0_reg(R_ESP
);
2569 gen_op_andl_A0_ffff();
2570 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2572 gen_op_addl_A0_seg(R_SS
);
2575 /* NOTE: wrap around in 16 bit not fully handled */
2576 static void gen_pusha(DisasContext
*s
)
2579 gen_op_movl_A0_reg(R_ESP
);
2580 gen_op_addl_A0_im(-16 << s
->dflag
);
2582 gen_op_andl_A0_ffff();
2583 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2585 gen_op_addl_A0_seg(R_SS
);
2586 for(i
= 0;i
< 8; i
++) {
2587 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2588 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2589 gen_op_addl_A0_im(2 << s
->dflag
);
2591 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2594 /* NOTE: wrap around in 16 bit not fully handled */
2595 static void gen_popa(DisasContext
*s
)
2598 gen_op_movl_A0_reg(R_ESP
);
2600 gen_op_andl_A0_ffff();
2601 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2602 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2604 gen_op_addl_A0_seg(R_SS
);
2605 for(i
= 0;i
< 8; i
++) {
2606 /* ESP is not reloaded */
2608 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2609 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2611 gen_op_addl_A0_im(2 << s
->dflag
);
2613 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2616 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2621 #ifdef TARGET_X86_64
2623 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2626 gen_op_movl_A0_reg(R_ESP
);
2627 gen_op_addq_A0_im(-opsize
);
2628 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2631 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2632 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2634 /* XXX: must save state */
2635 gen_helper_enter64_level(tcg_const_i32(level
),
2636 tcg_const_i32((ot
== OT_QUAD
)),
2639 gen_op_mov_reg_T1(ot
, R_EBP
);
2640 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2641 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2645 ot
= s
->dflag
+ OT_WORD
;
2646 opsize
= 2 << s
->dflag
;
2648 gen_op_movl_A0_reg(R_ESP
);
2649 gen_op_addl_A0_im(-opsize
);
2651 gen_op_andl_A0_ffff();
2652 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2654 gen_op_addl_A0_seg(R_SS
);
2656 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2657 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2659 /* XXX: must save state */
2660 gen_helper_enter_level(tcg_const_i32(level
),
2661 tcg_const_i32(s
->dflag
),
2664 gen_op_mov_reg_T1(ot
, R_EBP
);
2665 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2666 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2670 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2672 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2673 gen_op_set_cc_op(s
->cc_op
);
2674 gen_jmp_im(cur_eip
);
2675 gen_helper_raise_exception(tcg_const_i32(trapno
));
2679 /* an interrupt is different from an exception because of the
2681 static void gen_interrupt(DisasContext
*s
, int intno
,
2682 target_ulong cur_eip
, target_ulong next_eip
)
2684 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2685 gen_op_set_cc_op(s
->cc_op
);
2686 gen_jmp_im(cur_eip
);
2687 gen_helper_raise_interrupt(tcg_const_i32(intno
),
2688 tcg_const_i32(next_eip
- cur_eip
));
2692 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2694 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2695 gen_op_set_cc_op(s
->cc_op
);
2696 gen_jmp_im(cur_eip
);
2701 /* generate a generic end of block. Trace exception is also generated
2703 static void gen_eob(DisasContext
*s
)
2705 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2706 gen_op_set_cc_op(s
->cc_op
);
2707 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2708 gen_helper_reset_inhibit_irq();
2710 if (s
->tb
->flags
& HF_RF_MASK
) {
2711 gen_helper_reset_rf();
2713 if (s
->singlestep_enabled
) {
2716 gen_helper_single_step();
2723 /* generate a jump to eip. No segment change must happen before as a
2724 direct call to the next block may occur */
2725 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2728 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2729 gen_op_set_cc_op(s
->cc_op
);
2730 s
->cc_op
= CC_OP_DYNAMIC
;
2732 gen_goto_tb(s
, tb_num
, eip
);
2740 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2742 gen_jmp_tb(s
, eip
, 0);
2745 static inline void gen_ldq_env_A0(int idx
, int offset
)
2747 int mem_index
= (idx
>> 2) - 1;
2748 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2749 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2752 static inline void gen_stq_env_A0(int idx
, int offset
)
2754 int mem_index
= (idx
>> 2) - 1;
2755 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2756 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2759 static inline void gen_ldo_env_A0(int idx
, int offset
)
2761 int mem_index
= (idx
>> 2) - 1;
2762 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2763 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2764 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2765 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2766 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2769 static inline void gen_sto_env_A0(int idx
, int offset
)
2771 int mem_index
= (idx
>> 2) - 1;
2772 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2773 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2774 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2775 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2776 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2779 static inline void gen_op_movo(int d_offset
, int s_offset
)
2781 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2782 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2783 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2784 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2787 static inline void gen_op_movq(int d_offset
, int s_offset
)
2789 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2790 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2793 static inline void gen_op_movl(int d_offset
, int s_offset
)
2795 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2796 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2799 static inline void gen_op_movq_env_0(int d_offset
)
2801 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2802 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2805 #define SSE_SPECIAL ((void *)1)
2806 #define SSE_DUMMY ((void *)2)
2808 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2809 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2810 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2812 static void *sse_op_table1
[256][4] = {
2813 /* 3DNow! extensions */
2814 [0x0e] = { SSE_DUMMY
}, /* femms */
2815 [0x0f] = { SSE_DUMMY
}, /* pf... */
2816 /* pure SSE operations */
2817 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2818 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2819 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2820 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2821 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2822 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2823 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2824 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2826 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2827 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2828 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2829 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd */
2830 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2831 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2832 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2833 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2834 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2835 [0x51] = SSE_FOP(sqrt
),
2836 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2837 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2838 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2839 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2840 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2841 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2842 [0x58] = SSE_FOP(add
),
2843 [0x59] = SSE_FOP(mul
),
2844 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2845 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2846 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2847 [0x5c] = SSE_FOP(sub
),
2848 [0x5d] = SSE_FOP(min
),
2849 [0x5e] = SSE_FOP(div
),
2850 [0x5f] = SSE_FOP(max
),
2852 [0xc2] = SSE_FOP(cmpeq
),
2853 [0xc6] = { gen_helper_shufps
, gen_helper_shufpd
},
2855 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2856 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2858 /* MMX ops and their SSE extensions */
2859 [0x60] = MMX_OP2(punpcklbw
),
2860 [0x61] = MMX_OP2(punpcklwd
),
2861 [0x62] = MMX_OP2(punpckldq
),
2862 [0x63] = MMX_OP2(packsswb
),
2863 [0x64] = MMX_OP2(pcmpgtb
),
2864 [0x65] = MMX_OP2(pcmpgtw
),
2865 [0x66] = MMX_OP2(pcmpgtl
),
2866 [0x67] = MMX_OP2(packuswb
),
2867 [0x68] = MMX_OP2(punpckhbw
),
2868 [0x69] = MMX_OP2(punpckhwd
),
2869 [0x6a] = MMX_OP2(punpckhdq
),
2870 [0x6b] = MMX_OP2(packssdw
),
2871 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2872 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2873 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2874 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2875 [0x70] = { gen_helper_pshufw_mmx
,
2876 gen_helper_pshufd_xmm
,
2877 gen_helper_pshufhw_xmm
,
2878 gen_helper_pshuflw_xmm
},
2879 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2880 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2881 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2882 [0x74] = MMX_OP2(pcmpeqb
),
2883 [0x75] = MMX_OP2(pcmpeqw
),
2884 [0x76] = MMX_OP2(pcmpeql
),
2885 [0x77] = { SSE_DUMMY
}, /* emms */
2886 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2887 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2888 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2889 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2890 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2891 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2892 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2893 [0xd1] = MMX_OP2(psrlw
),
2894 [0xd2] = MMX_OP2(psrld
),
2895 [0xd3] = MMX_OP2(psrlq
),
2896 [0xd4] = MMX_OP2(paddq
),
2897 [0xd5] = MMX_OP2(pmullw
),
2898 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2899 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2900 [0xd8] = MMX_OP2(psubusb
),
2901 [0xd9] = MMX_OP2(psubusw
),
2902 [0xda] = MMX_OP2(pminub
),
2903 [0xdb] = MMX_OP2(pand
),
2904 [0xdc] = MMX_OP2(paddusb
),
2905 [0xdd] = MMX_OP2(paddusw
),
2906 [0xde] = MMX_OP2(pmaxub
),
2907 [0xdf] = MMX_OP2(pandn
),
2908 [0xe0] = MMX_OP2(pavgb
),
2909 [0xe1] = MMX_OP2(psraw
),
2910 [0xe2] = MMX_OP2(psrad
),
2911 [0xe3] = MMX_OP2(pavgw
),
2912 [0xe4] = MMX_OP2(pmulhuw
),
2913 [0xe5] = MMX_OP2(pmulhw
),
2914 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2915 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2916 [0xe8] = MMX_OP2(psubsb
),
2917 [0xe9] = MMX_OP2(psubsw
),
2918 [0xea] = MMX_OP2(pminsw
),
2919 [0xeb] = MMX_OP2(por
),
2920 [0xec] = MMX_OP2(paddsb
),
2921 [0xed] = MMX_OP2(paddsw
),
2922 [0xee] = MMX_OP2(pmaxsw
),
2923 [0xef] = MMX_OP2(pxor
),
2924 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2925 [0xf1] = MMX_OP2(psllw
),
2926 [0xf2] = MMX_OP2(pslld
),
2927 [0xf3] = MMX_OP2(psllq
),
2928 [0xf4] = MMX_OP2(pmuludq
),
2929 [0xf5] = MMX_OP2(pmaddwd
),
2930 [0xf6] = MMX_OP2(psadbw
),
2931 [0xf7] = MMX_OP2(maskmov
),
2932 [0xf8] = MMX_OP2(psubb
),
2933 [0xf9] = MMX_OP2(psubw
),
2934 [0xfa] = MMX_OP2(psubl
),
2935 [0xfb] = MMX_OP2(psubq
),
2936 [0xfc] = MMX_OP2(paddb
),
2937 [0xfd] = MMX_OP2(paddw
),
2938 [0xfe] = MMX_OP2(paddl
),
2941 static void *sse_op_table2
[3 * 8][2] = {
2942 [0 + 2] = MMX_OP2(psrlw
),
2943 [0 + 4] = MMX_OP2(psraw
),
2944 [0 + 6] = MMX_OP2(psllw
),
2945 [8 + 2] = MMX_OP2(psrld
),
2946 [8 + 4] = MMX_OP2(psrad
),
2947 [8 + 6] = MMX_OP2(pslld
),
2948 [16 + 2] = MMX_OP2(psrlq
),
2949 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2950 [16 + 6] = MMX_OP2(psllq
),
2951 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2954 static void *sse_op_table3
[4 * 3] = {
2955 gen_helper_cvtsi2ss
,
2956 gen_helper_cvtsi2sd
,
2957 X86_64_ONLY(gen_helper_cvtsq2ss
),
2958 X86_64_ONLY(gen_helper_cvtsq2sd
),
2960 gen_helper_cvttss2si
,
2961 gen_helper_cvttsd2si
,
2962 X86_64_ONLY(gen_helper_cvttss2sq
),
2963 X86_64_ONLY(gen_helper_cvttsd2sq
),
2965 gen_helper_cvtss2si
,
2966 gen_helper_cvtsd2si
,
2967 X86_64_ONLY(gen_helper_cvtss2sq
),
2968 X86_64_ONLY(gen_helper_cvtsd2sq
),
2971 static void *sse_op_table4
[8][4] = {
2982 static void *sse_op_table5
[256] = {
2983 [0x0c] = gen_helper_pi2fw
,
2984 [0x0d] = gen_helper_pi2fd
,
2985 [0x1c] = gen_helper_pf2iw
,
2986 [0x1d] = gen_helper_pf2id
,
2987 [0x8a] = gen_helper_pfnacc
,
2988 [0x8e] = gen_helper_pfpnacc
,
2989 [0x90] = gen_helper_pfcmpge
,
2990 [0x94] = gen_helper_pfmin
,
2991 [0x96] = gen_helper_pfrcp
,
2992 [0x97] = gen_helper_pfrsqrt
,
2993 [0x9a] = gen_helper_pfsub
,
2994 [0x9e] = gen_helper_pfadd
,
2995 [0xa0] = gen_helper_pfcmpgt
,
2996 [0xa4] = gen_helper_pfmax
,
2997 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2998 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2999 [0xaa] = gen_helper_pfsubr
,
3000 [0xae] = gen_helper_pfacc
,
3001 [0xb0] = gen_helper_pfcmpeq
,
3002 [0xb4] = gen_helper_pfmul
,
3003 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3004 [0xb7] = gen_helper_pmulhrw_mmx
,
3005 [0xbb] = gen_helper_pswapd
,
3006 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3009 struct sse_op_helper_s
{
3010 void *op
[2]; uint32_t ext_mask
;
3012 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3013 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3014 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3015 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3016 static struct sse_op_helper_s sse_op_table6
[256] = {
3017 [0x00] = SSSE3_OP(pshufb
),
3018 [0x01] = SSSE3_OP(phaddw
),
3019 [0x02] = SSSE3_OP(phaddd
),
3020 [0x03] = SSSE3_OP(phaddsw
),
3021 [0x04] = SSSE3_OP(pmaddubsw
),
3022 [0x05] = SSSE3_OP(phsubw
),
3023 [0x06] = SSSE3_OP(phsubd
),
3024 [0x07] = SSSE3_OP(phsubsw
),
3025 [0x08] = SSSE3_OP(psignb
),
3026 [0x09] = SSSE3_OP(psignw
),
3027 [0x0a] = SSSE3_OP(psignd
),
3028 [0x0b] = SSSE3_OP(pmulhrsw
),
3029 [0x10] = SSE41_OP(pblendvb
),
3030 [0x14] = SSE41_OP(blendvps
),
3031 [0x15] = SSE41_OP(blendvpd
),
3032 [0x17] = SSE41_OP(ptest
),
3033 [0x1c] = SSSE3_OP(pabsb
),
3034 [0x1d] = SSSE3_OP(pabsw
),
3035 [0x1e] = SSSE3_OP(pabsd
),
3036 [0x20] = SSE41_OP(pmovsxbw
),
3037 [0x21] = SSE41_OP(pmovsxbd
),
3038 [0x22] = SSE41_OP(pmovsxbq
),
3039 [0x23] = SSE41_OP(pmovsxwd
),
3040 [0x24] = SSE41_OP(pmovsxwq
),
3041 [0x25] = SSE41_OP(pmovsxdq
),
3042 [0x28] = SSE41_OP(pmuldq
),
3043 [0x29] = SSE41_OP(pcmpeqq
),
3044 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3045 [0x2b] = SSE41_OP(packusdw
),
3046 [0x30] = SSE41_OP(pmovzxbw
),
3047 [0x31] = SSE41_OP(pmovzxbd
),
3048 [0x32] = SSE41_OP(pmovzxbq
),
3049 [0x33] = SSE41_OP(pmovzxwd
),
3050 [0x34] = SSE41_OP(pmovzxwq
),
3051 [0x35] = SSE41_OP(pmovzxdq
),
3052 [0x37] = SSE42_OP(pcmpgtq
),
3053 [0x38] = SSE41_OP(pminsb
),
3054 [0x39] = SSE41_OP(pminsd
),
3055 [0x3a] = SSE41_OP(pminuw
),
3056 [0x3b] = SSE41_OP(pminud
),
3057 [0x3c] = SSE41_OP(pmaxsb
),
3058 [0x3d] = SSE41_OP(pmaxsd
),
3059 [0x3e] = SSE41_OP(pmaxuw
),
3060 [0x3f] = SSE41_OP(pmaxud
),
3061 [0x40] = SSE41_OP(pmulld
),
3062 [0x41] = SSE41_OP(phminposuw
),
3065 static struct sse_op_helper_s sse_op_table7
[256] = {
3066 [0x08] = SSE41_OP(roundps
),
3067 [0x09] = SSE41_OP(roundpd
),
3068 [0x0a] = SSE41_OP(roundss
),
3069 [0x0b] = SSE41_OP(roundsd
),
3070 [0x0c] = SSE41_OP(blendps
),
3071 [0x0d] = SSE41_OP(blendpd
),
3072 [0x0e] = SSE41_OP(pblendw
),
3073 [0x0f] = SSSE3_OP(palignr
),
3074 [0x14] = SSE41_SPECIAL
, /* pextrb */
3075 [0x15] = SSE41_SPECIAL
, /* pextrw */
3076 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3077 [0x17] = SSE41_SPECIAL
, /* extractps */
3078 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3079 [0x21] = SSE41_SPECIAL
, /* insertps */
3080 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3081 [0x40] = SSE41_OP(dpps
),
3082 [0x41] = SSE41_OP(dppd
),
3083 [0x42] = SSE41_OP(mpsadbw
),
3084 [0x60] = SSE42_OP(pcmpestrm
),
3085 [0x61] = SSE42_OP(pcmpestri
),
3086 [0x62] = SSE42_OP(pcmpistrm
),
3087 [0x63] = SSE42_OP(pcmpistri
),
3090 static void gen_sse(DisasContext
*s
, int b
, target_ulong pc_start
, int rex_r
)
3092 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3093 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3097 if (s
->prefix
& PREFIX_DATA
)
3099 else if (s
->prefix
& PREFIX_REPZ
)
3101 else if (s
->prefix
& PREFIX_REPNZ
)
3105 sse_op2
= sse_op_table1
[b
][b1
];
3108 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3118 /* simple MMX/SSE operation */
3119 if (s
->flags
& HF_TS_MASK
) {
3120 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3123 if (s
->flags
& HF_EM_MASK
) {
3125 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3128 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3129 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3132 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3143 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3144 the static cpu state) */
3146 gen_helper_enter_mmx();
3149 modrm
= ldub_code(s
->pc
++);
3150 reg
= ((modrm
>> 3) & 7);
3153 mod
= (modrm
>> 6) & 3;
3154 if (sse_op2
== SSE_SPECIAL
) {
3157 case 0x0e7: /* movntq */
3160 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3161 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3163 case 0x1e7: /* movntdq */
3164 case 0x02b: /* movntps */
3165 case 0x12b: /* movntps */
3166 case 0x3f0: /* lddqu */
3169 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3170 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3172 case 0x6e: /* movd mm, ea */
3173 #ifdef TARGET_X86_64
3174 if (s
->dflag
== 2) {
3175 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3176 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3180 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3181 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3182 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3183 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3184 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3187 case 0x16e: /* movd xmm, ea */
3188 #ifdef TARGET_X86_64
3189 if (s
->dflag
== 2) {
3190 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3191 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3192 offsetof(CPUX86State
,xmm_regs
[reg
]));
3193 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3197 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3198 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3199 offsetof(CPUX86State
,xmm_regs
[reg
]));
3200 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3201 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3204 case 0x6f: /* movq mm, ea */
3206 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3207 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3210 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3211 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3212 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3213 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3216 case 0x010: /* movups */
3217 case 0x110: /* movupd */
3218 case 0x028: /* movaps */
3219 case 0x128: /* movapd */
3220 case 0x16f: /* movdqa xmm, ea */
3221 case 0x26f: /* movdqu xmm, ea */
3223 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3224 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3226 rm
= (modrm
& 7) | REX_B(s
);
3227 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3228 offsetof(CPUX86State
,xmm_regs
[rm
]));
3231 case 0x210: /* movss xmm, ea */
3233 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3234 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3235 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3237 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3238 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3239 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3241 rm
= (modrm
& 7) | REX_B(s
);
3242 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3243 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3246 case 0x310: /* movsd xmm, ea */
3248 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3249 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3251 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3252 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3254 rm
= (modrm
& 7) | REX_B(s
);
3255 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3256 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3259 case 0x012: /* movlps */
3260 case 0x112: /* movlpd */
3262 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3263 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3266 rm
= (modrm
& 7) | REX_B(s
);
3267 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3268 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3271 case 0x212: /* movsldup */
3273 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3274 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3276 rm
= (modrm
& 7) | REX_B(s
);
3277 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3278 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3279 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3280 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3282 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3283 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3284 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3285 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3287 case 0x312: /* movddup */
3289 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3290 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3292 rm
= (modrm
& 7) | REX_B(s
);
3293 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3294 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3296 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3297 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3299 case 0x016: /* movhps */
3300 case 0x116: /* movhpd */
3302 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3303 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3306 rm
= (modrm
& 7) | REX_B(s
);
3307 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3308 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3311 case 0x216: /* movshdup */
3313 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3314 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3316 rm
= (modrm
& 7) | REX_B(s
);
3317 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3318 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3319 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3320 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3322 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3323 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3324 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3325 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3327 case 0x7e: /* movd ea, mm */
3328 #ifdef TARGET_X86_64
3329 if (s
->dflag
== 2) {
3330 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3331 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3332 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3336 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3337 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3338 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3341 case 0x17e: /* movd ea, xmm */
3342 #ifdef TARGET_X86_64
3343 if (s
->dflag
== 2) {
3344 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3345 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3346 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3350 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3351 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3352 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3355 case 0x27e: /* movq xmm, ea */
3357 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3358 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3360 rm
= (modrm
& 7) | REX_B(s
);
3361 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3362 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3364 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3366 case 0x7f: /* movq ea, mm */
3368 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3369 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3372 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3373 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3376 case 0x011: /* movups */
3377 case 0x111: /* movupd */
3378 case 0x029: /* movaps */
3379 case 0x129: /* movapd */
3380 case 0x17f: /* movdqa ea, xmm */
3381 case 0x27f: /* movdqu ea, xmm */
3383 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3384 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3386 rm
= (modrm
& 7) | REX_B(s
);
3387 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3388 offsetof(CPUX86State
,xmm_regs
[reg
]));
3391 case 0x211: /* movss ea, xmm */
3393 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3394 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3395 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3397 rm
= (modrm
& 7) | REX_B(s
);
3398 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3399 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3402 case 0x311: /* movsd ea, xmm */
3404 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3405 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3407 rm
= (modrm
& 7) | REX_B(s
);
3408 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3409 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3412 case 0x013: /* movlps */
3413 case 0x113: /* movlpd */
3415 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3416 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3421 case 0x017: /* movhps */
3422 case 0x117: /* movhpd */
3424 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3425 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3430 case 0x71: /* shift mm, im */
3433 case 0x171: /* shift xmm, im */
3436 val
= ldub_code(s
->pc
++);
3438 gen_op_movl_T0_im(val
);
3439 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3441 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3442 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3444 gen_op_movl_T0_im(val
);
3445 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3447 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3448 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3450 sse_op2
= sse_op_table2
[((b
- 1) & 3) * 8 + (((modrm
>> 3)) & 7)][b1
];
3454 rm
= (modrm
& 7) | REX_B(s
);
3455 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3458 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3460 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3461 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3462 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3464 case 0x050: /* movmskps */
3465 rm
= (modrm
& 7) | REX_B(s
);
3466 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3467 offsetof(CPUX86State
,xmm_regs
[rm
]));
3468 gen_helper_movmskps(cpu_tmp2_i32
, cpu_ptr0
);
3469 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3470 gen_op_mov_reg_T0(OT_LONG
, reg
);
3472 case 0x150: /* movmskpd */
3473 rm
= (modrm
& 7) | REX_B(s
);
3474 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3475 offsetof(CPUX86State
,xmm_regs
[rm
]));
3476 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_ptr0
);
3477 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3478 gen_op_mov_reg_T0(OT_LONG
, reg
);
3480 case 0x02a: /* cvtpi2ps */
3481 case 0x12a: /* cvtpi2pd */
3482 gen_helper_enter_mmx();
3484 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3485 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3486 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3489 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3491 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3492 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3493 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3496 gen_helper_cvtpi2ps(cpu_ptr0
, cpu_ptr1
);
3500 gen_helper_cvtpi2pd(cpu_ptr0
, cpu_ptr1
);
3504 case 0x22a: /* cvtsi2ss */
3505 case 0x32a: /* cvtsi2sd */
3506 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3507 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3508 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3509 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3510 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2)];
3511 if (ot
== OT_LONG
) {
3512 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3513 ((void (*)(TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_tmp2_i32
);
3515 ((void (*)(TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_T
[0]);
3518 case 0x02c: /* cvttps2pi */
3519 case 0x12c: /* cvttpd2pi */
3520 case 0x02d: /* cvtps2pi */
3521 case 0x12d: /* cvtpd2pi */
3522 gen_helper_enter_mmx();
3524 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3525 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3526 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3528 rm
= (modrm
& 7) | REX_B(s
);
3529 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3531 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3532 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3533 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3536 gen_helper_cvttps2pi(cpu_ptr0
, cpu_ptr1
);
3539 gen_helper_cvttpd2pi(cpu_ptr0
, cpu_ptr1
);
3542 gen_helper_cvtps2pi(cpu_ptr0
, cpu_ptr1
);
3545 gen_helper_cvtpd2pi(cpu_ptr0
, cpu_ptr1
);
3549 case 0x22c: /* cvttss2si */
3550 case 0x32c: /* cvttsd2si */
3551 case 0x22d: /* cvtss2si */
3552 case 0x32d: /* cvtsd2si */
3553 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3555 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3557 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3559 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3560 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3562 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3564 rm
= (modrm
& 7) | REX_B(s
);
3565 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3567 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2) + 4 +
3569 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3570 if (ot
== OT_LONG
) {
3571 ((void (*)(TCGv_i32
, TCGv_ptr
))sse_op2
)(cpu_tmp2_i32
, cpu_ptr0
);
3572 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3574 ((void (*)(TCGv
, TCGv_ptr
))sse_op2
)(cpu_T
[0], cpu_ptr0
);
3576 gen_op_mov_reg_T0(ot
, reg
);
3578 case 0xc4: /* pinsrw */
3581 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3582 val
= ldub_code(s
->pc
++);
3585 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3586 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3589 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3590 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3593 case 0xc5: /* pextrw */
3597 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3598 val
= ldub_code(s
->pc
++);
3601 rm
= (modrm
& 7) | REX_B(s
);
3602 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3603 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3607 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3608 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3610 reg
= ((modrm
>> 3) & 7) | rex_r
;
3611 gen_op_mov_reg_T0(ot
, reg
);
3613 case 0x1d6: /* movq ea, xmm */
3615 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3616 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3618 rm
= (modrm
& 7) | REX_B(s
);
3619 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3620 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3621 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3624 case 0x2d6: /* movq2dq */
3625 gen_helper_enter_mmx();
3627 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3628 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3629 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3631 case 0x3d6: /* movdq2q */
3632 gen_helper_enter_mmx();
3633 rm
= (modrm
& 7) | REX_B(s
);
3634 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3635 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3637 case 0xd7: /* pmovmskb */
3642 rm
= (modrm
& 7) | REX_B(s
);
3643 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3644 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_ptr0
);
3647 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3648 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_ptr0
);
3650 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3651 reg
= ((modrm
>> 3) & 7) | rex_r
;
3652 gen_op_mov_reg_T0(OT_LONG
, reg
);
3655 if (s
->prefix
& PREFIX_REPNZ
)
3659 modrm
= ldub_code(s
->pc
++);
3661 reg
= ((modrm
>> 3) & 7) | rex_r
;
3662 mod
= (modrm
>> 6) & 3;
3664 sse_op2
= sse_op_table6
[b
].op
[b1
];
3667 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3671 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3673 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3675 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3676 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3678 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3679 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3680 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3681 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3682 offsetof(XMMReg
, XMM_Q(0)));
3684 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3685 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3686 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3687 (s
->mem_index
>> 2) - 1);
3688 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3689 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3690 offsetof(XMMReg
, XMM_L(0)));
3692 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3693 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3694 (s
->mem_index
>> 2) - 1);
3695 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3696 offsetof(XMMReg
, XMM_W(0)));
3698 case 0x2a: /* movntqda */
3699 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3702 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3706 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3708 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3710 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3711 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3712 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3715 if (sse_op2
== SSE_SPECIAL
)
3718 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3719 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3720 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3723 s
->cc_op
= CC_OP_EFLAGS
;
3725 case 0x338: /* crc32 */
3728 modrm
= ldub_code(s
->pc
++);
3729 reg
= ((modrm
>> 3) & 7) | rex_r
;
3731 if (b
!= 0xf0 && b
!= 0xf1)
3733 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3738 else if (b
== 0xf1 && s
->dflag
!= 2)
3739 if (s
->prefix
& PREFIX_DATA
)
3746 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3748 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3749 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3750 cpu_T
[0], tcg_const_i32(8 << ot
));
3752 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3753 gen_op_mov_reg_T0(ot
, reg
);
3758 modrm
= ldub_code(s
->pc
++);
3760 reg
= ((modrm
>> 3) & 7) | rex_r
;
3761 mod
= (modrm
>> 6) & 3;
3763 sse_op2
= sse_op_table7
[b
].op
[b1
];
3766 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3769 if (sse_op2
== SSE_SPECIAL
) {
3770 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3771 rm
= (modrm
& 7) | REX_B(s
);
3773 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3774 reg
= ((modrm
>> 3) & 7) | rex_r
;
3775 val
= ldub_code(s
->pc
++);
3777 case 0x14: /* pextrb */
3778 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3779 xmm_regs
[reg
].XMM_B(val
& 15)));
3781 gen_op_mov_reg_T0(ot
, rm
);
3783 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3784 (s
->mem_index
>> 2) - 1);
3786 case 0x15: /* pextrw */
3787 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3788 xmm_regs
[reg
].XMM_W(val
& 7)));
3790 gen_op_mov_reg_T0(ot
, rm
);
3792 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
3793 (s
->mem_index
>> 2) - 1);
3796 if (ot
== OT_LONG
) { /* pextrd */
3797 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3798 offsetof(CPUX86State
,
3799 xmm_regs
[reg
].XMM_L(val
& 3)));
3800 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3802 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
3804 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3805 (s
->mem_index
>> 2) - 1);
3806 } else { /* pextrq */
3807 #ifdef TARGET_X86_64
3808 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3809 offsetof(CPUX86State
,
3810 xmm_regs
[reg
].XMM_Q(val
& 1)));
3812 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
3814 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
3815 (s
->mem_index
>> 2) - 1);
3821 case 0x17: /* extractps */
3822 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3823 xmm_regs
[reg
].XMM_L(val
& 3)));
3825 gen_op_mov_reg_T0(ot
, rm
);
3827 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3828 (s
->mem_index
>> 2) - 1);
3830 case 0x20: /* pinsrb */
3832 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
3834 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
3835 (s
->mem_index
>> 2) - 1);
3836 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
3837 xmm_regs
[reg
].XMM_B(val
& 15)));
3839 case 0x21: /* insertps */
3841 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3842 offsetof(CPUX86State
,xmm_regs
[rm
]
3843 .XMM_L((val
>> 6) & 3)));
3845 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3846 (s
->mem_index
>> 2) - 1);
3847 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3849 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3850 offsetof(CPUX86State
,xmm_regs
[reg
]
3851 .XMM_L((val
>> 4) & 3)));
3853 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3854 cpu_env
, offsetof(CPUX86State
,
3855 xmm_regs
[reg
].XMM_L(0)));
3857 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3858 cpu_env
, offsetof(CPUX86State
,
3859 xmm_regs
[reg
].XMM_L(1)));
3861 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3862 cpu_env
, offsetof(CPUX86State
,
3863 xmm_regs
[reg
].XMM_L(2)));
3865 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
3866 cpu_env
, offsetof(CPUX86State
,
3867 xmm_regs
[reg
].XMM_L(3)));
3870 if (ot
== OT_LONG
) { /* pinsrd */
3872 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
3874 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3875 (s
->mem_index
>> 2) - 1);
3876 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3877 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
3878 offsetof(CPUX86State
,
3879 xmm_regs
[reg
].XMM_L(val
& 3)));
3880 } else { /* pinsrq */
3881 #ifdef TARGET_X86_64
3883 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
3885 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
3886 (s
->mem_index
>> 2) - 1);
3887 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3888 offsetof(CPUX86State
,
3889 xmm_regs
[reg
].XMM_Q(val
& 1)));
3900 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3902 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3904 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3905 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3906 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3909 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3911 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3913 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3914 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3915 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3918 val
= ldub_code(s
->pc
++);
3920 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
3921 s
->cc_op
= CC_OP_EFLAGS
;
3924 /* The helper must use entire 64-bit gp registers */
3928 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3929 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3930 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
3936 /* generic MMX or SSE operation */
3938 case 0x70: /* pshufx insn */
3939 case 0xc6: /* pshufx insn */
3940 case 0xc2: /* compare insns */
3947 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3949 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3950 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3951 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
3953 /* specific case for SSE single instructions */
3956 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3957 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3960 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
3963 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3966 rm
= (modrm
& 7) | REX_B(s
);
3967 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3970 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3972 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3973 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3974 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3977 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3981 case 0x0f: /* 3DNow! data insns */
3982 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3984 val
= ldub_code(s
->pc
++);
3985 sse_op2
= sse_op_table5
[val
];
3988 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3989 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3990 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
3992 case 0x70: /* pshufx insn */
3993 case 0xc6: /* pshufx insn */
3994 val
= ldub_code(s
->pc
++);
3995 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3996 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3997 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv_i32
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4001 val
= ldub_code(s
->pc
++);
4004 sse_op2
= sse_op_table4
[val
][b1
];
4005 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4006 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4007 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4010 /* maskmov : we must prepare A0 */
4013 #ifdef TARGET_X86_64
4014 if (s
->aflag
== 2) {
4015 gen_op_movq_A0_reg(R_EDI
);
4019 gen_op_movl_A0_reg(R_EDI
);
4021 gen_op_andl_A0_ffff();
4023 gen_add_A0_ds_seg(s
);
4025 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4026 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4027 ((void (*)(TCGv_ptr
, TCGv_ptr
, TCGv
))sse_op2
)(cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4030 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4031 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4032 ((void (*)(TCGv_ptr
, TCGv_ptr
))sse_op2
)(cpu_ptr0
, cpu_ptr1
);
4035 if (b
== 0x2e || b
== 0x2f) {
4036 s
->cc_op
= CC_OP_EFLAGS
;
4041 /* convert one instruction. s->is_jmp is set if the translation must
4042 be stopped. Return the next pc value */
4043 static target_ulong
disas_insn(DisasContext
*s
, target_ulong pc_start
)
4045 int b
, prefixes
, aflag
, dflag
;
4047 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4048 target_ulong next_eip
, tval
;
4051 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
4052 tcg_gen_debug_insn_start(pc_start
);
4060 #ifdef TARGET_X86_64
4065 s
->rip_offset
= 0; /* for relative ip address */
4067 b
= ldub_code(s
->pc
);
4069 /* check prefixes */
4070 #ifdef TARGET_X86_64
4074 prefixes
|= PREFIX_REPZ
;
4077 prefixes
|= PREFIX_REPNZ
;
4080 prefixes
|= PREFIX_LOCK
;
4101 prefixes
|= PREFIX_DATA
;
4104 prefixes
|= PREFIX_ADR
;
4108 rex_w
= (b
>> 3) & 1;
4109 rex_r
= (b
& 0x4) << 1;
4110 s
->rex_x
= (b
& 0x2) << 2;
4111 REX_B(s
) = (b
& 0x1) << 3;
4112 x86_64_hregs
= 1; /* select uniform byte register addressing */
4116 /* 0x66 is ignored if rex.w is set */
4119 if (prefixes
& PREFIX_DATA
)
4122 if (!(prefixes
& PREFIX_ADR
))
4129 prefixes
|= PREFIX_REPZ
;
4132 prefixes
|= PREFIX_REPNZ
;
4135 prefixes
|= PREFIX_LOCK
;
4156 prefixes
|= PREFIX_DATA
;
4159 prefixes
|= PREFIX_ADR
;
4162 if (prefixes
& PREFIX_DATA
)
4164 if (prefixes
& PREFIX_ADR
)
4168 s
->prefix
= prefixes
;
4172 /* lock generation */
4173 if (prefixes
& PREFIX_LOCK
)
4176 /* now check op code */
4180 /**************************/
4181 /* extended op code */
4182 b
= ldub_code(s
->pc
++) | 0x100;
4185 /**************************/
4203 ot
= dflag
+ OT_WORD
;
4206 case 0: /* OP Ev, Gv */
4207 modrm
= ldub_code(s
->pc
++);
4208 reg
= ((modrm
>> 3) & 7) | rex_r
;
4209 mod
= (modrm
>> 6) & 3;
4210 rm
= (modrm
& 7) | REX_B(s
);
4212 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4214 } else if (op
== OP_XORL
&& rm
== reg
) {
4216 /* xor reg, reg optimisation */
4218 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4219 gen_op_mov_reg_T0(ot
, reg
);
4220 gen_op_update1_cc();
4225 gen_op_mov_TN_reg(ot
, 1, reg
);
4226 gen_op(s
, op
, ot
, opreg
);
4228 case 1: /* OP Gv, Ev */
4229 modrm
= ldub_code(s
->pc
++);
4230 mod
= (modrm
>> 6) & 3;
4231 reg
= ((modrm
>> 3) & 7) | rex_r
;
4232 rm
= (modrm
& 7) | REX_B(s
);
4234 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4235 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4236 } else if (op
== OP_XORL
&& rm
== reg
) {
4239 gen_op_mov_TN_reg(ot
, 1, rm
);
4241 gen_op(s
, op
, ot
, reg
);
4243 case 2: /* OP A, Iv */
4244 val
= insn_get(s
, ot
);
4245 gen_op_movl_T1_im(val
);
4246 gen_op(s
, op
, ot
, OR_EAX
);
4255 case 0x80: /* GRP1 */
4264 ot
= dflag
+ OT_WORD
;
4266 modrm
= ldub_code(s
->pc
++);
4267 mod
= (modrm
>> 6) & 3;
4268 rm
= (modrm
& 7) | REX_B(s
);
4269 op
= (modrm
>> 3) & 7;
4275 s
->rip_offset
= insn_const_size(ot
);
4276 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4287 val
= insn_get(s
, ot
);
4290 val
= (int8_t)insn_get(s
, OT_BYTE
);
4293 gen_op_movl_T1_im(val
);
4294 gen_op(s
, op
, ot
, opreg
);
4298 /**************************/
4299 /* inc, dec, and other misc arith */
4300 case 0x40 ... 0x47: /* inc Gv */
4301 ot
= dflag
? OT_LONG
: OT_WORD
;
4302 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4304 case 0x48 ... 0x4f: /* dec Gv */
4305 ot
= dflag
? OT_LONG
: OT_WORD
;
4306 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4308 case 0xf6: /* GRP3 */
4313 ot
= dflag
+ OT_WORD
;
4315 modrm
= ldub_code(s
->pc
++);
4316 mod
= (modrm
>> 6) & 3;
4317 rm
= (modrm
& 7) | REX_B(s
);
4318 op
= (modrm
>> 3) & 7;
4321 s
->rip_offset
= insn_const_size(ot
);
4322 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4323 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4325 gen_op_mov_TN_reg(ot
, 0, rm
);
4330 val
= insn_get(s
, ot
);
4331 gen_op_movl_T1_im(val
);
4332 gen_op_testl_T0_T1_cc();
4333 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4336 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4338 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4340 gen_op_mov_reg_T0(ot
, rm
);
4344 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4346 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4348 gen_op_mov_reg_T0(ot
, rm
);
4350 gen_op_update_neg_cc();
4351 s
->cc_op
= CC_OP_SUBB
+ ot
;
4356 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4357 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4358 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4359 /* XXX: use 32 bit mul which could be faster */
4360 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4361 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4362 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4363 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4364 s
->cc_op
= CC_OP_MULB
;
4367 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4368 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4369 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4370 /* XXX: use 32 bit mul which could be faster */
4371 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4372 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4373 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4374 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4375 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4376 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4377 s
->cc_op
= CC_OP_MULW
;
4381 #ifdef TARGET_X86_64
4382 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4383 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4384 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4385 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4386 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4387 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4388 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4389 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4390 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4394 t0
= tcg_temp_new_i64();
4395 t1
= tcg_temp_new_i64();
4396 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4397 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4398 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4399 tcg_gen_mul_i64(t0
, t0
, t1
);
4400 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4401 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4402 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4403 tcg_gen_shri_i64(t0
, t0
, 32);
4404 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4405 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4406 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4409 s
->cc_op
= CC_OP_MULL
;
4411 #ifdef TARGET_X86_64
4413 gen_helper_mulq_EAX_T0(cpu_T
[0]);
4414 s
->cc_op
= CC_OP_MULQ
;
4422 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4423 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4424 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4425 /* XXX: use 32 bit mul which could be faster */
4426 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4427 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4428 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4429 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4430 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4431 s
->cc_op
= CC_OP_MULB
;
4434 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4435 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4436 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4437 /* XXX: use 32 bit mul which could be faster */
4438 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4439 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4440 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4441 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4442 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4443 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4444 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4445 s
->cc_op
= CC_OP_MULW
;
4449 #ifdef TARGET_X86_64
4450 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4451 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4452 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4453 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4454 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4455 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4456 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4457 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4458 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4459 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4463 t0
= tcg_temp_new_i64();
4464 t1
= tcg_temp_new_i64();
4465 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4466 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4467 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4468 tcg_gen_mul_i64(t0
, t0
, t1
);
4469 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4470 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4471 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4472 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4473 tcg_gen_shri_i64(t0
, t0
, 32);
4474 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4475 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4476 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4479 s
->cc_op
= CC_OP_MULL
;
4481 #ifdef TARGET_X86_64
4483 gen_helper_imulq_EAX_T0(cpu_T
[0]);
4484 s
->cc_op
= CC_OP_MULQ
;
4492 gen_jmp_im(pc_start
- s
->cs_base
);
4493 gen_helper_divb_AL(cpu_T
[0]);
4496 gen_jmp_im(pc_start
- s
->cs_base
);
4497 gen_helper_divw_AX(cpu_T
[0]);
4501 gen_jmp_im(pc_start
- s
->cs_base
);
4502 gen_helper_divl_EAX(cpu_T
[0]);
4504 #ifdef TARGET_X86_64
4506 gen_jmp_im(pc_start
- s
->cs_base
);
4507 gen_helper_divq_EAX(cpu_T
[0]);
4515 gen_jmp_im(pc_start
- s
->cs_base
);
4516 gen_helper_idivb_AL(cpu_T
[0]);
4519 gen_jmp_im(pc_start
- s
->cs_base
);
4520 gen_helper_idivw_AX(cpu_T
[0]);
4524 gen_jmp_im(pc_start
- s
->cs_base
);
4525 gen_helper_idivl_EAX(cpu_T
[0]);
4527 #ifdef TARGET_X86_64
4529 gen_jmp_im(pc_start
- s
->cs_base
);
4530 gen_helper_idivq_EAX(cpu_T
[0]);
4540 case 0xfe: /* GRP4 */
4541 case 0xff: /* GRP5 */
4545 ot
= dflag
+ OT_WORD
;
4547 modrm
= ldub_code(s
->pc
++);
4548 mod
= (modrm
>> 6) & 3;
4549 rm
= (modrm
& 7) | REX_B(s
);
4550 op
= (modrm
>> 3) & 7;
4551 if (op
>= 2 && b
== 0xfe) {
4555 if (op
== 2 || op
== 4) {
4556 /* operand size for jumps is 64 bit */
4558 } else if (op
== 3 || op
== 5) {
4559 /* for call calls, the operand is 16 or 32 bit, even
4561 ot
= dflag
? OT_LONG
: OT_WORD
;
4562 } else if (op
== 6) {
4563 /* default push size is 64 bit */
4564 ot
= dflag
? OT_QUAD
: OT_WORD
;
4568 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4569 if (op
>= 2 && op
!= 3 && op
!= 5)
4570 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4572 gen_op_mov_TN_reg(ot
, 0, rm
);
4576 case 0: /* inc Ev */
4581 gen_inc(s
, ot
, opreg
, 1);
4583 case 1: /* dec Ev */
4588 gen_inc(s
, ot
, opreg
, -1);
4590 case 2: /* call Ev */
4591 /* XXX: optimize if memory (no 'and' is necessary) */
4593 gen_op_andl_T0_ffff();
4594 next_eip
= s
->pc
- s
->cs_base
;
4595 gen_movtl_T1_im(next_eip
);
4600 case 3: /* lcall Ev */
4601 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4602 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4603 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4605 if (s
->pe
&& !s
->vm86
) {
4606 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4607 gen_op_set_cc_op(s
->cc_op
);
4608 gen_jmp_im(pc_start
- s
->cs_base
);
4609 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4610 gen_helper_lcall_protected(cpu_tmp2_i32
, cpu_T
[1],
4611 tcg_const_i32(dflag
),
4612 tcg_const_i32(s
->pc
- pc_start
));
4614 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4615 gen_helper_lcall_real(cpu_tmp2_i32
, cpu_T
[1],
4616 tcg_const_i32(dflag
),
4617 tcg_const_i32(s
->pc
- s
->cs_base
));
4621 case 4: /* jmp Ev */
4623 gen_op_andl_T0_ffff();
4627 case 5: /* ljmp Ev */
4628 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4629 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4630 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4632 if (s
->pe
&& !s
->vm86
) {
4633 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4634 gen_op_set_cc_op(s
->cc_op
);
4635 gen_jmp_im(pc_start
- s
->cs_base
);
4636 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4637 gen_helper_ljmp_protected(cpu_tmp2_i32
, cpu_T
[1],
4638 tcg_const_i32(s
->pc
- pc_start
));
4640 gen_op_movl_seg_T0_vm(R_CS
);
4641 gen_op_movl_T0_T1();
4646 case 6: /* push Ev */
4654 case 0x84: /* test Ev, Gv */
4659 ot
= dflag
+ OT_WORD
;
4661 modrm
= ldub_code(s
->pc
++);
4662 mod
= (modrm
>> 6) & 3;
4663 rm
= (modrm
& 7) | REX_B(s
);
4664 reg
= ((modrm
>> 3) & 7) | rex_r
;
4666 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4667 gen_op_mov_TN_reg(ot
, 1, reg
);
4668 gen_op_testl_T0_T1_cc();
4669 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4672 case 0xa8: /* test eAX, Iv */
4677 ot
= dflag
+ OT_WORD
;
4678 val
= insn_get(s
, ot
);
4680 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4681 gen_op_movl_T1_im(val
);
4682 gen_op_testl_T0_T1_cc();
4683 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4686 case 0x98: /* CWDE/CBW */
4687 #ifdef TARGET_X86_64
4689 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4690 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4691 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4695 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4696 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4697 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4699 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4700 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4701 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4704 case 0x99: /* CDQ/CWD */
4705 #ifdef TARGET_X86_64
4707 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4708 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4709 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4713 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4714 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4715 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4716 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4718 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4719 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4720 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4721 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4724 case 0x1af: /* imul Gv, Ev */
4725 case 0x69: /* imul Gv, Ev, I */
4727 ot
= dflag
+ OT_WORD
;
4728 modrm
= ldub_code(s
->pc
++);
4729 reg
= ((modrm
>> 3) & 7) | rex_r
;
4731 s
->rip_offset
= insn_const_size(ot
);
4734 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4736 val
= insn_get(s
, ot
);
4737 gen_op_movl_T1_im(val
);
4738 } else if (b
== 0x6b) {
4739 val
= (int8_t)insn_get(s
, OT_BYTE
);
4740 gen_op_movl_T1_im(val
);
4742 gen_op_mov_TN_reg(ot
, 1, reg
);
4745 #ifdef TARGET_X86_64
4746 if (ot
== OT_QUAD
) {
4747 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4750 if (ot
== OT_LONG
) {
4751 #ifdef TARGET_X86_64
4752 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4753 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4754 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4755 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4756 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4757 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4761 t0
= tcg_temp_new_i64();
4762 t1
= tcg_temp_new_i64();
4763 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4764 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4765 tcg_gen_mul_i64(t0
, t0
, t1
);
4766 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4767 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4768 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4769 tcg_gen_shri_i64(t0
, t0
, 32);
4770 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4771 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4775 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4776 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4777 /* XXX: use 32 bit mul which could be faster */
4778 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4779 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4780 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4781 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4783 gen_op_mov_reg_T0(ot
, reg
);
4784 s
->cc_op
= CC_OP_MULB
+ ot
;
4787 case 0x1c1: /* xadd Ev, Gv */
4791 ot
= dflag
+ OT_WORD
;
4792 modrm
= ldub_code(s
->pc
++);
4793 reg
= ((modrm
>> 3) & 7) | rex_r
;
4794 mod
= (modrm
>> 6) & 3;
4796 rm
= (modrm
& 7) | REX_B(s
);
4797 gen_op_mov_TN_reg(ot
, 0, reg
);
4798 gen_op_mov_TN_reg(ot
, 1, rm
);
4799 gen_op_addl_T0_T1();
4800 gen_op_mov_reg_T1(ot
, reg
);
4801 gen_op_mov_reg_T0(ot
, rm
);
4803 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4804 gen_op_mov_TN_reg(ot
, 0, reg
);
4805 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4806 gen_op_addl_T0_T1();
4807 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4808 gen_op_mov_reg_T1(ot
, reg
);
4810 gen_op_update2_cc();
4811 s
->cc_op
= CC_OP_ADDB
+ ot
;
4814 case 0x1b1: /* cmpxchg Ev, Gv */
4817 TCGv t0
, t1
, t2
, a0
;
4822 ot
= dflag
+ OT_WORD
;
4823 modrm
= ldub_code(s
->pc
++);
4824 reg
= ((modrm
>> 3) & 7) | rex_r
;
4825 mod
= (modrm
>> 6) & 3;
4826 t0
= tcg_temp_local_new();
4827 t1
= tcg_temp_local_new();
4828 t2
= tcg_temp_local_new();
4829 a0
= tcg_temp_local_new();
4830 gen_op_mov_v_reg(ot
, t1
, reg
);
4832 rm
= (modrm
& 7) | REX_B(s
);
4833 gen_op_mov_v_reg(ot
, t0
, rm
);
4835 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4836 tcg_gen_mov_tl(a0
, cpu_A0
);
4837 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
4838 rm
= 0; /* avoid warning */
4840 label1
= gen_new_label();
4841 tcg_gen_sub_tl(t2
, cpu_regs
[R_EAX
], t0
);
4843 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
4845 label2
= gen_new_label();
4846 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4848 gen_set_label(label1
);
4849 gen_op_mov_reg_v(ot
, rm
, t1
);
4850 gen_set_label(label2
);
4852 tcg_gen_mov_tl(t1
, t0
);
4853 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4854 gen_set_label(label1
);
4856 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
4858 tcg_gen_mov_tl(cpu_cc_src
, t0
);
4859 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
4860 s
->cc_op
= CC_OP_SUBB
+ ot
;
4867 case 0x1c7: /* cmpxchg8b */
4868 modrm
= ldub_code(s
->pc
++);
4869 mod
= (modrm
>> 6) & 3;
4870 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
4872 #ifdef TARGET_X86_64
4874 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
4876 gen_jmp_im(pc_start
- s
->cs_base
);
4877 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4878 gen_op_set_cc_op(s
->cc_op
);
4879 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4880 gen_helper_cmpxchg16b(cpu_A0
);
4884 if (!(s
->cpuid_features
& CPUID_CX8
))
4886 gen_jmp_im(pc_start
- s
->cs_base
);
4887 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4888 gen_op_set_cc_op(s
->cc_op
);
4889 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4890 gen_helper_cmpxchg8b(cpu_A0
);
4892 s
->cc_op
= CC_OP_EFLAGS
;
4895 /**************************/
4897 case 0x50 ... 0x57: /* push */
4898 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
4901 case 0x58 ... 0x5f: /* pop */
4903 ot
= dflag
? OT_QUAD
: OT_WORD
;
4905 ot
= dflag
+ OT_WORD
;
4908 /* NOTE: order is important for pop %sp */
4910 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
4912 case 0x60: /* pusha */
4917 case 0x61: /* popa */
4922 case 0x68: /* push Iv */
4925 ot
= dflag
? OT_QUAD
: OT_WORD
;
4927 ot
= dflag
+ OT_WORD
;
4930 val
= insn_get(s
, ot
);
4932 val
= (int8_t)insn_get(s
, OT_BYTE
);
4933 gen_op_movl_T0_im(val
);
4936 case 0x8f: /* pop Ev */
4938 ot
= dflag
? OT_QUAD
: OT_WORD
;
4940 ot
= dflag
+ OT_WORD
;
4942 modrm
= ldub_code(s
->pc
++);
4943 mod
= (modrm
>> 6) & 3;
4946 /* NOTE: order is important for pop %sp */
4948 rm
= (modrm
& 7) | REX_B(s
);
4949 gen_op_mov_reg_T0(ot
, rm
);
4951 /* NOTE: order is important too for MMU exceptions */
4952 s
->popl_esp_hack
= 1 << ot
;
4953 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
4954 s
->popl_esp_hack
= 0;
4958 case 0xc8: /* enter */
4961 val
= lduw_code(s
->pc
);
4963 level
= ldub_code(s
->pc
++);
4964 gen_enter(s
, val
, level
);
4967 case 0xc9: /* leave */
4968 /* XXX: exception not precise (ESP is updated before potential exception) */
4970 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
4971 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
4972 } else if (s
->ss32
) {
4973 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
4974 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
4976 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
4977 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
4981 ot
= dflag
? OT_QUAD
: OT_WORD
;
4983 ot
= dflag
+ OT_WORD
;
4985 gen_op_mov_reg_T0(ot
, R_EBP
);
4988 case 0x06: /* push es */
4989 case 0x0e: /* push cs */
4990 case 0x16: /* push ss */
4991 case 0x1e: /* push ds */
4994 gen_op_movl_T0_seg(b
>> 3);
4997 case 0x1a0: /* push fs */
4998 case 0x1a8: /* push gs */
4999 gen_op_movl_T0_seg((b
>> 3) & 7);
5002 case 0x07: /* pop es */
5003 case 0x17: /* pop ss */
5004 case 0x1f: /* pop ds */
5009 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5012 /* if reg == SS, inhibit interrupts/trace. */
5013 /* If several instructions disable interrupts, only the
5015 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5016 gen_helper_set_inhibit_irq();
5020 gen_jmp_im(s
->pc
- s
->cs_base
);
5024 case 0x1a1: /* pop fs */
5025 case 0x1a9: /* pop gs */
5027 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5030 gen_jmp_im(s
->pc
- s
->cs_base
);
5035 /**************************/
5038 case 0x89: /* mov Gv, Ev */
5042 ot
= dflag
+ OT_WORD
;
5043 modrm
= ldub_code(s
->pc
++);
5044 reg
= ((modrm
>> 3) & 7) | rex_r
;
5046 /* generate a generic store */
5047 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
5050 case 0xc7: /* mov Ev, Iv */
5054 ot
= dflag
+ OT_WORD
;
5055 modrm
= ldub_code(s
->pc
++);
5056 mod
= (modrm
>> 6) & 3;
5058 s
->rip_offset
= insn_const_size(ot
);
5059 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5061 val
= insn_get(s
, ot
);
5062 gen_op_movl_T0_im(val
);
5064 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5066 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5069 case 0x8b: /* mov Ev, Gv */
5073 ot
= OT_WORD
+ dflag
;
5074 modrm
= ldub_code(s
->pc
++);
5075 reg
= ((modrm
>> 3) & 7) | rex_r
;
5077 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
5078 gen_op_mov_reg_T0(ot
, reg
);
5080 case 0x8e: /* mov seg, Gv */
5081 modrm
= ldub_code(s
->pc
++);
5082 reg
= (modrm
>> 3) & 7;
5083 if (reg
>= 6 || reg
== R_CS
)
5085 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5086 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5088 /* if reg == SS, inhibit interrupts/trace */
5089 /* If several instructions disable interrupts, only the
5091 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5092 gen_helper_set_inhibit_irq();
5096 gen_jmp_im(s
->pc
- s
->cs_base
);
5100 case 0x8c: /* mov Gv, seg */
5101 modrm
= ldub_code(s
->pc
++);
5102 reg
= (modrm
>> 3) & 7;
5103 mod
= (modrm
>> 6) & 3;
5106 gen_op_movl_T0_seg(reg
);
5108 ot
= OT_WORD
+ dflag
;
5111 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
5114 case 0x1b6: /* movzbS Gv, Eb */
5115 case 0x1b7: /* movzwS Gv, Eb */
5116 case 0x1be: /* movsbS Gv, Eb */
5117 case 0x1bf: /* movswS Gv, Eb */
5120 /* d_ot is the size of destination */
5121 d_ot
= dflag
+ OT_WORD
;
5122 /* ot is the size of source */
5123 ot
= (b
& 1) + OT_BYTE
;
5124 modrm
= ldub_code(s
->pc
++);
5125 reg
= ((modrm
>> 3) & 7) | rex_r
;
5126 mod
= (modrm
>> 6) & 3;
5127 rm
= (modrm
& 7) | REX_B(s
);
5130 gen_op_mov_TN_reg(ot
, 0, rm
);
5131 switch(ot
| (b
& 8)) {
5133 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5136 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5139 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5143 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5146 gen_op_mov_reg_T0(d_ot
, reg
);
5148 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5150 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5152 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5154 gen_op_mov_reg_T0(d_ot
, reg
);
5159 case 0x8d: /* lea */
5160 ot
= dflag
+ OT_WORD
;
5161 modrm
= ldub_code(s
->pc
++);
5162 mod
= (modrm
>> 6) & 3;
5165 reg
= ((modrm
>> 3) & 7) | rex_r
;
5166 /* we must ensure that no segment is added */
5170 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5172 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5175 case 0xa0: /* mov EAX, Ov */
5177 case 0xa2: /* mov Ov, EAX */
5180 target_ulong offset_addr
;
5185 ot
= dflag
+ OT_WORD
;
5186 #ifdef TARGET_X86_64
5187 if (s
->aflag
== 2) {
5188 offset_addr
= ldq_code(s
->pc
);
5190 gen_op_movq_A0_im(offset_addr
);
5195 offset_addr
= insn_get(s
, OT_LONG
);
5197 offset_addr
= insn_get(s
, OT_WORD
);
5199 gen_op_movl_A0_im(offset_addr
);
5201 gen_add_A0_ds_seg(s
);
5203 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5204 gen_op_mov_reg_T0(ot
, R_EAX
);
5206 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5207 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5211 case 0xd7: /* xlat */
5212 #ifdef TARGET_X86_64
5213 if (s
->aflag
== 2) {
5214 gen_op_movq_A0_reg(R_EBX
);
5215 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5216 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5217 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5221 gen_op_movl_A0_reg(R_EBX
);
5222 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5223 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5224 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5226 gen_op_andl_A0_ffff();
5228 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5230 gen_add_A0_ds_seg(s
);
5231 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5232 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5234 case 0xb0 ... 0xb7: /* mov R, Ib */
5235 val
= insn_get(s
, OT_BYTE
);
5236 gen_op_movl_T0_im(val
);
5237 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5239 case 0xb8 ... 0xbf: /* mov R, Iv */
5240 #ifdef TARGET_X86_64
5244 tmp
= ldq_code(s
->pc
);
5246 reg
= (b
& 7) | REX_B(s
);
5247 gen_movtl_T0_im(tmp
);
5248 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5252 ot
= dflag
? OT_LONG
: OT_WORD
;
5253 val
= insn_get(s
, ot
);
5254 reg
= (b
& 7) | REX_B(s
);
5255 gen_op_movl_T0_im(val
);
5256 gen_op_mov_reg_T0(ot
, reg
);
5260 case 0x91 ... 0x97: /* xchg R, EAX */
5261 ot
= dflag
+ OT_WORD
;
5262 reg
= (b
& 7) | REX_B(s
);
5266 case 0x87: /* xchg Ev, Gv */
5270 ot
= dflag
+ OT_WORD
;
5271 modrm
= ldub_code(s
->pc
++);
5272 reg
= ((modrm
>> 3) & 7) | rex_r
;
5273 mod
= (modrm
>> 6) & 3;
5275 rm
= (modrm
& 7) | REX_B(s
);
5277 gen_op_mov_TN_reg(ot
, 0, reg
);
5278 gen_op_mov_TN_reg(ot
, 1, rm
);
5279 gen_op_mov_reg_T0(ot
, rm
);
5280 gen_op_mov_reg_T1(ot
, reg
);
5282 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5283 gen_op_mov_TN_reg(ot
, 0, reg
);
5284 /* for xchg, lock is implicit */
5285 if (!(prefixes
& PREFIX_LOCK
))
5287 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5288 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5289 if (!(prefixes
& PREFIX_LOCK
))
5290 gen_helper_unlock();
5291 gen_op_mov_reg_T1(ot
, reg
);
5294 case 0xc4: /* les Gv */
5299 case 0xc5: /* lds Gv */
5304 case 0x1b2: /* lss Gv */
5307 case 0x1b4: /* lfs Gv */
5310 case 0x1b5: /* lgs Gv */
5313 ot
= dflag
? OT_LONG
: OT_WORD
;
5314 modrm
= ldub_code(s
->pc
++);
5315 reg
= ((modrm
>> 3) & 7) | rex_r
;
5316 mod
= (modrm
>> 6) & 3;
5319 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5320 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5321 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5322 /* load the segment first to handle exceptions properly */
5323 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5324 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5325 /* then put the data */
5326 gen_op_mov_reg_T1(ot
, reg
);
5328 gen_jmp_im(s
->pc
- s
->cs_base
);
5333 /************************/
5344 ot
= dflag
+ OT_WORD
;
5346 modrm
= ldub_code(s
->pc
++);
5347 mod
= (modrm
>> 6) & 3;
5348 op
= (modrm
>> 3) & 7;
5354 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5357 opreg
= (modrm
& 7) | REX_B(s
);
5362 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5365 shift
= ldub_code(s
->pc
++);
5367 gen_shifti(s
, op
, ot
, opreg
, shift
);
5382 case 0x1a4: /* shld imm */
5386 case 0x1a5: /* shld cl */
5390 case 0x1ac: /* shrd imm */
5394 case 0x1ad: /* shrd cl */
5398 ot
= dflag
+ OT_WORD
;
5399 modrm
= ldub_code(s
->pc
++);
5400 mod
= (modrm
>> 6) & 3;
5401 rm
= (modrm
& 7) | REX_B(s
);
5402 reg
= ((modrm
>> 3) & 7) | rex_r
;
5404 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5409 gen_op_mov_TN_reg(ot
, 1, reg
);
5412 val
= ldub_code(s
->pc
++);
5413 tcg_gen_movi_tl(cpu_T3
, val
);
5415 tcg_gen_mov_tl(cpu_T3
, cpu_regs
[R_ECX
]);
5417 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
5420 /************************/
5423 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5424 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5425 /* XXX: what to do if illegal op ? */
5426 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5429 modrm
= ldub_code(s
->pc
++);
5430 mod
= (modrm
>> 6) & 3;
5432 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5435 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5437 case 0x00 ... 0x07: /* fxxxs */
5438 case 0x10 ... 0x17: /* fixxxl */
5439 case 0x20 ... 0x27: /* fxxxl */
5440 case 0x30 ... 0x37: /* fixxx */
5447 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5448 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5449 gen_helper_flds_FT0(cpu_tmp2_i32
);
5452 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5453 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5454 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5457 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5458 (s
->mem_index
>> 2) - 1);
5459 gen_helper_fldl_FT0(cpu_tmp1_i64
);
5463 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5464 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5465 gen_helper_fildl_FT0(cpu_tmp2_i32
);
5469 gen_helper_fp_arith_ST0_FT0(op1
);
5471 /* fcomp needs pop */
5476 case 0x08: /* flds */
5477 case 0x0a: /* fsts */
5478 case 0x0b: /* fstps */
5479 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5480 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5481 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5486 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5487 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5488 gen_helper_flds_ST0(cpu_tmp2_i32
);
5491 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5492 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5493 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5496 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5497 (s
->mem_index
>> 2) - 1);
5498 gen_helper_fldl_ST0(cpu_tmp1_i64
);
5502 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5503 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5504 gen_helper_fildl_ST0(cpu_tmp2_i32
);
5509 /* XXX: the corresponding CPUID bit must be tested ! */
5512 gen_helper_fisttl_ST0(cpu_tmp2_i32
);
5513 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5514 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5517 gen_helper_fisttll_ST0(cpu_tmp1_i64
);
5518 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5519 (s
->mem_index
>> 2) - 1);
5523 gen_helper_fistt_ST0(cpu_tmp2_i32
);
5524 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5525 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5533 gen_helper_fsts_ST0(cpu_tmp2_i32
);
5534 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5535 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5538 gen_helper_fistl_ST0(cpu_tmp2_i32
);
5539 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5540 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5543 gen_helper_fstl_ST0(cpu_tmp1_i64
);
5544 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5545 (s
->mem_index
>> 2) - 1);
5549 gen_helper_fist_ST0(cpu_tmp2_i32
);
5550 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5551 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5559 case 0x0c: /* fldenv mem */
5560 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5561 gen_op_set_cc_op(s
->cc_op
);
5562 gen_jmp_im(pc_start
- s
->cs_base
);
5564 cpu_A0
, tcg_const_i32(s
->dflag
));
5566 case 0x0d: /* fldcw mem */
5567 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5568 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5569 gen_helper_fldcw(cpu_tmp2_i32
);
5571 case 0x0e: /* fnstenv mem */
5572 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5573 gen_op_set_cc_op(s
->cc_op
);
5574 gen_jmp_im(pc_start
- s
->cs_base
);
5575 gen_helper_fstenv(cpu_A0
, tcg_const_i32(s
->dflag
));
5577 case 0x0f: /* fnstcw mem */
5578 gen_helper_fnstcw(cpu_tmp2_i32
);
5579 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5580 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5582 case 0x1d: /* fldt mem */
5583 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5584 gen_op_set_cc_op(s
->cc_op
);
5585 gen_jmp_im(pc_start
- s
->cs_base
);
5586 gen_helper_fldt_ST0(cpu_A0
);
5588 case 0x1f: /* fstpt mem */
5589 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5590 gen_op_set_cc_op(s
->cc_op
);
5591 gen_jmp_im(pc_start
- s
->cs_base
);
5592 gen_helper_fstt_ST0(cpu_A0
);
5595 case 0x2c: /* frstor mem */
5596 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5597 gen_op_set_cc_op(s
->cc_op
);
5598 gen_jmp_im(pc_start
- s
->cs_base
);
5599 gen_helper_frstor(cpu_A0
, tcg_const_i32(s
->dflag
));
5601 case 0x2e: /* fnsave mem */
5602 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5603 gen_op_set_cc_op(s
->cc_op
);
5604 gen_jmp_im(pc_start
- s
->cs_base
);
5605 gen_helper_fsave(cpu_A0
, tcg_const_i32(s
->dflag
));
5607 case 0x2f: /* fnstsw mem */
5608 gen_helper_fnstsw(cpu_tmp2_i32
);
5609 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5610 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5612 case 0x3c: /* fbld */
5613 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5614 gen_op_set_cc_op(s
->cc_op
);
5615 gen_jmp_im(pc_start
- s
->cs_base
);
5616 gen_helper_fbld_ST0(cpu_A0
);
5618 case 0x3e: /* fbstp */
5619 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5620 gen_op_set_cc_op(s
->cc_op
);
5621 gen_jmp_im(pc_start
- s
->cs_base
);
5622 gen_helper_fbst_ST0(cpu_A0
);
5625 case 0x3d: /* fildll */
5626 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5627 (s
->mem_index
>> 2) - 1);
5628 gen_helper_fildll_ST0(cpu_tmp1_i64
);
5630 case 0x3f: /* fistpll */
5631 gen_helper_fistll_ST0(cpu_tmp1_i64
);
5632 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5633 (s
->mem_index
>> 2) - 1);
5640 /* register float ops */
5644 case 0x08: /* fld sti */
5646 gen_helper_fmov_ST0_STN(tcg_const_i32((opreg
+ 1) & 7));
5648 case 0x09: /* fxchg sti */
5649 case 0x29: /* fxchg4 sti, undocumented op */
5650 case 0x39: /* fxchg7 sti, undocumented op */
5651 gen_helper_fxchg_ST0_STN(tcg_const_i32(opreg
));
5653 case 0x0a: /* grp d9/2 */
5656 /* check exceptions (FreeBSD FPU probe) */
5657 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5658 gen_op_set_cc_op(s
->cc_op
);
5659 gen_jmp_im(pc_start
- s
->cs_base
);
5666 case 0x0c: /* grp d9/4 */
5669 gen_helper_fchs_ST0();
5672 gen_helper_fabs_ST0();
5675 gen_helper_fldz_FT0();
5676 gen_helper_fcom_ST0_FT0();
5679 gen_helper_fxam_ST0();
5685 case 0x0d: /* grp d9/5 */
5690 gen_helper_fld1_ST0();
5694 gen_helper_fldl2t_ST0();
5698 gen_helper_fldl2e_ST0();
5702 gen_helper_fldpi_ST0();
5706 gen_helper_fldlg2_ST0();
5710 gen_helper_fldln2_ST0();
5714 gen_helper_fldz_ST0();
5721 case 0x0e: /* grp d9/6 */
5732 case 3: /* fpatan */
5733 gen_helper_fpatan();
5735 case 4: /* fxtract */
5736 gen_helper_fxtract();
5738 case 5: /* fprem1 */
5739 gen_helper_fprem1();
5741 case 6: /* fdecstp */
5742 gen_helper_fdecstp();
5745 case 7: /* fincstp */
5746 gen_helper_fincstp();
5750 case 0x0f: /* grp d9/7 */
5755 case 1: /* fyl2xp1 */
5756 gen_helper_fyl2xp1();
5761 case 3: /* fsincos */
5762 gen_helper_fsincos();
5764 case 5: /* fscale */
5765 gen_helper_fscale();
5767 case 4: /* frndint */
5768 gen_helper_frndint();
5779 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5780 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5781 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5787 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5791 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5792 gen_helper_fp_arith_ST0_FT0(op1
);
5796 case 0x02: /* fcom */
5797 case 0x22: /* fcom2, undocumented op */
5798 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5799 gen_helper_fcom_ST0_FT0();
5801 case 0x03: /* fcomp */
5802 case 0x23: /* fcomp3, undocumented op */
5803 case 0x32: /* fcomp5, undocumented op */
5804 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5805 gen_helper_fcom_ST0_FT0();
5808 case 0x15: /* da/5 */
5810 case 1: /* fucompp */
5811 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5812 gen_helper_fucom_ST0_FT0();
5822 case 0: /* feni (287 only, just do nop here) */
5824 case 1: /* fdisi (287 only, just do nop here) */
5829 case 3: /* fninit */
5830 gen_helper_fninit();
5832 case 4: /* fsetpm (287 only, just do nop here) */
5838 case 0x1d: /* fucomi */
5839 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5840 gen_op_set_cc_op(s
->cc_op
);
5841 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5842 gen_helper_fucomi_ST0_FT0();
5843 s
->cc_op
= CC_OP_EFLAGS
;
5845 case 0x1e: /* fcomi */
5846 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5847 gen_op_set_cc_op(s
->cc_op
);
5848 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5849 gen_helper_fcomi_ST0_FT0();
5850 s
->cc_op
= CC_OP_EFLAGS
;
5852 case 0x28: /* ffree sti */
5853 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5855 case 0x2a: /* fst sti */
5856 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5858 case 0x2b: /* fstp sti */
5859 case 0x0b: /* fstp1 sti, undocumented op */
5860 case 0x3a: /* fstp8 sti, undocumented op */
5861 case 0x3b: /* fstp9 sti, undocumented op */
5862 gen_helper_fmov_STN_ST0(tcg_const_i32(opreg
));
5865 case 0x2c: /* fucom st(i) */
5866 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5867 gen_helper_fucom_ST0_FT0();
5869 case 0x2d: /* fucomp st(i) */
5870 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5871 gen_helper_fucom_ST0_FT0();
5874 case 0x33: /* de/3 */
5876 case 1: /* fcompp */
5877 gen_helper_fmov_FT0_STN(tcg_const_i32(1));
5878 gen_helper_fcom_ST0_FT0();
5886 case 0x38: /* ffreep sti, undocumented op */
5887 gen_helper_ffree_STN(tcg_const_i32(opreg
));
5890 case 0x3c: /* df/4 */
5893 gen_helper_fnstsw(cpu_tmp2_i32
);
5894 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5895 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
5901 case 0x3d: /* fucomip */
5902 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5903 gen_op_set_cc_op(s
->cc_op
);
5904 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5905 gen_helper_fucomi_ST0_FT0();
5907 s
->cc_op
= CC_OP_EFLAGS
;
5909 case 0x3e: /* fcomip */
5910 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5911 gen_op_set_cc_op(s
->cc_op
);
5912 gen_helper_fmov_FT0_STN(tcg_const_i32(opreg
));
5913 gen_helper_fcomi_ST0_FT0();
5915 s
->cc_op
= CC_OP_EFLAGS
;
5917 case 0x10 ... 0x13: /* fcmovxx */
5921 static const uint8_t fcmov_cc
[8] = {
5927 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
5928 l1
= gen_new_label();
5929 gen_jcc1(s
, s
->cc_op
, op1
, l1
);
5930 gen_helper_fmov_ST0_STN(tcg_const_i32(opreg
));
5939 /************************/
5942 case 0xa4: /* movsS */
5947 ot
= dflag
+ OT_WORD
;
5949 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5950 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5956 case 0xaa: /* stosS */
5961 ot
= dflag
+ OT_WORD
;
5963 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5964 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5969 case 0xac: /* lodsS */
5974 ot
= dflag
+ OT_WORD
;
5975 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5976 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5981 case 0xae: /* scasS */
5986 ot
= dflag
+ OT_WORD
;
5987 if (prefixes
& PREFIX_REPNZ
) {
5988 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
5989 } else if (prefixes
& PREFIX_REPZ
) {
5990 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
5993 s
->cc_op
= CC_OP_SUBB
+ ot
;
5997 case 0xa6: /* cmpsS */
6002 ot
= dflag
+ OT_WORD
;
6003 if (prefixes
& PREFIX_REPNZ
) {
6004 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6005 } else if (prefixes
& PREFIX_REPZ
) {
6006 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6009 s
->cc_op
= CC_OP_SUBB
+ ot
;
6012 case 0x6c: /* insS */
6017 ot
= dflag
? OT_LONG
: OT_WORD
;
6018 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6019 gen_op_andl_T0_ffff();
6020 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6021 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6022 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6023 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6027 gen_jmp(s
, s
->pc
- s
->cs_base
);
6031 case 0x6e: /* outsS */
6036 ot
= dflag
? OT_LONG
: OT_WORD
;
6037 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6038 gen_op_andl_T0_ffff();
6039 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6040 svm_is_rep(prefixes
) | 4);
6041 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6042 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6046 gen_jmp(s
, s
->pc
- s
->cs_base
);
6051 /************************/
6059 ot
= dflag
? OT_LONG
: OT_WORD
;
6060 val
= ldub_code(s
->pc
++);
6061 gen_op_movl_T0_im(val
);
6062 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6063 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6066 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6067 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6068 gen_op_mov_reg_T1(ot
, R_EAX
);
6071 gen_jmp(s
, s
->pc
- s
->cs_base
);
6079 ot
= dflag
? OT_LONG
: OT_WORD
;
6080 val
= ldub_code(s
->pc
++);
6081 gen_op_movl_T0_im(val
);
6082 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6083 svm_is_rep(prefixes
));
6084 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6088 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6089 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6090 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6091 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6094 gen_jmp(s
, s
->pc
- s
->cs_base
);
6102 ot
= dflag
? OT_LONG
: OT_WORD
;
6103 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6104 gen_op_andl_T0_ffff();
6105 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6106 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6109 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6110 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6111 gen_op_mov_reg_T1(ot
, R_EAX
);
6114 gen_jmp(s
, s
->pc
- s
->cs_base
);
6122 ot
= dflag
? OT_LONG
: OT_WORD
;
6123 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6124 gen_op_andl_T0_ffff();
6125 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6126 svm_is_rep(prefixes
));
6127 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6131 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6132 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
6133 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6134 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6137 gen_jmp(s
, s
->pc
- s
->cs_base
);
6141 /************************/
6143 case 0xc2: /* ret im */
6144 val
= ldsw_code(s
->pc
);
6147 if (CODE64(s
) && s
->dflag
)
6149 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6151 gen_op_andl_T0_ffff();
6155 case 0xc3: /* ret */
6159 gen_op_andl_T0_ffff();
6163 case 0xca: /* lret im */
6164 val
= ldsw_code(s
->pc
);
6167 if (s
->pe
&& !s
->vm86
) {
6168 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6169 gen_op_set_cc_op(s
->cc_op
);
6170 gen_jmp_im(pc_start
- s
->cs_base
);
6171 gen_helper_lret_protected(tcg_const_i32(s
->dflag
),
6172 tcg_const_i32(val
));
6176 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6178 gen_op_andl_T0_ffff();
6179 /* NOTE: keeping EIP updated is not a problem in case of
6183 gen_op_addl_A0_im(2 << s
->dflag
);
6184 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6185 gen_op_movl_seg_T0_vm(R_CS
);
6186 /* add stack offset */
6187 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6191 case 0xcb: /* lret */
6194 case 0xcf: /* iret */
6195 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6198 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6199 s
->cc_op
= CC_OP_EFLAGS
;
6200 } else if (s
->vm86
) {
6202 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6204 gen_helper_iret_real(tcg_const_i32(s
->dflag
));
6205 s
->cc_op
= CC_OP_EFLAGS
;
6208 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6209 gen_op_set_cc_op(s
->cc_op
);
6210 gen_jmp_im(pc_start
- s
->cs_base
);
6211 gen_helper_iret_protected(tcg_const_i32(s
->dflag
),
6212 tcg_const_i32(s
->pc
- s
->cs_base
));
6213 s
->cc_op
= CC_OP_EFLAGS
;
6217 case 0xe8: /* call im */
6220 tval
= (int32_t)insn_get(s
, OT_LONG
);
6222 tval
= (int16_t)insn_get(s
, OT_WORD
);
6223 next_eip
= s
->pc
- s
->cs_base
;
6227 gen_movtl_T0_im(next_eip
);
6232 case 0x9a: /* lcall im */
6234 unsigned int selector
, offset
;
6238 ot
= dflag
? OT_LONG
: OT_WORD
;
6239 offset
= insn_get(s
, ot
);
6240 selector
= insn_get(s
, OT_WORD
);
6242 gen_op_movl_T0_im(selector
);
6243 gen_op_movl_T1_imu(offset
);
6246 case 0xe9: /* jmp im */
6248 tval
= (int32_t)insn_get(s
, OT_LONG
);
6250 tval
= (int16_t)insn_get(s
, OT_WORD
);
6251 tval
+= s
->pc
- s
->cs_base
;
6258 case 0xea: /* ljmp im */
6260 unsigned int selector
, offset
;
6264 ot
= dflag
? OT_LONG
: OT_WORD
;
6265 offset
= insn_get(s
, ot
);
6266 selector
= insn_get(s
, OT_WORD
);
6268 gen_op_movl_T0_im(selector
);
6269 gen_op_movl_T1_imu(offset
);
6272 case 0xeb: /* jmp Jb */
6273 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6274 tval
+= s
->pc
- s
->cs_base
;
6279 case 0x70 ... 0x7f: /* jcc Jb */
6280 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6282 case 0x180 ... 0x18f: /* jcc Jv */
6284 tval
= (int32_t)insn_get(s
, OT_LONG
);
6286 tval
= (int16_t)insn_get(s
, OT_WORD
);
6289 next_eip
= s
->pc
- s
->cs_base
;
6293 gen_jcc(s
, b
, tval
, next_eip
);
6296 case 0x190 ... 0x19f: /* setcc Gv */
6297 modrm
= ldub_code(s
->pc
++);
6299 gen_ldst_modrm(s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6301 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6306 ot
= dflag
+ OT_WORD
;
6307 modrm
= ldub_code(s
->pc
++);
6308 reg
= ((modrm
>> 3) & 7) | rex_r
;
6309 mod
= (modrm
>> 6) & 3;
6310 t0
= tcg_temp_local_new();
6312 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6313 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6315 rm
= (modrm
& 7) | REX_B(s
);
6316 gen_op_mov_v_reg(ot
, t0
, rm
);
6318 #ifdef TARGET_X86_64
6319 if (ot
== OT_LONG
) {
6320 /* XXX: specific Intel behaviour ? */
6321 l1
= gen_new_label();
6322 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6323 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
6325 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_regs
[reg
]);
6329 l1
= gen_new_label();
6330 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
6331 gen_op_mov_reg_v(ot
, reg
, t0
);
6338 /************************/
6340 case 0x9c: /* pushf */
6341 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6342 if (s
->vm86
&& s
->iopl
!= 3) {
6343 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6345 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6346 gen_op_set_cc_op(s
->cc_op
);
6347 gen_helper_read_eflags(cpu_T
[0]);
6351 case 0x9d: /* popf */
6352 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6353 if (s
->vm86
&& s
->iopl
!= 3) {
6354 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6359 gen_helper_write_eflags(cpu_T
[0],
6360 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
)));
6362 gen_helper_write_eflags(cpu_T
[0],
6363 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
) & 0xffff));
6366 if (s
->cpl
<= s
->iopl
) {
6368 gen_helper_write_eflags(cpu_T
[0],
6369 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
)));
6371 gen_helper_write_eflags(cpu_T
[0],
6372 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
) & 0xffff));
6376 gen_helper_write_eflags(cpu_T
[0],
6377 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
)));
6379 gen_helper_write_eflags(cpu_T
[0],
6380 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
) & 0xffff));
6385 s
->cc_op
= CC_OP_EFLAGS
;
6386 /* abort translation because TF flag may change */
6387 gen_jmp_im(s
->pc
- s
->cs_base
);
6391 case 0x9e: /* sahf */
6392 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6394 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6395 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6396 gen_op_set_cc_op(s
->cc_op
);
6397 gen_compute_eflags(cpu_cc_src
);
6398 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6399 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6400 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6401 s
->cc_op
= CC_OP_EFLAGS
;
6403 case 0x9f: /* lahf */
6404 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6406 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6407 gen_op_set_cc_op(s
->cc_op
);
6408 gen_compute_eflags(cpu_T
[0]);
6409 /* Note: gen_compute_eflags() only gives the condition codes */
6410 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], 0x02);
6411 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6413 case 0xf5: /* cmc */
6414 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6415 gen_op_set_cc_op(s
->cc_op
);
6416 gen_compute_eflags(cpu_cc_src
);
6417 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6418 s
->cc_op
= CC_OP_EFLAGS
;
6420 case 0xf8: /* clc */
6421 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6422 gen_op_set_cc_op(s
->cc_op
);
6423 gen_compute_eflags(cpu_cc_src
);
6424 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6425 s
->cc_op
= CC_OP_EFLAGS
;
6427 case 0xf9: /* stc */
6428 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6429 gen_op_set_cc_op(s
->cc_op
);
6430 gen_compute_eflags(cpu_cc_src
);
6431 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6432 s
->cc_op
= CC_OP_EFLAGS
;
6434 case 0xfc: /* cld */
6435 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6436 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6438 case 0xfd: /* std */
6439 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6440 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6443 /************************/
6444 /* bit operations */
6445 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6446 ot
= dflag
+ OT_WORD
;
6447 modrm
= ldub_code(s
->pc
++);
6448 op
= (modrm
>> 3) & 7;
6449 mod
= (modrm
>> 6) & 3;
6450 rm
= (modrm
& 7) | REX_B(s
);
6453 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6454 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6456 gen_op_mov_TN_reg(ot
, 0, rm
);
6459 val
= ldub_code(s
->pc
++);
6460 gen_op_movl_T1_im(val
);
6465 case 0x1a3: /* bt Gv, Ev */
6468 case 0x1ab: /* bts */
6471 case 0x1b3: /* btr */
6474 case 0x1bb: /* btc */
6477 ot
= dflag
+ OT_WORD
;
6478 modrm
= ldub_code(s
->pc
++);
6479 reg
= ((modrm
>> 3) & 7) | rex_r
;
6480 mod
= (modrm
>> 6) & 3;
6481 rm
= (modrm
& 7) | REX_B(s
);
6482 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6484 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6485 /* specific case: we need to add a displacement */
6486 gen_exts(ot
, cpu_T
[1]);
6487 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6488 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6489 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6490 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6492 gen_op_mov_TN_reg(ot
, 0, rm
);
6495 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6498 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6499 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6502 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6503 tcg_gen_movi_tl(cpu_tmp0
, 1);
6504 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6505 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6508 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6509 tcg_gen_movi_tl(cpu_tmp0
, 1);
6510 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6511 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6512 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6516 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6517 tcg_gen_movi_tl(cpu_tmp0
, 1);
6518 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6519 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6522 s
->cc_op
= CC_OP_SARB
+ ot
;
6525 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6527 gen_op_mov_reg_T0(ot
, rm
);
6528 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6529 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6532 case 0x1bc: /* bsf */
6533 case 0x1bd: /* bsr */
6538 ot
= dflag
+ OT_WORD
;
6539 modrm
= ldub_code(s
->pc
++);
6540 reg
= ((modrm
>> 3) & 7) | rex_r
;
6541 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
6542 gen_extu(ot
, cpu_T
[0]);
6543 label1
= gen_new_label();
6544 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6545 t0
= tcg_temp_local_new();
6546 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6547 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6549 gen_helper_bsr(cpu_T
[0], t0
);
6551 gen_helper_bsf(cpu_T
[0], t0
);
6553 gen_op_mov_reg_T0(ot
, reg
);
6554 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6555 gen_set_label(label1
);
6556 tcg_gen_discard_tl(cpu_cc_src
);
6557 s
->cc_op
= CC_OP_LOGICB
+ ot
;
6561 /************************/
6563 case 0x27: /* daa */
6566 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6567 gen_op_set_cc_op(s
->cc_op
);
6569 s
->cc_op
= CC_OP_EFLAGS
;
6571 case 0x2f: /* das */
6574 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6575 gen_op_set_cc_op(s
->cc_op
);
6577 s
->cc_op
= CC_OP_EFLAGS
;
6579 case 0x37: /* aaa */
6582 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6583 gen_op_set_cc_op(s
->cc_op
);
6585 s
->cc_op
= CC_OP_EFLAGS
;
6587 case 0x3f: /* aas */
6590 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6591 gen_op_set_cc_op(s
->cc_op
);
6593 s
->cc_op
= CC_OP_EFLAGS
;
6595 case 0xd4: /* aam */
6598 val
= ldub_code(s
->pc
++);
6600 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6602 gen_helper_aam(tcg_const_i32(val
));
6603 s
->cc_op
= CC_OP_LOGICB
;
6606 case 0xd5: /* aad */
6609 val
= ldub_code(s
->pc
++);
6610 gen_helper_aad(tcg_const_i32(val
));
6611 s
->cc_op
= CC_OP_LOGICB
;
6613 /************************/
6615 case 0x90: /* nop */
6616 /* XXX: xchg + rex handling */
6617 /* XXX: correct lock test for all insn */
6618 if (prefixes
& PREFIX_LOCK
)
6620 if (prefixes
& PREFIX_REPZ
) {
6621 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6624 case 0x9b: /* fwait */
6625 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6626 (HF_MP_MASK
| HF_TS_MASK
)) {
6627 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6629 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6630 gen_op_set_cc_op(s
->cc_op
);
6631 gen_jmp_im(pc_start
- s
->cs_base
);
6635 case 0xcc: /* int3 */
6636 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6638 case 0xcd: /* int N */
6639 val
= ldub_code(s
->pc
++);
6640 if (s
->vm86
&& s
->iopl
!= 3) {
6641 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6643 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6646 case 0xce: /* into */
6649 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6650 gen_op_set_cc_op(s
->cc_op
);
6651 gen_jmp_im(pc_start
- s
->cs_base
);
6652 gen_helper_into(tcg_const_i32(s
->pc
- pc_start
));
6655 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6656 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6658 gen_debug(s
, pc_start
- s
->cs_base
);
6661 tb_flush(cpu_single_env
);
6662 cpu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6666 case 0xfa: /* cli */
6668 if (s
->cpl
<= s
->iopl
) {
6671 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6677 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6681 case 0xfb: /* sti */
6683 if (s
->cpl
<= s
->iopl
) {
6686 /* interruptions are enabled only the first insn after sti */
6687 /* If several instructions disable interrupts, only the
6689 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6690 gen_helper_set_inhibit_irq();
6691 /* give a chance to handle pending irqs */
6692 gen_jmp_im(s
->pc
- s
->cs_base
);
6695 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6701 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6705 case 0x62: /* bound */
6708 ot
= dflag
? OT_LONG
: OT_WORD
;
6709 modrm
= ldub_code(s
->pc
++);
6710 reg
= (modrm
>> 3) & 7;
6711 mod
= (modrm
>> 6) & 3;
6714 gen_op_mov_TN_reg(ot
, 0, reg
);
6715 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6716 gen_jmp_im(pc_start
- s
->cs_base
);
6717 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6719 gen_helper_boundw(cpu_A0
, cpu_tmp2_i32
);
6721 gen_helper_boundl(cpu_A0
, cpu_tmp2_i32
);
6723 case 0x1c8 ... 0x1cf: /* bswap reg */
6724 reg
= (b
& 7) | REX_B(s
);
6725 #ifdef TARGET_X86_64
6727 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6728 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6729 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6733 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6734 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6735 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6736 gen_op_mov_reg_T0(OT_LONG
, reg
);
6739 case 0xd6: /* salc */
6742 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6743 gen_op_set_cc_op(s
->cc_op
);
6744 gen_compute_eflags_c(cpu_T
[0]);
6745 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6746 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6748 case 0xe0: /* loopnz */
6749 case 0xe1: /* loopz */
6750 case 0xe2: /* loop */
6751 case 0xe3: /* jecxz */
6755 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6756 next_eip
= s
->pc
- s
->cs_base
;
6761 l1
= gen_new_label();
6762 l2
= gen_new_label();
6763 l3
= gen_new_label();
6766 case 0: /* loopnz */
6768 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6769 gen_op_set_cc_op(s
->cc_op
);
6770 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6771 gen_op_jz_ecx(s
->aflag
, l3
);
6772 gen_compute_eflags(cpu_tmp0
);
6773 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_Z
);
6775 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
6777 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, l1
);
6781 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6782 gen_op_jnz_ecx(s
->aflag
, l1
);
6786 gen_op_jz_ecx(s
->aflag
, l1
);
6791 gen_jmp_im(next_eip
);
6800 case 0x130: /* wrmsr */
6801 case 0x132: /* rdmsr */
6803 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6805 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6806 gen_op_set_cc_op(s
->cc_op
);
6807 gen_jmp_im(pc_start
- s
->cs_base
);
6815 case 0x131: /* rdtsc */
6816 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6817 gen_op_set_cc_op(s
->cc_op
);
6818 gen_jmp_im(pc_start
- s
->cs_base
);
6824 gen_jmp(s
, s
->pc
- s
->cs_base
);
6827 case 0x133: /* rdpmc */
6828 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6829 gen_op_set_cc_op(s
->cc_op
);
6830 gen_jmp_im(pc_start
- s
->cs_base
);
6833 case 0x134: /* sysenter */
6834 /* For Intel SYSENTER is valid on 64-bit */
6835 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6838 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6840 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6841 gen_op_set_cc_op(s
->cc_op
);
6842 s
->cc_op
= CC_OP_DYNAMIC
;
6844 gen_jmp_im(pc_start
- s
->cs_base
);
6845 gen_helper_sysenter();
6849 case 0x135: /* sysexit */
6850 /* For Intel SYSEXIT is valid on 64-bit */
6851 if (CODE64(s
) && cpu_single_env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6854 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6856 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6857 gen_op_set_cc_op(s
->cc_op
);
6858 s
->cc_op
= CC_OP_DYNAMIC
;
6860 gen_jmp_im(pc_start
- s
->cs_base
);
6861 gen_helper_sysexit(tcg_const_i32(dflag
));
6865 #ifdef TARGET_X86_64
6866 case 0x105: /* syscall */
6867 /* XXX: is it usable in real mode ? */
6868 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6869 gen_op_set_cc_op(s
->cc_op
);
6870 s
->cc_op
= CC_OP_DYNAMIC
;
6872 gen_jmp_im(pc_start
- s
->cs_base
);
6873 gen_helper_syscall(tcg_const_i32(s
->pc
- pc_start
));
6876 case 0x107: /* sysret */
6878 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6880 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6881 gen_op_set_cc_op(s
->cc_op
);
6882 s
->cc_op
= CC_OP_DYNAMIC
;
6884 gen_jmp_im(pc_start
- s
->cs_base
);
6885 gen_helper_sysret(tcg_const_i32(s
->dflag
));
6886 /* condition codes are modified only in long mode */
6888 s
->cc_op
= CC_OP_EFLAGS
;
6893 case 0x1a2: /* cpuid */
6894 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6895 gen_op_set_cc_op(s
->cc_op
);
6896 gen_jmp_im(pc_start
- s
->cs_base
);
6899 case 0xf4: /* hlt */
6901 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6903 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6904 gen_op_set_cc_op(s
->cc_op
);
6905 gen_jmp_im(pc_start
- s
->cs_base
);
6906 gen_helper_hlt(tcg_const_i32(s
->pc
- pc_start
));
6911 modrm
= ldub_code(s
->pc
++);
6912 mod
= (modrm
>> 6) & 3;
6913 op
= (modrm
>> 3) & 7;
6916 if (!s
->pe
|| s
->vm86
)
6918 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
6919 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
6923 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6926 if (!s
->pe
|| s
->vm86
)
6929 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6931 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
6932 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6933 gen_jmp_im(pc_start
- s
->cs_base
);
6934 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6935 gen_helper_lldt(cpu_tmp2_i32
);
6939 if (!s
->pe
|| s
->vm86
)
6941 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
6942 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
6946 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6949 if (!s
->pe
|| s
->vm86
)
6952 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6954 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
6955 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6956 gen_jmp_im(pc_start
- s
->cs_base
);
6957 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6958 gen_helper_ltr(cpu_tmp2_i32
);
6963 if (!s
->pe
|| s
->vm86
)
6965 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6966 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6967 gen_op_set_cc_op(s
->cc_op
);
6969 gen_helper_verr(cpu_T
[0]);
6971 gen_helper_verw(cpu_T
[0]);
6972 s
->cc_op
= CC_OP_EFLAGS
;
6979 modrm
= ldub_code(s
->pc
++);
6980 mod
= (modrm
>> 6) & 3;
6981 op
= (modrm
>> 3) & 7;
6987 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
6988 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6989 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
6990 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
6991 gen_add_A0_im(s
, 2);
6992 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
6994 gen_op_andl_T0_im(0xffffff);
6995 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7000 case 0: /* monitor */
7001 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7004 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7005 gen_op_set_cc_op(s
->cc_op
);
7006 gen_jmp_im(pc_start
- s
->cs_base
);
7007 #ifdef TARGET_X86_64
7008 if (s
->aflag
== 2) {
7009 gen_op_movq_A0_reg(R_EAX
);
7013 gen_op_movl_A0_reg(R_EAX
);
7015 gen_op_andl_A0_ffff();
7017 gen_add_A0_ds_seg(s
);
7018 gen_helper_monitor(cpu_A0
);
7021 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7024 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7025 gen_op_set_cc_op(s
->cc_op
);
7026 s
->cc_op
= CC_OP_DYNAMIC
;
7028 gen_jmp_im(pc_start
- s
->cs_base
);
7029 gen_helper_mwait(tcg_const_i32(s
->pc
- pc_start
));
7036 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7037 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7038 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7039 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7040 gen_add_A0_im(s
, 2);
7041 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7043 gen_op_andl_T0_im(0xffffff);
7044 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7050 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7051 gen_op_set_cc_op(s
->cc_op
);
7052 gen_jmp_im(pc_start
- s
->cs_base
);
7055 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7058 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7061 gen_helper_vmrun(tcg_const_i32(s
->aflag
),
7062 tcg_const_i32(s
->pc
- pc_start
));
7067 case 1: /* VMMCALL */
7068 if (!(s
->flags
& HF_SVME_MASK
))
7070 gen_helper_vmmcall();
7072 case 2: /* VMLOAD */
7073 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7076 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7079 gen_helper_vmload(tcg_const_i32(s
->aflag
));
7082 case 3: /* VMSAVE */
7083 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7086 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7089 gen_helper_vmsave(tcg_const_i32(s
->aflag
));
7093 if ((!(s
->flags
& HF_SVME_MASK
) &&
7094 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7098 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7105 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7108 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7114 case 6: /* SKINIT */
7115 if ((!(s
->flags
& HF_SVME_MASK
) &&
7116 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7119 gen_helper_skinit();
7121 case 7: /* INVLPGA */
7122 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7125 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7128 gen_helper_invlpga(tcg_const_i32(s
->aflag
));
7134 } else if (s
->cpl
!= 0) {
7135 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7137 gen_svm_check_intercept(s
, pc_start
,
7138 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7139 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7140 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7141 gen_add_A0_im(s
, 2);
7142 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7144 gen_op_andl_T0_im(0xffffff);
7146 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7147 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7149 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7150 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7155 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7156 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7157 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7159 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7161 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7165 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7167 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7168 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7169 gen_helper_lmsw(cpu_T
[0]);
7170 gen_jmp_im(s
->pc
- s
->cs_base
);
7174 case 7: /* invlpg */
7176 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7179 #ifdef TARGET_X86_64
7180 if (CODE64(s
) && rm
== 0) {
7182 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
7183 tcg_gen_ld_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
7184 tcg_gen_st_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
7185 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
7192 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7193 gen_op_set_cc_op(s
->cc_op
);
7194 gen_jmp_im(pc_start
- s
->cs_base
);
7195 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7196 gen_helper_invlpg(cpu_A0
);
7197 gen_jmp_im(s
->pc
- s
->cs_base
);
7206 case 0x108: /* invd */
7207 case 0x109: /* wbinvd */
7209 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7211 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7215 case 0x63: /* arpl or movslS (x86_64) */
7216 #ifdef TARGET_X86_64
7219 /* d_ot is the size of destination */
7220 d_ot
= dflag
+ OT_WORD
;
7222 modrm
= ldub_code(s
->pc
++);
7223 reg
= ((modrm
>> 3) & 7) | rex_r
;
7224 mod
= (modrm
>> 6) & 3;
7225 rm
= (modrm
& 7) | REX_B(s
);
7228 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7230 if (d_ot
== OT_QUAD
)
7231 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7232 gen_op_mov_reg_T0(d_ot
, reg
);
7234 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7235 if (d_ot
== OT_QUAD
) {
7236 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7238 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7240 gen_op_mov_reg_T0(d_ot
, reg
);
7248 if (!s
->pe
|| s
->vm86
)
7250 t0
= tcg_temp_local_new();
7251 t1
= tcg_temp_local_new();
7252 t2
= tcg_temp_local_new();
7254 modrm
= ldub_code(s
->pc
++);
7255 reg
= (modrm
>> 3) & 7;
7256 mod
= (modrm
>> 6) & 3;
7259 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7260 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7262 gen_op_mov_v_reg(ot
, t0
, rm
);
7264 gen_op_mov_v_reg(ot
, t1
, reg
);
7265 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7266 tcg_gen_andi_tl(t1
, t1
, 3);
7267 tcg_gen_movi_tl(t2
, 0);
7268 label1
= gen_new_label();
7269 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7270 tcg_gen_andi_tl(t0
, t0
, ~3);
7271 tcg_gen_or_tl(t0
, t0
, t1
);
7272 tcg_gen_movi_tl(t2
, CC_Z
);
7273 gen_set_label(label1
);
7275 gen_op_st_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7277 gen_op_mov_reg_v(ot
, rm
, t0
);
7279 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7280 gen_op_set_cc_op(s
->cc_op
);
7281 gen_compute_eflags(cpu_cc_src
);
7282 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7283 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7284 s
->cc_op
= CC_OP_EFLAGS
;
7290 case 0x102: /* lar */
7291 case 0x103: /* lsl */
7295 if (!s
->pe
|| s
->vm86
)
7297 ot
= dflag
? OT_LONG
: OT_WORD
;
7298 modrm
= ldub_code(s
->pc
++);
7299 reg
= ((modrm
>> 3) & 7) | rex_r
;
7300 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7301 t0
= tcg_temp_local_new();
7302 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7303 gen_op_set_cc_op(s
->cc_op
);
7305 gen_helper_lar(t0
, cpu_T
[0]);
7307 gen_helper_lsl(t0
, cpu_T
[0]);
7308 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7309 label1
= gen_new_label();
7310 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7311 gen_op_mov_reg_v(ot
, reg
, t0
);
7312 gen_set_label(label1
);
7313 s
->cc_op
= CC_OP_EFLAGS
;
7318 modrm
= ldub_code(s
->pc
++);
7319 mod
= (modrm
>> 6) & 3;
7320 op
= (modrm
>> 3) & 7;
7322 case 0: /* prefetchnta */
7323 case 1: /* prefetchnt0 */
7324 case 2: /* prefetchnt0 */
7325 case 3: /* prefetchnt0 */
7328 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7329 /* nothing more to do */
7331 default: /* nop (multi byte) */
7332 gen_nop_modrm(s
, modrm
);
7336 case 0x119 ... 0x11f: /* nop (multi byte) */
7337 modrm
= ldub_code(s
->pc
++);
7338 gen_nop_modrm(s
, modrm
);
7340 case 0x120: /* mov reg, crN */
7341 case 0x122: /* mov crN, reg */
7343 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7345 modrm
= ldub_code(s
->pc
++);
7346 if ((modrm
& 0xc0) != 0xc0)
7348 rm
= (modrm
& 7) | REX_B(s
);
7349 reg
= ((modrm
>> 3) & 7) | rex_r
;
7360 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7361 gen_op_set_cc_op(s
->cc_op
);
7362 gen_jmp_im(pc_start
- s
->cs_base
);
7364 gen_op_mov_TN_reg(ot
, 0, rm
);
7365 gen_helper_write_crN(tcg_const_i32(reg
), cpu_T
[0]);
7366 gen_jmp_im(s
->pc
- s
->cs_base
);
7369 gen_helper_read_crN(cpu_T
[0], tcg_const_i32(reg
));
7370 gen_op_mov_reg_T0(ot
, rm
);
7378 case 0x121: /* mov reg, drN */
7379 case 0x123: /* mov drN, reg */
7381 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7383 modrm
= ldub_code(s
->pc
++);
7384 if ((modrm
& 0xc0) != 0xc0)
7386 rm
= (modrm
& 7) | REX_B(s
);
7387 reg
= ((modrm
>> 3) & 7) | rex_r
;
7392 /* XXX: do it dynamically with CR4.DE bit */
7393 if (reg
== 4 || reg
== 5 || reg
>= 8)
7396 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7397 gen_op_mov_TN_reg(ot
, 0, rm
);
7398 gen_helper_movl_drN_T0(tcg_const_i32(reg
), cpu_T
[0]);
7399 gen_jmp_im(s
->pc
- s
->cs_base
);
7402 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7403 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7404 gen_op_mov_reg_T0(ot
, rm
);
7408 case 0x106: /* clts */
7410 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7412 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7414 /* abort block because static cpu state changed */
7415 gen_jmp_im(s
->pc
- s
->cs_base
);
7419 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7420 case 0x1c3: /* MOVNTI reg, mem */
7421 if (!(s
->cpuid_features
& CPUID_SSE2
))
7423 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7424 modrm
= ldub_code(s
->pc
++);
7425 mod
= (modrm
>> 6) & 3;
7428 reg
= ((modrm
>> 3) & 7) | rex_r
;
7429 /* generate a generic store */
7430 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
7433 modrm
= ldub_code(s
->pc
++);
7434 mod
= (modrm
>> 6) & 3;
7435 op
= (modrm
>> 3) & 7;
7437 case 0: /* fxsave */
7438 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7439 (s
->flags
& HF_EM_MASK
))
7441 if (s
->flags
& HF_TS_MASK
) {
7442 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7445 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7446 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7447 gen_op_set_cc_op(s
->cc_op
);
7448 gen_jmp_im(pc_start
- s
->cs_base
);
7449 gen_helper_fxsave(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7451 case 1: /* fxrstor */
7452 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7453 (s
->flags
& HF_EM_MASK
))
7455 if (s
->flags
& HF_TS_MASK
) {
7456 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7459 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7460 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7461 gen_op_set_cc_op(s
->cc_op
);
7462 gen_jmp_im(pc_start
- s
->cs_base
);
7463 gen_helper_fxrstor(cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7465 case 2: /* ldmxcsr */
7466 case 3: /* stmxcsr */
7467 if (s
->flags
& HF_TS_MASK
) {
7468 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7471 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7474 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7476 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7477 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7479 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7480 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7483 case 5: /* lfence */
7484 case 6: /* mfence */
7485 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE
))
7488 case 7: /* sfence / clflush */
7489 if ((modrm
& 0xc7) == 0xc0) {
7491 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7492 if (!(s
->cpuid_features
& CPUID_SSE
))
7496 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7498 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7505 case 0x10d: /* 3DNow! prefetch(w) */
7506 modrm
= ldub_code(s
->pc
++);
7507 mod
= (modrm
>> 6) & 3;
7510 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7511 /* ignore for now */
7513 case 0x1aa: /* rsm */
7514 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7515 if (!(s
->flags
& HF_SMM_MASK
))
7517 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7518 gen_op_set_cc_op(s
->cc_op
);
7519 s
->cc_op
= CC_OP_DYNAMIC
;
7521 gen_jmp_im(s
->pc
- s
->cs_base
);
7525 case 0x1b8: /* SSE4.2 popcnt */
7526 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7529 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7532 modrm
= ldub_code(s
->pc
++);
7533 reg
= ((modrm
>> 3) & 7);
7535 if (s
->prefix
& PREFIX_DATA
)
7537 else if (s
->dflag
!= 2)
7542 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
7543 gen_helper_popcnt(cpu_T
[0], cpu_T
[0], tcg_const_i32(ot
));
7544 gen_op_mov_reg_T0(ot
, reg
);
7546 s
->cc_op
= CC_OP_EFLAGS
;
7548 case 0x10e ... 0x10f:
7549 /* 3DNow! instructions, ignore prefixes */
7550 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7551 case 0x110 ... 0x117:
7552 case 0x128 ... 0x12f:
7553 case 0x138 ... 0x13a:
7554 case 0x150 ... 0x177:
7555 case 0x17c ... 0x17f:
7557 case 0x1c4 ... 0x1c6:
7558 case 0x1d0 ... 0x1fe:
7559 gen_sse(s
, b
, pc_start
, rex_r
);
7564 /* lock generation */
7565 if (s
->prefix
& PREFIX_LOCK
)
7566 gen_helper_unlock();
7569 if (s
->prefix
& PREFIX_LOCK
)
7570 gen_helper_unlock();
7571 /* XXX: ensure that no lock was generated */
7572 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7576 void optimize_flags_init(void)
7578 #if TCG_TARGET_REG_BITS == 32
7579 assert(sizeof(CCTable
) == (1 << 3));
7581 assert(sizeof(CCTable
) == (1 << 4));
7583 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7584 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7585 offsetof(CPUState
, cc_op
), "cc_op");
7586 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_src
),
7588 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_dst
),
7590 cpu_cc_tmp
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUState
, cc_tmp
),
7593 #ifdef TARGET_X86_64
7594 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7595 offsetof(CPUState
, regs
[R_EAX
]), "rax");
7596 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7597 offsetof(CPUState
, regs
[R_ECX
]), "rcx");
7598 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7599 offsetof(CPUState
, regs
[R_EDX
]), "rdx");
7600 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7601 offsetof(CPUState
, regs
[R_EBX
]), "rbx");
7602 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7603 offsetof(CPUState
, regs
[R_ESP
]), "rsp");
7604 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7605 offsetof(CPUState
, regs
[R_EBP
]), "rbp");
7606 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7607 offsetof(CPUState
, regs
[R_ESI
]), "rsi");
7608 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7609 offsetof(CPUState
, regs
[R_EDI
]), "rdi");
7610 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7611 offsetof(CPUState
, regs
[8]), "r8");
7612 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7613 offsetof(CPUState
, regs
[9]), "r9");
7614 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7615 offsetof(CPUState
, regs
[10]), "r10");
7616 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7617 offsetof(CPUState
, regs
[11]), "r11");
7618 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7619 offsetof(CPUState
, regs
[12]), "r12");
7620 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7621 offsetof(CPUState
, regs
[13]), "r13");
7622 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7623 offsetof(CPUState
, regs
[14]), "r14");
7624 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7625 offsetof(CPUState
, regs
[15]), "r15");
7627 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7628 offsetof(CPUState
, regs
[R_EAX
]), "eax");
7629 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7630 offsetof(CPUState
, regs
[R_ECX
]), "ecx");
7631 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7632 offsetof(CPUState
, regs
[R_EDX
]), "edx");
7633 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7634 offsetof(CPUState
, regs
[R_EBX
]), "ebx");
7635 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7636 offsetof(CPUState
, regs
[R_ESP
]), "esp");
7637 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7638 offsetof(CPUState
, regs
[R_EBP
]), "ebp");
7639 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7640 offsetof(CPUState
, regs
[R_ESI
]), "esi");
7641 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7642 offsetof(CPUState
, regs
[R_EDI
]), "edi");
7645 /* register helpers */
7646 #define GEN_HELPER 2
7650 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7651 basic block 'tb'. If search_pc is TRUE, also generate PC
7652 information for each intermediate instruction. */
7653 static inline void gen_intermediate_code_internal(CPUState
*env
,
7654 TranslationBlock
*tb
,
7657 DisasContext dc1
, *dc
= &dc1
;
7658 target_ulong pc_ptr
;
7659 uint16_t *gen_opc_end
;
7663 target_ulong pc_start
;
7664 target_ulong cs_base
;
7668 /* generate intermediate code */
7670 cs_base
= tb
->cs_base
;
7672 cflags
= tb
->cflags
;
7674 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7675 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7676 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7677 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7679 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7680 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7681 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7682 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7683 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7684 dc
->cc_op
= CC_OP_DYNAMIC
;
7685 dc
->cs_base
= cs_base
;
7687 dc
->popl_esp_hack
= 0;
7688 /* select memory access functions */
7690 if (flags
& HF_SOFTMMU_MASK
) {
7692 dc
->mem_index
= 2 * 4;
7694 dc
->mem_index
= 1 * 4;
7696 dc
->cpuid_features
= env
->cpuid_features
;
7697 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7698 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7699 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7700 #ifdef TARGET_X86_64
7701 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7702 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7705 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7706 (flags
& HF_INHIBIT_IRQ_MASK
)
7707 #ifndef CONFIG_SOFTMMU
7708 || (flags
& HF_SOFTMMU_MASK
)
7712 /* check addseg logic */
7713 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7714 printf("ERROR addseg\n");
7717 cpu_T
[0] = tcg_temp_new();
7718 cpu_T
[1] = tcg_temp_new();
7719 cpu_A0
= tcg_temp_new();
7720 cpu_T3
= tcg_temp_new();
7722 cpu_tmp0
= tcg_temp_new();
7723 cpu_tmp1_i64
= tcg_temp_new_i64();
7724 cpu_tmp2_i32
= tcg_temp_new_i32();
7725 cpu_tmp3_i32
= tcg_temp_new_i32();
7726 cpu_tmp4
= tcg_temp_new();
7727 cpu_tmp5
= tcg_temp_new();
7728 cpu_ptr0
= tcg_temp_new_ptr();
7729 cpu_ptr1
= tcg_temp_new_ptr();
7731 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
7733 dc
->is_jmp
= DISAS_NEXT
;
7737 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7739 max_insns
= CF_COUNT_MASK
;
7743 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7744 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7745 if (bp
->pc
== pc_ptr
&&
7746 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7747 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7753 j
= gen_opc_ptr
- gen_opc_buf
;
7757 gen_opc_instr_start
[lj
++] = 0;
7759 gen_opc_pc
[lj
] = pc_ptr
;
7760 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7761 gen_opc_instr_start
[lj
] = 1;
7762 gen_opc_icount
[lj
] = num_insns
;
7764 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7767 pc_ptr
= disas_insn(dc
, pc_ptr
);
7769 /* stop translation if indicated */
7772 /* if single step mode, we generate only one instruction and
7773 generate an exception */
7774 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7775 the flag and abort the translation to give the irqs a
7776 change to be happen */
7777 if (dc
->tf
|| dc
->singlestep_enabled
||
7778 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7779 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7783 /* if too long translation, stop generation too */
7784 if (gen_opc_ptr
>= gen_opc_end
||
7785 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7786 num_insns
>= max_insns
) {
7787 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7792 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7797 if (tb
->cflags
& CF_LAST_IO
)
7799 gen_icount_end(tb
, num_insns
);
7800 *gen_opc_ptr
= INDEX_op_end
;
7801 /* we don't forget to fill the last values */
7803 j
= gen_opc_ptr
- gen_opc_buf
;
7806 gen_opc_instr_start
[lj
++] = 0;
7810 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, X86_DUMP_CCOP
);
7811 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
7813 qemu_log("----------------\n");
7814 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7815 #ifdef TARGET_X86_64
7820 disas_flags
= !dc
->code32
;
7821 log_target_disas(pc_start
, pc_ptr
- pc_start
, disas_flags
);
7827 tb
->size
= pc_ptr
- pc_start
;
7828 tb
->icount
= num_insns
;
7832 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
7834 gen_intermediate_code_internal(env
, tb
, 0);
7837 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
7839 gen_intermediate_code_internal(env
, tb
, 1);
7842 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7843 unsigned long searched_pc
, int pc_pos
, void *puc
)
7847 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
7849 qemu_log("RESTORE:\n");
7850 for(i
= 0;i
<= pc_pos
; i
++) {
7851 if (gen_opc_instr_start
[i
]) {
7852 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
, gen_opc_pc
[i
]);
7855 qemu_log("spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
7856 searched_pc
, pc_pos
, gen_opc_pc
[pc_pos
] - tb
->cs_base
,
7857 (uint32_t)tb
->cs_base
);
7860 env
->eip
= gen_opc_pc
[pc_pos
] - tb
->cs_base
;
7861 cc_op
= gen_opc_cc_op
[pc_pos
];
7862 if (cc_op
!= CC_OP_DYNAMIC
)