4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
41 #define X86_64_ONLY(x) x
42 #define X86_64_DEF(x...) x
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
46 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */
48 #define BUGGY_64(x) NULL
51 #define X86_64_ONLY(x) NULL
52 #define X86_64_DEF(x...)
58 //#define MACRO_TEST 1
60 /* global register indexes */
61 static TCGv cpu_env
, cpu_A0
, cpu_cc_op
, cpu_cc_src
, cpu_cc_dst
, cpu_cc_tmp
;
63 static TCGv cpu_T
[2], cpu_T3
;
64 /* local register indexes (only used inside old micro ops) */
65 static TCGv cpu_tmp0
, cpu_tmp1_i64
, cpu_tmp2_i32
, cpu_tmp3_i32
, cpu_tmp4
, cpu_ptr0
, cpu_ptr1
;
66 static TCGv cpu_tmp5
, cpu_tmp6
;
68 #include "gen-icount.h"
71 static int x86_64_hregs
;
74 typedef struct DisasContext
{
75 /* current insn context */
76 int override
; /* -1 if no override */
79 target_ulong pc
; /* pc = eip + cs_base */
80 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base
; /* base of CS segment */
84 int pe
; /* protected mode */
85 int code32
; /* 32 bit code segment */
87 int lma
; /* long mode active */
88 int code64
; /* 64 bit code segment */
91 int ss32
; /* 32 bit stack segment */
92 int cc_op
; /* current CC operation */
93 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st
; /* currently unused */
95 int vm86
; /* vm86 mode */
98 int tf
; /* TF cpu flag */
99 int singlestep_enabled
; /* "hardware" single step enabled */
100 int jmp_opt
; /* use direct block chaining for direct jumps */
101 int mem_index
; /* select memory access functions */
102 uint64_t flags
; /* all execution flags */
103 struct TranslationBlock
*tb
;
104 int popl_esp_hack
; /* for correct popl with esp base handling */
105 int rip_offset
; /* only used in x86_64, but left for simplicity */
107 int cpuid_ext_features
;
108 int cpuid_ext2_features
;
109 int cpuid_ext3_features
;
112 static void gen_eob(DisasContext
*s
);
113 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
114 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
116 /* i386 arith/logic operations */
136 OP_SHL1
, /* undocumented */
160 /* I386 int registers */
161 OR_EAX
, /* MUST be even numbered */
170 OR_TMP0
= 16, /* temporary operand register */
172 OR_A0
, /* temporary register used when doing address evaluation */
175 static inline void gen_op_movl_T0_0(void)
177 tcg_gen_movi_tl(cpu_T
[0], 0);
180 static inline void gen_op_movl_T0_im(int32_t val
)
182 tcg_gen_movi_tl(cpu_T
[0], val
);
185 static inline void gen_op_movl_T0_imu(uint32_t val
)
187 tcg_gen_movi_tl(cpu_T
[0], val
);
190 static inline void gen_op_movl_T1_im(int32_t val
)
192 tcg_gen_movi_tl(cpu_T
[1], val
);
195 static inline void gen_op_movl_T1_imu(uint32_t val
)
197 tcg_gen_movi_tl(cpu_T
[1], val
);
200 static inline void gen_op_movl_A0_im(uint32_t val
)
202 tcg_gen_movi_tl(cpu_A0
, val
);
206 static inline void gen_op_movq_A0_im(int64_t val
)
208 tcg_gen_movi_tl(cpu_A0
, val
);
212 static inline void gen_movtl_T0_im(target_ulong val
)
214 tcg_gen_movi_tl(cpu_T
[0], val
);
217 static inline void gen_movtl_T1_im(target_ulong val
)
219 tcg_gen_movi_tl(cpu_T
[1], val
);
222 static inline void gen_op_andl_T0_ffff(void)
224 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
227 static inline void gen_op_andl_T0_im(uint32_t val
)
229 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
232 static inline void gen_op_movl_T0_T1(void)
234 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
237 static inline void gen_op_andl_A0_ffff(void)
239 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
244 #define NB_OP_SIZES 4
246 #else /* !TARGET_X86_64 */
248 #define NB_OP_SIZES 3
250 #endif /* !TARGET_X86_64 */
252 #if defined(WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
266 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
270 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
271 tcg_gen_st8_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_B_OFFSET
);
273 tcg_gen_st8_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
- 4]) + REG_H_OFFSET
);
277 tcg_gen_st16_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
281 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
282 /* high part of register set to zero */
283 tcg_gen_movi_tl(cpu_tmp0
, 0);
284 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
288 tcg_gen_st_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
293 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
299 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
301 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
304 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
306 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
309 static inline void gen_op_mov_reg_A0(int size
, int reg
)
313 tcg_gen_st16_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
317 tcg_gen_st32_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
318 /* high part of register set to zero */
319 tcg_gen_movi_tl(cpu_tmp0
, 0);
320 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
324 tcg_gen_st_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
329 tcg_gen_st32_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
335 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
339 if (reg
< 4 X86_64_DEF( || reg
>= 8 || x86_64_hregs
)) {
342 tcg_gen_ld8u_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
- 4]) + REG_H_OFFSET
);
347 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
352 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
354 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
357 static inline void gen_op_movl_A0_reg(int reg
)
359 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
362 static inline void gen_op_addl_A0_im(int32_t val
)
364 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
366 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
371 static inline void gen_op_addq_A0_im(int64_t val
)
373 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
377 static void gen_add_A0_im(DisasContext
*s
, int val
)
381 gen_op_addq_A0_im(val
);
384 gen_op_addl_A0_im(val
);
387 static inline void gen_op_addl_T0_T1(void)
389 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
392 static inline void gen_op_jmp_T0(void)
394 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, eip
));
397 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
401 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
402 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
403 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
406 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
407 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
409 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffff);
411 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
415 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
416 tcg_gen_addi_tl(cpu_tmp0
, cpu_tmp0
, val
);
417 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
423 static inline void gen_op_add_reg_T0(int size
, int reg
)
427 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
428 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
429 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_W_OFFSET
);
432 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
433 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
435 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, 0xffffffff);
437 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
441 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
442 tcg_gen_add_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[0]);
443 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
449 static inline void gen_op_set_cc_op(int32_t val
)
451 tcg_gen_movi_i32(cpu_cc_op
, val
);
454 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
456 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
458 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
459 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
461 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
465 static inline void gen_op_movl_A0_seg(int reg
)
467 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
) + REG_L_OFFSET
);
470 static inline void gen_op_addl_A0_seg(int reg
)
472 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
473 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
475 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
480 static inline void gen_op_movq_A0_seg(int reg
)
482 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
485 static inline void gen_op_addq_A0_seg(int reg
)
487 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, segs
[reg
].base
));
488 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
491 static inline void gen_op_movq_A0_reg(int reg
)
493 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
496 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
498 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]));
500 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
501 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
505 static inline void gen_op_lds_T0_A0(int idx
)
507 int mem_index
= (idx
>> 2) - 1;
510 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
513 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
517 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
522 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
524 int mem_index
= (idx
>> 2) - 1;
527 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
530 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
533 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
537 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
542 /* XXX: always use ldu or lds */
543 static inline void gen_op_ld_T0_A0(int idx
)
545 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
548 static inline void gen_op_ldu_T0_A0(int idx
)
550 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
553 static inline void gen_op_ld_T1_A0(int idx
)
555 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
558 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
560 int mem_index
= (idx
>> 2) - 1;
563 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
566 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
569 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
573 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
578 static inline void gen_op_st_T0_A0(int idx
)
580 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
583 static inline void gen_op_st_T1_A0(int idx
)
585 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
588 static inline void gen_jmp_im(target_ulong pc
)
590 tcg_gen_movi_tl(cpu_tmp0
, pc
);
591 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, eip
));
594 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
598 override
= s
->override
;
602 gen_op_movq_A0_seg(override
);
603 gen_op_addq_A0_reg_sN(0, R_ESI
);
605 gen_op_movq_A0_reg(R_ESI
);
611 if (s
->addseg
&& override
< 0)
614 gen_op_movl_A0_seg(override
);
615 gen_op_addl_A0_reg_sN(0, R_ESI
);
617 gen_op_movl_A0_reg(R_ESI
);
620 /* 16 address, always override */
623 gen_op_movl_A0_reg(R_ESI
);
624 gen_op_andl_A0_ffff();
625 gen_op_addl_A0_seg(override
);
629 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
633 gen_op_movq_A0_reg(R_EDI
);
638 gen_op_movl_A0_seg(R_ES
);
639 gen_op_addl_A0_reg_sN(0, R_EDI
);
641 gen_op_movl_A0_reg(R_EDI
);
644 gen_op_movl_A0_reg(R_EDI
);
645 gen_op_andl_A0_ffff();
646 gen_op_addl_A0_seg(R_ES
);
650 static inline void gen_op_movl_T0_Dshift(int ot
)
652 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUState
, df
));
653 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
656 static void gen_extu(int ot
, TCGv reg
)
660 tcg_gen_ext8u_tl(reg
, reg
);
663 tcg_gen_ext16u_tl(reg
, reg
);
666 tcg_gen_ext32u_tl(reg
, reg
);
673 static void gen_exts(int ot
, TCGv reg
)
677 tcg_gen_ext8s_tl(reg
, reg
);
680 tcg_gen_ext16s_tl(reg
, reg
);
683 tcg_gen_ext32s_tl(reg
, reg
);
690 static inline void gen_op_jnz_ecx(int size
, int label1
)
692 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
693 gen_extu(size
+ 1, cpu_tmp0
);
694 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
697 static inline void gen_op_jz_ecx(int size
, int label1
)
699 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
700 gen_extu(size
+ 1, cpu_tmp0
);
701 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
704 static void *helper_in_func
[3] = {
710 static void *helper_out_func
[3] = {
716 static void *gen_check_io_func
[3] = {
722 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
726 target_ulong next_eip
;
729 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
730 if (s
->cc_op
!= CC_OP_DYNAMIC
)
731 gen_op_set_cc_op(s
->cc_op
);
734 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
735 tcg_gen_helper_0_1(gen_check_io_func
[ot
],
738 if(s
->flags
& HF_SVMI_MASK
) {
740 if (s
->cc_op
!= CC_OP_DYNAMIC
)
741 gen_op_set_cc_op(s
->cc_op
);
745 svm_flags
|= (1 << (4 + ot
));
746 next_eip
= s
->pc
- s
->cs_base
;
747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
748 tcg_gen_helper_0_3(helper_svm_check_io
,
750 tcg_const_i32(svm_flags
),
751 tcg_const_i32(next_eip
- cur_eip
));
755 static inline void gen_movs(DisasContext
*s
, int ot
)
757 gen_string_movl_A0_ESI(s
);
758 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
759 gen_string_movl_A0_EDI(s
);
760 gen_op_st_T0_A0(ot
+ s
->mem_index
);
761 gen_op_movl_T0_Dshift(ot
);
762 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
763 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
766 static inline void gen_update_cc_op(DisasContext
*s
)
768 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
769 gen_op_set_cc_op(s
->cc_op
);
770 s
->cc_op
= CC_OP_DYNAMIC
;
774 static void gen_op_update1_cc(void)
776 tcg_gen_discard_tl(cpu_cc_src
);
777 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
780 static void gen_op_update2_cc(void)
782 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
783 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
786 static inline void gen_op_cmpl_T0_T1_cc(void)
788 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
789 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
792 static inline void gen_op_testl_T0_T1_cc(void)
794 tcg_gen_discard_tl(cpu_cc_src
);
795 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
798 static void gen_op_update_neg_cc(void)
800 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
801 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
804 /* compute eflags.C to reg */
805 static void gen_compute_eflags_c(TCGv reg
)
807 #if TCG_TARGET_REG_BITS == 32
808 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_cc_op
, 3);
809 tcg_gen_addi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
,
810 (long)cc_table
+ offsetof(CCTable
, compute_c
));
811 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0);
812 tcg_gen_call(&tcg_ctx
, cpu_tmp2_i32
, TCG_CALL_PURE
,
813 1, &cpu_tmp2_i32
, 0, NULL
);
815 tcg_gen_extu_i32_tl(cpu_tmp1_i64
, cpu_cc_op
);
816 tcg_gen_shli_i64(cpu_tmp1_i64
, cpu_tmp1_i64
, 4);
817 tcg_gen_addi_i64(cpu_tmp1_i64
, cpu_tmp1_i64
,
818 (long)cc_table
+ offsetof(CCTable
, compute_c
));
819 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_tmp1_i64
, 0);
820 tcg_gen_call(&tcg_ctx
, cpu_tmp1_i64
, TCG_CALL_PURE
,
821 1, &cpu_tmp2_i32
, 0, NULL
);
823 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
826 /* compute all eflags to cc_src */
827 static void gen_compute_eflags(TCGv reg
)
829 #if TCG_TARGET_REG_BITS == 32
830 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_cc_op
, 3);
831 tcg_gen_addi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
,
832 (long)cc_table
+ offsetof(CCTable
, compute_all
));
833 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0);
834 tcg_gen_call(&tcg_ctx
, cpu_tmp2_i32
, TCG_CALL_PURE
,
835 1, &cpu_tmp2_i32
, 0, NULL
);
837 tcg_gen_extu_i32_tl(cpu_tmp1_i64
, cpu_cc_op
);
838 tcg_gen_shli_i64(cpu_tmp1_i64
, cpu_tmp1_i64
, 4);
839 tcg_gen_addi_i64(cpu_tmp1_i64
, cpu_tmp1_i64
,
840 (long)cc_table
+ offsetof(CCTable
, compute_all
));
841 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_tmp1_i64
, 0);
842 tcg_gen_call(&tcg_ctx
, cpu_tmp1_i64
, TCG_CALL_PURE
,
843 1, &cpu_tmp2_i32
, 0, NULL
);
845 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
848 static inline void gen_setcc_slow_T0(DisasContext
*s
, int jcc_op
)
850 if (s
->cc_op
!= CC_OP_DYNAMIC
)
851 gen_op_set_cc_op(s
->cc_op
);
854 gen_compute_eflags(cpu_T
[0]);
855 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 11);
856 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
859 gen_compute_eflags_c(cpu_T
[0]);
862 gen_compute_eflags(cpu_T
[0]);
863 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 6);
864 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
867 gen_compute_eflags(cpu_tmp0
);
868 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 6);
869 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
870 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
873 gen_compute_eflags(cpu_T
[0]);
874 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 7);
875 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
878 gen_compute_eflags(cpu_T
[0]);
879 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 2);
880 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
883 gen_compute_eflags(cpu_tmp0
);
884 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
885 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 7); /* CC_S */
886 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
887 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
891 gen_compute_eflags(cpu_tmp0
);
892 tcg_gen_shri_tl(cpu_T
[0], cpu_tmp0
, 11); /* CC_O */
893 tcg_gen_shri_tl(cpu_tmp4
, cpu_tmp0
, 7); /* CC_S */
894 tcg_gen_shri_tl(cpu_tmp0
, cpu_tmp0
, 6); /* CC_Z */
895 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
896 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
897 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 1);
902 /* return true if setcc_slow is not needed (WARNING: must be kept in
903 sync with gen_jcc1) */
904 static int is_fast_jcc_case(DisasContext
*s
, int b
)
907 jcc_op
= (b
>> 1) & 7;
909 /* we optimize the cmp/jcc case */
914 if (jcc_op
== JCC_O
|| jcc_op
== JCC_P
)
918 /* some jumps are easy to compute */
943 if (jcc_op
!= JCC_Z
&& jcc_op
!= JCC_S
)
953 /* generate a conditional jump to label 'l1' according to jump opcode
954 value 'b'. In the fast case, T0 is guaranted not to be used. */
955 static inline void gen_jcc1(DisasContext
*s
, int cc_op
, int b
, int l1
)
957 int inv
, jcc_op
, size
, cond
;
961 jcc_op
= (b
>> 1) & 7;
964 /* we optimize the cmp/jcc case */
970 size
= cc_op
- CC_OP_SUBB
;
976 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xff);
980 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffff);
985 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0xffffffff);
993 tcg_gen_brcondi_tl(inv
? TCG_COND_NE
: TCG_COND_EQ
, t0
, 0, l1
);
999 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80);
1000 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1004 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x8000);
1005 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1008 #ifdef TARGET_X86_64
1010 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_dst
, 0x80000000);
1011 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
, cpu_tmp0
,
1016 tcg_gen_brcondi_tl(inv
? TCG_COND_GE
: TCG_COND_LT
, cpu_cc_dst
,
1023 cond
= inv
? TCG_COND_GEU
: TCG_COND_LTU
;
1026 cond
= inv
? TCG_COND_GTU
: TCG_COND_LEU
;
1028 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1032 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xff);
1033 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xff);
1037 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffff);
1038 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffff);
1040 #ifdef TARGET_X86_64
1043 tcg_gen_andi_tl(cpu_tmp4
, cpu_tmp4
, 0xffffffff);
1044 tcg_gen_andi_tl(t0
, cpu_cc_src
, 0xffffffff);
1051 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1055 cond
= inv
? TCG_COND_GE
: TCG_COND_LT
;
1058 cond
= inv
? TCG_COND_GT
: TCG_COND_LE
;
1060 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1064 tcg_gen_ext8s_tl(cpu_tmp4
, cpu_tmp4
);
1065 tcg_gen_ext8s_tl(t0
, cpu_cc_src
);
1069 tcg_gen_ext16s_tl(cpu_tmp4
, cpu_tmp4
);
1070 tcg_gen_ext16s_tl(t0
, cpu_cc_src
);
1072 #ifdef TARGET_X86_64
1075 tcg_gen_ext32s_tl(cpu_tmp4
, cpu_tmp4
);
1076 tcg_gen_ext32s_tl(t0
, cpu_cc_src
);
1083 tcg_gen_brcond_tl(cond
, cpu_tmp4
, t0
, l1
);
1091 /* some jumps are easy to compute */
1133 size
= (cc_op
- CC_OP_ADDB
) & 3;
1136 size
= (cc_op
- CC_OP_ADDB
) & 3;
1144 gen_setcc_slow_T0(s
, jcc_op
);
1145 tcg_gen_brcondi_tl(inv
? TCG_COND_EQ
: TCG_COND_NE
,
1151 /* XXX: does not work with gdbstub "ice" single step - not a
1153 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1157 l1
= gen_new_label();
1158 l2
= gen_new_label();
1159 gen_op_jnz_ecx(s
->aflag
, l1
);
1161 gen_jmp_tb(s
, next_eip
, 1);
1166 static inline void gen_stos(DisasContext
*s
, int ot
)
1168 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1169 gen_string_movl_A0_EDI(s
);
1170 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1171 gen_op_movl_T0_Dshift(ot
);
1172 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1175 static inline void gen_lods(DisasContext
*s
, int ot
)
1177 gen_string_movl_A0_ESI(s
);
1178 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1179 gen_op_mov_reg_T0(ot
, R_EAX
);
1180 gen_op_movl_T0_Dshift(ot
);
1181 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1184 static inline void gen_scas(DisasContext
*s
, int ot
)
1186 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1187 gen_string_movl_A0_EDI(s
);
1188 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1189 gen_op_cmpl_T0_T1_cc();
1190 gen_op_movl_T0_Dshift(ot
);
1191 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1194 static inline void gen_cmps(DisasContext
*s
, int ot
)
1196 gen_string_movl_A0_ESI(s
);
1197 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1198 gen_string_movl_A0_EDI(s
);
1199 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1200 gen_op_cmpl_T0_T1_cc();
1201 gen_op_movl_T0_Dshift(ot
);
1202 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1203 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1206 static inline void gen_ins(DisasContext
*s
, int ot
)
1210 gen_string_movl_A0_EDI(s
);
1211 /* Note: we must do this dummy write first to be restartable in
1212 case of page fault. */
1214 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1215 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1216 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1217 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1218 tcg_gen_helper_1_1(helper_in_func
[ot
], cpu_T
[0], cpu_tmp2_i32
);
1219 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1220 gen_op_movl_T0_Dshift(ot
);
1221 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1226 static inline void gen_outs(DisasContext
*s
, int ot
)
1230 gen_string_movl_A0_ESI(s
);
1231 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1233 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1234 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1235 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1236 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1237 tcg_gen_helper_0_2(helper_out_func
[ot
], cpu_tmp2_i32
, cpu_tmp3_i32
);
1239 gen_op_movl_T0_Dshift(ot
);
1240 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1245 /* same method as Valgrind : we generate jumps to current or next
1247 #define GEN_REPZ(op) \
1248 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1249 target_ulong cur_eip, target_ulong next_eip) \
1252 gen_update_cc_op(s); \
1253 l2 = gen_jz_ecx_string(s, next_eip); \
1254 gen_ ## op(s, ot); \
1255 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1256 /* a loop would cause two single step exceptions if ECX = 1 \
1257 before rep string_insn */ \
1259 gen_op_jz_ecx(s->aflag, l2); \
1260 gen_jmp(s, cur_eip); \
1263 #define GEN_REPZ2(op) \
1264 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1265 target_ulong cur_eip, \
1266 target_ulong next_eip, \
1270 gen_update_cc_op(s); \
1271 l2 = gen_jz_ecx_string(s, next_eip); \
1272 gen_ ## op(s, ot); \
1273 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1274 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1275 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1277 gen_op_jz_ecx(s->aflag, l2); \
1278 gen_jmp(s, cur_eip); \
1289 static void *helper_fp_arith_ST0_FT0
[8] = {
1290 helper_fadd_ST0_FT0
,
1291 helper_fmul_ST0_FT0
,
1292 helper_fcom_ST0_FT0
,
1293 helper_fcom_ST0_FT0
,
1294 helper_fsub_ST0_FT0
,
1295 helper_fsubr_ST0_FT0
,
1296 helper_fdiv_ST0_FT0
,
1297 helper_fdivr_ST0_FT0
,
1300 /* NOTE the exception in "r" op ordering */
1301 static void *helper_fp_arith_STN_ST0
[8] = {
1302 helper_fadd_STN_ST0
,
1303 helper_fmul_STN_ST0
,
1306 helper_fsubr_STN_ST0
,
1307 helper_fsub_STN_ST0
,
1308 helper_fdivr_STN_ST0
,
1309 helper_fdiv_STN_ST0
,
1312 /* if d == OR_TMP0, it means memory operand (address in A0) */
1313 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1316 gen_op_mov_TN_reg(ot
, 0, d
);
1318 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1322 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1323 gen_op_set_cc_op(s1
->cc_op
);
1324 gen_compute_eflags_c(cpu_tmp4
);
1325 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1326 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1328 gen_op_mov_reg_T0(ot
, d
);
1330 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1331 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1332 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1333 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1334 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1335 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1336 s1
->cc_op
= CC_OP_DYNAMIC
;
1339 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1340 gen_op_set_cc_op(s1
->cc_op
);
1341 gen_compute_eflags_c(cpu_tmp4
);
1342 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1343 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1345 gen_op_mov_reg_T0(ot
, d
);
1347 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1348 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1349 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1350 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1351 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1352 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1353 s1
->cc_op
= CC_OP_DYNAMIC
;
1356 gen_op_addl_T0_T1();
1358 gen_op_mov_reg_T0(ot
, d
);
1360 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1361 gen_op_update2_cc();
1362 s1
->cc_op
= CC_OP_ADDB
+ ot
;
1365 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1367 gen_op_mov_reg_T0(ot
, d
);
1369 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1370 gen_op_update2_cc();
1371 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1375 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1377 gen_op_mov_reg_T0(ot
, d
);
1379 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1380 gen_op_update1_cc();
1381 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1384 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1386 gen_op_mov_reg_T0(ot
, d
);
1388 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1389 gen_op_update1_cc();
1390 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1393 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1395 gen_op_mov_reg_T0(ot
, d
);
1397 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1398 gen_op_update1_cc();
1399 s1
->cc_op
= CC_OP_LOGICB
+ ot
;
1402 gen_op_cmpl_T0_T1_cc();
1403 s1
->cc_op
= CC_OP_SUBB
+ ot
;
1408 /* if d == OR_TMP0, it means memory operand (address in A0) */
1409 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1412 gen_op_mov_TN_reg(ot
, 0, d
);
1414 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1415 if (s1
->cc_op
!= CC_OP_DYNAMIC
)
1416 gen_op_set_cc_op(s1
->cc_op
);
1418 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1419 s1
->cc_op
= CC_OP_INCB
+ ot
;
1421 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1422 s1
->cc_op
= CC_OP_DECB
+ ot
;
1425 gen_op_mov_reg_T0(ot
, d
);
1427 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1428 gen_compute_eflags_c(cpu_cc_src
);
1429 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1432 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1433 int is_right
, int is_arith
)
1446 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1448 gen_op_mov_TN_reg(ot
, 0, op1
);
1450 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1452 tcg_gen_addi_tl(cpu_tmp5
, cpu_T
[1], -1);
1456 gen_exts(ot
, cpu_T
[0]);
1457 tcg_gen_sar_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1458 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1460 gen_extu(ot
, cpu_T
[0]);
1461 tcg_gen_shr_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1462 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1465 tcg_gen_shl_tl(cpu_T3
, cpu_T
[0], cpu_tmp5
);
1466 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1471 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1473 gen_op_mov_reg_T0(ot
, op1
);
1475 /* update eflags if non zero shift */
1476 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1477 gen_op_set_cc_op(s
->cc_op
);
1479 /* XXX: inefficient */
1480 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1481 t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1483 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1484 tcg_gen_mov_tl(t1
, cpu_T3
);
1486 shift_label
= gen_new_label();
1487 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_T
[1], 0, shift_label
);
1489 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1490 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1492 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1494 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1496 gen_set_label(shift_label
);
1497 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1503 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1504 int is_right
, int is_arith
)
1515 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1517 gen_op_mov_TN_reg(ot
, 0, op1
);
1523 gen_exts(ot
, cpu_T
[0]);
1524 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1525 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1527 gen_extu(ot
, cpu_T
[0]);
1528 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1529 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1532 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1533 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1539 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1541 gen_op_mov_reg_T0(ot
, op1
);
1543 /* update eflags if non zero shift */
1545 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1546 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1548 s
->cc_op
= CC_OP_SARB
+ ot
;
1550 s
->cc_op
= CC_OP_SHLB
+ ot
;
1554 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1557 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1559 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1562 /* XXX: add faster immediate case */
1563 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1567 int label1
, label2
, data_bits
;
1568 TCGv t0
, t1
, t2
, a0
;
1570 /* XXX: inefficient, but we must use local temps */
1571 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1572 t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1573 t2
= tcg_temp_local_new(TCG_TYPE_TL
);
1574 a0
= tcg_temp_local_new(TCG_TYPE_TL
);
1582 if (op1
== OR_TMP0
) {
1583 tcg_gen_mov_tl(a0
, cpu_A0
);
1584 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1586 gen_op_mov_v_reg(ot
, t0
, op1
);
1589 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1591 tcg_gen_andi_tl(t1
, t1
, mask
);
1593 /* Must test zero case to avoid using undefined behaviour in TCG
1595 label1
= gen_new_label();
1596 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1599 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1601 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1604 tcg_gen_mov_tl(t2
, t0
);
1606 data_bits
= 8 << ot
;
1607 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1608 fix TCG definition) */
1610 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1611 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(data_bits
), cpu_tmp0
);
1612 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1614 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1615 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(data_bits
), cpu_tmp0
);
1616 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1618 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1620 gen_set_label(label1
);
1622 if (op1
== OR_TMP0
) {
1623 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1625 gen_op_mov_reg_v(ot
, op1
, t0
);
1629 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1630 gen_op_set_cc_op(s
->cc_op
);
1632 label2
= gen_new_label();
1633 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1635 gen_compute_eflags(cpu_cc_src
);
1636 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1637 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1638 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1639 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1640 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1642 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1644 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1645 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1647 tcg_gen_discard_tl(cpu_cc_dst
);
1648 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1650 gen_set_label(label2
);
1651 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1659 static void *helper_rotc
[8] = {
1663 X86_64_ONLY(helper_rclq
),
1667 X86_64_ONLY(helper_rcrq
),
1670 /* XXX: add faster immediate = 1 case */
1671 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1676 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1677 gen_op_set_cc_op(s
->cc_op
);
1681 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1683 gen_op_mov_TN_reg(ot
, 0, op1
);
1685 tcg_gen_helper_1_2(helper_rotc
[ot
+ (is_right
* 4)],
1686 cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1689 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1691 gen_op_mov_reg_T0(ot
, op1
);
1694 label1
= gen_new_label();
1695 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_cc_tmp
, -1, label1
);
1697 tcg_gen_mov_tl(cpu_cc_src
, cpu_cc_tmp
);
1698 tcg_gen_discard_tl(cpu_cc_dst
);
1699 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_EFLAGS
);
1701 gen_set_label(label1
);
1702 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1705 /* XXX: add faster immediate case */
1706 static void gen_shiftd_rm_T1_T3(DisasContext
*s
, int ot
, int op1
,
1709 int label1
, label2
, data_bits
;
1711 TCGv t0
, t1
, t2
, a0
;
1713 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
1714 t1
= tcg_temp_local_new(TCG_TYPE_TL
);
1715 t2
= tcg_temp_local_new(TCG_TYPE_TL
);
1716 a0
= tcg_temp_local_new(TCG_TYPE_TL
);
1724 if (op1
== OR_TMP0
) {
1725 tcg_gen_mov_tl(a0
, cpu_A0
);
1726 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1728 gen_op_mov_v_reg(ot
, t0
, op1
);
1731 tcg_gen_andi_tl(cpu_T3
, cpu_T3
, mask
);
1733 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1734 tcg_gen_mov_tl(t2
, cpu_T3
);
1736 /* Must test zero case to avoid using undefined behaviour in TCG
1738 label1
= gen_new_label();
1739 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1741 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1742 if (ot
== OT_WORD
) {
1743 /* Note: we implement the Intel behaviour for shift count > 16 */
1745 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1746 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1747 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1748 tcg_gen_ext32u_tl(t0
, t0
);
1750 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1752 /* only needed if count > 16, but a test would complicate */
1753 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(32), t2
);
1754 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1756 tcg_gen_shr_tl(t0
, t0
, t2
);
1758 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1760 /* XXX: not optimal */
1761 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1762 tcg_gen_shli_tl(t1
, t1
, 16);
1763 tcg_gen_or_tl(t1
, t1
, t0
);
1764 tcg_gen_ext32u_tl(t1
, t1
);
1766 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1767 tcg_gen_sub_tl(cpu_tmp0
, tcg_const_tl(32), cpu_tmp5
);
1768 tcg_gen_shr_tl(cpu_tmp6
, t1
, cpu_tmp0
);
1769 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp6
);
1771 tcg_gen_shl_tl(t0
, t0
, t2
);
1772 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(32), t2
);
1773 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1774 tcg_gen_or_tl(t0
, t0
, t1
);
1777 data_bits
= 8 << ot
;
1780 tcg_gen_ext32u_tl(t0
, t0
);
1782 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1784 tcg_gen_shr_tl(t0
, t0
, t2
);
1785 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(data_bits
), t2
);
1786 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1787 tcg_gen_or_tl(t0
, t0
, t1
);
1791 tcg_gen_ext32u_tl(t1
, t1
);
1793 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1795 tcg_gen_shl_tl(t0
, t0
, t2
);
1796 tcg_gen_sub_tl(cpu_tmp5
, tcg_const_tl(data_bits
), t2
);
1797 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1798 tcg_gen_or_tl(t0
, t0
, t1
);
1801 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1803 gen_set_label(label1
);
1805 if (op1
== OR_TMP0
) {
1806 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1808 gen_op_mov_reg_v(ot
, op1
, t0
);
1812 if (s
->cc_op
!= CC_OP_DYNAMIC
)
1813 gen_op_set_cc_op(s
->cc_op
);
1815 label2
= gen_new_label();
1816 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1818 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1819 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1821 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1823 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1825 gen_set_label(label2
);
1826 s
->cc_op
= CC_OP_DYNAMIC
; /* cannot predict flags after */
1834 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1837 gen_op_mov_TN_reg(ot
, 1, s
);
1840 gen_rot_rm_T1(s1
, ot
, d
, 0);
1843 gen_rot_rm_T1(s1
, ot
, d
, 1);
1847 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1850 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1853 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1856 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1859 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1864 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1869 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1872 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1875 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1878 /* currently not optimized */
1879 gen_op_movl_T1_im(c
);
1880 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1885 static void gen_lea_modrm(DisasContext
*s
, int modrm
, int *reg_ptr
, int *offset_ptr
)
1893 int mod
, rm
, code
, override
, must_add_seg
;
1895 override
= s
->override
;
1896 must_add_seg
= s
->addseg
;
1899 mod
= (modrm
>> 6) & 3;
1911 code
= ldub_code(s
->pc
++);
1912 scale
= (code
>> 6) & 3;
1913 index
= ((code
>> 3) & 7) | REX_X(s
);
1920 if ((base
& 7) == 5) {
1922 disp
= (int32_t)ldl_code(s
->pc
);
1924 if (CODE64(s
) && !havesib
) {
1925 disp
+= s
->pc
+ s
->rip_offset
;
1932 disp
= (int8_t)ldub_code(s
->pc
++);
1936 disp
= ldl_code(s
->pc
);
1942 /* for correct popl handling with esp */
1943 if (base
== 4 && s
->popl_esp_hack
)
1944 disp
+= s
->popl_esp_hack
;
1945 #ifdef TARGET_X86_64
1946 if (s
->aflag
== 2) {
1947 gen_op_movq_A0_reg(base
);
1949 gen_op_addq_A0_im(disp
);
1954 gen_op_movl_A0_reg(base
);
1956 gen_op_addl_A0_im(disp
);
1959 #ifdef TARGET_X86_64
1960 if (s
->aflag
== 2) {
1961 gen_op_movq_A0_im(disp
);
1965 gen_op_movl_A0_im(disp
);
1968 /* XXX: index == 4 is always invalid */
1969 if (havesib
&& (index
!= 4 || scale
!= 0)) {
1970 #ifdef TARGET_X86_64
1971 if (s
->aflag
== 2) {
1972 gen_op_addq_A0_reg_sN(scale
, index
);
1976 gen_op_addl_A0_reg_sN(scale
, index
);
1981 if (base
== R_EBP
|| base
== R_ESP
)
1986 #ifdef TARGET_X86_64
1987 if (s
->aflag
== 2) {
1988 gen_op_addq_A0_seg(override
);
1992 gen_op_addl_A0_seg(override
);
1999 disp
= lduw_code(s
->pc
);
2001 gen_op_movl_A0_im(disp
);
2002 rm
= 0; /* avoid SS override */
2009 disp
= (int8_t)ldub_code(s
->pc
++);
2013 disp
= lduw_code(s
->pc
);
2019 gen_op_movl_A0_reg(R_EBX
);
2020 gen_op_addl_A0_reg_sN(0, R_ESI
);
2023 gen_op_movl_A0_reg(R_EBX
);
2024 gen_op_addl_A0_reg_sN(0, R_EDI
);
2027 gen_op_movl_A0_reg(R_EBP
);
2028 gen_op_addl_A0_reg_sN(0, R_ESI
);
2031 gen_op_movl_A0_reg(R_EBP
);
2032 gen_op_addl_A0_reg_sN(0, R_EDI
);
2035 gen_op_movl_A0_reg(R_ESI
);
2038 gen_op_movl_A0_reg(R_EDI
);
2041 gen_op_movl_A0_reg(R_EBP
);
2045 gen_op_movl_A0_reg(R_EBX
);
2049 gen_op_addl_A0_im(disp
);
2050 gen_op_andl_A0_ffff();
2054 if (rm
== 2 || rm
== 3 || rm
== 6)
2059 gen_op_addl_A0_seg(override
);
2069 static void gen_nop_modrm(DisasContext
*s
, int modrm
)
2071 int mod
, rm
, base
, code
;
2073 mod
= (modrm
>> 6) & 3;
2083 code
= ldub_code(s
->pc
++);
2119 /* used for LEA and MOV AX, mem */
2120 static void gen_add_A0_ds_seg(DisasContext
*s
)
2122 int override
, must_add_seg
;
2123 must_add_seg
= s
->addseg
;
2125 if (s
->override
>= 0) {
2126 override
= s
->override
;
2132 #ifdef TARGET_X86_64
2134 gen_op_addq_A0_seg(override
);
2138 gen_op_addl_A0_seg(override
);
2143 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
2145 static void gen_ldst_modrm(DisasContext
*s
, int modrm
, int ot
, int reg
, int is_store
)
2147 int mod
, rm
, opreg
, disp
;
2149 mod
= (modrm
>> 6) & 3;
2150 rm
= (modrm
& 7) | REX_B(s
);
2154 gen_op_mov_TN_reg(ot
, 0, reg
);
2155 gen_op_mov_reg_T0(ot
, rm
);
2157 gen_op_mov_TN_reg(ot
, 0, rm
);
2159 gen_op_mov_reg_T0(ot
, reg
);
2162 gen_lea_modrm(s
, modrm
, &opreg
, &disp
);
2165 gen_op_mov_TN_reg(ot
, 0, reg
);
2166 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2168 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2170 gen_op_mov_reg_T0(ot
, reg
);
2175 static inline uint32_t insn_get(DisasContext
*s
, int ot
)
2181 ret
= ldub_code(s
->pc
);
2185 ret
= lduw_code(s
->pc
);
2190 ret
= ldl_code(s
->pc
);
2197 static inline int insn_const_size(unsigned int ot
)
2205 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2207 TranslationBlock
*tb
;
2210 pc
= s
->cs_base
+ eip
;
2212 /* NOTE: we handle the case where the TB spans two pages here */
2213 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2214 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2215 /* jump to same page: we can use a direct jump */
2216 tcg_gen_goto_tb(tb_num
);
2218 tcg_gen_exit_tb((long)tb
+ tb_num
);
2220 /* jump to another page: currently not optimized */
2226 static inline void gen_jcc(DisasContext
*s
, int b
,
2227 target_ulong val
, target_ulong next_eip
)
2232 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2233 gen_op_set_cc_op(s
->cc_op
);
2234 s
->cc_op
= CC_OP_DYNAMIC
;
2237 l1
= gen_new_label();
2238 gen_jcc1(s
, cc_op
, b
, l1
);
2240 gen_goto_tb(s
, 0, next_eip
);
2243 gen_goto_tb(s
, 1, val
);
2247 l1
= gen_new_label();
2248 l2
= gen_new_label();
2249 gen_jcc1(s
, cc_op
, b
, l1
);
2251 gen_jmp_im(next_eip
);
2261 static void gen_setcc(DisasContext
*s
, int b
)
2263 int inv
, jcc_op
, l1
;
2266 if (is_fast_jcc_case(s
, b
)) {
2267 /* nominal case: we use a jump */
2268 /* XXX: make it faster by adding new instructions in TCG */
2269 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
2270 tcg_gen_movi_tl(t0
, 0);
2271 l1
= gen_new_label();
2272 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
2273 tcg_gen_movi_tl(t0
, 1);
2275 tcg_gen_mov_tl(cpu_T
[0], t0
);
2278 /* slow case: it is more efficient not to generate a jump,
2279 although it is questionnable whether this optimization is
2282 jcc_op
= (b
>> 1) & 7;
2283 gen_setcc_slow_T0(s
, jcc_op
);
2285 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], 1);
2290 static inline void gen_op_movl_T0_seg(int seg_reg
)
2292 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2293 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2296 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2298 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2299 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2300 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2301 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2302 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2303 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2306 /* move T0 to seg_reg and compute if the CPU state may change. Never
2307 call this function with seg_reg == R_CS */
2308 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2310 if (s
->pe
&& !s
->vm86
) {
2311 /* XXX: optimize by finding processor state dynamically */
2312 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2313 gen_op_set_cc_op(s
->cc_op
);
2314 gen_jmp_im(cur_eip
);
2315 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2316 tcg_gen_helper_0_2(helper_load_seg
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2317 /* abort translation because the addseg value may change or
2318 because ss32 may change. For R_SS, translation must always
2319 stop as a special handling must be done to disable hardware
2320 interrupts for the next instruction */
2321 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2324 gen_op_movl_seg_T0_vm(seg_reg
);
2325 if (seg_reg
== R_SS
)
2330 static inline int svm_is_rep(int prefixes
)
2332 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2336 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2337 uint32_t type
, uint64_t param
)
2339 /* no SVM activated; fast case */
2340 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2342 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2343 gen_op_set_cc_op(s
->cc_op
);
2344 gen_jmp_im(pc_start
- s
->cs_base
);
2345 tcg_gen_helper_0_2(helper_svm_check_intercept_param
,
2346 tcg_const_i32(type
), tcg_const_i64(param
));
2350 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2352 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2355 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2357 #ifdef TARGET_X86_64
2359 gen_op_add_reg_im(2, R_ESP
, addend
);
2363 gen_op_add_reg_im(1, R_ESP
, addend
);
2365 gen_op_add_reg_im(0, R_ESP
, addend
);
2369 /* generate a push. It depends on ss32, addseg and dflag */
2370 static void gen_push_T0(DisasContext
*s
)
2372 #ifdef TARGET_X86_64
2374 gen_op_movq_A0_reg(R_ESP
);
2376 gen_op_addq_A0_im(-8);
2377 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2379 gen_op_addq_A0_im(-2);
2380 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2382 gen_op_mov_reg_A0(2, R_ESP
);
2386 gen_op_movl_A0_reg(R_ESP
);
2388 gen_op_addl_A0_im(-2);
2390 gen_op_addl_A0_im(-4);
2393 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2394 gen_op_addl_A0_seg(R_SS
);
2397 gen_op_andl_A0_ffff();
2398 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2399 gen_op_addl_A0_seg(R_SS
);
2401 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2402 if (s
->ss32
&& !s
->addseg
)
2403 gen_op_mov_reg_A0(1, R_ESP
);
2405 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2409 /* generate a push. It depends on ss32, addseg and dflag */
2410 /* slower version for T1, only used for call Ev */
2411 static void gen_push_T1(DisasContext
*s
)
2413 #ifdef TARGET_X86_64
2415 gen_op_movq_A0_reg(R_ESP
);
2417 gen_op_addq_A0_im(-8);
2418 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2420 gen_op_addq_A0_im(-2);
2421 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2423 gen_op_mov_reg_A0(2, R_ESP
);
2427 gen_op_movl_A0_reg(R_ESP
);
2429 gen_op_addl_A0_im(-2);
2431 gen_op_addl_A0_im(-4);
2434 gen_op_addl_A0_seg(R_SS
);
2437 gen_op_andl_A0_ffff();
2438 gen_op_addl_A0_seg(R_SS
);
2440 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2442 if (s
->ss32
&& !s
->addseg
)
2443 gen_op_mov_reg_A0(1, R_ESP
);
2445 gen_stack_update(s
, (-2) << s
->dflag
);
2449 /* two step pop is necessary for precise exceptions */
2450 static void gen_pop_T0(DisasContext
*s
)
2452 #ifdef TARGET_X86_64
2454 gen_op_movq_A0_reg(R_ESP
);
2455 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2459 gen_op_movl_A0_reg(R_ESP
);
2462 gen_op_addl_A0_seg(R_SS
);
2464 gen_op_andl_A0_ffff();
2465 gen_op_addl_A0_seg(R_SS
);
2467 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2471 static void gen_pop_update(DisasContext
*s
)
2473 #ifdef TARGET_X86_64
2474 if (CODE64(s
) && s
->dflag
) {
2475 gen_stack_update(s
, 8);
2479 gen_stack_update(s
, 2 << s
->dflag
);
2483 static void gen_stack_A0(DisasContext
*s
)
2485 gen_op_movl_A0_reg(R_ESP
);
2487 gen_op_andl_A0_ffff();
2488 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2490 gen_op_addl_A0_seg(R_SS
);
2493 /* NOTE: wrap around in 16 bit not fully handled */
2494 static void gen_pusha(DisasContext
*s
)
2497 gen_op_movl_A0_reg(R_ESP
);
2498 gen_op_addl_A0_im(-16 << s
->dflag
);
2500 gen_op_andl_A0_ffff();
2501 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2503 gen_op_addl_A0_seg(R_SS
);
2504 for(i
= 0;i
< 8; i
++) {
2505 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2506 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2507 gen_op_addl_A0_im(2 << s
->dflag
);
2509 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2512 /* NOTE: wrap around in 16 bit not fully handled */
2513 static void gen_popa(DisasContext
*s
)
2516 gen_op_movl_A0_reg(R_ESP
);
2518 gen_op_andl_A0_ffff();
2519 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2520 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2522 gen_op_addl_A0_seg(R_SS
);
2523 for(i
= 0;i
< 8; i
++) {
2524 /* ESP is not reloaded */
2526 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2527 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2529 gen_op_addl_A0_im(2 << s
->dflag
);
2531 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2534 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2539 #ifdef TARGET_X86_64
2541 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2544 gen_op_movl_A0_reg(R_ESP
);
2545 gen_op_addq_A0_im(-opsize
);
2546 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2549 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2550 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2552 /* XXX: must save state */
2553 tcg_gen_helper_0_3(helper_enter64_level
,
2554 tcg_const_i32(level
),
2555 tcg_const_i32((ot
== OT_QUAD
)),
2558 gen_op_mov_reg_T1(ot
, R_EBP
);
2559 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2560 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2564 ot
= s
->dflag
+ OT_WORD
;
2565 opsize
= 2 << s
->dflag
;
2567 gen_op_movl_A0_reg(R_ESP
);
2568 gen_op_addl_A0_im(-opsize
);
2570 gen_op_andl_A0_ffff();
2571 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2573 gen_op_addl_A0_seg(R_SS
);
2575 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2576 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2578 /* XXX: must save state */
2579 tcg_gen_helper_0_3(helper_enter_level
,
2580 tcg_const_i32(level
),
2581 tcg_const_i32(s
->dflag
),
2584 gen_op_mov_reg_T1(ot
, R_EBP
);
2585 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2586 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2590 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2592 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2593 gen_op_set_cc_op(s
->cc_op
);
2594 gen_jmp_im(cur_eip
);
2595 tcg_gen_helper_0_1(helper_raise_exception
, tcg_const_i32(trapno
));
2599 /* an interrupt is different from an exception because of the
2601 static void gen_interrupt(DisasContext
*s
, int intno
,
2602 target_ulong cur_eip
, target_ulong next_eip
)
2604 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2605 gen_op_set_cc_op(s
->cc_op
);
2606 gen_jmp_im(cur_eip
);
2607 tcg_gen_helper_0_2(helper_raise_interrupt
,
2608 tcg_const_i32(intno
),
2609 tcg_const_i32(next_eip
- cur_eip
));
2613 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2615 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2616 gen_op_set_cc_op(s
->cc_op
);
2617 gen_jmp_im(cur_eip
);
2618 tcg_gen_helper_0_0(helper_debug
);
2622 /* generate a generic end of block. Trace exception is also generated
2624 static void gen_eob(DisasContext
*s
)
2626 if (s
->cc_op
!= CC_OP_DYNAMIC
)
2627 gen_op_set_cc_op(s
->cc_op
);
2628 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2629 tcg_gen_helper_0_0(helper_reset_inhibit_irq
);
2631 if (s
->singlestep_enabled
) {
2632 tcg_gen_helper_0_0(helper_debug
);
2634 tcg_gen_helper_0_0(helper_single_step
);
2641 /* generate a jump to eip. No segment change must happen before as a
2642 direct call to the next block may occur */
2643 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2646 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
2647 gen_op_set_cc_op(s
->cc_op
);
2648 s
->cc_op
= CC_OP_DYNAMIC
;
2650 gen_goto_tb(s
, tb_num
, eip
);
2658 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2660 gen_jmp_tb(s
, eip
, 0);
2663 static inline void gen_ldq_env_A0(int idx
, int offset
)
2665 int mem_index
= (idx
>> 2) - 1;
2666 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2667 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2670 static inline void gen_stq_env_A0(int idx
, int offset
)
2672 int mem_index
= (idx
>> 2) - 1;
2673 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2674 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2677 static inline void gen_ldo_env_A0(int idx
, int offset
)
2679 int mem_index
= (idx
>> 2) - 1;
2680 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2681 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2682 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2683 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2684 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2687 static inline void gen_sto_env_A0(int idx
, int offset
)
2689 int mem_index
= (idx
>> 2) - 1;
2690 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2691 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2692 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2693 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2694 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2697 static inline void gen_op_movo(int d_offset
, int s_offset
)
2699 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2700 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2701 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2702 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2705 static inline void gen_op_movq(int d_offset
, int s_offset
)
2707 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2708 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2711 static inline void gen_op_movl(int d_offset
, int s_offset
)
2713 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2714 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2717 static inline void gen_op_movq_env_0(int d_offset
)
2719 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2720 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2723 #define SSE_SPECIAL ((void *)1)
2724 #define SSE_DUMMY ((void *)2)
2726 #define MMX_OP2(x) { helper_ ## x ## _mmx, helper_ ## x ## _xmm }
2727 #define SSE_FOP(x) { helper_ ## x ## ps, helper_ ## x ## pd, \
2728 helper_ ## x ## ss, helper_ ## x ## sd, }
2730 static void *sse_op_table1
[256][4] = {
2731 /* 3DNow! extensions */
2732 [0x0e] = { SSE_DUMMY
}, /* femms */
2733 [0x0f] = { SSE_DUMMY
}, /* pf... */
2734 /* pure SSE operations */
2735 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2736 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2737 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2738 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2739 [0x14] = { helper_punpckldq_xmm
, helper_punpcklqdq_xmm
},
2740 [0x15] = { helper_punpckhdq_xmm
, helper_punpckhqdq_xmm
},
2741 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2742 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2744 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2745 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2746 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2747 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd */
2748 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2749 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2750 [0x2e] = { helper_ucomiss
, helper_ucomisd
},
2751 [0x2f] = { helper_comiss
, helper_comisd
},
2752 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2753 [0x51] = SSE_FOP(sqrt
),
2754 [0x52] = { helper_rsqrtps
, NULL
, helper_rsqrtss
, NULL
},
2755 [0x53] = { helper_rcpps
, NULL
, helper_rcpss
, NULL
},
2756 [0x54] = { helper_pand_xmm
, helper_pand_xmm
}, /* andps, andpd */
2757 [0x55] = { helper_pandn_xmm
, helper_pandn_xmm
}, /* andnps, andnpd */
2758 [0x56] = { helper_por_xmm
, helper_por_xmm
}, /* orps, orpd */
2759 [0x57] = { helper_pxor_xmm
, helper_pxor_xmm
}, /* xorps, xorpd */
2760 [0x58] = SSE_FOP(add
),
2761 [0x59] = SSE_FOP(mul
),
2762 [0x5a] = { helper_cvtps2pd
, helper_cvtpd2ps
,
2763 helper_cvtss2sd
, helper_cvtsd2ss
},
2764 [0x5b] = { helper_cvtdq2ps
, helper_cvtps2dq
, helper_cvttps2dq
},
2765 [0x5c] = SSE_FOP(sub
),
2766 [0x5d] = SSE_FOP(min
),
2767 [0x5e] = SSE_FOP(div
),
2768 [0x5f] = SSE_FOP(max
),
2770 [0xc2] = SSE_FOP(cmpeq
),
2771 [0xc6] = { helper_shufps
, helper_shufpd
},
2773 /* MMX ops and their SSE extensions */
2774 [0x60] = MMX_OP2(punpcklbw
),
2775 [0x61] = MMX_OP2(punpcklwd
),
2776 [0x62] = MMX_OP2(punpckldq
),
2777 [0x63] = MMX_OP2(packsswb
),
2778 [0x64] = MMX_OP2(pcmpgtb
),
2779 [0x65] = MMX_OP2(pcmpgtw
),
2780 [0x66] = MMX_OP2(pcmpgtl
),
2781 [0x67] = MMX_OP2(packuswb
),
2782 [0x68] = MMX_OP2(punpckhbw
),
2783 [0x69] = MMX_OP2(punpckhwd
),
2784 [0x6a] = MMX_OP2(punpckhdq
),
2785 [0x6b] = MMX_OP2(packssdw
),
2786 [0x6c] = { NULL
, helper_punpcklqdq_xmm
},
2787 [0x6d] = { NULL
, helper_punpckhqdq_xmm
},
2788 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2789 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2790 [0x70] = { helper_pshufw_mmx
,
2793 helper_pshuflw_xmm
},
2794 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2795 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2796 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2797 [0x74] = MMX_OP2(pcmpeqb
),
2798 [0x75] = MMX_OP2(pcmpeqw
),
2799 [0x76] = MMX_OP2(pcmpeql
),
2800 [0x77] = { SSE_DUMMY
}, /* emms */
2801 [0x7c] = { NULL
, helper_haddpd
, NULL
, helper_haddps
},
2802 [0x7d] = { NULL
, helper_hsubpd
, NULL
, helper_hsubps
},
2803 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2804 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2805 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2806 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2807 [0xd0] = { NULL
, helper_addsubpd
, NULL
, helper_addsubps
},
2808 [0xd1] = MMX_OP2(psrlw
),
2809 [0xd2] = MMX_OP2(psrld
),
2810 [0xd3] = MMX_OP2(psrlq
),
2811 [0xd4] = MMX_OP2(paddq
),
2812 [0xd5] = MMX_OP2(pmullw
),
2813 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2814 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2815 [0xd8] = MMX_OP2(psubusb
),
2816 [0xd9] = MMX_OP2(psubusw
),
2817 [0xda] = MMX_OP2(pminub
),
2818 [0xdb] = MMX_OP2(pand
),
2819 [0xdc] = MMX_OP2(paddusb
),
2820 [0xdd] = MMX_OP2(paddusw
),
2821 [0xde] = MMX_OP2(pmaxub
),
2822 [0xdf] = MMX_OP2(pandn
),
2823 [0xe0] = MMX_OP2(pavgb
),
2824 [0xe1] = MMX_OP2(psraw
),
2825 [0xe2] = MMX_OP2(psrad
),
2826 [0xe3] = MMX_OP2(pavgw
),
2827 [0xe4] = MMX_OP2(pmulhuw
),
2828 [0xe5] = MMX_OP2(pmulhw
),
2829 [0xe6] = { NULL
, helper_cvttpd2dq
, helper_cvtdq2pd
, helper_cvtpd2dq
},
2830 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2831 [0xe8] = MMX_OP2(psubsb
),
2832 [0xe9] = MMX_OP2(psubsw
),
2833 [0xea] = MMX_OP2(pminsw
),
2834 [0xeb] = MMX_OP2(por
),
2835 [0xec] = MMX_OP2(paddsb
),
2836 [0xed] = MMX_OP2(paddsw
),
2837 [0xee] = MMX_OP2(pmaxsw
),
2838 [0xef] = MMX_OP2(pxor
),
2839 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2840 [0xf1] = MMX_OP2(psllw
),
2841 [0xf2] = MMX_OP2(pslld
),
2842 [0xf3] = MMX_OP2(psllq
),
2843 [0xf4] = MMX_OP2(pmuludq
),
2844 [0xf5] = MMX_OP2(pmaddwd
),
2845 [0xf6] = MMX_OP2(psadbw
),
2846 [0xf7] = MMX_OP2(maskmov
),
2847 [0xf8] = MMX_OP2(psubb
),
2848 [0xf9] = MMX_OP2(psubw
),
2849 [0xfa] = MMX_OP2(psubl
),
2850 [0xfb] = MMX_OP2(psubq
),
2851 [0xfc] = MMX_OP2(paddb
),
2852 [0xfd] = MMX_OP2(paddw
),
2853 [0xfe] = MMX_OP2(paddl
),
2856 static void *sse_op_table2
[3 * 8][2] = {
2857 [0 + 2] = MMX_OP2(psrlw
),
2858 [0 + 4] = MMX_OP2(psraw
),
2859 [0 + 6] = MMX_OP2(psllw
),
2860 [8 + 2] = MMX_OP2(psrld
),
2861 [8 + 4] = MMX_OP2(psrad
),
2862 [8 + 6] = MMX_OP2(pslld
),
2863 [16 + 2] = MMX_OP2(psrlq
),
2864 [16 + 3] = { NULL
, helper_psrldq_xmm
},
2865 [16 + 6] = MMX_OP2(psllq
),
2866 [16 + 7] = { NULL
, helper_pslldq_xmm
},
2869 static void *sse_op_table3
[4 * 3] = {
2872 X86_64_ONLY(helper_cvtsq2ss
),
2873 X86_64_ONLY(helper_cvtsq2sd
),
2877 X86_64_ONLY(helper_cvttss2sq
),
2878 X86_64_ONLY(helper_cvttsd2sq
),
2882 X86_64_ONLY(helper_cvtss2sq
),
2883 X86_64_ONLY(helper_cvtsd2sq
),
2886 static void *sse_op_table4
[8][4] = {
2897 static void *sse_op_table5
[256] = {
2898 [0x0c] = helper_pi2fw
,
2899 [0x0d] = helper_pi2fd
,
2900 [0x1c] = helper_pf2iw
,
2901 [0x1d] = helper_pf2id
,
2902 [0x8a] = helper_pfnacc
,
2903 [0x8e] = helper_pfpnacc
,
2904 [0x90] = helper_pfcmpge
,
2905 [0x94] = helper_pfmin
,
2906 [0x96] = helper_pfrcp
,
2907 [0x97] = helper_pfrsqrt
,
2908 [0x9a] = helper_pfsub
,
2909 [0x9e] = helper_pfadd
,
2910 [0xa0] = helper_pfcmpgt
,
2911 [0xa4] = helper_pfmax
,
2912 [0xa6] = helper_movq
, /* pfrcpit1; no need to actually increase precision */
2913 [0xa7] = helper_movq
, /* pfrsqit1 */
2914 [0xaa] = helper_pfsubr
,
2915 [0xae] = helper_pfacc
,
2916 [0xb0] = helper_pfcmpeq
,
2917 [0xb4] = helper_pfmul
,
2918 [0xb6] = helper_movq
, /* pfrcpit2 */
2919 [0xb7] = helper_pmulhrw_mmx
,
2920 [0xbb] = helper_pswapd
,
2921 [0xbf] = helper_pavgb_mmx
/* pavgusb */
2924 static void gen_sse(DisasContext
*s
, int b
, target_ulong pc_start
, int rex_r
)
2926 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
2927 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
2931 if (s
->prefix
& PREFIX_DATA
)
2933 else if (s
->prefix
& PREFIX_REPZ
)
2935 else if (s
->prefix
& PREFIX_REPNZ
)
2939 sse_op2
= sse_op_table1
[b
][b1
];
2942 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
2952 /* simple MMX/SSE operation */
2953 if (s
->flags
& HF_TS_MASK
) {
2954 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
2957 if (s
->flags
& HF_EM_MASK
) {
2959 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
2962 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
2965 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
2968 tcg_gen_helper_0_0(helper_emms
);
2973 tcg_gen_helper_0_0(helper_emms
);
2976 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
2977 the static cpu state) */
2979 tcg_gen_helper_0_0(helper_enter_mmx
);
2982 modrm
= ldub_code(s
->pc
++);
2983 reg
= ((modrm
>> 3) & 7);
2986 mod
= (modrm
>> 6) & 3;
2987 if (sse_op2
== SSE_SPECIAL
) {
2990 case 0x0e7: /* movntq */
2993 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
2994 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
2996 case 0x1e7: /* movntdq */
2997 case 0x02b: /* movntps */
2998 case 0x12b: /* movntps */
2999 case 0x3f0: /* lddqu */
3002 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3003 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3005 case 0x6e: /* movd mm, ea */
3006 #ifdef TARGET_X86_64
3007 if (s
->dflag
== 2) {
3008 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3009 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3013 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3014 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3015 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3016 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx
, cpu_ptr0
, cpu_T
[0]);
3019 case 0x16e: /* movd xmm, ea */
3020 #ifdef TARGET_X86_64
3021 if (s
->dflag
== 2) {
3022 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3023 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3024 offsetof(CPUX86State
,xmm_regs
[reg
]));
3025 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm
, cpu_ptr0
, cpu_T
[0]);
3029 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3030 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3031 offsetof(CPUX86State
,xmm_regs
[reg
]));
3032 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3033 tcg_gen_helper_0_2(helper_movl_mm_T0_xmm
, cpu_ptr0
, cpu_tmp2_i32
);
3036 case 0x6f: /* movq mm, ea */
3038 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3039 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3042 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3043 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3044 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3045 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3048 case 0x010: /* movups */
3049 case 0x110: /* movupd */
3050 case 0x028: /* movaps */
3051 case 0x128: /* movapd */
3052 case 0x16f: /* movdqa xmm, ea */
3053 case 0x26f: /* movdqu xmm, ea */
3055 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3056 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3058 rm
= (modrm
& 7) | REX_B(s
);
3059 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3060 offsetof(CPUX86State
,xmm_regs
[rm
]));
3063 case 0x210: /* movss xmm, ea */
3065 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3066 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3067 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3069 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3070 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3071 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3073 rm
= (modrm
& 7) | REX_B(s
);
3074 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3075 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3078 case 0x310: /* movsd xmm, ea */
3080 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3081 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3083 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3084 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3086 rm
= (modrm
& 7) | REX_B(s
);
3087 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3088 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3091 case 0x012: /* movlps */
3092 case 0x112: /* movlpd */
3094 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3095 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3098 rm
= (modrm
& 7) | REX_B(s
);
3099 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3100 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3103 case 0x212: /* movsldup */
3105 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3106 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3108 rm
= (modrm
& 7) | REX_B(s
);
3109 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3110 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3111 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3112 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3114 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3115 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3116 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3117 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3119 case 0x312: /* movddup */
3121 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3122 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3124 rm
= (modrm
& 7) | REX_B(s
);
3125 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3126 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3128 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3129 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3131 case 0x016: /* movhps */
3132 case 0x116: /* movhpd */
3134 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3135 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3138 rm
= (modrm
& 7) | REX_B(s
);
3139 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3140 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3143 case 0x216: /* movshdup */
3145 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3146 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3148 rm
= (modrm
& 7) | REX_B(s
);
3149 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3150 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3151 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3152 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3154 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3155 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3156 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3157 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3159 case 0x7e: /* movd ea, mm */
3160 #ifdef TARGET_X86_64
3161 if (s
->dflag
== 2) {
3162 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3163 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3164 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3168 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3169 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3170 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3173 case 0x17e: /* movd ea, xmm */
3174 #ifdef TARGET_X86_64
3175 if (s
->dflag
== 2) {
3176 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3177 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3178 gen_ldst_modrm(s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3182 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3183 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3184 gen_ldst_modrm(s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3187 case 0x27e: /* movq xmm, ea */
3189 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3190 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3192 rm
= (modrm
& 7) | REX_B(s
);
3193 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3194 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3196 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3198 case 0x7f: /* movq ea, mm */
3200 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3201 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3204 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3205 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3208 case 0x011: /* movups */
3209 case 0x111: /* movupd */
3210 case 0x029: /* movaps */
3211 case 0x129: /* movapd */
3212 case 0x17f: /* movdqa ea, xmm */
3213 case 0x27f: /* movdqu ea, xmm */
3215 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3216 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3218 rm
= (modrm
& 7) | REX_B(s
);
3219 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3220 offsetof(CPUX86State
,xmm_regs
[reg
]));
3223 case 0x211: /* movss ea, xmm */
3225 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3226 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3227 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3229 rm
= (modrm
& 7) | REX_B(s
);
3230 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3231 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3234 case 0x311: /* movsd ea, xmm */
3236 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3237 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3239 rm
= (modrm
& 7) | REX_B(s
);
3240 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3241 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3244 case 0x013: /* movlps */
3245 case 0x113: /* movlpd */
3247 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3248 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3253 case 0x017: /* movhps */
3254 case 0x117: /* movhpd */
3256 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3257 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3262 case 0x71: /* shift mm, im */
3265 case 0x171: /* shift xmm, im */
3268 val
= ldub_code(s
->pc
++);
3270 gen_op_movl_T0_im(val
);
3271 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3273 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3274 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3276 gen_op_movl_T0_im(val
);
3277 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3279 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3280 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3282 sse_op2
= sse_op_table2
[((b
- 1) & 3) * 8 + (((modrm
>> 3)) & 7)][b1
];
3286 rm
= (modrm
& 7) | REX_B(s
);
3287 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3290 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3292 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3293 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3294 tcg_gen_helper_0_2(sse_op2
, cpu_ptr0
, cpu_ptr1
);
3296 case 0x050: /* movmskps */
3297 rm
= (modrm
& 7) | REX_B(s
);
3298 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3299 offsetof(CPUX86State
,xmm_regs
[rm
]));
3300 tcg_gen_helper_1_1(helper_movmskps
, cpu_tmp2_i32
, cpu_ptr0
);
3301 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3302 gen_op_mov_reg_T0(OT_LONG
, reg
);
3304 case 0x150: /* movmskpd */
3305 rm
= (modrm
& 7) | REX_B(s
);
3306 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3307 offsetof(CPUX86State
,xmm_regs
[rm
]));
3308 tcg_gen_helper_1_1(helper_movmskpd
, cpu_tmp2_i32
, cpu_ptr0
);
3309 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3310 gen_op_mov_reg_T0(OT_LONG
, reg
);
3312 case 0x02a: /* cvtpi2ps */
3313 case 0x12a: /* cvtpi2pd */
3314 tcg_gen_helper_0_0(helper_enter_mmx
);
3316 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3317 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3318 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3321 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3323 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3324 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3325 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3328 tcg_gen_helper_0_2(helper_cvtpi2ps
, cpu_ptr0
, cpu_ptr1
);
3332 tcg_gen_helper_0_2(helper_cvtpi2pd
, cpu_ptr0
, cpu_ptr1
);
3336 case 0x22a: /* cvtsi2ss */
3337 case 0x32a: /* cvtsi2sd */
3338 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3339 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
3340 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3341 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3342 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2)];
3343 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3344 tcg_gen_helper_0_2(sse_op2
, cpu_ptr0
, cpu_tmp2_i32
);
3346 case 0x02c: /* cvttps2pi */
3347 case 0x12c: /* cvttpd2pi */
3348 case 0x02d: /* cvtps2pi */
3349 case 0x12d: /* cvtpd2pi */
3350 tcg_gen_helper_0_0(helper_enter_mmx
);
3352 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3353 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3354 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3356 rm
= (modrm
& 7) | REX_B(s
);
3357 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3359 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3360 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3361 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3364 tcg_gen_helper_0_2(helper_cvttps2pi
, cpu_ptr0
, cpu_ptr1
);
3367 tcg_gen_helper_0_2(helper_cvttpd2pi
, cpu_ptr0
, cpu_ptr1
);
3370 tcg_gen_helper_0_2(helper_cvtps2pi
, cpu_ptr0
, cpu_ptr1
);
3373 tcg_gen_helper_0_2(helper_cvtpd2pi
, cpu_ptr0
, cpu_ptr1
);
3377 case 0x22c: /* cvttss2si */
3378 case 0x32c: /* cvttsd2si */
3379 case 0x22d: /* cvtss2si */
3380 case 0x32d: /* cvtsd2si */
3381 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3383 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3385 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3387 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3388 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3390 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3392 rm
= (modrm
& 7) | REX_B(s
);
3393 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3395 sse_op2
= sse_op_table3
[(s
->dflag
== 2) * 2 + ((b
>> 8) - 2) + 4 +
3397 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3398 if (ot
== OT_LONG
) {
3399 tcg_gen_helper_1_1(sse_op2
, cpu_tmp2_i32
, cpu_ptr0
);
3400 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3402 tcg_gen_helper_1_1(sse_op2
, cpu_T
[0], cpu_ptr0
);
3404 gen_op_mov_reg_T0(ot
, reg
);
3406 case 0xc4: /* pinsrw */
3409 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3410 val
= ldub_code(s
->pc
++);
3413 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3414 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3417 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3418 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3421 case 0xc5: /* pextrw */
3425 val
= ldub_code(s
->pc
++);
3428 rm
= (modrm
& 7) | REX_B(s
);
3429 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3430 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3434 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3435 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3437 reg
= ((modrm
>> 3) & 7) | rex_r
;
3438 gen_op_mov_reg_T0(OT_LONG
, reg
);
3440 case 0x1d6: /* movq ea, xmm */
3442 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3443 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3445 rm
= (modrm
& 7) | REX_B(s
);
3446 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3447 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3448 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3451 case 0x2d6: /* movq2dq */
3452 tcg_gen_helper_0_0(helper_enter_mmx
);
3454 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3455 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3456 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3458 case 0x3d6: /* movdq2q */
3459 tcg_gen_helper_0_0(helper_enter_mmx
);
3460 rm
= (modrm
& 7) | REX_B(s
);
3461 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3462 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3464 case 0xd7: /* pmovmskb */
3469 rm
= (modrm
& 7) | REX_B(s
);
3470 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3471 tcg_gen_helper_1_1(helper_pmovmskb_xmm
, cpu_tmp2_i32
, cpu_ptr0
);
3474 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3475 tcg_gen_helper_1_1(helper_pmovmskb_mmx
, cpu_tmp2_i32
, cpu_ptr0
);
3477 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3478 reg
= ((modrm
>> 3) & 7) | rex_r
;
3479 gen_op_mov_reg_T0(OT_LONG
, reg
);
3485 /* generic MMX or SSE operation */
3487 case 0x70: /* pshufx insn */
3488 case 0xc6: /* pshufx insn */
3489 case 0xc2: /* compare insns */
3496 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3498 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3499 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3500 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
3502 /* specific case for SSE single instructions */
3505 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3506 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3509 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
3512 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3515 rm
= (modrm
& 7) | REX_B(s
);
3516 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3519 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3521 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3522 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3523 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3526 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3530 case 0x0f: /* 3DNow! data insns */
3531 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3533 val
= ldub_code(s
->pc
++);
3534 sse_op2
= sse_op_table5
[val
];
3537 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3538 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3539 tcg_gen_helper_0_2(sse_op2
, cpu_ptr0
, cpu_ptr1
);
3541 case 0x70: /* pshufx insn */
3542 case 0xc6: /* pshufx insn */
3543 val
= ldub_code(s
->pc
++);
3544 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3545 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3546 tcg_gen_helper_0_3(sse_op2
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
3550 val
= ldub_code(s
->pc
++);
3553 sse_op2
= sse_op_table4
[val
][b1
];
3554 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3555 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3556 tcg_gen_helper_0_2(sse_op2
, cpu_ptr0
, cpu_ptr1
);
3559 /* maskmov : we must prepare A0 */
3562 #ifdef TARGET_X86_64
3563 if (s
->aflag
== 2) {
3564 gen_op_movq_A0_reg(R_EDI
);
3568 gen_op_movl_A0_reg(R_EDI
);
3570 gen_op_andl_A0_ffff();
3572 gen_add_A0_ds_seg(s
);
3574 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3575 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3576 tcg_gen_helper_0_3(sse_op2
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
3579 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3580 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3581 tcg_gen_helper_0_2(sse_op2
, cpu_ptr0
, cpu_ptr1
);
3584 if (b
== 0x2e || b
== 0x2f) {
3585 s
->cc_op
= CC_OP_EFLAGS
;
3590 /* convert one instruction. s->is_jmp is set if the translation must
3591 be stopped. Return the next pc value */
3592 static target_ulong
disas_insn(DisasContext
*s
, target_ulong pc_start
)
3594 int b
, prefixes
, aflag
, dflag
;
3596 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
3597 target_ulong next_eip
, tval
;
3600 if (unlikely(loglevel
& CPU_LOG_TB_OP
))
3601 tcg_gen_debug_insn_start(pc_start
);
3609 #ifdef TARGET_X86_64
3614 s
->rip_offset
= 0; /* for relative ip address */
3616 b
= ldub_code(s
->pc
);
3618 /* check prefixes */
3619 #ifdef TARGET_X86_64
3623 prefixes
|= PREFIX_REPZ
;
3626 prefixes
|= PREFIX_REPNZ
;
3629 prefixes
|= PREFIX_LOCK
;
3650 prefixes
|= PREFIX_DATA
;
3653 prefixes
|= PREFIX_ADR
;
3657 rex_w
= (b
>> 3) & 1;
3658 rex_r
= (b
& 0x4) << 1;
3659 s
->rex_x
= (b
& 0x2) << 2;
3660 REX_B(s
) = (b
& 0x1) << 3;
3661 x86_64_hregs
= 1; /* select uniform byte register addressing */
3665 /* 0x66 is ignored if rex.w is set */
3668 if (prefixes
& PREFIX_DATA
)
3671 if (!(prefixes
& PREFIX_ADR
))
3678 prefixes
|= PREFIX_REPZ
;
3681 prefixes
|= PREFIX_REPNZ
;
3684 prefixes
|= PREFIX_LOCK
;
3705 prefixes
|= PREFIX_DATA
;
3708 prefixes
|= PREFIX_ADR
;
3711 if (prefixes
& PREFIX_DATA
)
3713 if (prefixes
& PREFIX_ADR
)
3717 s
->prefix
= prefixes
;
3721 /* lock generation */
3722 if (prefixes
& PREFIX_LOCK
)
3723 tcg_gen_helper_0_0(helper_lock
);
3725 /* now check op code */
3729 /**************************/
3730 /* extended op code */
3731 b
= ldub_code(s
->pc
++) | 0x100;
3734 /**************************/
3752 ot
= dflag
+ OT_WORD
;
3755 case 0: /* OP Ev, Gv */
3756 modrm
= ldub_code(s
->pc
++);
3757 reg
= ((modrm
>> 3) & 7) | rex_r
;
3758 mod
= (modrm
>> 6) & 3;
3759 rm
= (modrm
& 7) | REX_B(s
);
3761 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3763 } else if (op
== OP_XORL
&& rm
== reg
) {
3765 /* xor reg, reg optimisation */
3767 s
->cc_op
= CC_OP_LOGICB
+ ot
;
3768 gen_op_mov_reg_T0(ot
, reg
);
3769 gen_op_update1_cc();
3774 gen_op_mov_TN_reg(ot
, 1, reg
);
3775 gen_op(s
, op
, ot
, opreg
);
3777 case 1: /* OP Gv, Ev */
3778 modrm
= ldub_code(s
->pc
++);
3779 mod
= (modrm
>> 6) & 3;
3780 reg
= ((modrm
>> 3) & 7) | rex_r
;
3781 rm
= (modrm
& 7) | REX_B(s
);
3783 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3784 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
3785 } else if (op
== OP_XORL
&& rm
== reg
) {
3788 gen_op_mov_TN_reg(ot
, 1, rm
);
3790 gen_op(s
, op
, ot
, reg
);
3792 case 2: /* OP A, Iv */
3793 val
= insn_get(s
, ot
);
3794 gen_op_movl_T1_im(val
);
3795 gen_op(s
, op
, ot
, OR_EAX
);
3804 case 0x80: /* GRP1 */
3813 ot
= dflag
+ OT_WORD
;
3815 modrm
= ldub_code(s
->pc
++);
3816 mod
= (modrm
>> 6) & 3;
3817 rm
= (modrm
& 7) | REX_B(s
);
3818 op
= (modrm
>> 3) & 7;
3824 s
->rip_offset
= insn_const_size(ot
);
3825 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3836 val
= insn_get(s
, ot
);
3839 val
= (int8_t)insn_get(s
, OT_BYTE
);
3842 gen_op_movl_T1_im(val
);
3843 gen_op(s
, op
, ot
, opreg
);
3847 /**************************/
3848 /* inc, dec, and other misc arith */
3849 case 0x40 ... 0x47: /* inc Gv */
3850 ot
= dflag
? OT_LONG
: OT_WORD
;
3851 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
3853 case 0x48 ... 0x4f: /* dec Gv */
3854 ot
= dflag
? OT_LONG
: OT_WORD
;
3855 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
3857 case 0xf6: /* GRP3 */
3862 ot
= dflag
+ OT_WORD
;
3864 modrm
= ldub_code(s
->pc
++);
3865 mod
= (modrm
>> 6) & 3;
3866 rm
= (modrm
& 7) | REX_B(s
);
3867 op
= (modrm
>> 3) & 7;
3870 s
->rip_offset
= insn_const_size(ot
);
3871 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
3872 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
3874 gen_op_mov_TN_reg(ot
, 0, rm
);
3879 val
= insn_get(s
, ot
);
3880 gen_op_movl_T1_im(val
);
3881 gen_op_testl_T0_T1_cc();
3882 s
->cc_op
= CC_OP_LOGICB
+ ot
;
3885 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
3887 gen_op_st_T0_A0(ot
+ s
->mem_index
);
3889 gen_op_mov_reg_T0(ot
, rm
);
3893 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
3895 gen_op_st_T0_A0(ot
+ s
->mem_index
);
3897 gen_op_mov_reg_T0(ot
, rm
);
3899 gen_op_update_neg_cc();
3900 s
->cc_op
= CC_OP_SUBB
+ ot
;
3905 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
3906 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
3907 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
3908 /* XXX: use 32 bit mul which could be faster */
3909 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3910 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
3911 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3912 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
3913 s
->cc_op
= CC_OP_MULB
;
3916 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
3917 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
3918 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
3919 /* XXX: use 32 bit mul which could be faster */
3920 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3921 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
3922 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3923 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
3924 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
3925 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
3926 s
->cc_op
= CC_OP_MULW
;
3930 #ifdef TARGET_X86_64
3931 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
3932 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
3933 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
3934 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3935 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
3936 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3937 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
3938 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
3939 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
3943 t0
= tcg_temp_new(TCG_TYPE_I64
);
3944 t1
= tcg_temp_new(TCG_TYPE_I64
);
3945 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
3946 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
3947 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
3948 tcg_gen_mul_i64(t0
, t0
, t1
);
3949 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
3950 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
3951 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3952 tcg_gen_shri_i64(t0
, t0
, 32);
3953 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
3954 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
3955 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
3958 s
->cc_op
= CC_OP_MULL
;
3960 #ifdef TARGET_X86_64
3962 tcg_gen_helper_0_1(helper_mulq_EAX_T0
, cpu_T
[0]);
3963 s
->cc_op
= CC_OP_MULQ
;
3971 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
3972 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
3973 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
3974 /* XXX: use 32 bit mul which could be faster */
3975 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3976 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
3977 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3978 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
3979 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
3980 s
->cc_op
= CC_OP_MULB
;
3983 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
3984 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
3985 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
3986 /* XXX: use 32 bit mul which could be faster */
3987 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3988 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
3989 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
3990 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
3991 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
3992 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
3993 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
3994 s
->cc_op
= CC_OP_MULW
;
3998 #ifdef TARGET_X86_64
3999 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4000 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4001 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4002 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4003 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4004 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4005 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4006 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4007 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4008 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4012 t0
= tcg_temp_new(TCG_TYPE_I64
);
4013 t1
= tcg_temp_new(TCG_TYPE_I64
);
4014 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4015 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4016 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4017 tcg_gen_mul_i64(t0
, t0
, t1
);
4018 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4019 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4020 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4021 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4022 tcg_gen_shri_i64(t0
, t0
, 32);
4023 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4024 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4025 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4028 s
->cc_op
= CC_OP_MULL
;
4030 #ifdef TARGET_X86_64
4032 tcg_gen_helper_0_1(helper_imulq_EAX_T0
, cpu_T
[0]);
4033 s
->cc_op
= CC_OP_MULQ
;
4041 gen_jmp_im(pc_start
- s
->cs_base
);
4042 tcg_gen_helper_0_1(helper_divb_AL
, cpu_T
[0]);
4045 gen_jmp_im(pc_start
- s
->cs_base
);
4046 tcg_gen_helper_0_1(helper_divw_AX
, cpu_T
[0]);
4050 gen_jmp_im(pc_start
- s
->cs_base
);
4051 tcg_gen_helper_0_1(helper_divl_EAX
, cpu_T
[0]);
4053 #ifdef TARGET_X86_64
4055 gen_jmp_im(pc_start
- s
->cs_base
);
4056 tcg_gen_helper_0_1(helper_divq_EAX
, cpu_T
[0]);
4064 gen_jmp_im(pc_start
- s
->cs_base
);
4065 tcg_gen_helper_0_1(helper_idivb_AL
, cpu_T
[0]);
4068 gen_jmp_im(pc_start
- s
->cs_base
);
4069 tcg_gen_helper_0_1(helper_idivw_AX
, cpu_T
[0]);
4073 gen_jmp_im(pc_start
- s
->cs_base
);
4074 tcg_gen_helper_0_1(helper_idivl_EAX
, cpu_T
[0]);
4076 #ifdef TARGET_X86_64
4078 gen_jmp_im(pc_start
- s
->cs_base
);
4079 tcg_gen_helper_0_1(helper_idivq_EAX
, cpu_T
[0]);
4089 case 0xfe: /* GRP4 */
4090 case 0xff: /* GRP5 */
4094 ot
= dflag
+ OT_WORD
;
4096 modrm
= ldub_code(s
->pc
++);
4097 mod
= (modrm
>> 6) & 3;
4098 rm
= (modrm
& 7) | REX_B(s
);
4099 op
= (modrm
>> 3) & 7;
4100 if (op
>= 2 && b
== 0xfe) {
4104 if (op
== 2 || op
== 4) {
4105 /* operand size for jumps is 64 bit */
4107 } else if (op
== 3 || op
== 5) {
4108 /* for call calls, the operand is 16 or 32 bit, even
4110 ot
= dflag
? OT_LONG
: OT_WORD
;
4111 } else if (op
== 6) {
4112 /* default push size is 64 bit */
4113 ot
= dflag
? OT_QUAD
: OT_WORD
;
4117 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4118 if (op
>= 2 && op
!= 3 && op
!= 5)
4119 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4121 gen_op_mov_TN_reg(ot
, 0, rm
);
4125 case 0: /* inc Ev */
4130 gen_inc(s
, ot
, opreg
, 1);
4132 case 1: /* dec Ev */
4137 gen_inc(s
, ot
, opreg
, -1);
4139 case 2: /* call Ev */
4140 /* XXX: optimize if memory (no 'and' is necessary) */
4142 gen_op_andl_T0_ffff();
4143 next_eip
= s
->pc
- s
->cs_base
;
4144 gen_movtl_T1_im(next_eip
);
4149 case 3: /* lcall Ev */
4150 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4151 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4152 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4154 if (s
->pe
&& !s
->vm86
) {
4155 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4156 gen_op_set_cc_op(s
->cc_op
);
4157 gen_jmp_im(pc_start
- s
->cs_base
);
4158 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4159 tcg_gen_helper_0_4(helper_lcall_protected
,
4160 cpu_tmp2_i32
, cpu_T
[1],
4161 tcg_const_i32(dflag
),
4162 tcg_const_i32(s
->pc
- pc_start
));
4164 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4165 tcg_gen_helper_0_4(helper_lcall_real
,
4166 cpu_tmp2_i32
, cpu_T
[1],
4167 tcg_const_i32(dflag
),
4168 tcg_const_i32(s
->pc
- s
->cs_base
));
4172 case 4: /* jmp Ev */
4174 gen_op_andl_T0_ffff();
4178 case 5: /* ljmp Ev */
4179 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4180 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4181 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4183 if (s
->pe
&& !s
->vm86
) {
4184 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4185 gen_op_set_cc_op(s
->cc_op
);
4186 gen_jmp_im(pc_start
- s
->cs_base
);
4187 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4188 tcg_gen_helper_0_3(helper_ljmp_protected
,
4191 tcg_const_i32(s
->pc
- pc_start
));
4193 gen_op_movl_seg_T0_vm(R_CS
);
4194 gen_op_movl_T0_T1();
4199 case 6: /* push Ev */
4207 case 0x84: /* test Ev, Gv */
4212 ot
= dflag
+ OT_WORD
;
4214 modrm
= ldub_code(s
->pc
++);
4215 mod
= (modrm
>> 6) & 3;
4216 rm
= (modrm
& 7) | REX_B(s
);
4217 reg
= ((modrm
>> 3) & 7) | rex_r
;
4219 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4220 gen_op_mov_TN_reg(ot
, 1, reg
);
4221 gen_op_testl_T0_T1_cc();
4222 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4225 case 0xa8: /* test eAX, Iv */
4230 ot
= dflag
+ OT_WORD
;
4231 val
= insn_get(s
, ot
);
4233 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4234 gen_op_movl_T1_im(val
);
4235 gen_op_testl_T0_T1_cc();
4236 s
->cc_op
= CC_OP_LOGICB
+ ot
;
4239 case 0x98: /* CWDE/CBW */
4240 #ifdef TARGET_X86_64
4242 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4243 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4244 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4248 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4249 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4250 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4252 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4253 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4254 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4257 case 0x99: /* CDQ/CWD */
4258 #ifdef TARGET_X86_64
4260 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4261 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4262 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4266 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4267 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4268 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4269 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4271 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4272 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4273 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4274 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4277 case 0x1af: /* imul Gv, Ev */
4278 case 0x69: /* imul Gv, Ev, I */
4280 ot
= dflag
+ OT_WORD
;
4281 modrm
= ldub_code(s
->pc
++);
4282 reg
= ((modrm
>> 3) & 7) | rex_r
;
4284 s
->rip_offset
= insn_const_size(ot
);
4287 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4289 val
= insn_get(s
, ot
);
4290 gen_op_movl_T1_im(val
);
4291 } else if (b
== 0x6b) {
4292 val
= (int8_t)insn_get(s
, OT_BYTE
);
4293 gen_op_movl_T1_im(val
);
4295 gen_op_mov_TN_reg(ot
, 1, reg
);
4298 #ifdef TARGET_X86_64
4299 if (ot
== OT_QUAD
) {
4300 tcg_gen_helper_1_2(helper_imulq_T0_T1
, cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4303 if (ot
== OT_LONG
) {
4304 #ifdef TARGET_X86_64
4305 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4306 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4307 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4308 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4309 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4310 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4314 t0
= tcg_temp_new(TCG_TYPE_I64
);
4315 t1
= tcg_temp_new(TCG_TYPE_I64
);
4316 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4317 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4318 tcg_gen_mul_i64(t0
, t0
, t1
);
4319 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4320 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4321 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4322 tcg_gen_shri_i64(t0
, t0
, 32);
4323 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4324 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4328 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4329 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4330 /* XXX: use 32 bit mul which could be faster */
4331 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4332 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4333 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4334 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4336 gen_op_mov_reg_T0(ot
, reg
);
4337 s
->cc_op
= CC_OP_MULB
+ ot
;
4340 case 0x1c1: /* xadd Ev, Gv */
4344 ot
= dflag
+ OT_WORD
;
4345 modrm
= ldub_code(s
->pc
++);
4346 reg
= ((modrm
>> 3) & 7) | rex_r
;
4347 mod
= (modrm
>> 6) & 3;
4349 rm
= (modrm
& 7) | REX_B(s
);
4350 gen_op_mov_TN_reg(ot
, 0, reg
);
4351 gen_op_mov_TN_reg(ot
, 1, rm
);
4352 gen_op_addl_T0_T1();
4353 gen_op_mov_reg_T1(ot
, reg
);
4354 gen_op_mov_reg_T0(ot
, rm
);
4356 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4357 gen_op_mov_TN_reg(ot
, 0, reg
);
4358 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4359 gen_op_addl_T0_T1();
4360 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4361 gen_op_mov_reg_T1(ot
, reg
);
4363 gen_op_update2_cc();
4364 s
->cc_op
= CC_OP_ADDB
+ ot
;
4367 case 0x1b1: /* cmpxchg Ev, Gv */
4370 TCGv t0
, t1
, t2
, a0
;
4375 ot
= dflag
+ OT_WORD
;
4376 modrm
= ldub_code(s
->pc
++);
4377 reg
= ((modrm
>> 3) & 7) | rex_r
;
4378 mod
= (modrm
>> 6) & 3;
4379 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
4380 t1
= tcg_temp_local_new(TCG_TYPE_TL
);
4381 t2
= tcg_temp_local_new(TCG_TYPE_TL
);
4382 a0
= tcg_temp_local_new(TCG_TYPE_TL
);
4383 gen_op_mov_v_reg(ot
, t1
, reg
);
4385 rm
= (modrm
& 7) | REX_B(s
);
4386 gen_op_mov_v_reg(ot
, t0
, rm
);
4388 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4389 tcg_gen_mov_tl(a0
, cpu_A0
);
4390 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
4391 rm
= 0; /* avoid warning */
4393 label1
= gen_new_label();
4394 tcg_gen_ld_tl(t2
, cpu_env
, offsetof(CPUState
, regs
[R_EAX
]));
4395 tcg_gen_sub_tl(t2
, t2
, t0
);
4397 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
4399 label2
= gen_new_label();
4400 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4402 gen_set_label(label1
);
4403 gen_op_mov_reg_v(ot
, rm
, t1
);
4404 gen_set_label(label2
);
4406 tcg_gen_mov_tl(t1
, t0
);
4407 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
4408 gen_set_label(label1
);
4410 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
4412 tcg_gen_mov_tl(cpu_cc_src
, t0
);
4413 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
4414 s
->cc_op
= CC_OP_SUBB
+ ot
;
4421 case 0x1c7: /* cmpxchg8b */
4422 modrm
= ldub_code(s
->pc
++);
4423 mod
= (modrm
>> 6) & 3;
4424 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
4426 #ifdef TARGET_X86_64
4428 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
4430 gen_jmp_im(pc_start
- s
->cs_base
);
4431 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4432 gen_op_set_cc_op(s
->cc_op
);
4433 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4434 tcg_gen_helper_0_1(helper_cmpxchg16b
, cpu_A0
);
4438 if (!(s
->cpuid_features
& CPUID_CX8
))
4440 gen_jmp_im(pc_start
- s
->cs_base
);
4441 if (s
->cc_op
!= CC_OP_DYNAMIC
)
4442 gen_op_set_cc_op(s
->cc_op
);
4443 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4444 tcg_gen_helper_0_1(helper_cmpxchg8b
, cpu_A0
);
4446 s
->cc_op
= CC_OP_EFLAGS
;
4449 /**************************/
4451 case 0x50 ... 0x57: /* push */
4452 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
4455 case 0x58 ... 0x5f: /* pop */
4457 ot
= dflag
? OT_QUAD
: OT_WORD
;
4459 ot
= dflag
+ OT_WORD
;
4462 /* NOTE: order is important for pop %sp */
4464 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
4466 case 0x60: /* pusha */
4471 case 0x61: /* popa */
4476 case 0x68: /* push Iv */
4479 ot
= dflag
? OT_QUAD
: OT_WORD
;
4481 ot
= dflag
+ OT_WORD
;
4484 val
= insn_get(s
, ot
);
4486 val
= (int8_t)insn_get(s
, OT_BYTE
);
4487 gen_op_movl_T0_im(val
);
4490 case 0x8f: /* pop Ev */
4492 ot
= dflag
? OT_QUAD
: OT_WORD
;
4494 ot
= dflag
+ OT_WORD
;
4496 modrm
= ldub_code(s
->pc
++);
4497 mod
= (modrm
>> 6) & 3;
4500 /* NOTE: order is important for pop %sp */
4502 rm
= (modrm
& 7) | REX_B(s
);
4503 gen_op_mov_reg_T0(ot
, rm
);
4505 /* NOTE: order is important too for MMU exceptions */
4506 s
->popl_esp_hack
= 1 << ot
;
4507 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
4508 s
->popl_esp_hack
= 0;
4512 case 0xc8: /* enter */
4515 val
= lduw_code(s
->pc
);
4517 level
= ldub_code(s
->pc
++);
4518 gen_enter(s
, val
, level
);
4521 case 0xc9: /* leave */
4522 /* XXX: exception not precise (ESP is updated before potential exception) */
4524 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
4525 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
4526 } else if (s
->ss32
) {
4527 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
4528 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
4530 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
4531 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
4535 ot
= dflag
? OT_QUAD
: OT_WORD
;
4537 ot
= dflag
+ OT_WORD
;
4539 gen_op_mov_reg_T0(ot
, R_EBP
);
4542 case 0x06: /* push es */
4543 case 0x0e: /* push cs */
4544 case 0x16: /* push ss */
4545 case 0x1e: /* push ds */
4548 gen_op_movl_T0_seg(b
>> 3);
4551 case 0x1a0: /* push fs */
4552 case 0x1a8: /* push gs */
4553 gen_op_movl_T0_seg((b
>> 3) & 7);
4556 case 0x07: /* pop es */
4557 case 0x17: /* pop ss */
4558 case 0x1f: /* pop ds */
4563 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
4566 /* if reg == SS, inhibit interrupts/trace. */
4567 /* If several instructions disable interrupts, only the
4569 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
4570 tcg_gen_helper_0_0(helper_set_inhibit_irq
);
4574 gen_jmp_im(s
->pc
- s
->cs_base
);
4578 case 0x1a1: /* pop fs */
4579 case 0x1a9: /* pop gs */
4581 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
4584 gen_jmp_im(s
->pc
- s
->cs_base
);
4589 /**************************/
4592 case 0x89: /* mov Gv, Ev */
4596 ot
= dflag
+ OT_WORD
;
4597 modrm
= ldub_code(s
->pc
++);
4598 reg
= ((modrm
>> 3) & 7) | rex_r
;
4600 /* generate a generic store */
4601 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
4604 case 0xc7: /* mov Ev, Iv */
4608 ot
= dflag
+ OT_WORD
;
4609 modrm
= ldub_code(s
->pc
++);
4610 mod
= (modrm
>> 6) & 3;
4612 s
->rip_offset
= insn_const_size(ot
);
4613 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4615 val
= insn_get(s
, ot
);
4616 gen_op_movl_T0_im(val
);
4618 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4620 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
4623 case 0x8b: /* mov Ev, Gv */
4627 ot
= OT_WORD
+ dflag
;
4628 modrm
= ldub_code(s
->pc
++);
4629 reg
= ((modrm
>> 3) & 7) | rex_r
;
4631 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
4632 gen_op_mov_reg_T0(ot
, reg
);
4634 case 0x8e: /* mov seg, Gv */
4635 modrm
= ldub_code(s
->pc
++);
4636 reg
= (modrm
>> 3) & 7;
4637 if (reg
>= 6 || reg
== R_CS
)
4639 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
4640 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
4642 /* if reg == SS, inhibit interrupts/trace */
4643 /* If several instructions disable interrupts, only the
4645 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
4646 tcg_gen_helper_0_0(helper_set_inhibit_irq
);
4650 gen_jmp_im(s
->pc
- s
->cs_base
);
4654 case 0x8c: /* mov Gv, seg */
4655 modrm
= ldub_code(s
->pc
++);
4656 reg
= (modrm
>> 3) & 7;
4657 mod
= (modrm
>> 6) & 3;
4660 gen_op_movl_T0_seg(reg
);
4662 ot
= OT_WORD
+ dflag
;
4665 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
4668 case 0x1b6: /* movzbS Gv, Eb */
4669 case 0x1b7: /* movzwS Gv, Eb */
4670 case 0x1be: /* movsbS Gv, Eb */
4671 case 0x1bf: /* movswS Gv, Eb */
4674 /* d_ot is the size of destination */
4675 d_ot
= dflag
+ OT_WORD
;
4676 /* ot is the size of source */
4677 ot
= (b
& 1) + OT_BYTE
;
4678 modrm
= ldub_code(s
->pc
++);
4679 reg
= ((modrm
>> 3) & 7) | rex_r
;
4680 mod
= (modrm
>> 6) & 3;
4681 rm
= (modrm
& 7) | REX_B(s
);
4684 gen_op_mov_TN_reg(ot
, 0, rm
);
4685 switch(ot
| (b
& 8)) {
4687 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4690 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4693 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4697 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4700 gen_op_mov_reg_T0(d_ot
, reg
);
4702 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4704 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
4706 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
4708 gen_op_mov_reg_T0(d_ot
, reg
);
4713 case 0x8d: /* lea */
4714 ot
= dflag
+ OT_WORD
;
4715 modrm
= ldub_code(s
->pc
++);
4716 mod
= (modrm
>> 6) & 3;
4719 reg
= ((modrm
>> 3) & 7) | rex_r
;
4720 /* we must ensure that no segment is added */
4724 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4726 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
4729 case 0xa0: /* mov EAX, Ov */
4731 case 0xa2: /* mov Ov, EAX */
4734 target_ulong offset_addr
;
4739 ot
= dflag
+ OT_WORD
;
4740 #ifdef TARGET_X86_64
4741 if (s
->aflag
== 2) {
4742 offset_addr
= ldq_code(s
->pc
);
4744 gen_op_movq_A0_im(offset_addr
);
4749 offset_addr
= insn_get(s
, OT_LONG
);
4751 offset_addr
= insn_get(s
, OT_WORD
);
4753 gen_op_movl_A0_im(offset_addr
);
4755 gen_add_A0_ds_seg(s
);
4757 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4758 gen_op_mov_reg_T0(ot
, R_EAX
);
4760 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
4761 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4765 case 0xd7: /* xlat */
4766 #ifdef TARGET_X86_64
4767 if (s
->aflag
== 2) {
4768 gen_op_movq_A0_reg(R_EBX
);
4769 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4770 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
4771 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
4775 gen_op_movl_A0_reg(R_EBX
);
4776 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4777 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
4778 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
4780 gen_op_andl_A0_ffff();
4782 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
4784 gen_add_A0_ds_seg(s
);
4785 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
4786 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
4788 case 0xb0 ... 0xb7: /* mov R, Ib */
4789 val
= insn_get(s
, OT_BYTE
);
4790 gen_op_movl_T0_im(val
);
4791 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
4793 case 0xb8 ... 0xbf: /* mov R, Iv */
4794 #ifdef TARGET_X86_64
4798 tmp
= ldq_code(s
->pc
);
4800 reg
= (b
& 7) | REX_B(s
);
4801 gen_movtl_T0_im(tmp
);
4802 gen_op_mov_reg_T0(OT_QUAD
, reg
);
4806 ot
= dflag
? OT_LONG
: OT_WORD
;
4807 val
= insn_get(s
, ot
);
4808 reg
= (b
& 7) | REX_B(s
);
4809 gen_op_movl_T0_im(val
);
4810 gen_op_mov_reg_T0(ot
, reg
);
4814 case 0x91 ... 0x97: /* xchg R, EAX */
4815 ot
= dflag
+ OT_WORD
;
4816 reg
= (b
& 7) | REX_B(s
);
4820 case 0x87: /* xchg Ev, Gv */
4824 ot
= dflag
+ OT_WORD
;
4825 modrm
= ldub_code(s
->pc
++);
4826 reg
= ((modrm
>> 3) & 7) | rex_r
;
4827 mod
= (modrm
>> 6) & 3;
4829 rm
= (modrm
& 7) | REX_B(s
);
4831 gen_op_mov_TN_reg(ot
, 0, reg
);
4832 gen_op_mov_TN_reg(ot
, 1, rm
);
4833 gen_op_mov_reg_T0(ot
, rm
);
4834 gen_op_mov_reg_T1(ot
, reg
);
4836 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4837 gen_op_mov_TN_reg(ot
, 0, reg
);
4838 /* for xchg, lock is implicit */
4839 if (!(prefixes
& PREFIX_LOCK
))
4840 tcg_gen_helper_0_0(helper_lock
);
4841 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4842 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4843 if (!(prefixes
& PREFIX_LOCK
))
4844 tcg_gen_helper_0_0(helper_unlock
);
4845 gen_op_mov_reg_T1(ot
, reg
);
4848 case 0xc4: /* les Gv */
4853 case 0xc5: /* lds Gv */
4858 case 0x1b2: /* lss Gv */
4861 case 0x1b4: /* lfs Gv */
4864 case 0x1b5: /* lgs Gv */
4867 ot
= dflag
? OT_LONG
: OT_WORD
;
4868 modrm
= ldub_code(s
->pc
++);
4869 reg
= ((modrm
>> 3) & 7) | rex_r
;
4870 mod
= (modrm
>> 6) & 3;
4873 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4874 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4875 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4876 /* load the segment first to handle exceptions properly */
4877 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4878 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
4879 /* then put the data */
4880 gen_op_mov_reg_T1(ot
, reg
);
4882 gen_jmp_im(s
->pc
- s
->cs_base
);
4887 /************************/
4898 ot
= dflag
+ OT_WORD
;
4900 modrm
= ldub_code(s
->pc
++);
4901 mod
= (modrm
>> 6) & 3;
4902 op
= (modrm
>> 3) & 7;
4908 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4911 opreg
= (modrm
& 7) | REX_B(s
);
4916 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
4919 shift
= ldub_code(s
->pc
++);
4921 gen_shifti(s
, op
, ot
, opreg
, shift
);
4936 case 0x1a4: /* shld imm */
4940 case 0x1a5: /* shld cl */
4944 case 0x1ac: /* shrd imm */
4948 case 0x1ad: /* shrd cl */
4952 ot
= dflag
+ OT_WORD
;
4953 modrm
= ldub_code(s
->pc
++);
4954 mod
= (modrm
>> 6) & 3;
4955 rm
= (modrm
& 7) | REX_B(s
);
4956 reg
= ((modrm
>> 3) & 7) | rex_r
;
4958 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4963 gen_op_mov_TN_reg(ot
, 1, reg
);
4966 val
= ldub_code(s
->pc
++);
4967 tcg_gen_movi_tl(cpu_T3
, val
);
4969 tcg_gen_ld_tl(cpu_T3
, cpu_env
, offsetof(CPUState
, regs
[R_ECX
]));
4971 gen_shiftd_rm_T1_T3(s
, ot
, opreg
, op
);
4974 /************************/
4977 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
4978 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
4979 /* XXX: what to do if illegal op ? */
4980 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
4983 modrm
= ldub_code(s
->pc
++);
4984 mod
= (modrm
>> 6) & 3;
4986 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
4989 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
4991 case 0x00 ... 0x07: /* fxxxs */
4992 case 0x10 ... 0x17: /* fixxxl */
4993 case 0x20 ... 0x27: /* fxxxl */
4994 case 0x30 ... 0x37: /* fixxx */
5001 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5002 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5003 tcg_gen_helper_0_1(helper_flds_FT0
, cpu_tmp2_i32
);
5006 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5007 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5008 tcg_gen_helper_0_1(helper_fildl_FT0
, cpu_tmp2_i32
);
5011 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5012 (s
->mem_index
>> 2) - 1);
5013 tcg_gen_helper_0_1(helper_fldl_FT0
, cpu_tmp1_i64
);
5017 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5018 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5019 tcg_gen_helper_0_1(helper_fildl_FT0
, cpu_tmp2_i32
);
5023 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0
[op1
]);
5025 /* fcomp needs pop */
5026 tcg_gen_helper_0_0(helper_fpop
);
5030 case 0x08: /* flds */
5031 case 0x0a: /* fsts */
5032 case 0x0b: /* fstps */
5033 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5034 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5035 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5040 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5041 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5042 tcg_gen_helper_0_1(helper_flds_ST0
, cpu_tmp2_i32
);
5045 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5046 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5047 tcg_gen_helper_0_1(helper_fildl_ST0
, cpu_tmp2_i32
);
5050 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5051 (s
->mem_index
>> 2) - 1);
5052 tcg_gen_helper_0_1(helper_fldl_ST0
, cpu_tmp1_i64
);
5056 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5057 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5058 tcg_gen_helper_0_1(helper_fildl_ST0
, cpu_tmp2_i32
);
5063 /* XXX: the corresponding CPUID bit must be tested ! */
5066 tcg_gen_helper_1_0(helper_fisttl_ST0
, cpu_tmp2_i32
);
5067 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5068 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5071 tcg_gen_helper_1_0(helper_fisttll_ST0
, cpu_tmp1_i64
);
5072 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5073 (s
->mem_index
>> 2) - 1);
5077 tcg_gen_helper_1_0(helper_fistt_ST0
, cpu_tmp2_i32
);
5078 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5079 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5082 tcg_gen_helper_0_0(helper_fpop
);
5087 tcg_gen_helper_1_0(helper_fsts_ST0
, cpu_tmp2_i32
);
5088 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5089 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5092 tcg_gen_helper_1_0(helper_fistl_ST0
, cpu_tmp2_i32
);
5093 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5094 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5097 tcg_gen_helper_1_0(helper_fstl_ST0
, cpu_tmp1_i64
);
5098 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5099 (s
->mem_index
>> 2) - 1);
5103 tcg_gen_helper_1_0(helper_fist_ST0
, cpu_tmp2_i32
);
5104 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5105 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5109 tcg_gen_helper_0_0(helper_fpop
);
5113 case 0x0c: /* fldenv mem */
5114 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5115 gen_op_set_cc_op(s
->cc_op
);
5116 gen_jmp_im(pc_start
- s
->cs_base
);
5117 tcg_gen_helper_0_2(helper_fldenv
,
5118 cpu_A0
, tcg_const_i32(s
->dflag
));
5120 case 0x0d: /* fldcw mem */
5121 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5122 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5123 tcg_gen_helper_0_1(helper_fldcw
, cpu_tmp2_i32
);
5125 case 0x0e: /* fnstenv mem */
5126 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5127 gen_op_set_cc_op(s
->cc_op
);
5128 gen_jmp_im(pc_start
- s
->cs_base
);
5129 tcg_gen_helper_0_2(helper_fstenv
,
5130 cpu_A0
, tcg_const_i32(s
->dflag
));
5132 case 0x0f: /* fnstcw mem */
5133 tcg_gen_helper_1_0(helper_fnstcw
, cpu_tmp2_i32
);
5134 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5135 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5137 case 0x1d: /* fldt mem */
5138 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5139 gen_op_set_cc_op(s
->cc_op
);
5140 gen_jmp_im(pc_start
- s
->cs_base
);
5141 tcg_gen_helper_0_1(helper_fldt_ST0
, cpu_A0
);
5143 case 0x1f: /* fstpt mem */
5144 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5145 gen_op_set_cc_op(s
->cc_op
);
5146 gen_jmp_im(pc_start
- s
->cs_base
);
5147 tcg_gen_helper_0_1(helper_fstt_ST0
, cpu_A0
);
5148 tcg_gen_helper_0_0(helper_fpop
);
5150 case 0x2c: /* frstor mem */
5151 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5152 gen_op_set_cc_op(s
->cc_op
);
5153 gen_jmp_im(pc_start
- s
->cs_base
);
5154 tcg_gen_helper_0_2(helper_frstor
,
5155 cpu_A0
, tcg_const_i32(s
->dflag
));
5157 case 0x2e: /* fnsave mem */
5158 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5159 gen_op_set_cc_op(s
->cc_op
);
5160 gen_jmp_im(pc_start
- s
->cs_base
);
5161 tcg_gen_helper_0_2(helper_fsave
,
5162 cpu_A0
, tcg_const_i32(s
->dflag
));
5164 case 0x2f: /* fnstsw mem */
5165 tcg_gen_helper_1_0(helper_fnstsw
, cpu_tmp2_i32
);
5166 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5167 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5169 case 0x3c: /* fbld */
5170 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5171 gen_op_set_cc_op(s
->cc_op
);
5172 gen_jmp_im(pc_start
- s
->cs_base
);
5173 tcg_gen_helper_0_1(helper_fbld_ST0
, cpu_A0
);
5175 case 0x3e: /* fbstp */
5176 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5177 gen_op_set_cc_op(s
->cc_op
);
5178 gen_jmp_im(pc_start
- s
->cs_base
);
5179 tcg_gen_helper_0_1(helper_fbst_ST0
, cpu_A0
);
5180 tcg_gen_helper_0_0(helper_fpop
);
5182 case 0x3d: /* fildll */
5183 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5184 (s
->mem_index
>> 2) - 1);
5185 tcg_gen_helper_0_1(helper_fildll_ST0
, cpu_tmp1_i64
);
5187 case 0x3f: /* fistpll */
5188 tcg_gen_helper_1_0(helper_fistll_ST0
, cpu_tmp1_i64
);
5189 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5190 (s
->mem_index
>> 2) - 1);
5191 tcg_gen_helper_0_0(helper_fpop
);
5197 /* register float ops */
5201 case 0x08: /* fld sti */
5202 tcg_gen_helper_0_0(helper_fpush
);
5203 tcg_gen_helper_0_1(helper_fmov_ST0_STN
, tcg_const_i32((opreg
+ 1) & 7));
5205 case 0x09: /* fxchg sti */
5206 case 0x29: /* fxchg4 sti, undocumented op */
5207 case 0x39: /* fxchg7 sti, undocumented op */
5208 tcg_gen_helper_0_1(helper_fxchg_ST0_STN
, tcg_const_i32(opreg
));
5210 case 0x0a: /* grp d9/2 */
5213 /* check exceptions (FreeBSD FPU probe) */
5214 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5215 gen_op_set_cc_op(s
->cc_op
);
5216 gen_jmp_im(pc_start
- s
->cs_base
);
5217 tcg_gen_helper_0_0(helper_fwait
);
5223 case 0x0c: /* grp d9/4 */
5226 tcg_gen_helper_0_0(helper_fchs_ST0
);
5229 tcg_gen_helper_0_0(helper_fabs_ST0
);
5232 tcg_gen_helper_0_0(helper_fldz_FT0
);
5233 tcg_gen_helper_0_0(helper_fcom_ST0_FT0
);
5236 tcg_gen_helper_0_0(helper_fxam_ST0
);
5242 case 0x0d: /* grp d9/5 */
5246 tcg_gen_helper_0_0(helper_fpush
);
5247 tcg_gen_helper_0_0(helper_fld1_ST0
);
5250 tcg_gen_helper_0_0(helper_fpush
);
5251 tcg_gen_helper_0_0(helper_fldl2t_ST0
);
5254 tcg_gen_helper_0_0(helper_fpush
);
5255 tcg_gen_helper_0_0(helper_fldl2e_ST0
);
5258 tcg_gen_helper_0_0(helper_fpush
);
5259 tcg_gen_helper_0_0(helper_fldpi_ST0
);
5262 tcg_gen_helper_0_0(helper_fpush
);
5263 tcg_gen_helper_0_0(helper_fldlg2_ST0
);
5266 tcg_gen_helper_0_0(helper_fpush
);
5267 tcg_gen_helper_0_0(helper_fldln2_ST0
);
5270 tcg_gen_helper_0_0(helper_fpush
);
5271 tcg_gen_helper_0_0(helper_fldz_ST0
);
5278 case 0x0e: /* grp d9/6 */
5281 tcg_gen_helper_0_0(helper_f2xm1
);
5284 tcg_gen_helper_0_0(helper_fyl2x
);
5287 tcg_gen_helper_0_0(helper_fptan
);
5289 case 3: /* fpatan */
5290 tcg_gen_helper_0_0(helper_fpatan
);
5292 case 4: /* fxtract */
5293 tcg_gen_helper_0_0(helper_fxtract
);
5295 case 5: /* fprem1 */
5296 tcg_gen_helper_0_0(helper_fprem1
);
5298 case 6: /* fdecstp */
5299 tcg_gen_helper_0_0(helper_fdecstp
);
5302 case 7: /* fincstp */
5303 tcg_gen_helper_0_0(helper_fincstp
);
5307 case 0x0f: /* grp d9/7 */
5310 tcg_gen_helper_0_0(helper_fprem
);
5312 case 1: /* fyl2xp1 */
5313 tcg_gen_helper_0_0(helper_fyl2xp1
);
5316 tcg_gen_helper_0_0(helper_fsqrt
);
5318 case 3: /* fsincos */
5319 tcg_gen_helper_0_0(helper_fsincos
);
5321 case 5: /* fscale */
5322 tcg_gen_helper_0_0(helper_fscale
);
5324 case 4: /* frndint */
5325 tcg_gen_helper_0_0(helper_frndint
);
5328 tcg_gen_helper_0_0(helper_fsin
);
5332 tcg_gen_helper_0_0(helper_fcos
);
5336 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5337 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5338 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5344 tcg_gen_helper_0_1(helper_fp_arith_STN_ST0
[op1
], tcg_const_i32(opreg
));
5346 tcg_gen_helper_0_0(helper_fpop
);
5348 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5349 tcg_gen_helper_0_0(helper_fp_arith_ST0_FT0
[op1
]);
5353 case 0x02: /* fcom */
5354 case 0x22: /* fcom2, undocumented op */
5355 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5356 tcg_gen_helper_0_0(helper_fcom_ST0_FT0
);
5358 case 0x03: /* fcomp */
5359 case 0x23: /* fcomp3, undocumented op */
5360 case 0x32: /* fcomp5, undocumented op */
5361 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5362 tcg_gen_helper_0_0(helper_fcom_ST0_FT0
);
5363 tcg_gen_helper_0_0(helper_fpop
);
5365 case 0x15: /* da/5 */
5367 case 1: /* fucompp */
5368 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(1));
5369 tcg_gen_helper_0_0(helper_fucom_ST0_FT0
);
5370 tcg_gen_helper_0_0(helper_fpop
);
5371 tcg_gen_helper_0_0(helper_fpop
);
5379 case 0: /* feni (287 only, just do nop here) */
5381 case 1: /* fdisi (287 only, just do nop here) */
5384 tcg_gen_helper_0_0(helper_fclex
);
5386 case 3: /* fninit */
5387 tcg_gen_helper_0_0(helper_fninit
);
5389 case 4: /* fsetpm (287 only, just do nop here) */
5395 case 0x1d: /* fucomi */
5396 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5397 gen_op_set_cc_op(s
->cc_op
);
5398 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5399 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0
);
5400 s
->cc_op
= CC_OP_EFLAGS
;
5402 case 0x1e: /* fcomi */
5403 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5404 gen_op_set_cc_op(s
->cc_op
);
5405 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5406 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0
);
5407 s
->cc_op
= CC_OP_EFLAGS
;
5409 case 0x28: /* ffree sti */
5410 tcg_gen_helper_0_1(helper_ffree_STN
, tcg_const_i32(opreg
));
5412 case 0x2a: /* fst sti */
5413 tcg_gen_helper_0_1(helper_fmov_STN_ST0
, tcg_const_i32(opreg
));
5415 case 0x2b: /* fstp sti */
5416 case 0x0b: /* fstp1 sti, undocumented op */
5417 case 0x3a: /* fstp8 sti, undocumented op */
5418 case 0x3b: /* fstp9 sti, undocumented op */
5419 tcg_gen_helper_0_1(helper_fmov_STN_ST0
, tcg_const_i32(opreg
));
5420 tcg_gen_helper_0_0(helper_fpop
);
5422 case 0x2c: /* fucom st(i) */
5423 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5424 tcg_gen_helper_0_0(helper_fucom_ST0_FT0
);
5426 case 0x2d: /* fucomp st(i) */
5427 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5428 tcg_gen_helper_0_0(helper_fucom_ST0_FT0
);
5429 tcg_gen_helper_0_0(helper_fpop
);
5431 case 0x33: /* de/3 */
5433 case 1: /* fcompp */
5434 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(1));
5435 tcg_gen_helper_0_0(helper_fcom_ST0_FT0
);
5436 tcg_gen_helper_0_0(helper_fpop
);
5437 tcg_gen_helper_0_0(helper_fpop
);
5443 case 0x38: /* ffreep sti, undocumented op */
5444 tcg_gen_helper_0_1(helper_ffree_STN
, tcg_const_i32(opreg
));
5445 tcg_gen_helper_0_0(helper_fpop
);
5447 case 0x3c: /* df/4 */
5450 tcg_gen_helper_1_0(helper_fnstsw
, cpu_tmp2_i32
);
5451 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5452 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
5458 case 0x3d: /* fucomip */
5459 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5460 gen_op_set_cc_op(s
->cc_op
);
5461 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5462 tcg_gen_helper_0_0(helper_fucomi_ST0_FT0
);
5463 tcg_gen_helper_0_0(helper_fpop
);
5464 s
->cc_op
= CC_OP_EFLAGS
;
5466 case 0x3e: /* fcomip */
5467 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5468 gen_op_set_cc_op(s
->cc_op
);
5469 tcg_gen_helper_0_1(helper_fmov_FT0_STN
, tcg_const_i32(opreg
));
5470 tcg_gen_helper_0_0(helper_fcomi_ST0_FT0
);
5471 tcg_gen_helper_0_0(helper_fpop
);
5472 s
->cc_op
= CC_OP_EFLAGS
;
5474 case 0x10 ... 0x13: /* fcmovxx */
5478 static const uint8_t fcmov_cc
[8] = {
5484 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
5485 l1
= gen_new_label();
5486 gen_jcc1(s
, s
->cc_op
, op1
, l1
);
5487 tcg_gen_helper_0_1(helper_fmov_ST0_STN
, tcg_const_i32(opreg
));
5496 /************************/
5499 case 0xa4: /* movsS */
5504 ot
= dflag
+ OT_WORD
;
5506 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5507 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5513 case 0xaa: /* stosS */
5518 ot
= dflag
+ OT_WORD
;
5520 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5521 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5526 case 0xac: /* lodsS */
5531 ot
= dflag
+ OT_WORD
;
5532 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5533 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5538 case 0xae: /* scasS */
5543 ot
= dflag
+ OT_WORD
;
5544 if (prefixes
& PREFIX_REPNZ
) {
5545 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
5546 } else if (prefixes
& PREFIX_REPZ
) {
5547 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
5550 s
->cc_op
= CC_OP_SUBB
+ ot
;
5554 case 0xa6: /* cmpsS */
5559 ot
= dflag
+ OT_WORD
;
5560 if (prefixes
& PREFIX_REPNZ
) {
5561 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
5562 } else if (prefixes
& PREFIX_REPZ
) {
5563 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
5566 s
->cc_op
= CC_OP_SUBB
+ ot
;
5569 case 0x6c: /* insS */
5574 ot
= dflag
? OT_LONG
: OT_WORD
;
5575 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
5576 gen_op_andl_T0_ffff();
5577 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5578 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
5579 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5580 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5584 gen_jmp(s
, s
->pc
- s
->cs_base
);
5588 case 0x6e: /* outsS */
5593 ot
= dflag
? OT_LONG
: OT_WORD
;
5594 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
5595 gen_op_andl_T0_ffff();
5596 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5597 svm_is_rep(prefixes
) | 4);
5598 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
5599 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
5603 gen_jmp(s
, s
->pc
- s
->cs_base
);
5608 /************************/
5616 ot
= dflag
? OT_LONG
: OT_WORD
;
5617 val
= ldub_code(s
->pc
++);
5618 gen_op_movl_T0_im(val
);
5619 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5620 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
5623 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5624 tcg_gen_helper_1_1(helper_in_func
[ot
], cpu_T
[1], cpu_tmp2_i32
);
5625 gen_op_mov_reg_T1(ot
, R_EAX
);
5628 gen_jmp(s
, s
->pc
- s
->cs_base
);
5636 ot
= dflag
? OT_LONG
: OT_WORD
;
5637 val
= ldub_code(s
->pc
++);
5638 gen_op_movl_T0_im(val
);
5639 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5640 svm_is_rep(prefixes
));
5641 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
5645 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5646 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
5647 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5648 tcg_gen_helper_0_2(helper_out_func
[ot
], cpu_tmp2_i32
, cpu_tmp3_i32
);
5651 gen_jmp(s
, s
->pc
- s
->cs_base
);
5659 ot
= dflag
? OT_LONG
: OT_WORD
;
5660 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
5661 gen_op_andl_T0_ffff();
5662 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5663 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
5666 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5667 tcg_gen_helper_1_1(helper_in_func
[ot
], cpu_T
[1], cpu_tmp2_i32
);
5668 gen_op_mov_reg_T1(ot
, R_EAX
);
5671 gen_jmp(s
, s
->pc
- s
->cs_base
);
5679 ot
= dflag
? OT_LONG
: OT_WORD
;
5680 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
5681 gen_op_andl_T0_ffff();
5682 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
5683 svm_is_rep(prefixes
));
5684 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
5688 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5689 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
5690 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5691 tcg_gen_helper_0_2(helper_out_func
[ot
], cpu_tmp2_i32
, cpu_tmp3_i32
);
5694 gen_jmp(s
, s
->pc
- s
->cs_base
);
5698 /************************/
5700 case 0xc2: /* ret im */
5701 val
= ldsw_code(s
->pc
);
5704 if (CODE64(s
) && s
->dflag
)
5706 gen_stack_update(s
, val
+ (2 << s
->dflag
));
5708 gen_op_andl_T0_ffff();
5712 case 0xc3: /* ret */
5716 gen_op_andl_T0_ffff();
5720 case 0xca: /* lret im */
5721 val
= ldsw_code(s
->pc
);
5724 if (s
->pe
&& !s
->vm86
) {
5725 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5726 gen_op_set_cc_op(s
->cc_op
);
5727 gen_jmp_im(pc_start
- s
->cs_base
);
5728 tcg_gen_helper_0_2(helper_lret_protected
,
5729 tcg_const_i32(s
->dflag
),
5730 tcg_const_i32(val
));
5734 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
5736 gen_op_andl_T0_ffff();
5737 /* NOTE: keeping EIP updated is not a problem in case of
5741 gen_op_addl_A0_im(2 << s
->dflag
);
5742 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
5743 gen_op_movl_seg_T0_vm(R_CS
);
5744 /* add stack offset */
5745 gen_stack_update(s
, val
+ (4 << s
->dflag
));
5749 case 0xcb: /* lret */
5752 case 0xcf: /* iret */
5753 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
5756 tcg_gen_helper_0_1(helper_iret_real
, tcg_const_i32(s
->dflag
));
5757 s
->cc_op
= CC_OP_EFLAGS
;
5758 } else if (s
->vm86
) {
5760 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
5762 tcg_gen_helper_0_1(helper_iret_real
, tcg_const_i32(s
->dflag
));
5763 s
->cc_op
= CC_OP_EFLAGS
;
5766 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5767 gen_op_set_cc_op(s
->cc_op
);
5768 gen_jmp_im(pc_start
- s
->cs_base
);
5769 tcg_gen_helper_0_2(helper_iret_protected
,
5770 tcg_const_i32(s
->dflag
),
5771 tcg_const_i32(s
->pc
- s
->cs_base
));
5772 s
->cc_op
= CC_OP_EFLAGS
;
5776 case 0xe8: /* call im */
5779 tval
= (int32_t)insn_get(s
, OT_LONG
);
5781 tval
= (int16_t)insn_get(s
, OT_WORD
);
5782 next_eip
= s
->pc
- s
->cs_base
;
5786 gen_movtl_T0_im(next_eip
);
5791 case 0x9a: /* lcall im */
5793 unsigned int selector
, offset
;
5797 ot
= dflag
? OT_LONG
: OT_WORD
;
5798 offset
= insn_get(s
, ot
);
5799 selector
= insn_get(s
, OT_WORD
);
5801 gen_op_movl_T0_im(selector
);
5802 gen_op_movl_T1_imu(offset
);
5805 case 0xe9: /* jmp im */
5807 tval
= (int32_t)insn_get(s
, OT_LONG
);
5809 tval
= (int16_t)insn_get(s
, OT_WORD
);
5810 tval
+= s
->pc
- s
->cs_base
;
5815 case 0xea: /* ljmp im */
5817 unsigned int selector
, offset
;
5821 ot
= dflag
? OT_LONG
: OT_WORD
;
5822 offset
= insn_get(s
, ot
);
5823 selector
= insn_get(s
, OT_WORD
);
5825 gen_op_movl_T0_im(selector
);
5826 gen_op_movl_T1_imu(offset
);
5829 case 0xeb: /* jmp Jb */
5830 tval
= (int8_t)insn_get(s
, OT_BYTE
);
5831 tval
+= s
->pc
- s
->cs_base
;
5836 case 0x70 ... 0x7f: /* jcc Jb */
5837 tval
= (int8_t)insn_get(s
, OT_BYTE
);
5839 case 0x180 ... 0x18f: /* jcc Jv */
5841 tval
= (int32_t)insn_get(s
, OT_LONG
);
5843 tval
= (int16_t)insn_get(s
, OT_WORD
);
5846 next_eip
= s
->pc
- s
->cs_base
;
5850 gen_jcc(s
, b
, tval
, next_eip
);
5853 case 0x190 ... 0x19f: /* setcc Gv */
5854 modrm
= ldub_code(s
->pc
++);
5856 gen_ldst_modrm(s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
5858 case 0x140 ... 0x14f: /* cmov Gv, Ev */
5863 ot
= dflag
+ OT_WORD
;
5864 modrm
= ldub_code(s
->pc
++);
5865 reg
= ((modrm
>> 3) & 7) | rex_r
;
5866 mod
= (modrm
>> 6) & 3;
5867 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
5869 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
5870 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
5872 rm
= (modrm
& 7) | REX_B(s
);
5873 gen_op_mov_v_reg(ot
, t0
, rm
);
5875 #ifdef TARGET_X86_64
5876 if (ot
== OT_LONG
) {
5877 /* XXX: specific Intel behaviour ? */
5878 l1
= gen_new_label();
5879 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
5880 tcg_gen_st32_tl(t0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_L_OFFSET
);
5882 tcg_gen_movi_tl(cpu_tmp0
, 0);
5883 tcg_gen_st32_tl(cpu_tmp0
, cpu_env
, offsetof(CPUState
, regs
[reg
]) + REG_LH_OFFSET
);
5887 l1
= gen_new_label();
5888 gen_jcc1(s
, s
->cc_op
, b
^ 1, l1
);
5889 gen_op_mov_reg_v(ot
, reg
, t0
);
5896 /************************/
5898 case 0x9c: /* pushf */
5899 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
5900 if (s
->vm86
&& s
->iopl
!= 3) {
5901 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
5903 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5904 gen_op_set_cc_op(s
->cc_op
);
5905 tcg_gen_helper_1_0(helper_read_eflags
, cpu_T
[0]);
5909 case 0x9d: /* popf */
5910 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
5911 if (s
->vm86
&& s
->iopl
!= 3) {
5912 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
5917 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5918 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
)));
5920 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5921 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
| IOPL_MASK
) & 0xffff));
5924 if (s
->cpl
<= s
->iopl
) {
5926 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5927 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
)));
5929 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5930 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
| IF_MASK
) & 0xffff));
5934 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5935 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
)));
5937 tcg_gen_helper_0_2(helper_write_eflags
, cpu_T
[0],
5938 tcg_const_i32((TF_MASK
| AC_MASK
| ID_MASK
| NT_MASK
) & 0xffff));
5943 s
->cc_op
= CC_OP_EFLAGS
;
5944 /* abort translation because TF flag may change */
5945 gen_jmp_im(s
->pc
- s
->cs_base
);
5949 case 0x9e: /* sahf */
5950 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
5952 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
5953 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5954 gen_op_set_cc_op(s
->cc_op
);
5955 gen_compute_eflags(cpu_cc_src
);
5956 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
5957 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
5958 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
5959 s
->cc_op
= CC_OP_EFLAGS
;
5961 case 0x9f: /* lahf */
5962 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
5964 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5965 gen_op_set_cc_op(s
->cc_op
);
5966 gen_compute_eflags(cpu_T
[0]);
5967 /* Note: gen_compute_eflags() only gives the condition codes */
5968 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], 0x02);
5969 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
5971 case 0xf5: /* cmc */
5972 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5973 gen_op_set_cc_op(s
->cc_op
);
5974 gen_compute_eflags(cpu_cc_src
);
5975 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
5976 s
->cc_op
= CC_OP_EFLAGS
;
5978 case 0xf8: /* clc */
5979 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5980 gen_op_set_cc_op(s
->cc_op
);
5981 gen_compute_eflags(cpu_cc_src
);
5982 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
5983 s
->cc_op
= CC_OP_EFLAGS
;
5985 case 0xf9: /* stc */
5986 if (s
->cc_op
!= CC_OP_DYNAMIC
)
5987 gen_op_set_cc_op(s
->cc_op
);
5988 gen_compute_eflags(cpu_cc_src
);
5989 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
5990 s
->cc_op
= CC_OP_EFLAGS
;
5992 case 0xfc: /* cld */
5993 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
5994 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
5996 case 0xfd: /* std */
5997 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
5998 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUState
, df
));
6001 /************************/
6002 /* bit operations */
6003 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6004 ot
= dflag
+ OT_WORD
;
6005 modrm
= ldub_code(s
->pc
++);
6006 op
= (modrm
>> 3) & 7;
6007 mod
= (modrm
>> 6) & 3;
6008 rm
= (modrm
& 7) | REX_B(s
);
6011 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6012 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6014 gen_op_mov_TN_reg(ot
, 0, rm
);
6017 val
= ldub_code(s
->pc
++);
6018 gen_op_movl_T1_im(val
);
6023 case 0x1a3: /* bt Gv, Ev */
6026 case 0x1ab: /* bts */
6029 case 0x1b3: /* btr */
6032 case 0x1bb: /* btc */
6035 ot
= dflag
+ OT_WORD
;
6036 modrm
= ldub_code(s
->pc
++);
6037 reg
= ((modrm
>> 3) & 7) | rex_r
;
6038 mod
= (modrm
>> 6) & 3;
6039 rm
= (modrm
& 7) | REX_B(s
);
6040 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6042 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6043 /* specific case: we need to add a displacement */
6044 gen_exts(ot
, cpu_T
[1]);
6045 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6046 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6047 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6048 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6050 gen_op_mov_TN_reg(ot
, 0, rm
);
6053 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6056 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6057 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6060 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6061 tcg_gen_movi_tl(cpu_tmp0
, 1);
6062 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6063 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6066 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6067 tcg_gen_movi_tl(cpu_tmp0
, 1);
6068 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6069 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6070 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6074 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6075 tcg_gen_movi_tl(cpu_tmp0
, 1);
6076 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6077 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6080 s
->cc_op
= CC_OP_SARB
+ ot
;
6083 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6085 gen_op_mov_reg_T0(ot
, rm
);
6086 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6087 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6090 case 0x1bc: /* bsf */
6091 case 0x1bd: /* bsr */
6096 ot
= dflag
+ OT_WORD
;
6097 modrm
= ldub_code(s
->pc
++);
6098 reg
= ((modrm
>> 3) & 7) | rex_r
;
6099 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 0);
6100 gen_extu(ot
, cpu_T
[0]);
6101 label1
= gen_new_label();
6102 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6103 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6104 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6105 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6107 tcg_gen_helper_1_1(helper_bsr
, cpu_T
[0], t0
);
6109 tcg_gen_helper_1_1(helper_bsf
, cpu_T
[0], t0
);
6111 gen_op_mov_reg_T0(ot
, reg
);
6112 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6113 gen_set_label(label1
);
6114 tcg_gen_discard_tl(cpu_cc_src
);
6115 s
->cc_op
= CC_OP_LOGICB
+ ot
;
6119 /************************/
6121 case 0x27: /* daa */
6124 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6125 gen_op_set_cc_op(s
->cc_op
);
6126 tcg_gen_helper_0_0(helper_daa
);
6127 s
->cc_op
= CC_OP_EFLAGS
;
6129 case 0x2f: /* das */
6132 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6133 gen_op_set_cc_op(s
->cc_op
);
6134 tcg_gen_helper_0_0(helper_das
);
6135 s
->cc_op
= CC_OP_EFLAGS
;
6137 case 0x37: /* aaa */
6140 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6141 gen_op_set_cc_op(s
->cc_op
);
6142 tcg_gen_helper_0_0(helper_aaa
);
6143 s
->cc_op
= CC_OP_EFLAGS
;
6145 case 0x3f: /* aas */
6148 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6149 gen_op_set_cc_op(s
->cc_op
);
6150 tcg_gen_helper_0_0(helper_aas
);
6151 s
->cc_op
= CC_OP_EFLAGS
;
6153 case 0xd4: /* aam */
6156 val
= ldub_code(s
->pc
++);
6158 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6160 tcg_gen_helper_0_1(helper_aam
, tcg_const_i32(val
));
6161 s
->cc_op
= CC_OP_LOGICB
;
6164 case 0xd5: /* aad */
6167 val
= ldub_code(s
->pc
++);
6168 tcg_gen_helper_0_1(helper_aad
, tcg_const_i32(val
));
6169 s
->cc_op
= CC_OP_LOGICB
;
6171 /************************/
6173 case 0x90: /* nop */
6174 /* XXX: xchg + rex handling */
6175 /* XXX: correct lock test for all insn */
6176 if (prefixes
& PREFIX_LOCK
)
6178 if (prefixes
& PREFIX_REPZ
) {
6179 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6182 case 0x9b: /* fwait */
6183 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6184 (HF_MP_MASK
| HF_TS_MASK
)) {
6185 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6187 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6188 gen_op_set_cc_op(s
->cc_op
);
6189 gen_jmp_im(pc_start
- s
->cs_base
);
6190 tcg_gen_helper_0_0(helper_fwait
);
6193 case 0xcc: /* int3 */
6194 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6196 case 0xcd: /* int N */
6197 val
= ldub_code(s
->pc
++);
6198 if (s
->vm86
&& s
->iopl
!= 3) {
6199 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6201 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6204 case 0xce: /* into */
6207 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6208 gen_op_set_cc_op(s
->cc_op
);
6209 gen_jmp_im(pc_start
- s
->cs_base
);
6210 tcg_gen_helper_0_1(helper_into
, tcg_const_i32(s
->pc
- pc_start
));
6212 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6213 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6215 gen_debug(s
, pc_start
- s
->cs_base
);
6218 tb_flush(cpu_single_env
);
6219 cpu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6222 case 0xfa: /* cli */
6224 if (s
->cpl
<= s
->iopl
) {
6225 tcg_gen_helper_0_0(helper_cli
);
6227 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6231 tcg_gen_helper_0_0(helper_cli
);
6233 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6237 case 0xfb: /* sti */
6239 if (s
->cpl
<= s
->iopl
) {
6241 tcg_gen_helper_0_0(helper_sti
);
6242 /* interruptions are enabled only the first insn after sti */
6243 /* If several instructions disable interrupts, only the
6245 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6246 tcg_gen_helper_0_0(helper_set_inhibit_irq
);
6247 /* give a chance to handle pending irqs */
6248 gen_jmp_im(s
->pc
- s
->cs_base
);
6251 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6257 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6261 case 0x62: /* bound */
6264 ot
= dflag
? OT_LONG
: OT_WORD
;
6265 modrm
= ldub_code(s
->pc
++);
6266 reg
= (modrm
>> 3) & 7;
6267 mod
= (modrm
>> 6) & 3;
6270 gen_op_mov_TN_reg(ot
, 0, reg
);
6271 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6272 gen_jmp_im(pc_start
- s
->cs_base
);
6273 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6275 tcg_gen_helper_0_2(helper_boundw
, cpu_A0
, cpu_tmp2_i32
);
6277 tcg_gen_helper_0_2(helper_boundl
, cpu_A0
, cpu_tmp2_i32
);
6279 case 0x1c8 ... 0x1cf: /* bswap reg */
6280 reg
= (b
& 7) | REX_B(s
);
6281 #ifdef TARGET_X86_64
6283 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6284 tcg_gen_bswap_i64(cpu_T
[0], cpu_T
[0]);
6285 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6289 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6291 tmp0
= tcg_temp_new(TCG_TYPE_I32
);
6292 tcg_gen_trunc_i64_i32(tmp0
, cpu_T
[0]);
6293 tcg_gen_bswap_i32(tmp0
, tmp0
);
6294 tcg_gen_extu_i32_i64(cpu_T
[0], tmp0
);
6295 gen_op_mov_reg_T0(OT_LONG
, reg
);
6299 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6300 tcg_gen_bswap_i32(cpu_T
[0], cpu_T
[0]);
6301 gen_op_mov_reg_T0(OT_LONG
, reg
);
6305 case 0xd6: /* salc */
6308 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6309 gen_op_set_cc_op(s
->cc_op
);
6310 gen_compute_eflags_c(cpu_T
[0]);
6311 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6312 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6314 case 0xe0: /* loopnz */
6315 case 0xe1: /* loopz */
6316 case 0xe2: /* loop */
6317 case 0xe3: /* jecxz */
6321 tval
= (int8_t)insn_get(s
, OT_BYTE
);
6322 next_eip
= s
->pc
- s
->cs_base
;
6327 l1
= gen_new_label();
6328 l2
= gen_new_label();
6329 l3
= gen_new_label();
6332 case 0: /* loopnz */
6334 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6335 gen_op_set_cc_op(s
->cc_op
);
6336 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6337 gen_op_jz_ecx(s
->aflag
, l3
);
6338 gen_compute_eflags(cpu_tmp0
);
6339 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_Z
);
6341 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, l1
);
6343 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, l1
);
6347 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6348 gen_op_jnz_ecx(s
->aflag
, l1
);
6352 gen_op_jz_ecx(s
->aflag
, l1
);
6357 gen_jmp_im(next_eip
);
6366 case 0x130: /* wrmsr */
6367 case 0x132: /* rdmsr */
6369 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6371 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6372 gen_op_set_cc_op(s
->cc_op
);
6373 gen_jmp_im(pc_start
- s
->cs_base
);
6375 tcg_gen_helper_0_0(helper_rdmsr
);
6377 tcg_gen_helper_0_0(helper_wrmsr
);
6381 case 0x131: /* rdtsc */
6382 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6383 gen_op_set_cc_op(s
->cc_op
);
6384 gen_jmp_im(pc_start
- s
->cs_base
);
6387 tcg_gen_helper_0_0(helper_rdtsc
);
6390 gen_jmp(s
, s
->pc
- s
->cs_base
);
6393 case 0x133: /* rdpmc */
6394 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6395 gen_op_set_cc_op(s
->cc_op
);
6396 gen_jmp_im(pc_start
- s
->cs_base
);
6397 tcg_gen_helper_0_0(helper_rdpmc
);
6399 case 0x134: /* sysenter */
6403 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6405 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6406 gen_op_set_cc_op(s
->cc_op
);
6407 s
->cc_op
= CC_OP_DYNAMIC
;
6409 gen_jmp_im(pc_start
- s
->cs_base
);
6410 tcg_gen_helper_0_0(helper_sysenter
);
6414 case 0x135: /* sysexit */
6418 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6420 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6421 gen_op_set_cc_op(s
->cc_op
);
6422 s
->cc_op
= CC_OP_DYNAMIC
;
6424 gen_jmp_im(pc_start
- s
->cs_base
);
6425 tcg_gen_helper_0_0(helper_sysexit
);
6429 #ifdef TARGET_X86_64
6430 case 0x105: /* syscall */
6431 /* XXX: is it usable in real mode ? */
6432 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6433 gen_op_set_cc_op(s
->cc_op
);
6434 s
->cc_op
= CC_OP_DYNAMIC
;
6436 gen_jmp_im(pc_start
- s
->cs_base
);
6437 tcg_gen_helper_0_1(helper_syscall
, tcg_const_i32(s
->pc
- pc_start
));
6440 case 0x107: /* sysret */
6442 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6444 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6445 gen_op_set_cc_op(s
->cc_op
);
6446 s
->cc_op
= CC_OP_DYNAMIC
;
6448 gen_jmp_im(pc_start
- s
->cs_base
);
6449 tcg_gen_helper_0_1(helper_sysret
, tcg_const_i32(s
->dflag
));
6450 /* condition codes are modified only in long mode */
6452 s
->cc_op
= CC_OP_EFLAGS
;
6457 case 0x1a2: /* cpuid */
6458 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6459 gen_op_set_cc_op(s
->cc_op
);
6460 gen_jmp_im(pc_start
- s
->cs_base
);
6461 tcg_gen_helper_0_0(helper_cpuid
);
6463 case 0xf4: /* hlt */
6465 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6467 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6468 gen_op_set_cc_op(s
->cc_op
);
6469 gen_jmp_im(pc_start
- s
->cs_base
);
6470 tcg_gen_helper_0_1(helper_hlt
, tcg_const_i32(s
->pc
- pc_start
));
6475 modrm
= ldub_code(s
->pc
++);
6476 mod
= (modrm
>> 6) & 3;
6477 op
= (modrm
>> 3) & 7;
6480 if (!s
->pe
|| s
->vm86
)
6482 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
6483 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
6487 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6490 if (!s
->pe
|| s
->vm86
)
6493 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6495 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
6496 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6497 gen_jmp_im(pc_start
- s
->cs_base
);
6498 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6499 tcg_gen_helper_0_1(helper_lldt
, cpu_tmp2_i32
);
6503 if (!s
->pe
|| s
->vm86
)
6505 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
6506 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
6510 gen_ldst_modrm(s
, modrm
, ot
, OR_TMP0
, 1);
6513 if (!s
->pe
|| s
->vm86
)
6516 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6518 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
6519 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6520 gen_jmp_im(pc_start
- s
->cs_base
);
6521 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6522 tcg_gen_helper_0_1(helper_ltr
, cpu_tmp2_i32
);
6527 if (!s
->pe
|| s
->vm86
)
6529 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6530 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6531 gen_op_set_cc_op(s
->cc_op
);
6533 tcg_gen_helper_0_1(helper_verr
, cpu_T
[0]);
6535 tcg_gen_helper_0_1(helper_verw
, cpu_T
[0]);
6536 s
->cc_op
= CC_OP_EFLAGS
;
6543 modrm
= ldub_code(s
->pc
++);
6544 mod
= (modrm
>> 6) & 3;
6545 op
= (modrm
>> 3) & 7;
6551 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
6552 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6553 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
6554 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
6555 gen_add_A0_im(s
, 2);
6556 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
6558 gen_op_andl_T0_im(0xffffff);
6559 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
6564 case 0: /* monitor */
6565 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
6568 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6569 gen_op_set_cc_op(s
->cc_op
);
6570 gen_jmp_im(pc_start
- s
->cs_base
);
6571 #ifdef TARGET_X86_64
6572 if (s
->aflag
== 2) {
6573 gen_op_movq_A0_reg(R_EAX
);
6577 gen_op_movl_A0_reg(R_EAX
);
6579 gen_op_andl_A0_ffff();
6581 gen_add_A0_ds_seg(s
);
6582 tcg_gen_helper_0_1(helper_monitor
, cpu_A0
);
6585 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
6588 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
6589 gen_op_set_cc_op(s
->cc_op
);
6590 s
->cc_op
= CC_OP_DYNAMIC
;
6592 gen_jmp_im(pc_start
- s
->cs_base
);
6593 tcg_gen_helper_0_1(helper_mwait
, tcg_const_i32(s
->pc
- pc_start
));
6600 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
6601 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6602 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
6603 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
6604 gen_add_A0_im(s
, 2);
6605 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
6607 gen_op_andl_T0_im(0xffffff);
6608 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
6614 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6615 gen_op_set_cc_op(s
->cc_op
);
6616 gen_jmp_im(pc_start
- s
->cs_base
);
6619 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
6622 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6625 tcg_gen_helper_0_2(helper_vmrun
,
6626 tcg_const_i32(s
->aflag
),
6627 tcg_const_i32(s
->pc
- pc_start
));
6632 case 1: /* VMMCALL */
6633 if (!(s
->flags
& HF_SVME_MASK
))
6635 tcg_gen_helper_0_0(helper_vmmcall
);
6637 case 2: /* VMLOAD */
6638 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
6641 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6644 tcg_gen_helper_0_1(helper_vmload
,
6645 tcg_const_i32(s
->aflag
));
6648 case 3: /* VMSAVE */
6649 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
6652 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6655 tcg_gen_helper_0_1(helper_vmsave
,
6656 tcg_const_i32(s
->aflag
));
6660 if ((!(s
->flags
& HF_SVME_MASK
) &&
6661 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
6665 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6668 tcg_gen_helper_0_0(helper_stgi
);
6672 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
6675 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6678 tcg_gen_helper_0_0(helper_clgi
);
6681 case 6: /* SKINIT */
6682 if ((!(s
->flags
& HF_SVME_MASK
) &&
6683 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
6686 tcg_gen_helper_0_0(helper_skinit
);
6688 case 7: /* INVLPGA */
6689 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
6692 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6695 tcg_gen_helper_0_1(helper_invlpga
,
6696 tcg_const_i32(s
->aflag
));
6702 } else if (s
->cpl
!= 0) {
6703 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6705 gen_svm_check_intercept(s
, pc_start
,
6706 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
6707 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6708 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
6709 gen_add_A0_im(s
, 2);
6710 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
6712 gen_op_andl_T0_im(0xffffff);
6714 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
6715 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
6717 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
6718 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
6723 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
6724 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
6725 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 1);
6729 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6731 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
6732 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6733 tcg_gen_helper_0_1(helper_lmsw
, cpu_T
[0]);
6734 gen_jmp_im(s
->pc
- s
->cs_base
);
6738 case 7: /* invlpg */
6740 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6743 #ifdef TARGET_X86_64
6744 if (CODE64(s
) && rm
== 0) {
6746 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
6747 tcg_gen_ld_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
6748 tcg_gen_st_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,segs
[R_GS
].base
));
6749 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,kernelgsbase
));
6756 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6757 gen_op_set_cc_op(s
->cc_op
);
6758 gen_jmp_im(pc_start
- s
->cs_base
);
6759 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6760 tcg_gen_helper_0_1(helper_invlpg
, cpu_A0
);
6761 gen_jmp_im(s
->pc
- s
->cs_base
);
6770 case 0x108: /* invd */
6771 case 0x109: /* wbinvd */
6773 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6775 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
6779 case 0x63: /* arpl or movslS (x86_64) */
6780 #ifdef TARGET_X86_64
6783 /* d_ot is the size of destination */
6784 d_ot
= dflag
+ OT_WORD
;
6786 modrm
= ldub_code(s
->pc
++);
6787 reg
= ((modrm
>> 3) & 7) | rex_r
;
6788 mod
= (modrm
>> 6) & 3;
6789 rm
= (modrm
& 7) | REX_B(s
);
6792 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
6794 if (d_ot
== OT_QUAD
)
6795 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
6796 gen_op_mov_reg_T0(d_ot
, reg
);
6798 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6799 if (d_ot
== OT_QUAD
) {
6800 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
6802 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
6804 gen_op_mov_reg_T0(d_ot
, reg
);
6812 if (!s
->pe
|| s
->vm86
)
6814 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6815 t1
= tcg_temp_local_new(TCG_TYPE_TL
);
6816 t2
= tcg_temp_local_new(TCG_TYPE_TL
);
6818 modrm
= ldub_code(s
->pc
++);
6819 reg
= (modrm
>> 3) & 7;
6820 mod
= (modrm
>> 6) & 3;
6823 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6824 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6826 gen_op_mov_v_reg(ot
, t0
, rm
);
6828 gen_op_mov_v_reg(ot
, t1
, reg
);
6829 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
6830 tcg_gen_andi_tl(t1
, t1
, 3);
6831 tcg_gen_movi_tl(t2
, 0);
6832 label1
= gen_new_label();
6833 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
6834 tcg_gen_andi_tl(t0
, t0
, ~3);
6835 tcg_gen_or_tl(t0
, t0
, t1
);
6836 tcg_gen_movi_tl(t2
, CC_Z
);
6837 gen_set_label(label1
);
6839 gen_op_st_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
6841 gen_op_mov_reg_v(ot
, rm
, t0
);
6843 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6844 gen_op_set_cc_op(s
->cc_op
);
6845 gen_compute_eflags(cpu_cc_src
);
6846 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
6847 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
6848 s
->cc_op
= CC_OP_EFLAGS
;
6854 case 0x102: /* lar */
6855 case 0x103: /* lsl */
6859 if (!s
->pe
|| s
->vm86
)
6861 ot
= dflag
? OT_LONG
: OT_WORD
;
6862 modrm
= ldub_code(s
->pc
++);
6863 reg
= ((modrm
>> 3) & 7) | rex_r
;
6864 gen_ldst_modrm(s
, modrm
, OT_WORD
, OR_TMP0
, 0);
6865 t0
= tcg_temp_local_new(TCG_TYPE_TL
);
6866 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6867 gen_op_set_cc_op(s
->cc_op
);
6869 tcg_gen_helper_1_1(helper_lar
, t0
, cpu_T
[0]);
6871 tcg_gen_helper_1_1(helper_lsl
, t0
, cpu_T
[0]);
6872 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
6873 label1
= gen_new_label();
6874 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
6875 gen_op_mov_reg_v(ot
, reg
, t0
);
6876 gen_set_label(label1
);
6877 s
->cc_op
= CC_OP_EFLAGS
;
6882 modrm
= ldub_code(s
->pc
++);
6883 mod
= (modrm
>> 6) & 3;
6884 op
= (modrm
>> 3) & 7;
6886 case 0: /* prefetchnta */
6887 case 1: /* prefetchnt0 */
6888 case 2: /* prefetchnt0 */
6889 case 3: /* prefetchnt0 */
6892 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
6893 /* nothing more to do */
6895 default: /* nop (multi byte) */
6896 gen_nop_modrm(s
, modrm
);
6900 case 0x119 ... 0x11f: /* nop (multi byte) */
6901 modrm
= ldub_code(s
->pc
++);
6902 gen_nop_modrm(s
, modrm
);
6904 case 0x120: /* mov reg, crN */
6905 case 0x122: /* mov crN, reg */
6907 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6909 modrm
= ldub_code(s
->pc
++);
6910 if ((modrm
& 0xc0) != 0xc0)
6912 rm
= (modrm
& 7) | REX_B(s
);
6913 reg
= ((modrm
>> 3) & 7) | rex_r
;
6924 if (s
->cc_op
!= CC_OP_DYNAMIC
)
6925 gen_op_set_cc_op(s
->cc_op
);
6926 gen_jmp_im(pc_start
- s
->cs_base
);
6928 gen_op_mov_TN_reg(ot
, 0, rm
);
6929 tcg_gen_helper_0_2(helper_write_crN
,
6930 tcg_const_i32(reg
), cpu_T
[0]);
6931 gen_jmp_im(s
->pc
- s
->cs_base
);
6934 tcg_gen_helper_1_1(helper_read_crN
,
6935 cpu_T
[0], tcg_const_i32(reg
));
6936 gen_op_mov_reg_T0(ot
, rm
);
6944 case 0x121: /* mov reg, drN */
6945 case 0x123: /* mov drN, reg */
6947 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6949 modrm
= ldub_code(s
->pc
++);
6950 if ((modrm
& 0xc0) != 0xc0)
6952 rm
= (modrm
& 7) | REX_B(s
);
6953 reg
= ((modrm
>> 3) & 7) | rex_r
;
6958 /* XXX: do it dynamically with CR4.DE bit */
6959 if (reg
== 4 || reg
== 5 || reg
>= 8)
6962 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
6963 gen_op_mov_TN_reg(ot
, 0, rm
);
6964 tcg_gen_helper_0_2(helper_movl_drN_T0
,
6965 tcg_const_i32(reg
), cpu_T
[0]);
6966 gen_jmp_im(s
->pc
- s
->cs_base
);
6969 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
6970 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
6971 gen_op_mov_reg_T0(ot
, rm
);
6975 case 0x106: /* clts */
6977 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6979 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
6980 tcg_gen_helper_0_0(helper_clts
);
6981 /* abort block because static cpu state changed */
6982 gen_jmp_im(s
->pc
- s
->cs_base
);
6986 /* MMX/3DNow!/SSE/SSE2/SSE3 support */
6987 case 0x1c3: /* MOVNTI reg, mem */
6988 if (!(s
->cpuid_features
& CPUID_SSE2
))
6990 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
6991 modrm
= ldub_code(s
->pc
++);
6992 mod
= (modrm
>> 6) & 3;
6995 reg
= ((modrm
>> 3) & 7) | rex_r
;
6996 /* generate a generic store */
6997 gen_ldst_modrm(s
, modrm
, ot
, reg
, 1);
7000 modrm
= ldub_code(s
->pc
++);
7001 mod
= (modrm
>> 6) & 3;
7002 op
= (modrm
>> 3) & 7;
7004 case 0: /* fxsave */
7005 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7006 (s
->flags
& HF_EM_MASK
))
7008 if (s
->flags
& HF_TS_MASK
) {
7009 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7012 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7013 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7014 gen_op_set_cc_op(s
->cc_op
);
7015 gen_jmp_im(pc_start
- s
->cs_base
);
7016 tcg_gen_helper_0_2(helper_fxsave
,
7017 cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7019 case 1: /* fxrstor */
7020 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7021 (s
->flags
& HF_EM_MASK
))
7023 if (s
->flags
& HF_TS_MASK
) {
7024 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7027 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7028 if (s
->cc_op
!= CC_OP_DYNAMIC
)
7029 gen_op_set_cc_op(s
->cc_op
);
7030 gen_jmp_im(pc_start
- s
->cs_base
);
7031 tcg_gen_helper_0_2(helper_fxrstor
,
7032 cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7034 case 2: /* ldmxcsr */
7035 case 3: /* stmxcsr */
7036 if (s
->flags
& HF_TS_MASK
) {
7037 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7040 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7043 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7045 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7046 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7048 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7049 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7052 case 5: /* lfence */
7053 case 6: /* mfence */
7054 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE
))
7057 case 7: /* sfence / clflush */
7058 if ((modrm
& 0xc7) == 0xc0) {
7060 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7061 if (!(s
->cpuid_features
& CPUID_SSE
))
7065 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7067 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7074 case 0x10d: /* 3DNow! prefetch(w) */
7075 modrm
= ldub_code(s
->pc
++);
7076 mod
= (modrm
>> 6) & 3;
7079 gen_lea_modrm(s
, modrm
, ®_addr
, &offset_addr
);
7080 /* ignore for now */
7082 case 0x1aa: /* rsm */
7083 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7084 if (!(s
->flags
& HF_SMM_MASK
))
7086 if (s
->cc_op
!= CC_OP_DYNAMIC
) {
7087 gen_op_set_cc_op(s
->cc_op
);
7088 s
->cc_op
= CC_OP_DYNAMIC
;
7090 gen_jmp_im(s
->pc
- s
->cs_base
);
7091 tcg_gen_helper_0_0(helper_rsm
);
7094 case 0x10e ... 0x10f:
7095 /* 3DNow! instructions, ignore prefixes */
7096 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7097 case 0x110 ... 0x117:
7098 case 0x128 ... 0x12f:
7099 case 0x150 ... 0x177:
7100 case 0x17c ... 0x17f:
7102 case 0x1c4 ... 0x1c6:
7103 case 0x1d0 ... 0x1fe:
7104 gen_sse(s
, b
, pc_start
, rex_r
);
7109 /* lock generation */
7110 if (s
->prefix
& PREFIX_LOCK
)
7111 tcg_gen_helper_0_0(helper_unlock
);
7114 if (s
->prefix
& PREFIX_LOCK
)
7115 tcg_gen_helper_0_0(helper_unlock
);
7116 /* XXX: ensure that no lock was generated */
7117 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7121 void optimize_flags_init(void)
7123 #if TCG_TARGET_REG_BITS == 32
7124 assert(sizeof(CCTable
) == (1 << 3));
7126 assert(sizeof(CCTable
) == (1 << 4));
7128 cpu_env
= tcg_global_reg_new(TCG_TYPE_PTR
, TCG_AREG0
, "env");
7129 cpu_cc_op
= tcg_global_mem_new(TCG_TYPE_I32
,
7130 TCG_AREG0
, offsetof(CPUState
, cc_op
), "cc_op");
7131 cpu_cc_src
= tcg_global_mem_new(TCG_TYPE_TL
,
7132 TCG_AREG0
, offsetof(CPUState
, cc_src
), "cc_src");
7133 cpu_cc_dst
= tcg_global_mem_new(TCG_TYPE_TL
,
7134 TCG_AREG0
, offsetof(CPUState
, cc_dst
), "cc_dst");
7135 cpu_cc_tmp
= tcg_global_mem_new(TCG_TYPE_TL
,
7136 TCG_AREG0
, offsetof(CPUState
, cc_tmp
), "cc_tmp");
7138 /* register helpers */
7140 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
7144 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7145 basic block 'tb'. If search_pc is TRUE, also generate PC
7146 information for each intermediate instruction. */
7147 static inline int gen_intermediate_code_internal(CPUState
*env
,
7148 TranslationBlock
*tb
,
7151 DisasContext dc1
, *dc
= &dc1
;
7152 target_ulong pc_ptr
;
7153 uint16_t *gen_opc_end
;
7156 target_ulong pc_start
;
7157 target_ulong cs_base
;
7161 /* generate intermediate code */
7163 cs_base
= tb
->cs_base
;
7165 cflags
= tb
->cflags
;
7167 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7168 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7169 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7170 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7172 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7173 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7174 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7175 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7176 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7177 dc
->cc_op
= CC_OP_DYNAMIC
;
7178 dc
->cs_base
= cs_base
;
7180 dc
->popl_esp_hack
= 0;
7181 /* select memory access functions */
7183 if (flags
& HF_SOFTMMU_MASK
) {
7185 dc
->mem_index
= 2 * 4;
7187 dc
->mem_index
= 1 * 4;
7189 dc
->cpuid_features
= env
->cpuid_features
;
7190 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7191 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7192 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7193 #ifdef TARGET_X86_64
7194 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7195 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7198 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7199 (flags
& HF_INHIBIT_IRQ_MASK
)
7200 #ifndef CONFIG_SOFTMMU
7201 || (flags
& HF_SOFTMMU_MASK
)
7205 /* check addseg logic */
7206 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7207 printf("ERROR addseg\n");
7210 cpu_T
[0] = tcg_temp_new(TCG_TYPE_TL
);
7211 cpu_T
[1] = tcg_temp_new(TCG_TYPE_TL
);
7212 cpu_A0
= tcg_temp_new(TCG_TYPE_TL
);
7213 cpu_T3
= tcg_temp_new(TCG_TYPE_TL
);
7215 cpu_tmp0
= tcg_temp_new(TCG_TYPE_TL
);
7216 cpu_tmp1_i64
= tcg_temp_new(TCG_TYPE_I64
);
7217 cpu_tmp2_i32
= tcg_temp_new(TCG_TYPE_I32
);
7218 cpu_tmp3_i32
= tcg_temp_new(TCG_TYPE_I32
);
7219 cpu_tmp4
= tcg_temp_new(TCG_TYPE_TL
);
7220 cpu_tmp5
= tcg_temp_new(TCG_TYPE_TL
);
7221 cpu_tmp6
= tcg_temp_new(TCG_TYPE_TL
);
7222 cpu_ptr0
= tcg_temp_new(TCG_TYPE_PTR
);
7223 cpu_ptr1
= tcg_temp_new(TCG_TYPE_PTR
);
7225 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
7227 dc
->is_jmp
= DISAS_NEXT
;
7231 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7233 max_insns
= CF_COUNT_MASK
;
7237 if (env
->nb_breakpoints
> 0) {
7238 for(j
= 0; j
< env
->nb_breakpoints
; j
++) {
7239 if (env
->breakpoints
[j
] == pc_ptr
) {
7240 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7246 j
= gen_opc_ptr
- gen_opc_buf
;
7250 gen_opc_instr_start
[lj
++] = 0;
7252 gen_opc_pc
[lj
] = pc_ptr
;
7253 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7254 gen_opc_instr_start
[lj
] = 1;
7255 gen_opc_icount
[lj
] = num_insns
;
7257 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7260 pc_ptr
= disas_insn(dc
, pc_ptr
);
7262 /* stop translation if indicated */
7265 /* if single step mode, we generate only one instruction and
7266 generate an exception */
7267 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7268 the flag and abort the translation to give the irqs a
7269 change to be happen */
7270 if (dc
->tf
|| dc
->singlestep_enabled
||
7271 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7272 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7276 /* if too long translation, stop generation too */
7277 if (gen_opc_ptr
>= gen_opc_end
||
7278 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7279 num_insns
>= max_insns
) {
7280 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7285 if (tb
->cflags
& CF_LAST_IO
)
7287 gen_icount_end(tb
, num_insns
);
7288 *gen_opc_ptr
= INDEX_op_end
;
7289 /* we don't forget to fill the last values */
7291 j
= gen_opc_ptr
- gen_opc_buf
;
7294 gen_opc_instr_start
[lj
++] = 0;
7298 if (loglevel
& CPU_LOG_TB_CPU
) {
7299 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
7301 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
7303 fprintf(logfile
, "----------------\n");
7304 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc_start
));
7305 #ifdef TARGET_X86_64
7310 disas_flags
= !dc
->code32
;
7311 target_disas(logfile
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
7312 fprintf(logfile
, "\n");
7317 tb
->size
= pc_ptr
- pc_start
;
7318 tb
->icount
= num_insns
;
7323 int gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
7325 return gen_intermediate_code_internal(env
, tb
, 0);
7328 int gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
7330 return gen_intermediate_code_internal(env
, tb
, 1);
7333 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
7334 unsigned long searched_pc
, int pc_pos
, void *puc
)
7338 if (loglevel
& CPU_LOG_TB_OP
) {
7340 fprintf(logfile
, "RESTORE:\n");
7341 for(i
= 0;i
<= pc_pos
; i
++) {
7342 if (gen_opc_instr_start
[i
]) {
7343 fprintf(logfile
, "0x%04x: " TARGET_FMT_lx
"\n", i
, gen_opc_pc
[i
]);
7346 fprintf(logfile
, "spc=0x%08lx pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
7347 searched_pc
, pc_pos
, gen_opc_pc
[pc_pos
] - tb
->cs_base
,
7348 (uint32_t)tb
->cs_base
);
7351 env
->eip
= gen_opc_pc
[pc_pos
] - tb
->cs_base
;
7352 cc_op
= gen_opc_cc_op
[pc_pos
];
7353 if (cc_op
!= CC_OP_DYNAMIC
)