4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
42 #define CODE64(s) ((s)->code64)
43 #define REX_X(s) ((s)->rex_x)
44 #define REX_B(s) ((s)->rex_b)
59 //#define MACRO_TEST 1
61 /* global register indexes */
62 static TCGv_ptr cpu_env
;
63 static TCGv cpu_A0
, cpu_cc_src
, cpu_cc_dst
;
64 static TCGv_i32 cpu_cc_op
;
65 static TCGv cpu_regs
[CPU_NB_REGS
];
68 /* local register indexes (only used inside old micro ops) */
69 static TCGv cpu_tmp0
, cpu_tmp4
;
70 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
71 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
72 static TCGv_i64 cpu_tmp1_i64
;
75 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
77 #include "exec/gen-icount.h"
80 static int x86_64_hregs
;
83 typedef struct DisasContext
{
84 /* current insn context */
85 int override
; /* -1 if no override */
88 target_ulong pc
; /* pc = eip + cs_base */
89 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
90 static state change (stop translation) */
91 /* current block context */
92 target_ulong cs_base
; /* base of CS segment */
93 int pe
; /* protected mode */
94 int code32
; /* 32 bit code segment */
96 int lma
; /* long mode active */
97 int code64
; /* 64 bit code segment */
100 int ss32
; /* 32 bit stack segment */
101 CCOp cc_op
; /* current CC operation */
103 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
104 int f_st
; /* currently unused */
105 int vm86
; /* vm86 mode */
108 int tf
; /* TF cpu flag */
109 int singlestep_enabled
; /* "hardware" single step enabled */
110 int jmp_opt
; /* use direct block chaining for direct jumps */
111 int mem_index
; /* select memory access functions */
112 uint64_t flags
; /* all execution flags */
113 struct TranslationBlock
*tb
;
114 int popl_esp_hack
; /* for correct popl with esp base handling */
115 int rip_offset
; /* only used in x86_64, but left for simplicity */
117 int cpuid_ext_features
;
118 int cpuid_ext2_features
;
119 int cpuid_ext3_features
;
120 int cpuid_7_0_ebx_features
;
123 static void gen_eob(DisasContext
*s
);
124 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
125 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
126 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
);
128 /* i386 arith/logic operations */
148 OP_SHL1
, /* undocumented */
172 /* I386 int registers */
173 OR_EAX
, /* MUST be even numbered */
182 OR_TMP0
= 16, /* temporary operand register */
184 OR_A0
, /* temporary register used when doing address evaluation */
192 /* Bit set if the global variable is live after setting CC_OP to X. */
193 static const uint8_t cc_op_live
[CC_OP_NB
] = {
194 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_EFLAGS
] = USES_CC_SRC
,
196 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
197 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
198 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
,
199 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
202 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
208 static void set_cc_op(DisasContext
*s
, CCOp op
)
212 if (s
->cc_op
== op
) {
216 /* Discard CC computation that will no longer be used. */
217 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
218 if (dead
& USES_CC_DST
) {
219 tcg_gen_discard_tl(cpu_cc_dst
);
221 if (dead
& USES_CC_SRC
) {
222 tcg_gen_discard_tl(cpu_cc_src
);
226 /* The DYNAMIC setting is translator only, and should never be
227 stored. Thus we always consider it clean. */
228 s
->cc_op_dirty
= (op
!= CC_OP_DYNAMIC
);
231 static void gen_update_cc_op(DisasContext
*s
)
233 if (s
->cc_op_dirty
) {
234 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
235 s
->cc_op_dirty
= false;
239 static inline void gen_op_movl_T0_0(void)
241 tcg_gen_movi_tl(cpu_T
[0], 0);
244 static inline void gen_op_movl_T0_im(int32_t val
)
246 tcg_gen_movi_tl(cpu_T
[0], val
);
249 static inline void gen_op_movl_T0_imu(uint32_t val
)
251 tcg_gen_movi_tl(cpu_T
[0], val
);
254 static inline void gen_op_movl_T1_im(int32_t val
)
256 tcg_gen_movi_tl(cpu_T
[1], val
);
259 static inline void gen_op_movl_T1_imu(uint32_t val
)
261 tcg_gen_movi_tl(cpu_T
[1], val
);
264 static inline void gen_op_movl_A0_im(uint32_t val
)
266 tcg_gen_movi_tl(cpu_A0
, val
);
270 static inline void gen_op_movq_A0_im(int64_t val
)
272 tcg_gen_movi_tl(cpu_A0
, val
);
276 static inline void gen_movtl_T0_im(target_ulong val
)
278 tcg_gen_movi_tl(cpu_T
[0], val
);
281 static inline void gen_movtl_T1_im(target_ulong val
)
283 tcg_gen_movi_tl(cpu_T
[1], val
);
286 static inline void gen_op_andl_T0_ffff(void)
288 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
291 static inline void gen_op_andl_T0_im(uint32_t val
)
293 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
296 static inline void gen_op_movl_T0_T1(void)
298 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
301 static inline void gen_op_andl_A0_ffff(void)
303 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
308 #define NB_OP_SIZES 4
310 #else /* !TARGET_X86_64 */
312 #define NB_OP_SIZES 3
314 #endif /* !TARGET_X86_64 */
316 #if defined(HOST_WORDS_BIGENDIAN)
317 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
318 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
319 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
320 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
321 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
323 #define REG_B_OFFSET 0
324 #define REG_H_OFFSET 1
325 #define REG_W_OFFSET 0
326 #define REG_L_OFFSET 0
327 #define REG_LH_OFFSET 4
330 /* In instruction encodings for byte register accesses the
331 * register number usually indicates "low 8 bits of register N";
332 * however there are some special cases where N 4..7 indicates
333 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
334 * true for this special case, false otherwise.
336 static inline bool byte_reg_is_xH(int reg
)
342 if (reg
>= 8 || x86_64_hregs
) {
349 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
353 if (!byte_reg_is_xH(reg
)) {
354 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
356 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
360 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
362 default: /* XXX this shouldn't be reached; abort? */
364 /* For x86_64, this sets the higher half of register to zero.
365 For i386, this is equivalent to a mov. */
366 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
370 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
376 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
378 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
381 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
383 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
386 static inline void gen_op_mov_reg_A0(int size
, int reg
)
390 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
392 default: /* XXX this shouldn't be reached; abort? */
394 /* For x86_64, this sets the higher half of register to zero.
395 For i386, this is equivalent to a mov. */
396 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
400 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
406 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
408 if (ot
== OT_BYTE
&& byte_reg_is_xH(reg
)) {
409 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
410 tcg_gen_ext8u_tl(t0
, t0
);
412 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
416 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
418 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
421 static inline void gen_op_movl_A0_reg(int reg
)
423 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
426 static inline void gen_op_addl_A0_im(int32_t val
)
428 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
430 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
435 static inline void gen_op_addq_A0_im(int64_t val
)
437 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
441 static void gen_add_A0_im(DisasContext
*s
, int val
)
445 gen_op_addq_A0_im(val
);
448 gen_op_addl_A0_im(val
);
451 static inline void gen_op_addl_T0_T1(void)
453 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
456 static inline void gen_op_jmp_T0(void)
458 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
461 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
465 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
466 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
469 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
470 /* For x86_64, this sets the higher half of register to zero.
471 For i386, this is equivalent to a nop. */
472 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
473 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
477 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
483 static inline void gen_op_add_reg_T0(int size
, int reg
)
487 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
488 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
491 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
492 /* For x86_64, this sets the higher half of register to zero.
493 For i386, this is equivalent to a nop. */
494 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
495 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
499 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
505 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
507 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
509 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
510 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
511 /* For x86_64, this sets the higher half of register to zero.
512 For i386, this is equivalent to a nop. */
513 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
516 static inline void gen_op_movl_A0_seg(int reg
)
518 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
521 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
523 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
526 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
527 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
529 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
530 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
533 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
538 static inline void gen_op_movq_A0_seg(int reg
)
540 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
543 static inline void gen_op_addq_A0_seg(int reg
)
545 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
546 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
549 static inline void gen_op_movq_A0_reg(int reg
)
551 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
554 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
556 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
558 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
559 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
563 static inline void gen_op_lds_T0_A0(int idx
)
565 int mem_index
= (idx
>> 2) - 1;
568 tcg_gen_qemu_ld8s(cpu_T
[0], cpu_A0
, mem_index
);
571 tcg_gen_qemu_ld16s(cpu_T
[0], cpu_A0
, mem_index
);
575 tcg_gen_qemu_ld32s(cpu_T
[0], cpu_A0
, mem_index
);
580 static inline void gen_op_ld_v(int idx
, TCGv t0
, TCGv a0
)
582 int mem_index
= (idx
>> 2) - 1;
585 tcg_gen_qemu_ld8u(t0
, a0
, mem_index
);
588 tcg_gen_qemu_ld16u(t0
, a0
, mem_index
);
591 tcg_gen_qemu_ld32u(t0
, a0
, mem_index
);
595 /* Should never happen on 32-bit targets. */
597 tcg_gen_qemu_ld64(t0
, a0
, mem_index
);
603 /* XXX: always use ldu or lds */
604 static inline void gen_op_ld_T0_A0(int idx
)
606 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
609 static inline void gen_op_ldu_T0_A0(int idx
)
611 gen_op_ld_v(idx
, cpu_T
[0], cpu_A0
);
614 static inline void gen_op_ld_T1_A0(int idx
)
616 gen_op_ld_v(idx
, cpu_T
[1], cpu_A0
);
619 static inline void gen_op_st_v(int idx
, TCGv t0
, TCGv a0
)
621 int mem_index
= (idx
>> 2) - 1;
624 tcg_gen_qemu_st8(t0
, a0
, mem_index
);
627 tcg_gen_qemu_st16(t0
, a0
, mem_index
);
630 tcg_gen_qemu_st32(t0
, a0
, mem_index
);
634 /* Should never happen on 32-bit targets. */
636 tcg_gen_qemu_st64(t0
, a0
, mem_index
);
642 static inline void gen_op_st_T0_A0(int idx
)
644 gen_op_st_v(idx
, cpu_T
[0], cpu_A0
);
647 static inline void gen_op_st_T1_A0(int idx
)
649 gen_op_st_v(idx
, cpu_T
[1], cpu_A0
);
652 static inline void gen_jmp_im(target_ulong pc
)
654 tcg_gen_movi_tl(cpu_tmp0
, pc
);
655 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
658 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
662 override
= s
->override
;
666 gen_op_movq_A0_seg(override
);
667 gen_op_addq_A0_reg_sN(0, R_ESI
);
669 gen_op_movq_A0_reg(R_ESI
);
675 if (s
->addseg
&& override
< 0)
678 gen_op_movl_A0_seg(override
);
679 gen_op_addl_A0_reg_sN(0, R_ESI
);
681 gen_op_movl_A0_reg(R_ESI
);
684 /* 16 address, always override */
687 gen_op_movl_A0_reg(R_ESI
);
688 gen_op_andl_A0_ffff();
689 gen_op_addl_A0_seg(s
, override
);
693 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
697 gen_op_movq_A0_reg(R_EDI
);
702 gen_op_movl_A0_seg(R_ES
);
703 gen_op_addl_A0_reg_sN(0, R_EDI
);
705 gen_op_movl_A0_reg(R_EDI
);
708 gen_op_movl_A0_reg(R_EDI
);
709 gen_op_andl_A0_ffff();
710 gen_op_addl_A0_seg(s
, R_ES
);
714 static inline void gen_op_movl_T0_Dshift(int ot
)
716 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
717 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
720 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
725 tcg_gen_ext8s_tl(dst
, src
);
727 tcg_gen_ext8u_tl(dst
, src
);
732 tcg_gen_ext16s_tl(dst
, src
);
734 tcg_gen_ext16u_tl(dst
, src
);
740 tcg_gen_ext32s_tl(dst
, src
);
742 tcg_gen_ext32u_tl(dst
, src
);
751 static void gen_extu(int ot
, TCGv reg
)
753 gen_ext_tl(reg
, reg
, ot
, false);
756 static void gen_exts(int ot
, TCGv reg
)
758 gen_ext_tl(reg
, reg
, ot
, true);
761 static inline void gen_op_jnz_ecx(int size
, int label1
)
763 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
764 gen_extu(size
+ 1, cpu_tmp0
);
765 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
768 static inline void gen_op_jz_ecx(int size
, int label1
)
770 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
771 gen_extu(size
+ 1, cpu_tmp0
);
772 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
775 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
779 gen_helper_inb(v
, n
);
782 gen_helper_inw(v
, n
);
785 gen_helper_inl(v
, n
);
790 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
794 gen_helper_outb(v
, n
);
797 gen_helper_outw(v
, n
);
800 gen_helper_outl(v
, n
);
805 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
809 target_ulong next_eip
;
812 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
816 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
819 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
822 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
825 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
829 if(s
->flags
& HF_SVMI_MASK
) {
834 svm_flags
|= (1 << (4 + ot
));
835 next_eip
= s
->pc
- s
->cs_base
;
836 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
837 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
838 tcg_const_i32(svm_flags
),
839 tcg_const_i32(next_eip
- cur_eip
));
843 static inline void gen_movs(DisasContext
*s
, int ot
)
845 gen_string_movl_A0_ESI(s
);
846 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
847 gen_string_movl_A0_EDI(s
);
848 gen_op_st_T0_A0(ot
+ s
->mem_index
);
849 gen_op_movl_T0_Dshift(ot
);
850 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
851 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
854 static void gen_op_update1_cc(void)
856 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
859 static void gen_op_update2_cc(void)
861 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
862 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
865 static inline void gen_op_testl_T0_T1_cc(void)
867 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
870 static void gen_op_update_neg_cc(void)
872 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
873 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
876 /* compute all eflags to cc_src */
877 static void gen_compute_eflags(DisasContext
*s
)
879 if (s
->cc_op
== CC_OP_EFLAGS
) {
883 gen_helper_cc_compute_all(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
884 set_cc_op(s
, CC_OP_EFLAGS
);
885 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
888 typedef struct CCPrepare
{
898 /* compute eflags.C to reg */
899 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
905 case CC_OP_SUBB
... CC_OP_SUBQ
:
906 /* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
907 size
= s
->cc_op
- CC_OP_SUBB
;
908 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
909 /* If no temporary was used, be careful not to alias t1 and t0. */
910 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
911 tcg_gen_add_tl(t0
, cpu_cc_dst
, cpu_cc_src
);
915 case CC_OP_ADDB
... CC_OP_ADDQ
:
916 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
917 size
= s
->cc_op
- CC_OP_ADDB
;
918 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
919 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
921 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
922 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
924 case CC_OP_SBBB
... CC_OP_SBBQ
:
925 /* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
926 size
= s
->cc_op
- CC_OP_SBBB
;
927 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
928 if (TCGV_EQUAL(t1
, reg
) && TCGV_EQUAL(reg
, cpu_cc_src
)) {
929 tcg_gen_mov_tl(cpu_tmp0
, cpu_cc_src
);
933 tcg_gen_add_tl(reg
, cpu_cc_dst
, cpu_cc_src
);
934 tcg_gen_addi_tl(reg
, reg
, 1);
939 case CC_OP_ADCB
... CC_OP_ADCQ
:
940 /* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
941 size
= s
->cc_op
- CC_OP_ADCB
;
942 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
943 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
945 return (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= t0
,
946 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
948 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
949 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
951 case CC_OP_INCB
... CC_OP_INCQ
:
952 case CC_OP_DECB
... CC_OP_DECQ
:
953 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
954 .mask
= -1, .no_setcond
= true };
956 case CC_OP_SHLB
... CC_OP_SHLQ
:
957 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
958 size
= s
->cc_op
- CC_OP_SHLB
;
959 shift
= (8 << size
) - 1;
960 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
961 .mask
= (target_ulong
)1 << shift
};
963 case CC_OP_MULB
... CC_OP_MULQ
:
964 return (CCPrepare
) { .cond
= TCG_COND_NE
,
965 .reg
= cpu_cc_src
, .mask
= -1 };
968 case CC_OP_SARB
... CC_OP_SARQ
:
970 return (CCPrepare
) { .cond
= TCG_COND_NE
,
971 .reg
= cpu_cc_src
, .mask
= CC_C
};
974 /* The need to compute only C from CC_OP_DYNAMIC is important
975 in efficiently implementing e.g. INC at the start of a TB. */
977 gen_helper_cc_compute_c(cpu_tmp2_i32
, cpu_env
, cpu_cc_op
);
978 tcg_gen_extu_i32_tl(reg
, cpu_tmp2_i32
);
979 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
980 .mask
= -1, .no_setcond
= true };
984 /* compute eflags.P to reg */
985 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
987 gen_compute_eflags(s
);
988 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
992 /* compute eflags.S to reg */
993 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
997 gen_compute_eflags(s
);
1000 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1004 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1005 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
1006 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
1011 /* compute eflags.O to reg */
1012 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
1014 gen_compute_eflags(s
);
1015 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1019 /* compute eflags.Z to reg */
1020 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
1024 gen_compute_eflags(s
);
1027 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1031 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1032 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1033 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
1038 /* perform a conditional store into register 'reg' according to jump opcode
1039 value 'b'. In the fast case, T0 is guaranted not to be used. */
1040 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
1042 int inv
, jcc_op
, size
, cond
;
1047 jcc_op
= (b
>> 1) & 7;
1050 case CC_OP_SUBB
... CC_OP_SUBQ
:
1051 /* We optimize relational operators for the cmp/jcc case. */
1052 size
= s
->cc_op
- CC_OP_SUBB
;
1055 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1056 gen_extu(size
, cpu_tmp4
);
1057 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1058 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
1059 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1068 tcg_gen_add_tl(cpu_tmp4
, cpu_cc_dst
, cpu_cc_src
);
1069 gen_exts(size
, cpu_tmp4
);
1070 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1071 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1072 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1082 /* This actually generates good code for JC, JZ and JS. */
1085 cc
= gen_prepare_eflags_o(s
, reg
);
1088 cc
= gen_prepare_eflags_c(s
, reg
);
1091 cc
= gen_prepare_eflags_z(s
, reg
);
1094 gen_compute_eflags(s
);
1095 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1096 .mask
= CC_Z
| CC_C
};
1099 cc
= gen_prepare_eflags_s(s
, reg
);
1102 cc
= gen_prepare_eflags_p(s
, reg
);
1105 gen_compute_eflags(s
);
1106 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1109 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1110 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1111 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1116 gen_compute_eflags(s
);
1117 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1120 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1121 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1122 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1123 .mask
= CC_S
| CC_Z
};
1130 cc
.cond
= tcg_invert_cond(cc
.cond
);
1135 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1137 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1139 if (cc
.no_setcond
) {
1140 if (cc
.cond
== TCG_COND_EQ
) {
1141 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1143 tcg_gen_mov_tl(reg
, cc
.reg
);
1148 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1149 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1150 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1151 tcg_gen_andi_tl(reg
, reg
, 1);
1154 if (cc
.mask
!= -1) {
1155 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1159 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1161 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1165 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1167 gen_setcc1(s
, JCC_B
<< 1, reg
);
1170 /* generate a conditional jump to label 'l1' according to jump opcode
1171 value 'b'. In the fast case, T0 is guaranted not to be used. */
1172 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1174 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1176 if (cc
.mask
!= -1) {
1177 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1181 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1183 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1187 /* Generate a conditional jump to label 'l1' according to jump opcode
1188 value 'b'. In the fast case, T0 is guaranted not to be used.
1189 A translation block must end soon. */
1190 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1192 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1194 gen_update_cc_op(s
);
1195 if (cc
.mask
!= -1) {
1196 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1199 set_cc_op(s
, CC_OP_DYNAMIC
);
1201 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1203 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1207 /* XXX: does not work with gdbstub "ice" single step - not a
1209 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1213 l1
= gen_new_label();
1214 l2
= gen_new_label();
1215 gen_op_jnz_ecx(s
->aflag
, l1
);
1217 gen_jmp_tb(s
, next_eip
, 1);
1222 static inline void gen_stos(DisasContext
*s
, int ot
)
1224 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
1225 gen_string_movl_A0_EDI(s
);
1226 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1227 gen_op_movl_T0_Dshift(ot
);
1228 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1231 static inline void gen_lods(DisasContext
*s
, int ot
)
1233 gen_string_movl_A0_ESI(s
);
1234 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1235 gen_op_mov_reg_T0(ot
, R_EAX
);
1236 gen_op_movl_T0_Dshift(ot
);
1237 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1240 static inline void gen_scas(DisasContext
*s
, int ot
)
1242 gen_string_movl_A0_EDI(s
);
1243 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1244 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1245 gen_op_movl_T0_Dshift(ot
);
1246 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1249 static inline void gen_cmps(DisasContext
*s
, int ot
)
1251 gen_string_movl_A0_EDI(s
);
1252 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
1253 gen_string_movl_A0_ESI(s
);
1254 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1255 gen_op_movl_T0_Dshift(ot
);
1256 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1257 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1260 static inline void gen_ins(DisasContext
*s
, int ot
)
1264 gen_string_movl_A0_EDI(s
);
1265 /* Note: we must do this dummy write first to be restartable in
1266 case of page fault. */
1268 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1269 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1270 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1271 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1272 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1273 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1274 gen_op_movl_T0_Dshift(ot
);
1275 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1280 static inline void gen_outs(DisasContext
*s
, int ot
)
1284 gen_string_movl_A0_ESI(s
);
1285 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1287 gen_op_mov_TN_reg(OT_WORD
, 1, R_EDX
);
1288 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1289 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1290 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1291 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1293 gen_op_movl_T0_Dshift(ot
);
1294 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1299 /* same method as Valgrind : we generate jumps to current or next
1301 #define GEN_REPZ(op) \
1302 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1303 target_ulong cur_eip, target_ulong next_eip) \
1306 gen_update_cc_op(s); \
1307 l2 = gen_jz_ecx_string(s, next_eip); \
1308 gen_ ## op(s, ot); \
1309 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1310 /* a loop would cause two single step exceptions if ECX = 1 \
1311 before rep string_insn */ \
1313 gen_op_jz_ecx(s->aflag, l2); \
1314 gen_jmp(s, cur_eip); \
1317 #define GEN_REPZ2(op) \
1318 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1319 target_ulong cur_eip, \
1320 target_ulong next_eip, \
1324 gen_update_cc_op(s); \
1325 l2 = gen_jz_ecx_string(s, next_eip); \
1326 gen_ ## op(s, ot); \
1327 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1328 gen_update_cc_op(s); \
1329 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1331 gen_op_jz_ecx(s->aflag, l2); \
1332 gen_jmp(s, cur_eip); \
1343 static void gen_helper_fp_arith_ST0_FT0(int op
)
1347 gen_helper_fadd_ST0_FT0(cpu_env
);
1350 gen_helper_fmul_ST0_FT0(cpu_env
);
1353 gen_helper_fcom_ST0_FT0(cpu_env
);
1356 gen_helper_fcom_ST0_FT0(cpu_env
);
1359 gen_helper_fsub_ST0_FT0(cpu_env
);
1362 gen_helper_fsubr_ST0_FT0(cpu_env
);
1365 gen_helper_fdiv_ST0_FT0(cpu_env
);
1368 gen_helper_fdivr_ST0_FT0(cpu_env
);
1373 /* NOTE the exception in "r" op ordering */
1374 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1376 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1379 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1382 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1385 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1388 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1391 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1394 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1399 /* if d == OR_TMP0, it means memory operand (address in A0) */
1400 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1403 gen_op_mov_TN_reg(ot
, 0, d
);
1405 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1409 gen_compute_eflags_c(s1
, cpu_tmp4
);
1410 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1411 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1413 gen_op_mov_reg_T0(ot
, d
);
1415 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1416 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1417 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1418 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1419 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1420 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_ADDB
+ ot
);
1421 set_cc_op(s1
, CC_OP_DYNAMIC
);
1424 gen_compute_eflags_c(s1
, cpu_tmp4
);
1425 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1426 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1428 gen_op_mov_reg_T0(ot
, d
);
1430 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1431 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1432 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1433 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp4
);
1434 tcg_gen_shli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 2);
1435 tcg_gen_addi_i32(cpu_cc_op
, cpu_tmp2_i32
, CC_OP_SUBB
+ ot
);
1436 set_cc_op(s1
, CC_OP_DYNAMIC
);
1439 gen_op_addl_T0_T1();
1441 gen_op_mov_reg_T0(ot
, d
);
1443 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1444 gen_op_update2_cc();
1445 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1448 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1450 gen_op_mov_reg_T0(ot
, d
);
1452 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1453 gen_op_update2_cc();
1454 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1458 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1460 gen_op_mov_reg_T0(ot
, d
);
1462 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1463 gen_op_update1_cc();
1464 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1467 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1469 gen_op_mov_reg_T0(ot
, d
);
1471 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1472 gen_op_update1_cc();
1473 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1476 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1478 gen_op_mov_reg_T0(ot
, d
);
1480 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1481 gen_op_update1_cc();
1482 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1485 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1486 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1487 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1492 /* if d == OR_TMP0, it means memory operand (address in A0) */
1493 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1496 gen_op_mov_TN_reg(ot
, 0, d
);
1498 gen_op_ld_T0_A0(ot
+ s1
->mem_index
);
1499 gen_compute_eflags_c(s1
, cpu_cc_src
);
1501 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1502 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1504 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1505 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1508 gen_op_mov_reg_T0(ot
, d
);
1510 gen_op_st_T0_A0(ot
+ s1
->mem_index
);
1511 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1514 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1515 int is_right
, int is_arith
)
1521 if (ot
== OT_QUAD
) {
1528 if (op1
== OR_TMP0
) {
1529 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1531 gen_op_mov_TN_reg(ot
, 0, op1
);
1534 t0
= tcg_temp_local_new();
1535 t1
= tcg_temp_local_new();
1536 t2
= tcg_temp_local_new();
1538 tcg_gen_andi_tl(t2
, cpu_T
[1], mask
);
1542 gen_exts(ot
, cpu_T
[0]);
1543 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1544 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], t2
);
1546 gen_extu(ot
, cpu_T
[0]);
1547 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1548 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], t2
);
1551 tcg_gen_mov_tl(t0
, cpu_T
[0]);
1552 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], t2
);
1556 if (op1
== OR_TMP0
) {
1557 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1559 gen_op_mov_reg_T0(ot
, op1
);
1563 gen_update_cc_op(s
);
1565 tcg_gen_mov_tl(t1
, cpu_T
[0]);
1567 shift_label
= gen_new_label();
1568 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, shift_label
);
1570 tcg_gen_addi_tl(t2
, t2
, -1);
1571 tcg_gen_mov_tl(cpu_cc_dst
, t1
);
1575 tcg_gen_sar_tl(cpu_cc_src
, t0
, t2
);
1577 tcg_gen_shr_tl(cpu_cc_src
, t0
, t2
);
1580 tcg_gen_shl_tl(cpu_cc_src
, t0
, t2
);
1584 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1586 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1589 gen_set_label(shift_label
);
1590 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
1597 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1598 int is_right
, int is_arith
)
1609 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1611 gen_op_mov_TN_reg(ot
, 0, op1
);
1617 gen_exts(ot
, cpu_T
[0]);
1618 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1619 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1621 gen_extu(ot
, cpu_T
[0]);
1622 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1623 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1626 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1627 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1633 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1635 gen_op_mov_reg_T0(ot
, op1
);
1637 /* update eflags if non zero shift */
1639 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1640 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1641 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1645 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1648 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1650 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1653 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
,
1657 int label1
, label2
, data_bits
;
1658 TCGv t0
, t1
, t2
, a0
;
1660 /* XXX: inefficient, but we must use local temps */
1661 t0
= tcg_temp_local_new();
1662 t1
= tcg_temp_local_new();
1663 t2
= tcg_temp_local_new();
1664 a0
= tcg_temp_local_new();
1672 if (op1
== OR_TMP0
) {
1673 tcg_gen_mov_tl(a0
, cpu_A0
);
1674 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1676 gen_op_mov_v_reg(ot
, t0
, op1
);
1679 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1681 tcg_gen_andi_tl(t1
, t1
, mask
);
1683 /* Must test zero case to avoid using undefined behaviour in TCG
1685 label1
= gen_new_label();
1686 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label1
);
1689 tcg_gen_andi_tl(cpu_tmp0
, t1
, (1 << (3 + ot
)) - 1);
1691 tcg_gen_mov_tl(cpu_tmp0
, t1
);
1694 tcg_gen_mov_tl(t2
, t0
);
1696 data_bits
= 8 << ot
;
1697 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1698 fix TCG definition) */
1700 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1701 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1702 tcg_gen_shl_tl(t0
, t0
, cpu_tmp0
);
1704 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp0
);
1705 tcg_gen_subfi_tl(cpu_tmp0
, data_bits
, cpu_tmp0
);
1706 tcg_gen_shr_tl(t0
, t0
, cpu_tmp0
);
1708 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1710 gen_set_label(label1
);
1712 if (op1
== OR_TMP0
) {
1713 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1715 gen_op_mov_reg_v(ot
, op1
, t0
);
1718 /* update eflags. It is needed anyway most of the time, do it always. */
1719 gen_compute_eflags(s
);
1720 assert(s
->cc_op
== CC_OP_EFLAGS
);
1722 label2
= gen_new_label();
1723 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, label2
);
1725 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1726 tcg_gen_xor_tl(cpu_tmp0
, t2
, t0
);
1727 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1728 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1729 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1731 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1733 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1734 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1736 gen_set_label(label2
);
1744 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1751 /* XXX: inefficient, but we must use local temps */
1752 t0
= tcg_temp_local_new();
1753 t1
= tcg_temp_local_new();
1754 a0
= tcg_temp_local_new();
1762 if (op1
== OR_TMP0
) {
1763 tcg_gen_mov_tl(a0
, cpu_A0
);
1764 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1766 gen_op_mov_v_reg(ot
, t0
, op1
);
1770 tcg_gen_mov_tl(t1
, t0
);
1773 data_bits
= 8 << ot
;
1775 int shift
= op2
& ((1 << (3 + ot
)) - 1);
1777 tcg_gen_shri_tl(cpu_tmp4
, t0
, shift
);
1778 tcg_gen_shli_tl(t0
, t0
, data_bits
- shift
);
1781 tcg_gen_shli_tl(cpu_tmp4
, t0
, shift
);
1782 tcg_gen_shri_tl(t0
, t0
, data_bits
- shift
);
1784 tcg_gen_or_tl(t0
, t0
, cpu_tmp4
);
1788 if (op1
== OR_TMP0
) {
1789 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1791 gen_op_mov_reg_v(ot
, op1
, t0
);
1796 gen_compute_eflags(s
);
1797 assert(s
->cc_op
== CC_OP_EFLAGS
);
1799 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~(CC_O
| CC_C
));
1800 tcg_gen_xor_tl(cpu_tmp0
, t1
, t0
);
1801 tcg_gen_lshift(cpu_tmp0
, cpu_tmp0
, 11 - (data_bits
- 1));
1802 tcg_gen_andi_tl(cpu_tmp0
, cpu_tmp0
, CC_O
);
1803 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_tmp0
);
1805 tcg_gen_shri_tl(t0
, t0
, data_bits
- 1);
1807 tcg_gen_andi_tl(t0
, t0
, CC_C
);
1808 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t0
);
1816 /* XXX: add faster immediate = 1 case */
1817 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1820 gen_compute_eflags(s
);
1821 assert(s
->cc_op
== CC_OP_EFLAGS
);
1825 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
1827 gen_op_mov_TN_reg(ot
, 0, op1
);
1832 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1835 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1838 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1840 #ifdef TARGET_X86_64
1842 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1849 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1852 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1855 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1857 #ifdef TARGET_X86_64
1859 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1866 gen_op_st_T0_A0(ot
+ s
->mem_index
);
1868 gen_op_mov_reg_T0(ot
, op1
);
1871 /* XXX: add faster immediate case */
1872 static void gen_shiftd_rm_T1(DisasContext
*s
, int ot
, int op1
,
1873 int is_right
, TCGv count
)
1875 int label1
, label2
, data_bits
;
1877 TCGv t0
, t1
, t2
, a0
;
1879 t0
= tcg_temp_local_new();
1880 t1
= tcg_temp_local_new();
1881 t2
= tcg_temp_local_new();
1882 a0
= tcg_temp_local_new();
1890 if (op1
== OR_TMP0
) {
1891 tcg_gen_mov_tl(a0
, cpu_A0
);
1892 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
1894 gen_op_mov_v_reg(ot
, t0
, op1
);
1897 tcg_gen_andi_tl(t2
, count
, mask
);
1898 tcg_gen_mov_tl(t1
, cpu_T
[1]);
1900 /* Must test zero case to avoid using undefined behaviour in TCG
1902 label1
= gen_new_label();
1903 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
1905 tcg_gen_addi_tl(cpu_tmp5
, t2
, -1);
1906 if (ot
== OT_WORD
) {
1907 /* Note: we implement the Intel behaviour for shift count > 16 */
1909 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1910 tcg_gen_shli_tl(cpu_tmp0
, t1
, 16);
1911 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1912 tcg_gen_ext32u_tl(t0
, t0
);
1914 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1916 /* only needed if count > 16, but a test would complicate */
1917 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1918 tcg_gen_shl_tl(cpu_tmp0
, t0
, cpu_tmp5
);
1920 tcg_gen_shr_tl(t0
, t0
, t2
);
1922 tcg_gen_or_tl(t0
, t0
, cpu_tmp0
);
1924 /* XXX: not optimal */
1925 tcg_gen_andi_tl(t0
, t0
, 0xffff);
1926 tcg_gen_shli_tl(t1
, t1
, 16);
1927 tcg_gen_or_tl(t1
, t1
, t0
);
1928 tcg_gen_ext32u_tl(t1
, t1
);
1930 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1931 tcg_gen_subfi_tl(cpu_tmp0
, 32, cpu_tmp5
);
1932 tcg_gen_shr_tl(cpu_tmp5
, t1
, cpu_tmp0
);
1933 tcg_gen_or_tl(cpu_tmp4
, cpu_tmp4
, cpu_tmp5
);
1935 tcg_gen_shl_tl(t0
, t0
, t2
);
1936 tcg_gen_subfi_tl(cpu_tmp5
, 32, t2
);
1937 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1938 tcg_gen_or_tl(t0
, t0
, t1
);
1941 data_bits
= 8 << ot
;
1944 tcg_gen_ext32u_tl(t0
, t0
);
1946 tcg_gen_shr_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1948 tcg_gen_shr_tl(t0
, t0
, t2
);
1949 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1950 tcg_gen_shl_tl(t1
, t1
, cpu_tmp5
);
1951 tcg_gen_or_tl(t0
, t0
, t1
);
1955 tcg_gen_ext32u_tl(t1
, t1
);
1957 tcg_gen_shl_tl(cpu_tmp4
, t0
, cpu_tmp5
);
1959 tcg_gen_shl_tl(t0
, t0
, t2
);
1960 tcg_gen_subfi_tl(cpu_tmp5
, data_bits
, t2
);
1961 tcg_gen_shr_tl(t1
, t1
, cpu_tmp5
);
1962 tcg_gen_or_tl(t0
, t0
, t1
);
1965 tcg_gen_mov_tl(t1
, cpu_tmp4
);
1967 gen_set_label(label1
);
1969 if (op1
== OR_TMP0
) {
1970 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
1972 gen_op_mov_reg_v(ot
, op1
, t0
);
1976 gen_update_cc_op(s
);
1978 label2
= gen_new_label();
1979 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label2
);
1981 tcg_gen_mov_tl(cpu_cc_src
, t1
);
1982 tcg_gen_mov_tl(cpu_cc_dst
, t0
);
1984 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SARB
+ ot
);
1986 tcg_gen_movi_i32(cpu_cc_op
, CC_OP_SHLB
+ ot
);
1988 gen_set_label(label2
);
1989 set_cc_op(s
, CC_OP_DYNAMIC
); /* cannot predict flags after */
1997 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
2000 gen_op_mov_TN_reg(ot
, 1, s
);
2003 gen_rot_rm_T1(s1
, ot
, d
, 0);
2006 gen_rot_rm_T1(s1
, ot
, d
, 1);
2010 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
2013 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
2016 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
2019 gen_rotc_rm_T1(s1
, ot
, d
, 0);
2022 gen_rotc_rm_T1(s1
, ot
, d
, 1);
2027 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
2031 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
2034 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
2038 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
2041 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
2044 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
2047 /* currently not optimized */
2048 gen_op_movl_T1_im(c
);
2049 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
2054 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2055 int *reg_ptr
, int *offset_ptr
)
2063 int mod
, rm
, code
, override
, must_add_seg
;
2065 override
= s
->override
;
2066 must_add_seg
= s
->addseg
;
2069 mod
= (modrm
>> 6) & 3;
2081 code
= cpu_ldub_code(env
, s
->pc
++);
2082 scale
= (code
>> 6) & 3;
2083 index
= ((code
>> 3) & 7) | REX_X(s
);
2090 if ((base
& 7) == 5) {
2092 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2094 if (CODE64(s
) && !havesib
) {
2095 disp
+= s
->pc
+ s
->rip_offset
;
2102 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2106 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2112 /* for correct popl handling with esp */
2113 if (base
== 4 && s
->popl_esp_hack
)
2114 disp
+= s
->popl_esp_hack
;
2115 #ifdef TARGET_X86_64
2116 if (s
->aflag
== 2) {
2117 gen_op_movq_A0_reg(base
);
2119 gen_op_addq_A0_im(disp
);
2124 gen_op_movl_A0_reg(base
);
2126 gen_op_addl_A0_im(disp
);
2129 #ifdef TARGET_X86_64
2130 if (s
->aflag
== 2) {
2131 gen_op_movq_A0_im(disp
);
2135 gen_op_movl_A0_im(disp
);
2138 /* index == 4 means no index */
2139 if (havesib
&& (index
!= 4)) {
2140 #ifdef TARGET_X86_64
2141 if (s
->aflag
== 2) {
2142 gen_op_addq_A0_reg_sN(scale
, index
);
2146 gen_op_addl_A0_reg_sN(scale
, index
);
2151 if (base
== R_EBP
|| base
== R_ESP
)
2156 #ifdef TARGET_X86_64
2157 if (s
->aflag
== 2) {
2158 gen_op_addq_A0_seg(override
);
2162 gen_op_addl_A0_seg(s
, override
);
2169 disp
= cpu_lduw_code(env
, s
->pc
);
2171 gen_op_movl_A0_im(disp
);
2172 rm
= 0; /* avoid SS override */
2179 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2183 disp
= cpu_lduw_code(env
, s
->pc
);
2189 gen_op_movl_A0_reg(R_EBX
);
2190 gen_op_addl_A0_reg_sN(0, R_ESI
);
2193 gen_op_movl_A0_reg(R_EBX
);
2194 gen_op_addl_A0_reg_sN(0, R_EDI
);
2197 gen_op_movl_A0_reg(R_EBP
);
2198 gen_op_addl_A0_reg_sN(0, R_ESI
);
2201 gen_op_movl_A0_reg(R_EBP
);
2202 gen_op_addl_A0_reg_sN(0, R_EDI
);
2205 gen_op_movl_A0_reg(R_ESI
);
2208 gen_op_movl_A0_reg(R_EDI
);
2211 gen_op_movl_A0_reg(R_EBP
);
2215 gen_op_movl_A0_reg(R_EBX
);
2219 gen_op_addl_A0_im(disp
);
2220 gen_op_andl_A0_ffff();
2224 if (rm
== 2 || rm
== 3 || rm
== 6)
2229 gen_op_addl_A0_seg(s
, override
);
2239 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2241 int mod
, rm
, base
, code
;
2243 mod
= (modrm
>> 6) & 3;
2253 code
= cpu_ldub_code(env
, s
->pc
++);
2289 /* used for LEA and MOV AX, mem */
2290 static void gen_add_A0_ds_seg(DisasContext
*s
)
2292 int override
, must_add_seg
;
2293 must_add_seg
= s
->addseg
;
2295 if (s
->override
>= 0) {
2296 override
= s
->override
;
2300 #ifdef TARGET_X86_64
2302 gen_op_addq_A0_seg(override
);
2306 gen_op_addl_A0_seg(s
, override
);
2311 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2313 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2314 int ot
, int reg
, int is_store
)
2316 int mod
, rm
, opreg
, disp
;
2318 mod
= (modrm
>> 6) & 3;
2319 rm
= (modrm
& 7) | REX_B(s
);
2323 gen_op_mov_TN_reg(ot
, 0, reg
);
2324 gen_op_mov_reg_T0(ot
, rm
);
2326 gen_op_mov_TN_reg(ot
, 0, rm
);
2328 gen_op_mov_reg_T0(ot
, reg
);
2331 gen_lea_modrm(env
, s
, modrm
, &opreg
, &disp
);
2334 gen_op_mov_TN_reg(ot
, 0, reg
);
2335 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2337 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
2339 gen_op_mov_reg_T0(ot
, reg
);
2344 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2350 ret
= cpu_ldub_code(env
, s
->pc
);
2354 ret
= cpu_lduw_code(env
, s
->pc
);
2359 ret
= cpu_ldl_code(env
, s
->pc
);
2366 static inline int insn_const_size(unsigned int ot
)
2374 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2376 TranslationBlock
*tb
;
2379 pc
= s
->cs_base
+ eip
;
2381 /* NOTE: we handle the case where the TB spans two pages here */
2382 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2383 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2384 /* jump to same page: we can use a direct jump */
2385 tcg_gen_goto_tb(tb_num
);
2387 tcg_gen_exit_tb((tcg_target_long
)tb
+ tb_num
);
2389 /* jump to another page: currently not optimized */
2395 static inline void gen_jcc(DisasContext
*s
, int b
,
2396 target_ulong val
, target_ulong next_eip
)
2401 l1
= gen_new_label();
2404 gen_goto_tb(s
, 0, next_eip
);
2407 gen_goto_tb(s
, 1, val
);
2408 s
->is_jmp
= DISAS_TB_JUMP
;
2410 l1
= gen_new_label();
2411 l2
= gen_new_label();
2414 gen_jmp_im(next_eip
);
2424 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, int ot
, int b
,
2429 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2431 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2432 if (cc
.mask
!= -1) {
2433 TCGv t0
= tcg_temp_new();
2434 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2438 cc
.reg2
= tcg_const_tl(cc
.imm
);
2441 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2442 cpu_T
[0], cpu_regs
[reg
]);
2443 gen_op_mov_reg_T0(ot
, reg
);
2445 if (cc
.mask
!= -1) {
2446 tcg_temp_free(cc
.reg
);
2449 tcg_temp_free(cc
.reg2
);
2453 static inline void gen_op_movl_T0_seg(int seg_reg
)
2455 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2456 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2459 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2461 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2462 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2463 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2464 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2465 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2466 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2469 /* move T0 to seg_reg and compute if the CPU state may change. Never
2470 call this function with seg_reg == R_CS */
2471 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2473 if (s
->pe
&& !s
->vm86
) {
2474 /* XXX: optimize by finding processor state dynamically */
2475 gen_update_cc_op(s
);
2476 gen_jmp_im(cur_eip
);
2477 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2478 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2479 /* abort translation because the addseg value may change or
2480 because ss32 may change. For R_SS, translation must always
2481 stop as a special handling must be done to disable hardware
2482 interrupts for the next instruction */
2483 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2484 s
->is_jmp
= DISAS_TB_JUMP
;
2486 gen_op_movl_seg_T0_vm(seg_reg
);
2487 if (seg_reg
== R_SS
)
2488 s
->is_jmp
= DISAS_TB_JUMP
;
2492 static inline int svm_is_rep(int prefixes
)
2494 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2498 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2499 uint32_t type
, uint64_t param
)
2501 /* no SVM activated; fast case */
2502 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2504 gen_update_cc_op(s
);
2505 gen_jmp_im(pc_start
- s
->cs_base
);
2506 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2507 tcg_const_i64(param
));
2511 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2513 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2516 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2518 #ifdef TARGET_X86_64
2520 gen_op_add_reg_im(2, R_ESP
, addend
);
2524 gen_op_add_reg_im(1, R_ESP
, addend
);
2526 gen_op_add_reg_im(0, R_ESP
, addend
);
2530 /* generate a push. It depends on ss32, addseg and dflag */
2531 static void gen_push_T0(DisasContext
*s
)
2533 #ifdef TARGET_X86_64
2535 gen_op_movq_A0_reg(R_ESP
);
2537 gen_op_addq_A0_im(-8);
2538 gen_op_st_T0_A0(OT_QUAD
+ s
->mem_index
);
2540 gen_op_addq_A0_im(-2);
2541 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2543 gen_op_mov_reg_A0(2, R_ESP
);
2547 gen_op_movl_A0_reg(R_ESP
);
2549 gen_op_addl_A0_im(-2);
2551 gen_op_addl_A0_im(-4);
2554 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2555 gen_op_addl_A0_seg(s
, R_SS
);
2558 gen_op_andl_A0_ffff();
2559 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2560 gen_op_addl_A0_seg(s
, R_SS
);
2562 gen_op_st_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2563 if (s
->ss32
&& !s
->addseg
)
2564 gen_op_mov_reg_A0(1, R_ESP
);
2566 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2570 /* generate a push. It depends on ss32, addseg and dflag */
2571 /* slower version for T1, only used for call Ev */
2572 static void gen_push_T1(DisasContext
*s
)
2574 #ifdef TARGET_X86_64
2576 gen_op_movq_A0_reg(R_ESP
);
2578 gen_op_addq_A0_im(-8);
2579 gen_op_st_T1_A0(OT_QUAD
+ s
->mem_index
);
2581 gen_op_addq_A0_im(-2);
2582 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
2584 gen_op_mov_reg_A0(2, R_ESP
);
2588 gen_op_movl_A0_reg(R_ESP
);
2590 gen_op_addl_A0_im(-2);
2592 gen_op_addl_A0_im(-4);
2595 gen_op_addl_A0_seg(s
, R_SS
);
2598 gen_op_andl_A0_ffff();
2599 gen_op_addl_A0_seg(s
, R_SS
);
2601 gen_op_st_T1_A0(s
->dflag
+ 1 + s
->mem_index
);
2603 if (s
->ss32
&& !s
->addseg
)
2604 gen_op_mov_reg_A0(1, R_ESP
);
2606 gen_stack_update(s
, (-2) << s
->dflag
);
2610 /* two step pop is necessary for precise exceptions */
2611 static void gen_pop_T0(DisasContext
*s
)
2613 #ifdef TARGET_X86_64
2615 gen_op_movq_A0_reg(R_ESP
);
2616 gen_op_ld_T0_A0((s
->dflag
? OT_QUAD
: OT_WORD
) + s
->mem_index
);
2620 gen_op_movl_A0_reg(R_ESP
);
2623 gen_op_addl_A0_seg(s
, R_SS
);
2625 gen_op_andl_A0_ffff();
2626 gen_op_addl_A0_seg(s
, R_SS
);
2628 gen_op_ld_T0_A0(s
->dflag
+ 1 + s
->mem_index
);
2632 static void gen_pop_update(DisasContext
*s
)
2634 #ifdef TARGET_X86_64
2635 if (CODE64(s
) && s
->dflag
) {
2636 gen_stack_update(s
, 8);
2640 gen_stack_update(s
, 2 << s
->dflag
);
2644 static void gen_stack_A0(DisasContext
*s
)
2646 gen_op_movl_A0_reg(R_ESP
);
2648 gen_op_andl_A0_ffff();
2649 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2651 gen_op_addl_A0_seg(s
, R_SS
);
2654 /* NOTE: wrap around in 16 bit not fully handled */
2655 static void gen_pusha(DisasContext
*s
)
2658 gen_op_movl_A0_reg(R_ESP
);
2659 gen_op_addl_A0_im(-16 << s
->dflag
);
2661 gen_op_andl_A0_ffff();
2662 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2664 gen_op_addl_A0_seg(s
, R_SS
);
2665 for(i
= 0;i
< 8; i
++) {
2666 gen_op_mov_TN_reg(OT_LONG
, 0, 7 - i
);
2667 gen_op_st_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2668 gen_op_addl_A0_im(2 << s
->dflag
);
2670 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2673 /* NOTE: wrap around in 16 bit not fully handled */
2674 static void gen_popa(DisasContext
*s
)
2677 gen_op_movl_A0_reg(R_ESP
);
2679 gen_op_andl_A0_ffff();
2680 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2681 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2683 gen_op_addl_A0_seg(s
, R_SS
);
2684 for(i
= 0;i
< 8; i
++) {
2685 /* ESP is not reloaded */
2687 gen_op_ld_T0_A0(OT_WORD
+ s
->dflag
+ s
->mem_index
);
2688 gen_op_mov_reg_T0(OT_WORD
+ s
->dflag
, 7 - i
);
2690 gen_op_addl_A0_im(2 << s
->dflag
);
2692 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2695 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2700 #ifdef TARGET_X86_64
2702 ot
= s
->dflag
? OT_QUAD
: OT_WORD
;
2705 gen_op_movl_A0_reg(R_ESP
);
2706 gen_op_addq_A0_im(-opsize
);
2707 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2710 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2711 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2713 /* XXX: must save state */
2714 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2715 tcg_const_i32((ot
== OT_QUAD
)),
2718 gen_op_mov_reg_T1(ot
, R_EBP
);
2719 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2720 gen_op_mov_reg_T1(OT_QUAD
, R_ESP
);
2724 ot
= s
->dflag
+ OT_WORD
;
2725 opsize
= 2 << s
->dflag
;
2727 gen_op_movl_A0_reg(R_ESP
);
2728 gen_op_addl_A0_im(-opsize
);
2730 gen_op_andl_A0_ffff();
2731 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2733 gen_op_addl_A0_seg(s
, R_SS
);
2735 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
2736 gen_op_st_T0_A0(ot
+ s
->mem_index
);
2738 /* XXX: must save state */
2739 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2740 tcg_const_i32(s
->dflag
),
2743 gen_op_mov_reg_T1(ot
, R_EBP
);
2744 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2745 gen_op_mov_reg_T1(OT_WORD
+ s
->ss32
, R_ESP
);
2749 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2751 gen_update_cc_op(s
);
2752 gen_jmp_im(cur_eip
);
2753 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2754 s
->is_jmp
= DISAS_TB_JUMP
;
2757 /* an interrupt is different from an exception because of the
2759 static void gen_interrupt(DisasContext
*s
, int intno
,
2760 target_ulong cur_eip
, target_ulong next_eip
)
2762 gen_update_cc_op(s
);
2763 gen_jmp_im(cur_eip
);
2764 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2765 tcg_const_i32(next_eip
- cur_eip
));
2766 s
->is_jmp
= DISAS_TB_JUMP
;
2769 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2771 gen_update_cc_op(s
);
2772 gen_jmp_im(cur_eip
);
2773 gen_helper_debug(cpu_env
);
2774 s
->is_jmp
= DISAS_TB_JUMP
;
2777 /* generate a generic end of block. Trace exception is also generated
2779 static void gen_eob(DisasContext
*s
)
2781 gen_update_cc_op(s
);
2782 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2783 gen_helper_reset_inhibit_irq(cpu_env
);
2785 if (s
->tb
->flags
& HF_RF_MASK
) {
2786 gen_helper_reset_rf(cpu_env
);
2788 if (s
->singlestep_enabled
) {
2789 gen_helper_debug(cpu_env
);
2791 gen_helper_single_step(cpu_env
);
2795 s
->is_jmp
= DISAS_TB_JUMP
;
2798 /* generate a jump to eip. No segment change must happen before as a
2799 direct call to the next block may occur */
2800 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2803 gen_update_cc_op(s
);
2804 gen_goto_tb(s
, tb_num
, eip
);
2805 s
->is_jmp
= DISAS_TB_JUMP
;
2812 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2814 gen_jmp_tb(s
, eip
, 0);
2817 static inline void gen_ldq_env_A0(int idx
, int offset
)
2819 int mem_index
= (idx
>> 2) - 1;
2820 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2821 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2824 static inline void gen_stq_env_A0(int idx
, int offset
)
2826 int mem_index
= (idx
>> 2) - 1;
2827 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2828 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2831 static inline void gen_ldo_env_A0(int idx
, int offset
)
2833 int mem_index
= (idx
>> 2) - 1;
2834 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2835 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2836 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2837 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2838 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2841 static inline void gen_sto_env_A0(int idx
, int offset
)
2843 int mem_index
= (idx
>> 2) - 1;
2844 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2845 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
, mem_index
);
2846 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2847 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2848 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
);
2851 static inline void gen_op_movo(int d_offset
, int s_offset
)
2853 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2854 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2855 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2856 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2859 static inline void gen_op_movq(int d_offset
, int s_offset
)
2861 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2862 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2865 static inline void gen_op_movl(int d_offset
, int s_offset
)
2867 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2868 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2871 static inline void gen_op_movq_env_0(int d_offset
)
2873 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2874 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2877 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2878 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2879 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2880 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2881 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2882 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2884 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2885 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2888 #define SSE_SPECIAL ((void *)1)
2889 #define SSE_DUMMY ((void *)2)
2891 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2892 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2893 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2895 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2896 /* 3DNow! extensions */
2897 [0x0e] = { SSE_DUMMY
}, /* femms */
2898 [0x0f] = { SSE_DUMMY
}, /* pf... */
2899 /* pure SSE operations */
2900 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2901 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2902 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2903 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2904 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2905 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2906 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2907 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2909 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2910 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2911 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2912 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2913 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2914 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2915 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2916 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2917 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2918 [0x51] = SSE_FOP(sqrt
),
2919 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2920 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2921 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2922 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2923 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2924 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2925 [0x58] = SSE_FOP(add
),
2926 [0x59] = SSE_FOP(mul
),
2927 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2928 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2929 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2930 [0x5c] = SSE_FOP(sub
),
2931 [0x5d] = SSE_FOP(min
),
2932 [0x5e] = SSE_FOP(div
),
2933 [0x5f] = SSE_FOP(max
),
2935 [0xc2] = SSE_FOP(cmpeq
),
2936 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2937 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2939 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2940 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* SSSE3/SSE4 */
2942 /* MMX ops and their SSE extensions */
2943 [0x60] = MMX_OP2(punpcklbw
),
2944 [0x61] = MMX_OP2(punpcklwd
),
2945 [0x62] = MMX_OP2(punpckldq
),
2946 [0x63] = MMX_OP2(packsswb
),
2947 [0x64] = MMX_OP2(pcmpgtb
),
2948 [0x65] = MMX_OP2(pcmpgtw
),
2949 [0x66] = MMX_OP2(pcmpgtl
),
2950 [0x67] = MMX_OP2(packuswb
),
2951 [0x68] = MMX_OP2(punpckhbw
),
2952 [0x69] = MMX_OP2(punpckhwd
),
2953 [0x6a] = MMX_OP2(punpckhdq
),
2954 [0x6b] = MMX_OP2(packssdw
),
2955 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2956 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2957 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2958 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2959 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2960 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2961 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2962 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2963 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2964 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2965 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2966 [0x74] = MMX_OP2(pcmpeqb
),
2967 [0x75] = MMX_OP2(pcmpeqw
),
2968 [0x76] = MMX_OP2(pcmpeql
),
2969 [0x77] = { SSE_DUMMY
}, /* emms */
2970 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2971 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2972 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2973 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2974 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2975 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2976 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2977 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2978 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2979 [0xd1] = MMX_OP2(psrlw
),
2980 [0xd2] = MMX_OP2(psrld
),
2981 [0xd3] = MMX_OP2(psrlq
),
2982 [0xd4] = MMX_OP2(paddq
),
2983 [0xd5] = MMX_OP2(pmullw
),
2984 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2985 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2986 [0xd8] = MMX_OP2(psubusb
),
2987 [0xd9] = MMX_OP2(psubusw
),
2988 [0xda] = MMX_OP2(pminub
),
2989 [0xdb] = MMX_OP2(pand
),
2990 [0xdc] = MMX_OP2(paddusb
),
2991 [0xdd] = MMX_OP2(paddusw
),
2992 [0xde] = MMX_OP2(pmaxub
),
2993 [0xdf] = MMX_OP2(pandn
),
2994 [0xe0] = MMX_OP2(pavgb
),
2995 [0xe1] = MMX_OP2(psraw
),
2996 [0xe2] = MMX_OP2(psrad
),
2997 [0xe3] = MMX_OP2(pavgw
),
2998 [0xe4] = MMX_OP2(pmulhuw
),
2999 [0xe5] = MMX_OP2(pmulhw
),
3000 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
3001 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
3002 [0xe8] = MMX_OP2(psubsb
),
3003 [0xe9] = MMX_OP2(psubsw
),
3004 [0xea] = MMX_OP2(pminsw
),
3005 [0xeb] = MMX_OP2(por
),
3006 [0xec] = MMX_OP2(paddsb
),
3007 [0xed] = MMX_OP2(paddsw
),
3008 [0xee] = MMX_OP2(pmaxsw
),
3009 [0xef] = MMX_OP2(pxor
),
3010 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
3011 [0xf1] = MMX_OP2(psllw
),
3012 [0xf2] = MMX_OP2(pslld
),
3013 [0xf3] = MMX_OP2(psllq
),
3014 [0xf4] = MMX_OP2(pmuludq
),
3015 [0xf5] = MMX_OP2(pmaddwd
),
3016 [0xf6] = MMX_OP2(psadbw
),
3017 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
3018 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
3019 [0xf8] = MMX_OP2(psubb
),
3020 [0xf9] = MMX_OP2(psubw
),
3021 [0xfa] = MMX_OP2(psubl
),
3022 [0xfb] = MMX_OP2(psubq
),
3023 [0xfc] = MMX_OP2(paddb
),
3024 [0xfd] = MMX_OP2(paddw
),
3025 [0xfe] = MMX_OP2(paddl
),
3028 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
3029 [0 + 2] = MMX_OP2(psrlw
),
3030 [0 + 4] = MMX_OP2(psraw
),
3031 [0 + 6] = MMX_OP2(psllw
),
3032 [8 + 2] = MMX_OP2(psrld
),
3033 [8 + 4] = MMX_OP2(psrad
),
3034 [8 + 6] = MMX_OP2(pslld
),
3035 [16 + 2] = MMX_OP2(psrlq
),
3036 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
3037 [16 + 6] = MMX_OP2(psllq
),
3038 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
3041 static const SSEFunc_0_epi sse_op_table3ai
[] = {
3042 gen_helper_cvtsi2ss
,
3046 #ifdef TARGET_X86_64
3047 static const SSEFunc_0_epl sse_op_table3aq
[] = {
3048 gen_helper_cvtsq2ss
,
3053 static const SSEFunc_i_ep sse_op_table3bi
[] = {
3054 gen_helper_cvttss2si
,
3055 gen_helper_cvtss2si
,
3056 gen_helper_cvttsd2si
,
3060 #ifdef TARGET_X86_64
3061 static const SSEFunc_l_ep sse_op_table3bq
[] = {
3062 gen_helper_cvttss2sq
,
3063 gen_helper_cvtss2sq
,
3064 gen_helper_cvttsd2sq
,
3069 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
3080 static const SSEFunc_0_epp sse_op_table5
[256] = {
3081 [0x0c] = gen_helper_pi2fw
,
3082 [0x0d] = gen_helper_pi2fd
,
3083 [0x1c] = gen_helper_pf2iw
,
3084 [0x1d] = gen_helper_pf2id
,
3085 [0x8a] = gen_helper_pfnacc
,
3086 [0x8e] = gen_helper_pfpnacc
,
3087 [0x90] = gen_helper_pfcmpge
,
3088 [0x94] = gen_helper_pfmin
,
3089 [0x96] = gen_helper_pfrcp
,
3090 [0x97] = gen_helper_pfrsqrt
,
3091 [0x9a] = gen_helper_pfsub
,
3092 [0x9e] = gen_helper_pfadd
,
3093 [0xa0] = gen_helper_pfcmpgt
,
3094 [0xa4] = gen_helper_pfmax
,
3095 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
3096 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
3097 [0xaa] = gen_helper_pfsubr
,
3098 [0xae] = gen_helper_pfacc
,
3099 [0xb0] = gen_helper_pfcmpeq
,
3100 [0xb4] = gen_helper_pfmul
,
3101 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3102 [0xb7] = gen_helper_pmulhrw_mmx
,
3103 [0xbb] = gen_helper_pswapd
,
3104 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3107 struct SSEOpHelper_epp
{
3108 SSEFunc_0_epp op
[2];
3112 struct SSEOpHelper_eppi
{
3113 SSEFunc_0_eppi op
[2];
3117 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3118 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3119 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3120 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3122 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3123 [0x00] = SSSE3_OP(pshufb
),
3124 [0x01] = SSSE3_OP(phaddw
),
3125 [0x02] = SSSE3_OP(phaddd
),
3126 [0x03] = SSSE3_OP(phaddsw
),
3127 [0x04] = SSSE3_OP(pmaddubsw
),
3128 [0x05] = SSSE3_OP(phsubw
),
3129 [0x06] = SSSE3_OP(phsubd
),
3130 [0x07] = SSSE3_OP(phsubsw
),
3131 [0x08] = SSSE3_OP(psignb
),
3132 [0x09] = SSSE3_OP(psignw
),
3133 [0x0a] = SSSE3_OP(psignd
),
3134 [0x0b] = SSSE3_OP(pmulhrsw
),
3135 [0x10] = SSE41_OP(pblendvb
),
3136 [0x14] = SSE41_OP(blendvps
),
3137 [0x15] = SSE41_OP(blendvpd
),
3138 [0x17] = SSE41_OP(ptest
),
3139 [0x1c] = SSSE3_OP(pabsb
),
3140 [0x1d] = SSSE3_OP(pabsw
),
3141 [0x1e] = SSSE3_OP(pabsd
),
3142 [0x20] = SSE41_OP(pmovsxbw
),
3143 [0x21] = SSE41_OP(pmovsxbd
),
3144 [0x22] = SSE41_OP(pmovsxbq
),
3145 [0x23] = SSE41_OP(pmovsxwd
),
3146 [0x24] = SSE41_OP(pmovsxwq
),
3147 [0x25] = SSE41_OP(pmovsxdq
),
3148 [0x28] = SSE41_OP(pmuldq
),
3149 [0x29] = SSE41_OP(pcmpeqq
),
3150 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3151 [0x2b] = SSE41_OP(packusdw
),
3152 [0x30] = SSE41_OP(pmovzxbw
),
3153 [0x31] = SSE41_OP(pmovzxbd
),
3154 [0x32] = SSE41_OP(pmovzxbq
),
3155 [0x33] = SSE41_OP(pmovzxwd
),
3156 [0x34] = SSE41_OP(pmovzxwq
),
3157 [0x35] = SSE41_OP(pmovzxdq
),
3158 [0x37] = SSE42_OP(pcmpgtq
),
3159 [0x38] = SSE41_OP(pminsb
),
3160 [0x39] = SSE41_OP(pminsd
),
3161 [0x3a] = SSE41_OP(pminuw
),
3162 [0x3b] = SSE41_OP(pminud
),
3163 [0x3c] = SSE41_OP(pmaxsb
),
3164 [0x3d] = SSE41_OP(pmaxsd
),
3165 [0x3e] = SSE41_OP(pmaxuw
),
3166 [0x3f] = SSE41_OP(pmaxud
),
3167 [0x40] = SSE41_OP(pmulld
),
3168 [0x41] = SSE41_OP(phminposuw
),
3171 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3172 [0x08] = SSE41_OP(roundps
),
3173 [0x09] = SSE41_OP(roundpd
),
3174 [0x0a] = SSE41_OP(roundss
),
3175 [0x0b] = SSE41_OP(roundsd
),
3176 [0x0c] = SSE41_OP(blendps
),
3177 [0x0d] = SSE41_OP(blendpd
),
3178 [0x0e] = SSE41_OP(pblendw
),
3179 [0x0f] = SSSE3_OP(palignr
),
3180 [0x14] = SSE41_SPECIAL
, /* pextrb */
3181 [0x15] = SSE41_SPECIAL
, /* pextrw */
3182 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3183 [0x17] = SSE41_SPECIAL
, /* extractps */
3184 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3185 [0x21] = SSE41_SPECIAL
, /* insertps */
3186 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3187 [0x40] = SSE41_OP(dpps
),
3188 [0x41] = SSE41_OP(dppd
),
3189 [0x42] = SSE41_OP(mpsadbw
),
3190 [0x60] = SSE42_OP(pcmpestrm
),
3191 [0x61] = SSE42_OP(pcmpestri
),
3192 [0x62] = SSE42_OP(pcmpistrm
),
3193 [0x63] = SSE42_OP(pcmpistri
),
3196 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3197 target_ulong pc_start
, int rex_r
)
3199 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3200 int modrm
, mod
, rm
, reg
, reg_addr
, offset_addr
;
3201 SSEFunc_0_epp sse_fn_epp
;
3202 SSEFunc_0_eppi sse_fn_eppi
;
3203 SSEFunc_0_ppi sse_fn_ppi
;
3204 SSEFunc_0_eppt sse_fn_eppt
;
3207 if (s
->prefix
& PREFIX_DATA
)
3209 else if (s
->prefix
& PREFIX_REPZ
)
3211 else if (s
->prefix
& PREFIX_REPNZ
)
3215 sse_fn_epp
= sse_op_table1
[b
][b1
];
3219 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3229 /* simple MMX/SSE operation */
3230 if (s
->flags
& HF_TS_MASK
) {
3231 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3234 if (s
->flags
& HF_EM_MASK
) {
3236 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3239 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3240 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3243 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3246 gen_helper_emms(cpu_env
);
3251 gen_helper_emms(cpu_env
);
3254 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3255 the static cpu state) */
3257 gen_helper_enter_mmx(cpu_env
);
3260 modrm
= cpu_ldub_code(env
, s
->pc
++);
3261 reg
= ((modrm
>> 3) & 7);
3264 mod
= (modrm
>> 6) & 3;
3265 if (sse_fn_epp
== SSE_SPECIAL
) {
3268 case 0x0e7: /* movntq */
3271 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3272 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3274 case 0x1e7: /* movntdq */
3275 case 0x02b: /* movntps */
3276 case 0x12b: /* movntps */
3279 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3280 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3282 case 0x3f0: /* lddqu */
3285 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3286 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3288 case 0x22b: /* movntss */
3289 case 0x32b: /* movntsd */
3292 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3294 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,
3297 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3298 xmm_regs
[reg
].XMM_L(0)));
3299 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3302 case 0x6e: /* movd mm, ea */
3303 #ifdef TARGET_X86_64
3304 if (s
->dflag
== 2) {
3305 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3306 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3310 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3311 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3312 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3313 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3314 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3317 case 0x16e: /* movd xmm, ea */
3318 #ifdef TARGET_X86_64
3319 if (s
->dflag
== 2) {
3320 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 0);
3321 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3322 offsetof(CPUX86State
,xmm_regs
[reg
]));
3323 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3327 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 0);
3328 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3329 offsetof(CPUX86State
,xmm_regs
[reg
]));
3330 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3331 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3334 case 0x6f: /* movq mm, ea */
3336 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3337 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3340 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3341 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3342 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3343 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3346 case 0x010: /* movups */
3347 case 0x110: /* movupd */
3348 case 0x028: /* movaps */
3349 case 0x128: /* movapd */
3350 case 0x16f: /* movdqa xmm, ea */
3351 case 0x26f: /* movdqu xmm, ea */
3353 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3354 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3356 rm
= (modrm
& 7) | REX_B(s
);
3357 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3358 offsetof(CPUX86State
,xmm_regs
[rm
]));
3361 case 0x210: /* movss xmm, ea */
3363 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3364 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3365 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3367 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3368 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3369 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3371 rm
= (modrm
& 7) | REX_B(s
);
3372 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3373 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3376 case 0x310: /* movsd xmm, ea */
3378 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3379 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3381 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3382 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3384 rm
= (modrm
& 7) | REX_B(s
);
3385 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3386 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3389 case 0x012: /* movlps */
3390 case 0x112: /* movlpd */
3392 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3393 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3396 rm
= (modrm
& 7) | REX_B(s
);
3397 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3398 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3401 case 0x212: /* movsldup */
3403 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3404 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3406 rm
= (modrm
& 7) | REX_B(s
);
3407 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3408 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3409 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3410 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3412 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3413 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3414 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3415 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3417 case 0x312: /* movddup */
3419 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3420 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3422 rm
= (modrm
& 7) | REX_B(s
);
3423 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3424 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3426 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3427 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3429 case 0x016: /* movhps */
3430 case 0x116: /* movhpd */
3432 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3433 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3436 rm
= (modrm
& 7) | REX_B(s
);
3437 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3438 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3441 case 0x216: /* movshdup */
3443 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3444 gen_ldo_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3446 rm
= (modrm
& 7) | REX_B(s
);
3447 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3448 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3449 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3450 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3452 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3453 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3454 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3455 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3460 int bit_index
, field_length
;
3462 if (b1
== 1 && reg
!= 0)
3464 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3465 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3466 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3467 offsetof(CPUX86State
,xmm_regs
[reg
]));
3469 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3470 tcg_const_i32(bit_index
),
3471 tcg_const_i32(field_length
));
3473 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3474 tcg_const_i32(bit_index
),
3475 tcg_const_i32(field_length
));
3478 case 0x7e: /* movd ea, mm */
3479 #ifdef TARGET_X86_64
3480 if (s
->dflag
== 2) {
3481 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3482 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3483 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3487 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3488 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3489 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3492 case 0x17e: /* movd ea, xmm */
3493 #ifdef TARGET_X86_64
3494 if (s
->dflag
== 2) {
3495 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3496 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3497 gen_ldst_modrm(env
, s
, modrm
, OT_QUAD
, OR_TMP0
, 1);
3501 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3502 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3503 gen_ldst_modrm(env
, s
, modrm
, OT_LONG
, OR_TMP0
, 1);
3506 case 0x27e: /* movq xmm, ea */
3508 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3509 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3511 rm
= (modrm
& 7) | REX_B(s
);
3512 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3513 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3515 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3517 case 0x7f: /* movq ea, mm */
3519 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3520 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3523 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3524 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3527 case 0x011: /* movups */
3528 case 0x111: /* movupd */
3529 case 0x029: /* movaps */
3530 case 0x129: /* movapd */
3531 case 0x17f: /* movdqa ea, xmm */
3532 case 0x27f: /* movdqu ea, xmm */
3534 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3535 gen_sto_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
]));
3537 rm
= (modrm
& 7) | REX_B(s
);
3538 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3539 offsetof(CPUX86State
,xmm_regs
[reg
]));
3542 case 0x211: /* movss ea, xmm */
3544 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3545 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3546 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
3548 rm
= (modrm
& 7) | REX_B(s
);
3549 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3550 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3553 case 0x311: /* movsd ea, xmm */
3555 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3556 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3558 rm
= (modrm
& 7) | REX_B(s
);
3559 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3560 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3563 case 0x013: /* movlps */
3564 case 0x113: /* movlpd */
3566 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3567 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3572 case 0x017: /* movhps */
3573 case 0x117: /* movhpd */
3575 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3576 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3581 case 0x71: /* shift mm, im */
3584 case 0x171: /* shift xmm, im */
3590 val
= cpu_ldub_code(env
, s
->pc
++);
3592 gen_op_movl_T0_im(val
);
3593 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3595 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3596 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3598 gen_op_movl_T0_im(val
);
3599 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3601 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3602 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3604 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3605 (((modrm
>> 3)) & 7)][b1
];
3610 rm
= (modrm
& 7) | REX_B(s
);
3611 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3614 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3616 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3617 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3618 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3620 case 0x050: /* movmskps */
3621 rm
= (modrm
& 7) | REX_B(s
);
3622 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3623 offsetof(CPUX86State
,xmm_regs
[rm
]));
3624 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3625 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3626 gen_op_mov_reg_T0(OT_LONG
, reg
);
3628 case 0x150: /* movmskpd */
3629 rm
= (modrm
& 7) | REX_B(s
);
3630 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3631 offsetof(CPUX86State
,xmm_regs
[rm
]));
3632 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3633 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3634 gen_op_mov_reg_T0(OT_LONG
, reg
);
3636 case 0x02a: /* cvtpi2ps */
3637 case 0x12a: /* cvtpi2pd */
3638 gen_helper_enter_mmx(cpu_env
);
3640 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3641 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3642 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3645 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3647 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3648 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3649 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3652 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3656 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3660 case 0x22a: /* cvtsi2ss */
3661 case 0x32a: /* cvtsi2sd */
3662 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3663 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3664 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3665 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3666 if (ot
== OT_LONG
) {
3667 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3668 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3669 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3671 #ifdef TARGET_X86_64
3672 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3673 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3679 case 0x02c: /* cvttps2pi */
3680 case 0x12c: /* cvttpd2pi */
3681 case 0x02d: /* cvtps2pi */
3682 case 0x12d: /* cvtpd2pi */
3683 gen_helper_enter_mmx(cpu_env
);
3685 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3686 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3687 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3689 rm
= (modrm
& 7) | REX_B(s
);
3690 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3692 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3693 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3694 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3697 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3700 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3703 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3706 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3710 case 0x22c: /* cvttss2si */
3711 case 0x32c: /* cvttsd2si */
3712 case 0x22d: /* cvtss2si */
3713 case 0x32d: /* cvtsd2si */
3714 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3716 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3718 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_Q(0)));
3720 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
3721 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3723 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3725 rm
= (modrm
& 7) | REX_B(s
);
3726 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3728 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3729 if (ot
== OT_LONG
) {
3730 SSEFunc_i_ep sse_fn_i_ep
=
3731 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3732 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3733 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3735 #ifdef TARGET_X86_64
3736 SSEFunc_l_ep sse_fn_l_ep
=
3737 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3738 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3743 gen_op_mov_reg_T0(ot
, reg
);
3745 case 0xc4: /* pinsrw */
3748 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
3749 val
= cpu_ldub_code(env
, s
->pc
++);
3752 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3753 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3756 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3757 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3760 case 0xc5: /* pextrw */
3764 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3765 val
= cpu_ldub_code(env
, s
->pc
++);
3768 rm
= (modrm
& 7) | REX_B(s
);
3769 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3770 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3774 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3775 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3777 reg
= ((modrm
>> 3) & 7) | rex_r
;
3778 gen_op_mov_reg_T0(ot
, reg
);
3780 case 0x1d6: /* movq ea, xmm */
3782 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3783 gen_stq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3785 rm
= (modrm
& 7) | REX_B(s
);
3786 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3787 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3788 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3791 case 0x2d6: /* movq2dq */
3792 gen_helper_enter_mmx(cpu_env
);
3794 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3795 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3796 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3798 case 0x3d6: /* movdq2q */
3799 gen_helper_enter_mmx(cpu_env
);
3800 rm
= (modrm
& 7) | REX_B(s
);
3801 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3802 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3804 case 0xd7: /* pmovmskb */
3809 rm
= (modrm
& 7) | REX_B(s
);
3810 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3811 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3814 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3815 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3817 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3818 reg
= ((modrm
>> 3) & 7) | rex_r
;
3819 gen_op_mov_reg_T0(OT_LONG
, reg
);
3822 if (s
->prefix
& PREFIX_REPNZ
)
3826 modrm
= cpu_ldub_code(env
, s
->pc
++);
3828 reg
= ((modrm
>> 3) & 7) | rex_r
;
3829 mod
= (modrm
>> 6) & 3;
3834 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3838 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3842 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3844 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3846 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3847 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3849 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3850 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3851 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3852 gen_ldq_env_A0(s
->mem_index
, op2_offset
+
3853 offsetof(XMMReg
, XMM_Q(0)));
3855 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3856 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3857 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
3858 (s
->mem_index
>> 2) - 1);
3859 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
3860 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3861 offsetof(XMMReg
, XMM_L(0)));
3863 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3864 tcg_gen_qemu_ld16u(cpu_tmp0
, cpu_A0
,
3865 (s
->mem_index
>> 2) - 1);
3866 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3867 offsetof(XMMReg
, XMM_W(0)));
3869 case 0x2a: /* movntqda */
3870 gen_ldo_env_A0(s
->mem_index
, op1_offset
);
3873 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
3877 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3879 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3881 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3882 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3883 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
3886 if (sse_fn_epp
== SSE_SPECIAL
) {
3890 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3891 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3892 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3895 set_cc_op(s
, CC_OP_EFLAGS
);
3898 case 0x338: /* crc32 */
3901 modrm
= cpu_ldub_code(env
, s
->pc
++);
3902 reg
= ((modrm
>> 3) & 7) | rex_r
;
3904 if (b
!= 0xf0 && b
!= 0xf1)
3906 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
))
3911 else if (b
== 0xf1 && s
->dflag
!= 2)
3912 if (s
->prefix
& PREFIX_DATA
)
3919 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
3920 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3921 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3922 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3923 cpu_T
[0], tcg_const_i32(8 << ot
));
3925 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3926 gen_op_mov_reg_T0(ot
, reg
);
3931 modrm
= cpu_ldub_code(env
, s
->pc
++);
3933 reg
= ((modrm
>> 3) & 7) | rex_r
;
3934 mod
= (modrm
>> 6) & 3;
3939 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
3943 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
3946 if (sse_fn_eppi
== SSE_SPECIAL
) {
3947 ot
= (s
->dflag
== 2) ? OT_QUAD
: OT_LONG
;
3948 rm
= (modrm
& 7) | REX_B(s
);
3950 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
3951 reg
= ((modrm
>> 3) & 7) | rex_r
;
3952 val
= cpu_ldub_code(env
, s
->pc
++);
3954 case 0x14: /* pextrb */
3955 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3956 xmm_regs
[reg
].XMM_B(val
& 15)));
3958 gen_op_mov_reg_T0(ot
, rm
);
3960 tcg_gen_qemu_st8(cpu_T
[0], cpu_A0
,
3961 (s
->mem_index
>> 2) - 1);
3963 case 0x15: /* pextrw */
3964 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3965 xmm_regs
[reg
].XMM_W(val
& 7)));
3967 gen_op_mov_reg_T0(ot
, rm
);
3969 tcg_gen_qemu_st16(cpu_T
[0], cpu_A0
,
3970 (s
->mem_index
>> 2) - 1);
3973 if (ot
== OT_LONG
) { /* pextrd */
3974 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
3975 offsetof(CPUX86State
,
3976 xmm_regs
[reg
].XMM_L(val
& 3)));
3977 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3979 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
3981 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
3982 (s
->mem_index
>> 2) - 1);
3983 } else { /* pextrq */
3984 #ifdef TARGET_X86_64
3985 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3986 offsetof(CPUX86State
,
3987 xmm_regs
[reg
].XMM_Q(val
& 1)));
3989 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
3991 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
3992 (s
->mem_index
>> 2) - 1);
3998 case 0x17: /* extractps */
3999 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4000 xmm_regs
[reg
].XMM_L(val
& 3)));
4002 gen_op_mov_reg_T0(ot
, rm
);
4004 tcg_gen_qemu_st32(cpu_T
[0], cpu_A0
,
4005 (s
->mem_index
>> 2) - 1);
4007 case 0x20: /* pinsrb */
4009 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
4011 tcg_gen_qemu_ld8u(cpu_tmp0
, cpu_A0
,
4012 (s
->mem_index
>> 2) - 1);
4013 tcg_gen_st8_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
,
4014 xmm_regs
[reg
].XMM_B(val
& 15)));
4016 case 0x21: /* insertps */
4018 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4019 offsetof(CPUX86State
,xmm_regs
[rm
]
4020 .XMM_L((val
>> 6) & 3)));
4022 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4023 (s
->mem_index
>> 2) - 1);
4024 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4026 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4027 offsetof(CPUX86State
,xmm_regs
[reg
]
4028 .XMM_L((val
>> 4) & 3)));
4030 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4031 cpu_env
, offsetof(CPUX86State
,
4032 xmm_regs
[reg
].XMM_L(0)));
4034 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4035 cpu_env
, offsetof(CPUX86State
,
4036 xmm_regs
[reg
].XMM_L(1)));
4038 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4039 cpu_env
, offsetof(CPUX86State
,
4040 xmm_regs
[reg
].XMM_L(2)));
4042 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4043 cpu_env
, offsetof(CPUX86State
,
4044 xmm_regs
[reg
].XMM_L(3)));
4047 if (ot
== OT_LONG
) { /* pinsrd */
4049 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4051 tcg_gen_qemu_ld32u(cpu_tmp0
, cpu_A0
,
4052 (s
->mem_index
>> 2) - 1);
4053 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4054 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4055 offsetof(CPUX86State
,
4056 xmm_regs
[reg
].XMM_L(val
& 3)));
4057 } else { /* pinsrq */
4058 #ifdef TARGET_X86_64
4060 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4062 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
4063 (s
->mem_index
>> 2) - 1);
4064 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4065 offsetof(CPUX86State
,
4066 xmm_regs
[reg
].XMM_Q(val
& 1)));
4077 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4079 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4081 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4082 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4083 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4086 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4088 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4090 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4091 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4092 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4095 val
= cpu_ldub_code(env
, s
->pc
++);
4097 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4098 set_cc_op(s
, CC_OP_EFLAGS
);
4101 /* The helper must use entire 64-bit gp registers */
4105 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4106 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4107 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4113 /* generic MMX or SSE operation */
4115 case 0x70: /* pshufx insn */
4116 case 0xc6: /* pshufx insn */
4117 case 0xc2: /* compare insns */
4124 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4126 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4127 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4128 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4130 /* specific case for SSE single instructions */
4133 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
4134 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4137 gen_ldq_env_A0(s
->mem_index
, offsetof(CPUX86State
,xmm_t0
.XMM_D(0)));
4140 gen_ldo_env_A0(s
->mem_index
, op2_offset
);
4143 rm
= (modrm
& 7) | REX_B(s
);
4144 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4147 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4149 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4150 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4151 gen_ldq_env_A0(s
->mem_index
, op2_offset
);
4154 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4158 case 0x0f: /* 3DNow! data insns */
4159 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4161 val
= cpu_ldub_code(env
, s
->pc
++);
4162 sse_fn_epp
= sse_op_table5
[val
];
4166 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4167 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4168 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4170 case 0x70: /* pshufx insn */
4171 case 0xc6: /* pshufx insn */
4172 val
= cpu_ldub_code(env
, s
->pc
++);
4173 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4174 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4175 /* XXX: introduce a new table? */
4176 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4177 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4181 val
= cpu_ldub_code(env
, s
->pc
++);
4184 sse_fn_epp
= sse_op_table4
[val
][b1
];
4186 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4187 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4188 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4191 /* maskmov : we must prepare A0 */
4194 #ifdef TARGET_X86_64
4195 if (s
->aflag
== 2) {
4196 gen_op_movq_A0_reg(R_EDI
);
4200 gen_op_movl_A0_reg(R_EDI
);
4202 gen_op_andl_A0_ffff();
4204 gen_add_A0_ds_seg(s
);
4206 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4207 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4208 /* XXX: introduce a new table? */
4209 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4210 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4213 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4214 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4215 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4218 if (b
== 0x2e || b
== 0x2f) {
4219 set_cc_op(s
, CC_OP_EFLAGS
);
4224 /* convert one instruction. s->is_jmp is set if the translation must
4225 be stopped. Return the next pc value */
4226 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4227 target_ulong pc_start
)
4229 int b
, prefixes
, aflag
, dflag
;
4231 int modrm
, reg
, rm
, mod
, reg_addr
, op
, opreg
, offset_addr
, val
;
4232 target_ulong next_eip
, tval
;
4235 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4236 tcg_gen_debug_insn_start(pc_start
);
4245 #ifdef TARGET_X86_64
4250 s
->rip_offset
= 0; /* for relative ip address */
4252 b
= cpu_ldub_code(env
, s
->pc
);
4254 /* check prefixes */
4255 #ifdef TARGET_X86_64
4259 prefixes
|= PREFIX_REPZ
;
4262 prefixes
|= PREFIX_REPNZ
;
4265 prefixes
|= PREFIX_LOCK
;
4286 prefixes
|= PREFIX_DATA
;
4289 prefixes
|= PREFIX_ADR
;
4293 rex_w
= (b
>> 3) & 1;
4294 rex_r
= (b
& 0x4) << 1;
4295 s
->rex_x
= (b
& 0x2) << 2;
4296 REX_B(s
) = (b
& 0x1) << 3;
4297 x86_64_hregs
= 1; /* select uniform byte register addressing */
4301 /* 0x66 is ignored if rex.w is set */
4304 if (prefixes
& PREFIX_DATA
)
4307 if (!(prefixes
& PREFIX_ADR
))
4314 prefixes
|= PREFIX_REPZ
;
4317 prefixes
|= PREFIX_REPNZ
;
4320 prefixes
|= PREFIX_LOCK
;
4341 prefixes
|= PREFIX_DATA
;
4344 prefixes
|= PREFIX_ADR
;
4347 if (prefixes
& PREFIX_DATA
)
4349 if (prefixes
& PREFIX_ADR
)
4353 s
->prefix
= prefixes
;
4357 /* lock generation */
4358 if (prefixes
& PREFIX_LOCK
)
4361 /* now check op code */
4365 /**************************/
4366 /* extended op code */
4367 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4370 /**************************/
4388 ot
= dflag
+ OT_WORD
;
4391 case 0: /* OP Ev, Gv */
4392 modrm
= cpu_ldub_code(env
, s
->pc
++);
4393 reg
= ((modrm
>> 3) & 7) | rex_r
;
4394 mod
= (modrm
>> 6) & 3;
4395 rm
= (modrm
& 7) | REX_B(s
);
4397 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4399 } else if (op
== OP_XORL
&& rm
== reg
) {
4401 /* xor reg, reg optimisation */
4403 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4404 gen_op_mov_reg_T0(ot
, reg
);
4405 gen_op_update1_cc();
4410 gen_op_mov_TN_reg(ot
, 1, reg
);
4411 gen_op(s
, op
, ot
, opreg
);
4413 case 1: /* OP Gv, Ev */
4414 modrm
= cpu_ldub_code(env
, s
->pc
++);
4415 mod
= (modrm
>> 6) & 3;
4416 reg
= ((modrm
>> 3) & 7) | rex_r
;
4417 rm
= (modrm
& 7) | REX_B(s
);
4419 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4420 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4421 } else if (op
== OP_XORL
&& rm
== reg
) {
4424 gen_op_mov_TN_reg(ot
, 1, rm
);
4426 gen_op(s
, op
, ot
, reg
);
4428 case 2: /* OP A, Iv */
4429 val
= insn_get(env
, s
, ot
);
4430 gen_op_movl_T1_im(val
);
4431 gen_op(s
, op
, ot
, OR_EAX
);
4440 case 0x80: /* GRP1 */
4449 ot
= dflag
+ OT_WORD
;
4451 modrm
= cpu_ldub_code(env
, s
->pc
++);
4452 mod
= (modrm
>> 6) & 3;
4453 rm
= (modrm
& 7) | REX_B(s
);
4454 op
= (modrm
>> 3) & 7;
4460 s
->rip_offset
= insn_const_size(ot
);
4461 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4472 val
= insn_get(env
, s
, ot
);
4475 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4478 gen_op_movl_T1_im(val
);
4479 gen_op(s
, op
, ot
, opreg
);
4483 /**************************/
4484 /* inc, dec, and other misc arith */
4485 case 0x40 ... 0x47: /* inc Gv */
4486 ot
= dflag
? OT_LONG
: OT_WORD
;
4487 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4489 case 0x48 ... 0x4f: /* dec Gv */
4490 ot
= dflag
? OT_LONG
: OT_WORD
;
4491 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4493 case 0xf6: /* GRP3 */
4498 ot
= dflag
+ OT_WORD
;
4500 modrm
= cpu_ldub_code(env
, s
->pc
++);
4501 mod
= (modrm
>> 6) & 3;
4502 rm
= (modrm
& 7) | REX_B(s
);
4503 op
= (modrm
>> 3) & 7;
4506 s
->rip_offset
= insn_const_size(ot
);
4507 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4508 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4510 gen_op_mov_TN_reg(ot
, 0, rm
);
4515 val
= insn_get(env
, s
, ot
);
4516 gen_op_movl_T1_im(val
);
4517 gen_op_testl_T0_T1_cc();
4518 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4521 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4523 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4525 gen_op_mov_reg_T0(ot
, rm
);
4529 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4531 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4533 gen_op_mov_reg_T0(ot
, rm
);
4535 gen_op_update_neg_cc();
4536 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4541 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4542 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4543 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4544 /* XXX: use 32 bit mul which could be faster */
4545 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4546 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4547 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4548 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4549 set_cc_op(s
, CC_OP_MULB
);
4552 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4553 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4554 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4555 /* XXX: use 32 bit mul which could be faster */
4556 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4557 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4558 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4559 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4560 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4561 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4562 set_cc_op(s
, CC_OP_MULW
);
4566 #ifdef TARGET_X86_64
4567 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4568 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4569 tcg_gen_ext32u_tl(cpu_T
[1], cpu_T
[1]);
4570 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4571 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4572 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4573 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4574 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4575 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4579 t0
= tcg_temp_new_i64();
4580 t1
= tcg_temp_new_i64();
4581 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4582 tcg_gen_extu_i32_i64(t0
, cpu_T
[0]);
4583 tcg_gen_extu_i32_i64(t1
, cpu_T
[1]);
4584 tcg_gen_mul_i64(t0
, t0
, t1
);
4585 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4586 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4587 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4588 tcg_gen_shri_i64(t0
, t0
, 32);
4589 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4590 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4591 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4594 set_cc_op(s
, CC_OP_MULL
);
4596 #ifdef TARGET_X86_64
4598 gen_helper_mulq_EAX_T0(cpu_env
, cpu_T
[0]);
4599 set_cc_op(s
, CC_OP_MULQ
);
4607 gen_op_mov_TN_reg(OT_BYTE
, 1, R_EAX
);
4608 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4609 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4610 /* XXX: use 32 bit mul which could be faster */
4611 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4612 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4613 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4614 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4615 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4616 set_cc_op(s
, CC_OP_MULB
);
4619 gen_op_mov_TN_reg(OT_WORD
, 1, R_EAX
);
4620 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4621 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4622 /* XXX: use 32 bit mul which could be faster */
4623 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4624 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4625 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4626 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4627 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4628 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4629 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4630 set_cc_op(s
, CC_OP_MULW
);
4634 #ifdef TARGET_X86_64
4635 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4636 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4637 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4638 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4639 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4640 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4641 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4642 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4643 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 32);
4644 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4648 t0
= tcg_temp_new_i64();
4649 t1
= tcg_temp_new_i64();
4650 gen_op_mov_TN_reg(OT_LONG
, 1, R_EAX
);
4651 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4652 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4653 tcg_gen_mul_i64(t0
, t0
, t1
);
4654 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4655 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4656 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4657 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4658 tcg_gen_shri_i64(t0
, t0
, 32);
4659 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4660 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4661 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4664 set_cc_op(s
, CC_OP_MULL
);
4666 #ifdef TARGET_X86_64
4668 gen_helper_imulq_EAX_T0(cpu_env
, cpu_T
[0]);
4669 set_cc_op(s
, CC_OP_MULQ
);
4677 gen_jmp_im(pc_start
- s
->cs_base
);
4678 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4681 gen_jmp_im(pc_start
- s
->cs_base
);
4682 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4686 gen_jmp_im(pc_start
- s
->cs_base
);
4687 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4689 #ifdef TARGET_X86_64
4691 gen_jmp_im(pc_start
- s
->cs_base
);
4692 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4700 gen_jmp_im(pc_start
- s
->cs_base
);
4701 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4704 gen_jmp_im(pc_start
- s
->cs_base
);
4705 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4709 gen_jmp_im(pc_start
- s
->cs_base
);
4710 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
4712 #ifdef TARGET_X86_64
4714 gen_jmp_im(pc_start
- s
->cs_base
);
4715 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
4725 case 0xfe: /* GRP4 */
4726 case 0xff: /* GRP5 */
4730 ot
= dflag
+ OT_WORD
;
4732 modrm
= cpu_ldub_code(env
, s
->pc
++);
4733 mod
= (modrm
>> 6) & 3;
4734 rm
= (modrm
& 7) | REX_B(s
);
4735 op
= (modrm
>> 3) & 7;
4736 if (op
>= 2 && b
== 0xfe) {
4740 if (op
== 2 || op
== 4) {
4741 /* operand size for jumps is 64 bit */
4743 } else if (op
== 3 || op
== 5) {
4744 ot
= dflag
? OT_LONG
+ (rex_w
== 1) : OT_WORD
;
4745 } else if (op
== 6) {
4746 /* default push size is 64 bit */
4747 ot
= dflag
? OT_QUAD
: OT_WORD
;
4751 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4752 if (op
>= 2 && op
!= 3 && op
!= 5)
4753 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
4755 gen_op_mov_TN_reg(ot
, 0, rm
);
4759 case 0: /* inc Ev */
4764 gen_inc(s
, ot
, opreg
, 1);
4766 case 1: /* dec Ev */
4771 gen_inc(s
, ot
, opreg
, -1);
4773 case 2: /* call Ev */
4774 /* XXX: optimize if memory (no 'and' is necessary) */
4776 gen_op_andl_T0_ffff();
4777 next_eip
= s
->pc
- s
->cs_base
;
4778 gen_movtl_T1_im(next_eip
);
4783 case 3: /* lcall Ev */
4784 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4785 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4786 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4788 if (s
->pe
&& !s
->vm86
) {
4789 gen_update_cc_op(s
);
4790 gen_jmp_im(pc_start
- s
->cs_base
);
4791 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4792 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4793 tcg_const_i32(dflag
),
4794 tcg_const_i32(s
->pc
- pc_start
));
4796 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4797 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4798 tcg_const_i32(dflag
),
4799 tcg_const_i32(s
->pc
- s
->cs_base
));
4803 case 4: /* jmp Ev */
4805 gen_op_andl_T0_ffff();
4809 case 5: /* ljmp Ev */
4810 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4811 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
4812 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
4814 if (s
->pe
&& !s
->vm86
) {
4815 gen_update_cc_op(s
);
4816 gen_jmp_im(pc_start
- s
->cs_base
);
4817 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4818 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
4819 tcg_const_i32(s
->pc
- pc_start
));
4821 gen_op_movl_seg_T0_vm(R_CS
);
4822 gen_op_movl_T0_T1();
4827 case 6: /* push Ev */
4835 case 0x84: /* test Ev, Gv */
4840 ot
= dflag
+ OT_WORD
;
4842 modrm
= cpu_ldub_code(env
, s
->pc
++);
4843 reg
= ((modrm
>> 3) & 7) | rex_r
;
4845 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4846 gen_op_mov_TN_reg(ot
, 1, reg
);
4847 gen_op_testl_T0_T1_cc();
4848 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4851 case 0xa8: /* test eAX, Iv */
4856 ot
= dflag
+ OT_WORD
;
4857 val
= insn_get(env
, s
, ot
);
4859 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
4860 gen_op_movl_T1_im(val
);
4861 gen_op_testl_T0_T1_cc();
4862 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4865 case 0x98: /* CWDE/CBW */
4866 #ifdef TARGET_X86_64
4868 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4869 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4870 gen_op_mov_reg_T0(OT_QUAD
, R_EAX
);
4874 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4875 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4876 gen_op_mov_reg_T0(OT_LONG
, R_EAX
);
4878 gen_op_mov_TN_reg(OT_BYTE
, 0, R_EAX
);
4879 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4880 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
4883 case 0x99: /* CDQ/CWD */
4884 #ifdef TARGET_X86_64
4886 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
4887 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
4888 gen_op_mov_reg_T0(OT_QUAD
, R_EDX
);
4892 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
4893 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4894 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
4895 gen_op_mov_reg_T0(OT_LONG
, R_EDX
);
4897 gen_op_mov_TN_reg(OT_WORD
, 0, R_EAX
);
4898 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4899 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
4900 gen_op_mov_reg_T0(OT_WORD
, R_EDX
);
4903 case 0x1af: /* imul Gv, Ev */
4904 case 0x69: /* imul Gv, Ev, I */
4906 ot
= dflag
+ OT_WORD
;
4907 modrm
= cpu_ldub_code(env
, s
->pc
++);
4908 reg
= ((modrm
>> 3) & 7) | rex_r
;
4910 s
->rip_offset
= insn_const_size(ot
);
4913 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4915 val
= insn_get(env
, s
, ot
);
4916 gen_op_movl_T1_im(val
);
4917 } else if (b
== 0x6b) {
4918 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
4919 gen_op_movl_T1_im(val
);
4921 gen_op_mov_TN_reg(ot
, 1, reg
);
4924 #ifdef TARGET_X86_64
4925 if (ot
== OT_QUAD
) {
4926 gen_helper_imulq_T0_T1(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
4929 if (ot
== OT_LONG
) {
4930 #ifdef TARGET_X86_64
4931 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4932 tcg_gen_ext32s_tl(cpu_T
[1], cpu_T
[1]);
4933 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4934 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4935 tcg_gen_ext32s_tl(cpu_tmp0
, cpu_T
[0]);
4936 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4940 t0
= tcg_temp_new_i64();
4941 t1
= tcg_temp_new_i64();
4942 tcg_gen_ext_i32_i64(t0
, cpu_T
[0]);
4943 tcg_gen_ext_i32_i64(t1
, cpu_T
[1]);
4944 tcg_gen_mul_i64(t0
, t0
, t1
);
4945 tcg_gen_trunc_i64_i32(cpu_T
[0], t0
);
4946 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4947 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[0], 31);
4948 tcg_gen_shri_i64(t0
, t0
, 32);
4949 tcg_gen_trunc_i64_i32(cpu_T
[1], t0
);
4950 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[1], cpu_tmp0
);
4954 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4955 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4956 /* XXX: use 32 bit mul which could be faster */
4957 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4958 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4959 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4960 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4962 gen_op_mov_reg_T0(ot
, reg
);
4963 set_cc_op(s
, CC_OP_MULB
+ ot
);
4966 case 0x1c1: /* xadd Ev, Gv */
4970 ot
= dflag
+ OT_WORD
;
4971 modrm
= cpu_ldub_code(env
, s
->pc
++);
4972 reg
= ((modrm
>> 3) & 7) | rex_r
;
4973 mod
= (modrm
>> 6) & 3;
4975 rm
= (modrm
& 7) | REX_B(s
);
4976 gen_op_mov_TN_reg(ot
, 0, reg
);
4977 gen_op_mov_TN_reg(ot
, 1, rm
);
4978 gen_op_addl_T0_T1();
4979 gen_op_mov_reg_T1(ot
, reg
);
4980 gen_op_mov_reg_T0(ot
, rm
);
4982 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
4983 gen_op_mov_TN_reg(ot
, 0, reg
);
4984 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
4985 gen_op_addl_T0_T1();
4986 gen_op_st_T0_A0(ot
+ s
->mem_index
);
4987 gen_op_mov_reg_T1(ot
, reg
);
4989 gen_op_update2_cc();
4990 set_cc_op(s
, CC_OP_ADDB
+ ot
);
4993 case 0x1b1: /* cmpxchg Ev, Gv */
4996 TCGv t0
, t1
, t2
, a0
;
5001 ot
= dflag
+ OT_WORD
;
5002 modrm
= cpu_ldub_code(env
, s
->pc
++);
5003 reg
= ((modrm
>> 3) & 7) | rex_r
;
5004 mod
= (modrm
>> 6) & 3;
5005 t0
= tcg_temp_local_new();
5006 t1
= tcg_temp_local_new();
5007 t2
= tcg_temp_local_new();
5008 a0
= tcg_temp_local_new();
5009 gen_op_mov_v_reg(ot
, t1
, reg
);
5011 rm
= (modrm
& 7) | REX_B(s
);
5012 gen_op_mov_v_reg(ot
, t0
, rm
);
5014 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5015 tcg_gen_mov_tl(a0
, cpu_A0
);
5016 gen_op_ld_v(ot
+ s
->mem_index
, t0
, a0
);
5017 rm
= 0; /* avoid warning */
5019 label1
= gen_new_label();
5020 tcg_gen_sub_tl(t2
, cpu_regs
[R_EAX
], t0
);
5022 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, label1
);
5023 label2
= gen_new_label();
5025 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5027 gen_set_label(label1
);
5028 gen_op_mov_reg_v(ot
, rm
, t1
);
5030 /* perform no-op store cycle like physical cpu; must be
5031 before changing accumulator to ensure idempotency if
5032 the store faults and the instruction is restarted */
5033 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
5034 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5036 gen_set_label(label1
);
5037 gen_op_st_v(ot
+ s
->mem_index
, t1
, a0
);
5039 gen_set_label(label2
);
5040 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5041 tcg_gen_mov_tl(cpu_cc_dst
, t2
);
5042 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5049 case 0x1c7: /* cmpxchg8b */
5050 modrm
= cpu_ldub_code(env
, s
->pc
++);
5051 mod
= (modrm
>> 6) & 3;
5052 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5054 #ifdef TARGET_X86_64
5056 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5058 gen_jmp_im(pc_start
- s
->cs_base
);
5059 gen_update_cc_op(s
);
5060 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5061 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5065 if (!(s
->cpuid_features
& CPUID_CX8
))
5067 gen_jmp_im(pc_start
- s
->cs_base
);
5068 gen_update_cc_op(s
);
5069 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5070 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5072 set_cc_op(s
, CC_OP_EFLAGS
);
5075 /**************************/
5077 case 0x50 ... 0x57: /* push */
5078 gen_op_mov_TN_reg(OT_LONG
, 0, (b
& 7) | REX_B(s
));
5081 case 0x58 ... 0x5f: /* pop */
5083 ot
= dflag
? OT_QUAD
: OT_WORD
;
5085 ot
= dflag
+ OT_WORD
;
5088 /* NOTE: order is important for pop %sp */
5090 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5092 case 0x60: /* pusha */
5097 case 0x61: /* popa */
5102 case 0x68: /* push Iv */
5105 ot
= dflag
? OT_QUAD
: OT_WORD
;
5107 ot
= dflag
+ OT_WORD
;
5110 val
= insn_get(env
, s
, ot
);
5112 val
= (int8_t)insn_get(env
, s
, OT_BYTE
);
5113 gen_op_movl_T0_im(val
);
5116 case 0x8f: /* pop Ev */
5118 ot
= dflag
? OT_QUAD
: OT_WORD
;
5120 ot
= dflag
+ OT_WORD
;
5122 modrm
= cpu_ldub_code(env
, s
->pc
++);
5123 mod
= (modrm
>> 6) & 3;
5126 /* NOTE: order is important for pop %sp */
5128 rm
= (modrm
& 7) | REX_B(s
);
5129 gen_op_mov_reg_T0(ot
, rm
);
5131 /* NOTE: order is important too for MMU exceptions */
5132 s
->popl_esp_hack
= 1 << ot
;
5133 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5134 s
->popl_esp_hack
= 0;
5138 case 0xc8: /* enter */
5141 val
= cpu_lduw_code(env
, s
->pc
);
5143 level
= cpu_ldub_code(env
, s
->pc
++);
5144 gen_enter(s
, val
, level
);
5147 case 0xc9: /* leave */
5148 /* XXX: exception not precise (ESP is updated before potential exception) */
5150 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EBP
);
5151 gen_op_mov_reg_T0(OT_QUAD
, R_ESP
);
5152 } else if (s
->ss32
) {
5153 gen_op_mov_TN_reg(OT_LONG
, 0, R_EBP
);
5154 gen_op_mov_reg_T0(OT_LONG
, R_ESP
);
5156 gen_op_mov_TN_reg(OT_WORD
, 0, R_EBP
);
5157 gen_op_mov_reg_T0(OT_WORD
, R_ESP
);
5161 ot
= dflag
? OT_QUAD
: OT_WORD
;
5163 ot
= dflag
+ OT_WORD
;
5165 gen_op_mov_reg_T0(ot
, R_EBP
);
5168 case 0x06: /* push es */
5169 case 0x0e: /* push cs */
5170 case 0x16: /* push ss */
5171 case 0x1e: /* push ds */
5174 gen_op_movl_T0_seg(b
>> 3);
5177 case 0x1a0: /* push fs */
5178 case 0x1a8: /* push gs */
5179 gen_op_movl_T0_seg((b
>> 3) & 7);
5182 case 0x07: /* pop es */
5183 case 0x17: /* pop ss */
5184 case 0x1f: /* pop ds */
5189 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5192 /* if reg == SS, inhibit interrupts/trace. */
5193 /* If several instructions disable interrupts, only the
5195 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5196 gen_helper_set_inhibit_irq(cpu_env
);
5200 gen_jmp_im(s
->pc
- s
->cs_base
);
5204 case 0x1a1: /* pop fs */
5205 case 0x1a9: /* pop gs */
5207 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5210 gen_jmp_im(s
->pc
- s
->cs_base
);
5215 /**************************/
5218 case 0x89: /* mov Gv, Ev */
5222 ot
= dflag
+ OT_WORD
;
5223 modrm
= cpu_ldub_code(env
, s
->pc
++);
5224 reg
= ((modrm
>> 3) & 7) | rex_r
;
5226 /* generate a generic store */
5227 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5230 case 0xc7: /* mov Ev, Iv */
5234 ot
= dflag
+ OT_WORD
;
5235 modrm
= cpu_ldub_code(env
, s
->pc
++);
5236 mod
= (modrm
>> 6) & 3;
5238 s
->rip_offset
= insn_const_size(ot
);
5239 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5241 val
= insn_get(env
, s
, ot
);
5242 gen_op_movl_T0_im(val
);
5244 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5246 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5249 case 0x8b: /* mov Ev, Gv */
5253 ot
= OT_WORD
+ dflag
;
5254 modrm
= cpu_ldub_code(env
, s
->pc
++);
5255 reg
= ((modrm
>> 3) & 7) | rex_r
;
5257 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5258 gen_op_mov_reg_T0(ot
, reg
);
5260 case 0x8e: /* mov seg, Gv */
5261 modrm
= cpu_ldub_code(env
, s
->pc
++);
5262 reg
= (modrm
>> 3) & 7;
5263 if (reg
>= 6 || reg
== R_CS
)
5265 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
5266 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5268 /* if reg == SS, inhibit interrupts/trace */
5269 /* If several instructions disable interrupts, only the
5271 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5272 gen_helper_set_inhibit_irq(cpu_env
);
5276 gen_jmp_im(s
->pc
- s
->cs_base
);
5280 case 0x8c: /* mov Gv, seg */
5281 modrm
= cpu_ldub_code(env
, s
->pc
++);
5282 reg
= (modrm
>> 3) & 7;
5283 mod
= (modrm
>> 6) & 3;
5286 gen_op_movl_T0_seg(reg
);
5288 ot
= OT_WORD
+ dflag
;
5291 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5294 case 0x1b6: /* movzbS Gv, Eb */
5295 case 0x1b7: /* movzwS Gv, Eb */
5296 case 0x1be: /* movsbS Gv, Eb */
5297 case 0x1bf: /* movswS Gv, Eb */
5300 /* d_ot is the size of destination */
5301 d_ot
= dflag
+ OT_WORD
;
5302 /* ot is the size of source */
5303 ot
= (b
& 1) + OT_BYTE
;
5304 modrm
= cpu_ldub_code(env
, s
->pc
++);
5305 reg
= ((modrm
>> 3) & 7) | rex_r
;
5306 mod
= (modrm
>> 6) & 3;
5307 rm
= (modrm
& 7) | REX_B(s
);
5310 gen_op_mov_TN_reg(ot
, 0, rm
);
5311 switch(ot
| (b
& 8)) {
5313 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5316 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5319 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5323 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5326 gen_op_mov_reg_T0(d_ot
, reg
);
5328 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5330 gen_op_lds_T0_A0(ot
+ s
->mem_index
);
5332 gen_op_ldu_T0_A0(ot
+ s
->mem_index
);
5334 gen_op_mov_reg_T0(d_ot
, reg
);
5339 case 0x8d: /* lea */
5340 ot
= dflag
+ OT_WORD
;
5341 modrm
= cpu_ldub_code(env
, s
->pc
++);
5342 mod
= (modrm
>> 6) & 3;
5345 reg
= ((modrm
>> 3) & 7) | rex_r
;
5346 /* we must ensure that no segment is added */
5350 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5352 gen_op_mov_reg_A0(ot
- OT_WORD
, reg
);
5355 case 0xa0: /* mov EAX, Ov */
5357 case 0xa2: /* mov Ov, EAX */
5360 target_ulong offset_addr
;
5365 ot
= dflag
+ OT_WORD
;
5366 #ifdef TARGET_X86_64
5367 if (s
->aflag
== 2) {
5368 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5370 gen_op_movq_A0_im(offset_addr
);
5375 offset_addr
= insn_get(env
, s
, OT_LONG
);
5377 offset_addr
= insn_get(env
, s
, OT_WORD
);
5379 gen_op_movl_A0_im(offset_addr
);
5381 gen_add_A0_ds_seg(s
);
5383 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
5384 gen_op_mov_reg_T0(ot
, R_EAX
);
5386 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5387 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5391 case 0xd7: /* xlat */
5392 #ifdef TARGET_X86_64
5393 if (s
->aflag
== 2) {
5394 gen_op_movq_A0_reg(R_EBX
);
5395 gen_op_mov_TN_reg(OT_QUAD
, 0, R_EAX
);
5396 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5397 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5401 gen_op_movl_A0_reg(R_EBX
);
5402 gen_op_mov_TN_reg(OT_LONG
, 0, R_EAX
);
5403 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5404 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5406 gen_op_andl_A0_ffff();
5408 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5410 gen_add_A0_ds_seg(s
);
5411 gen_op_ldu_T0_A0(OT_BYTE
+ s
->mem_index
);
5412 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
5414 case 0xb0 ... 0xb7: /* mov R, Ib */
5415 val
= insn_get(env
, s
, OT_BYTE
);
5416 gen_op_movl_T0_im(val
);
5417 gen_op_mov_reg_T0(OT_BYTE
, (b
& 7) | REX_B(s
));
5419 case 0xb8 ... 0xbf: /* mov R, Iv */
5420 #ifdef TARGET_X86_64
5424 tmp
= cpu_ldq_code(env
, s
->pc
);
5426 reg
= (b
& 7) | REX_B(s
);
5427 gen_movtl_T0_im(tmp
);
5428 gen_op_mov_reg_T0(OT_QUAD
, reg
);
5432 ot
= dflag
? OT_LONG
: OT_WORD
;
5433 val
= insn_get(env
, s
, ot
);
5434 reg
= (b
& 7) | REX_B(s
);
5435 gen_op_movl_T0_im(val
);
5436 gen_op_mov_reg_T0(ot
, reg
);
5440 case 0x91 ... 0x97: /* xchg R, EAX */
5442 ot
= dflag
+ OT_WORD
;
5443 reg
= (b
& 7) | REX_B(s
);
5447 case 0x87: /* xchg Ev, Gv */
5451 ot
= dflag
+ OT_WORD
;
5452 modrm
= cpu_ldub_code(env
, s
->pc
++);
5453 reg
= ((modrm
>> 3) & 7) | rex_r
;
5454 mod
= (modrm
>> 6) & 3;
5456 rm
= (modrm
& 7) | REX_B(s
);
5458 gen_op_mov_TN_reg(ot
, 0, reg
);
5459 gen_op_mov_TN_reg(ot
, 1, rm
);
5460 gen_op_mov_reg_T0(ot
, rm
);
5461 gen_op_mov_reg_T1(ot
, reg
);
5463 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5464 gen_op_mov_TN_reg(ot
, 0, reg
);
5465 /* for xchg, lock is implicit */
5466 if (!(prefixes
& PREFIX_LOCK
))
5468 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5469 gen_op_st_T0_A0(ot
+ s
->mem_index
);
5470 if (!(prefixes
& PREFIX_LOCK
))
5471 gen_helper_unlock();
5472 gen_op_mov_reg_T1(ot
, reg
);
5475 case 0xc4: /* les Gv */
5480 case 0xc5: /* lds Gv */
5485 case 0x1b2: /* lss Gv */
5488 case 0x1b4: /* lfs Gv */
5491 case 0x1b5: /* lgs Gv */
5494 ot
= dflag
? OT_LONG
: OT_WORD
;
5495 modrm
= cpu_ldub_code(env
, s
->pc
++);
5496 reg
= ((modrm
>> 3) & 7) | rex_r
;
5497 mod
= (modrm
>> 6) & 3;
5500 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5501 gen_op_ld_T1_A0(ot
+ s
->mem_index
);
5502 gen_add_A0_im(s
, 1 << (ot
- OT_WORD
+ 1));
5503 /* load the segment first to handle exceptions properly */
5504 gen_op_ldu_T0_A0(OT_WORD
+ s
->mem_index
);
5505 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5506 /* then put the data */
5507 gen_op_mov_reg_T1(ot
, reg
);
5509 gen_jmp_im(s
->pc
- s
->cs_base
);
5514 /************************/
5525 ot
= dflag
+ OT_WORD
;
5527 modrm
= cpu_ldub_code(env
, s
->pc
++);
5528 mod
= (modrm
>> 6) & 3;
5529 op
= (modrm
>> 3) & 7;
5535 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5538 opreg
= (modrm
& 7) | REX_B(s
);
5543 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5546 shift
= cpu_ldub_code(env
, s
->pc
++);
5548 gen_shifti(s
, op
, ot
, opreg
, shift
);
5563 case 0x1a4: /* shld imm */
5567 case 0x1a5: /* shld cl */
5571 case 0x1ac: /* shrd imm */
5575 case 0x1ad: /* shrd cl */
5579 ot
= dflag
+ OT_WORD
;
5580 modrm
= cpu_ldub_code(env
, s
->pc
++);
5581 mod
= (modrm
>> 6) & 3;
5582 rm
= (modrm
& 7) | REX_B(s
);
5583 reg
= ((modrm
>> 3) & 7) | rex_r
;
5585 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5590 gen_op_mov_TN_reg(ot
, 1, reg
);
5593 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5594 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5597 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5601 /************************/
5604 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5605 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5606 /* XXX: what to do if illegal op ? */
5607 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5610 modrm
= cpu_ldub_code(env
, s
->pc
++);
5611 mod
= (modrm
>> 6) & 3;
5613 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5616 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
5618 case 0x00 ... 0x07: /* fxxxs */
5619 case 0x10 ... 0x17: /* fixxxl */
5620 case 0x20 ... 0x27: /* fxxxl */
5621 case 0x30 ... 0x37: /* fixxx */
5628 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5629 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5630 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5633 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5634 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5635 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5638 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5639 (s
->mem_index
>> 2) - 1);
5640 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5644 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5645 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5646 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5650 gen_helper_fp_arith_ST0_FT0(op1
);
5652 /* fcomp needs pop */
5653 gen_helper_fpop(cpu_env
);
5657 case 0x08: /* flds */
5658 case 0x0a: /* fsts */
5659 case 0x0b: /* fstps */
5660 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5661 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5662 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5667 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5668 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5669 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5672 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
5673 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5674 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5677 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5678 (s
->mem_index
>> 2) - 1);
5679 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5683 gen_op_lds_T0_A0(OT_WORD
+ s
->mem_index
);
5684 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5685 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5690 /* XXX: the corresponding CPUID bit must be tested ! */
5693 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5694 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5695 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5698 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5699 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5700 (s
->mem_index
>> 2) - 1);
5704 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5705 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5706 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5709 gen_helper_fpop(cpu_env
);
5714 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5715 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5716 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5719 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
5720 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5721 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
5724 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
5725 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5726 (s
->mem_index
>> 2) - 1);
5730 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
5731 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5732 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5736 gen_helper_fpop(cpu_env
);
5740 case 0x0c: /* fldenv mem */
5741 gen_update_cc_op(s
);
5742 gen_jmp_im(pc_start
- s
->cs_base
);
5743 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5745 case 0x0d: /* fldcw mem */
5746 gen_op_ld_T0_A0(OT_WORD
+ s
->mem_index
);
5747 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5748 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
5750 case 0x0e: /* fnstenv mem */
5751 gen_update_cc_op(s
);
5752 gen_jmp_im(pc_start
- s
->cs_base
);
5753 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5755 case 0x0f: /* fnstcw mem */
5756 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
5757 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5758 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5760 case 0x1d: /* fldt mem */
5761 gen_update_cc_op(s
);
5762 gen_jmp_im(pc_start
- s
->cs_base
);
5763 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
5765 case 0x1f: /* fstpt mem */
5766 gen_update_cc_op(s
);
5767 gen_jmp_im(pc_start
- s
->cs_base
);
5768 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
5769 gen_helper_fpop(cpu_env
);
5771 case 0x2c: /* frstor mem */
5772 gen_update_cc_op(s
);
5773 gen_jmp_im(pc_start
- s
->cs_base
);
5774 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5776 case 0x2e: /* fnsave mem */
5777 gen_update_cc_op(s
);
5778 gen_jmp_im(pc_start
- s
->cs_base
);
5779 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
5781 case 0x2f: /* fnstsw mem */
5782 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
5783 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5784 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
5786 case 0x3c: /* fbld */
5787 gen_update_cc_op(s
);
5788 gen_jmp_im(pc_start
- s
->cs_base
);
5789 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
5791 case 0x3e: /* fbstp */
5792 gen_update_cc_op(s
);
5793 gen_jmp_im(pc_start
- s
->cs_base
);
5794 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
5795 gen_helper_fpop(cpu_env
);
5797 case 0x3d: /* fildll */
5798 tcg_gen_qemu_ld64(cpu_tmp1_i64
, cpu_A0
,
5799 (s
->mem_index
>> 2) - 1);
5800 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
5802 case 0x3f: /* fistpll */
5803 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
5804 tcg_gen_qemu_st64(cpu_tmp1_i64
, cpu_A0
,
5805 (s
->mem_index
>> 2) - 1);
5806 gen_helper_fpop(cpu_env
);
5812 /* register float ops */
5816 case 0x08: /* fld sti */
5817 gen_helper_fpush(cpu_env
);
5818 gen_helper_fmov_ST0_STN(cpu_env
,
5819 tcg_const_i32((opreg
+ 1) & 7));
5821 case 0x09: /* fxchg sti */
5822 case 0x29: /* fxchg4 sti, undocumented op */
5823 case 0x39: /* fxchg7 sti, undocumented op */
5824 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
5826 case 0x0a: /* grp d9/2 */
5829 /* check exceptions (FreeBSD FPU probe) */
5830 gen_update_cc_op(s
);
5831 gen_jmp_im(pc_start
- s
->cs_base
);
5832 gen_helper_fwait(cpu_env
);
5838 case 0x0c: /* grp d9/4 */
5841 gen_helper_fchs_ST0(cpu_env
);
5844 gen_helper_fabs_ST0(cpu_env
);
5847 gen_helper_fldz_FT0(cpu_env
);
5848 gen_helper_fcom_ST0_FT0(cpu_env
);
5851 gen_helper_fxam_ST0(cpu_env
);
5857 case 0x0d: /* grp d9/5 */
5861 gen_helper_fpush(cpu_env
);
5862 gen_helper_fld1_ST0(cpu_env
);
5865 gen_helper_fpush(cpu_env
);
5866 gen_helper_fldl2t_ST0(cpu_env
);
5869 gen_helper_fpush(cpu_env
);
5870 gen_helper_fldl2e_ST0(cpu_env
);
5873 gen_helper_fpush(cpu_env
);
5874 gen_helper_fldpi_ST0(cpu_env
);
5877 gen_helper_fpush(cpu_env
);
5878 gen_helper_fldlg2_ST0(cpu_env
);
5881 gen_helper_fpush(cpu_env
);
5882 gen_helper_fldln2_ST0(cpu_env
);
5885 gen_helper_fpush(cpu_env
);
5886 gen_helper_fldz_ST0(cpu_env
);
5893 case 0x0e: /* grp d9/6 */
5896 gen_helper_f2xm1(cpu_env
);
5899 gen_helper_fyl2x(cpu_env
);
5902 gen_helper_fptan(cpu_env
);
5904 case 3: /* fpatan */
5905 gen_helper_fpatan(cpu_env
);
5907 case 4: /* fxtract */
5908 gen_helper_fxtract(cpu_env
);
5910 case 5: /* fprem1 */
5911 gen_helper_fprem1(cpu_env
);
5913 case 6: /* fdecstp */
5914 gen_helper_fdecstp(cpu_env
);
5917 case 7: /* fincstp */
5918 gen_helper_fincstp(cpu_env
);
5922 case 0x0f: /* grp d9/7 */
5925 gen_helper_fprem(cpu_env
);
5927 case 1: /* fyl2xp1 */
5928 gen_helper_fyl2xp1(cpu_env
);
5931 gen_helper_fsqrt(cpu_env
);
5933 case 3: /* fsincos */
5934 gen_helper_fsincos(cpu_env
);
5936 case 5: /* fscale */
5937 gen_helper_fscale(cpu_env
);
5939 case 4: /* frndint */
5940 gen_helper_frndint(cpu_env
);
5943 gen_helper_fsin(cpu_env
);
5947 gen_helper_fcos(cpu_env
);
5951 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5952 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5953 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5959 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
5961 gen_helper_fpop(cpu_env
);
5963 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5964 gen_helper_fp_arith_ST0_FT0(op1
);
5968 case 0x02: /* fcom */
5969 case 0x22: /* fcom2, undocumented op */
5970 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5971 gen_helper_fcom_ST0_FT0(cpu_env
);
5973 case 0x03: /* fcomp */
5974 case 0x23: /* fcomp3, undocumented op */
5975 case 0x32: /* fcomp5, undocumented op */
5976 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
5977 gen_helper_fcom_ST0_FT0(cpu_env
);
5978 gen_helper_fpop(cpu_env
);
5980 case 0x15: /* da/5 */
5982 case 1: /* fucompp */
5983 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
5984 gen_helper_fucom_ST0_FT0(cpu_env
);
5985 gen_helper_fpop(cpu_env
);
5986 gen_helper_fpop(cpu_env
);
5994 case 0: /* feni (287 only, just do nop here) */
5996 case 1: /* fdisi (287 only, just do nop here) */
5999 gen_helper_fclex(cpu_env
);
6001 case 3: /* fninit */
6002 gen_helper_fninit(cpu_env
);
6004 case 4: /* fsetpm (287 only, just do nop here) */
6010 case 0x1d: /* fucomi */
6011 gen_update_cc_op(s
);
6012 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6013 gen_helper_fucomi_ST0_FT0(cpu_env
);
6014 set_cc_op(s
, CC_OP_EFLAGS
);
6016 case 0x1e: /* fcomi */
6017 gen_update_cc_op(s
);
6018 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6019 gen_helper_fcomi_ST0_FT0(cpu_env
);
6020 set_cc_op(s
, CC_OP_EFLAGS
);
6022 case 0x28: /* ffree sti */
6023 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6025 case 0x2a: /* fst sti */
6026 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6028 case 0x2b: /* fstp sti */
6029 case 0x0b: /* fstp1 sti, undocumented op */
6030 case 0x3a: /* fstp8 sti, undocumented op */
6031 case 0x3b: /* fstp9 sti, undocumented op */
6032 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6033 gen_helper_fpop(cpu_env
);
6035 case 0x2c: /* fucom st(i) */
6036 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6037 gen_helper_fucom_ST0_FT0(cpu_env
);
6039 case 0x2d: /* fucomp st(i) */
6040 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6041 gen_helper_fucom_ST0_FT0(cpu_env
);
6042 gen_helper_fpop(cpu_env
);
6044 case 0x33: /* de/3 */
6046 case 1: /* fcompp */
6047 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6048 gen_helper_fcom_ST0_FT0(cpu_env
);
6049 gen_helper_fpop(cpu_env
);
6050 gen_helper_fpop(cpu_env
);
6056 case 0x38: /* ffreep sti, undocumented op */
6057 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6058 gen_helper_fpop(cpu_env
);
6060 case 0x3c: /* df/4 */
6063 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6064 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6065 gen_op_mov_reg_T0(OT_WORD
, R_EAX
);
6071 case 0x3d: /* fucomip */
6072 gen_update_cc_op(s
);
6073 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6074 gen_helper_fucomi_ST0_FT0(cpu_env
);
6075 gen_helper_fpop(cpu_env
);
6076 set_cc_op(s
, CC_OP_EFLAGS
);
6078 case 0x3e: /* fcomip */
6079 gen_update_cc_op(s
);
6080 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6081 gen_helper_fcomi_ST0_FT0(cpu_env
);
6082 gen_helper_fpop(cpu_env
);
6083 set_cc_op(s
, CC_OP_EFLAGS
);
6085 case 0x10 ... 0x13: /* fcmovxx */
6089 static const uint8_t fcmov_cc
[8] = {
6095 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6096 l1
= gen_new_label();
6097 gen_jcc1_noeob(s
, op1
, l1
);
6098 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6107 /************************/
6110 case 0xa4: /* movsS */
6115 ot
= dflag
+ OT_WORD
;
6117 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6118 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6124 case 0xaa: /* stosS */
6129 ot
= dflag
+ OT_WORD
;
6131 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6132 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6137 case 0xac: /* lodsS */
6142 ot
= dflag
+ OT_WORD
;
6143 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6144 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6149 case 0xae: /* scasS */
6154 ot
= dflag
+ OT_WORD
;
6155 if (prefixes
& PREFIX_REPNZ
) {
6156 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6157 } else if (prefixes
& PREFIX_REPZ
) {
6158 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6164 case 0xa6: /* cmpsS */
6169 ot
= dflag
+ OT_WORD
;
6170 if (prefixes
& PREFIX_REPNZ
) {
6171 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6172 } else if (prefixes
& PREFIX_REPZ
) {
6173 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6178 case 0x6c: /* insS */
6183 ot
= dflag
? OT_LONG
: OT_WORD
;
6184 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6185 gen_op_andl_T0_ffff();
6186 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6187 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6188 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6189 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6193 gen_jmp(s
, s
->pc
- s
->cs_base
);
6197 case 0x6e: /* outsS */
6202 ot
= dflag
? OT_LONG
: OT_WORD
;
6203 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6204 gen_op_andl_T0_ffff();
6205 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6206 svm_is_rep(prefixes
) | 4);
6207 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6208 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6212 gen_jmp(s
, s
->pc
- s
->cs_base
);
6217 /************************/
6225 ot
= dflag
? OT_LONG
: OT_WORD
;
6226 val
= cpu_ldub_code(env
, s
->pc
++);
6227 gen_op_movl_T0_im(val
);
6228 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6229 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6232 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6233 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6234 gen_op_mov_reg_T1(ot
, R_EAX
);
6237 gen_jmp(s
, s
->pc
- s
->cs_base
);
6245 ot
= dflag
? OT_LONG
: OT_WORD
;
6246 val
= cpu_ldub_code(env
, s
->pc
++);
6247 gen_op_movl_T0_im(val
);
6248 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6249 svm_is_rep(prefixes
));
6250 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6254 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6255 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6256 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6259 gen_jmp(s
, s
->pc
- s
->cs_base
);
6267 ot
= dflag
? OT_LONG
: OT_WORD
;
6268 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6269 gen_op_andl_T0_ffff();
6270 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6271 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6274 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6275 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6276 gen_op_mov_reg_T1(ot
, R_EAX
);
6279 gen_jmp(s
, s
->pc
- s
->cs_base
);
6287 ot
= dflag
? OT_LONG
: OT_WORD
;
6288 gen_op_mov_TN_reg(OT_WORD
, 0, R_EDX
);
6289 gen_op_andl_T0_ffff();
6290 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6291 svm_is_rep(prefixes
));
6292 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6296 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6297 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6298 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6301 gen_jmp(s
, s
->pc
- s
->cs_base
);
6305 /************************/
6307 case 0xc2: /* ret im */
6308 val
= cpu_ldsw_code(env
, s
->pc
);
6311 if (CODE64(s
) && s
->dflag
)
6313 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6315 gen_op_andl_T0_ffff();
6319 case 0xc3: /* ret */
6323 gen_op_andl_T0_ffff();
6327 case 0xca: /* lret im */
6328 val
= cpu_ldsw_code(env
, s
->pc
);
6331 if (s
->pe
&& !s
->vm86
) {
6332 gen_update_cc_op(s
);
6333 gen_jmp_im(pc_start
- s
->cs_base
);
6334 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6335 tcg_const_i32(val
));
6339 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6341 gen_op_andl_T0_ffff();
6342 /* NOTE: keeping EIP updated is not a problem in case of
6346 gen_op_addl_A0_im(2 << s
->dflag
);
6347 gen_op_ld_T0_A0(1 + s
->dflag
+ s
->mem_index
);
6348 gen_op_movl_seg_T0_vm(R_CS
);
6349 /* add stack offset */
6350 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6354 case 0xcb: /* lret */
6357 case 0xcf: /* iret */
6358 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6361 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6362 set_cc_op(s
, CC_OP_EFLAGS
);
6363 } else if (s
->vm86
) {
6365 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6367 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6368 set_cc_op(s
, CC_OP_EFLAGS
);
6371 gen_update_cc_op(s
);
6372 gen_jmp_im(pc_start
- s
->cs_base
);
6373 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6374 tcg_const_i32(s
->pc
- s
->cs_base
));
6375 set_cc_op(s
, CC_OP_EFLAGS
);
6379 case 0xe8: /* call im */
6382 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6384 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6385 next_eip
= s
->pc
- s
->cs_base
;
6391 gen_movtl_T0_im(next_eip
);
6396 case 0x9a: /* lcall im */
6398 unsigned int selector
, offset
;
6402 ot
= dflag
? OT_LONG
: OT_WORD
;
6403 offset
= insn_get(env
, s
, ot
);
6404 selector
= insn_get(env
, s
, OT_WORD
);
6406 gen_op_movl_T0_im(selector
);
6407 gen_op_movl_T1_imu(offset
);
6410 case 0xe9: /* jmp im */
6412 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6414 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6415 tval
+= s
->pc
- s
->cs_base
;
6422 case 0xea: /* ljmp im */
6424 unsigned int selector
, offset
;
6428 ot
= dflag
? OT_LONG
: OT_WORD
;
6429 offset
= insn_get(env
, s
, ot
);
6430 selector
= insn_get(env
, s
, OT_WORD
);
6432 gen_op_movl_T0_im(selector
);
6433 gen_op_movl_T1_imu(offset
);
6436 case 0xeb: /* jmp Jb */
6437 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6438 tval
+= s
->pc
- s
->cs_base
;
6443 case 0x70 ... 0x7f: /* jcc Jb */
6444 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6446 case 0x180 ... 0x18f: /* jcc Jv */
6448 tval
= (int32_t)insn_get(env
, s
, OT_LONG
);
6450 tval
= (int16_t)insn_get(env
, s
, OT_WORD
);
6453 next_eip
= s
->pc
- s
->cs_base
;
6457 gen_jcc(s
, b
, tval
, next_eip
);
6460 case 0x190 ... 0x19f: /* setcc Gv */
6461 modrm
= cpu_ldub_code(env
, s
->pc
++);
6462 gen_setcc1(s
, b
, cpu_T
[0]);
6463 gen_ldst_modrm(env
, s
, modrm
, OT_BYTE
, OR_TMP0
, 1);
6465 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6466 ot
= dflag
+ OT_WORD
;
6467 modrm
= cpu_ldub_code(env
, s
->pc
++);
6468 reg
= ((modrm
>> 3) & 7) | rex_r
;
6469 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6472 /************************/
6474 case 0x9c: /* pushf */
6475 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6476 if (s
->vm86
&& s
->iopl
!= 3) {
6477 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6479 gen_update_cc_op(s
);
6480 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6484 case 0x9d: /* popf */
6485 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6486 if (s
->vm86
&& s
->iopl
!= 3) {
6487 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6492 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6493 tcg_const_i32((TF_MASK
| AC_MASK
|
6498 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6499 tcg_const_i32((TF_MASK
| AC_MASK
|
6501 IF_MASK
| IOPL_MASK
)
6505 if (s
->cpl
<= s
->iopl
) {
6507 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6508 tcg_const_i32((TF_MASK
|
6514 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6515 tcg_const_i32((TF_MASK
|
6524 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6525 tcg_const_i32((TF_MASK
| AC_MASK
|
6526 ID_MASK
| NT_MASK
)));
6528 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6529 tcg_const_i32((TF_MASK
| AC_MASK
|
6536 set_cc_op(s
, CC_OP_EFLAGS
);
6537 /* abort translation because TF/AC flag may change */
6538 gen_jmp_im(s
->pc
- s
->cs_base
);
6542 case 0x9e: /* sahf */
6543 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6545 gen_op_mov_TN_reg(OT_BYTE
, 0, R_AH
);
6546 gen_compute_eflags(s
);
6547 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6548 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6549 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6551 case 0x9f: /* lahf */
6552 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6554 gen_compute_eflags(s
);
6555 /* Note: gen_compute_eflags() only gives the condition codes */
6556 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6557 gen_op_mov_reg_T0(OT_BYTE
, R_AH
);
6559 case 0xf5: /* cmc */
6560 gen_compute_eflags(s
);
6561 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6563 case 0xf8: /* clc */
6564 gen_compute_eflags(s
);
6565 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6567 case 0xf9: /* stc */
6568 gen_compute_eflags(s
);
6569 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6571 case 0xfc: /* cld */
6572 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6573 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6575 case 0xfd: /* std */
6576 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6577 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6580 /************************/
6581 /* bit operations */
6582 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6583 ot
= dflag
+ OT_WORD
;
6584 modrm
= cpu_ldub_code(env
, s
->pc
++);
6585 op
= (modrm
>> 3) & 7;
6586 mod
= (modrm
>> 6) & 3;
6587 rm
= (modrm
& 7) | REX_B(s
);
6590 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6591 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6593 gen_op_mov_TN_reg(ot
, 0, rm
);
6596 val
= cpu_ldub_code(env
, s
->pc
++);
6597 gen_op_movl_T1_im(val
);
6602 case 0x1a3: /* bt Gv, Ev */
6605 case 0x1ab: /* bts */
6608 case 0x1b3: /* btr */
6611 case 0x1bb: /* btc */
6614 ot
= dflag
+ OT_WORD
;
6615 modrm
= cpu_ldub_code(env
, s
->pc
++);
6616 reg
= ((modrm
>> 3) & 7) | rex_r
;
6617 mod
= (modrm
>> 6) & 3;
6618 rm
= (modrm
& 7) | REX_B(s
);
6619 gen_op_mov_TN_reg(OT_LONG
, 1, reg
);
6621 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6622 /* specific case: we need to add a displacement */
6623 gen_exts(ot
, cpu_T
[1]);
6624 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6625 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6626 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6627 gen_op_ld_T0_A0(ot
+ s
->mem_index
);
6629 gen_op_mov_TN_reg(ot
, 0, rm
);
6632 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6635 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6636 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6639 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6640 tcg_gen_movi_tl(cpu_tmp0
, 1);
6641 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6642 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6645 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6646 tcg_gen_movi_tl(cpu_tmp0
, 1);
6647 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6648 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6649 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6653 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6654 tcg_gen_movi_tl(cpu_tmp0
, 1);
6655 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6656 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6659 set_cc_op(s
, CC_OP_SARB
+ ot
);
6662 gen_op_st_T0_A0(ot
+ s
->mem_index
);
6664 gen_op_mov_reg_T0(ot
, rm
);
6665 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6666 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6669 case 0x1bc: /* bsf */
6670 case 0x1bd: /* bsr */
6675 ot
= dflag
+ OT_WORD
;
6676 modrm
= cpu_ldub_code(env
, s
->pc
++);
6677 reg
= ((modrm
>> 3) & 7) | rex_r
;
6678 gen_ldst_modrm(env
, s
,modrm
, ot
, OR_TMP0
, 0);
6679 gen_extu(ot
, cpu_T
[0]);
6680 t0
= tcg_temp_local_new();
6681 tcg_gen_mov_tl(t0
, cpu_T
[0]);
6682 if ((b
& 1) && (prefixes
& PREFIX_REPZ
) &&
6683 (s
->cpuid_ext3_features
& CPUID_EXT3_ABM
)) {
6685 case OT_WORD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6686 tcg_const_i32(16)); break;
6687 case OT_LONG
: gen_helper_lzcnt(cpu_T
[0], t0
,
6688 tcg_const_i32(32)); break;
6689 case OT_QUAD
: gen_helper_lzcnt(cpu_T
[0], t0
,
6690 tcg_const_i32(64)); break;
6692 gen_op_mov_reg_T0(ot
, reg
);
6694 label1
= gen_new_label();
6695 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6696 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, label1
);
6698 gen_helper_bsr(cpu_T
[0], t0
);
6700 gen_helper_bsf(cpu_T
[0], t0
);
6702 gen_op_mov_reg_T0(ot
, reg
);
6703 tcg_gen_movi_tl(cpu_cc_dst
, 1);
6704 gen_set_label(label1
);
6705 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
6710 /************************/
6712 case 0x27: /* daa */
6715 gen_update_cc_op(s
);
6716 gen_helper_daa(cpu_env
);
6717 set_cc_op(s
, CC_OP_EFLAGS
);
6719 case 0x2f: /* das */
6722 gen_update_cc_op(s
);
6723 gen_helper_das(cpu_env
);
6724 set_cc_op(s
, CC_OP_EFLAGS
);
6726 case 0x37: /* aaa */
6729 gen_update_cc_op(s
);
6730 gen_helper_aaa(cpu_env
);
6731 set_cc_op(s
, CC_OP_EFLAGS
);
6733 case 0x3f: /* aas */
6736 gen_update_cc_op(s
);
6737 gen_helper_aas(cpu_env
);
6738 set_cc_op(s
, CC_OP_EFLAGS
);
6740 case 0xd4: /* aam */
6743 val
= cpu_ldub_code(env
, s
->pc
++);
6745 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
6747 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
6748 set_cc_op(s
, CC_OP_LOGICB
);
6751 case 0xd5: /* aad */
6754 val
= cpu_ldub_code(env
, s
->pc
++);
6755 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
6756 set_cc_op(s
, CC_OP_LOGICB
);
6758 /************************/
6760 case 0x90: /* nop */
6761 /* XXX: correct lock test for all insn */
6762 if (prefixes
& PREFIX_LOCK
) {
6765 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6767 goto do_xchg_reg_eax
;
6769 if (prefixes
& PREFIX_REPZ
) {
6770 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PAUSE
);
6773 case 0x9b: /* fwait */
6774 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
6775 (HF_MP_MASK
| HF_TS_MASK
)) {
6776 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
6778 gen_update_cc_op(s
);
6779 gen_jmp_im(pc_start
- s
->cs_base
);
6780 gen_helper_fwait(cpu_env
);
6783 case 0xcc: /* int3 */
6784 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6786 case 0xcd: /* int N */
6787 val
= cpu_ldub_code(env
, s
->pc
++);
6788 if (s
->vm86
&& s
->iopl
!= 3) {
6789 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6791 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6794 case 0xce: /* into */
6797 gen_update_cc_op(s
);
6798 gen_jmp_im(pc_start
- s
->cs_base
);
6799 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
6802 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6803 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
6805 gen_debug(s
, pc_start
- s
->cs_base
);
6809 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
6813 case 0xfa: /* cli */
6815 if (s
->cpl
<= s
->iopl
) {
6816 gen_helper_cli(cpu_env
);
6818 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6822 gen_helper_cli(cpu_env
);
6824 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6828 case 0xfb: /* sti */
6830 if (s
->cpl
<= s
->iopl
) {
6832 gen_helper_sti(cpu_env
);
6833 /* interruptions are enabled only the first insn after sti */
6834 /* If several instructions disable interrupts, only the
6836 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
6837 gen_helper_set_inhibit_irq(cpu_env
);
6838 /* give a chance to handle pending irqs */
6839 gen_jmp_im(s
->pc
- s
->cs_base
);
6842 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6848 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6852 case 0x62: /* bound */
6855 ot
= dflag
? OT_LONG
: OT_WORD
;
6856 modrm
= cpu_ldub_code(env
, s
->pc
++);
6857 reg
= (modrm
>> 3) & 7;
6858 mod
= (modrm
>> 6) & 3;
6861 gen_op_mov_TN_reg(ot
, 0, reg
);
6862 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
6863 gen_jmp_im(pc_start
- s
->cs_base
);
6864 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6865 if (ot
== OT_WORD
) {
6866 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6868 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
6871 case 0x1c8 ... 0x1cf: /* bswap reg */
6872 reg
= (b
& 7) | REX_B(s
);
6873 #ifdef TARGET_X86_64
6875 gen_op_mov_TN_reg(OT_QUAD
, 0, reg
);
6876 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
6877 gen_op_mov_reg_T0(OT_QUAD
, reg
);
6881 gen_op_mov_TN_reg(OT_LONG
, 0, reg
);
6882 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
6883 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
6884 gen_op_mov_reg_T0(OT_LONG
, reg
);
6887 case 0xd6: /* salc */
6890 gen_compute_eflags_c(s
, cpu_T
[0]);
6891 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
6892 gen_op_mov_reg_T0(OT_BYTE
, R_EAX
);
6894 case 0xe0: /* loopnz */
6895 case 0xe1: /* loopz */
6896 case 0xe2: /* loop */
6897 case 0xe3: /* jecxz */
6901 tval
= (int8_t)insn_get(env
, s
, OT_BYTE
);
6902 next_eip
= s
->pc
- s
->cs_base
;
6907 l1
= gen_new_label();
6908 l2
= gen_new_label();
6909 l3
= gen_new_label();
6912 case 0: /* loopnz */
6914 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6915 gen_op_jz_ecx(s
->aflag
, l3
);
6916 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
6919 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
6920 gen_op_jnz_ecx(s
->aflag
, l1
);
6924 gen_op_jz_ecx(s
->aflag
, l1
);
6929 gen_jmp_im(next_eip
);
6938 case 0x130: /* wrmsr */
6939 case 0x132: /* rdmsr */
6941 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6943 gen_update_cc_op(s
);
6944 gen_jmp_im(pc_start
- s
->cs_base
);
6946 gen_helper_rdmsr(cpu_env
);
6948 gen_helper_wrmsr(cpu_env
);
6952 case 0x131: /* rdtsc */
6953 gen_update_cc_op(s
);
6954 gen_jmp_im(pc_start
- s
->cs_base
);
6957 gen_helper_rdtsc(cpu_env
);
6960 gen_jmp(s
, s
->pc
- s
->cs_base
);
6963 case 0x133: /* rdpmc */
6964 gen_update_cc_op(s
);
6965 gen_jmp_im(pc_start
- s
->cs_base
);
6966 gen_helper_rdpmc(cpu_env
);
6968 case 0x134: /* sysenter */
6969 /* For Intel SYSENTER is valid on 64-bit */
6970 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6973 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6975 gen_update_cc_op(s
);
6976 gen_jmp_im(pc_start
- s
->cs_base
);
6977 gen_helper_sysenter(cpu_env
);
6981 case 0x135: /* sysexit */
6982 /* For Intel SYSEXIT is valid on 64-bit */
6983 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
6986 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6988 gen_update_cc_op(s
);
6989 gen_jmp_im(pc_start
- s
->cs_base
);
6990 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
6994 #ifdef TARGET_X86_64
6995 case 0x105: /* syscall */
6996 /* XXX: is it usable in real mode ? */
6997 gen_update_cc_op(s
);
6998 gen_jmp_im(pc_start
- s
->cs_base
);
6999 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7002 case 0x107: /* sysret */
7004 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7006 gen_update_cc_op(s
);
7007 gen_jmp_im(pc_start
- s
->cs_base
);
7008 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7009 /* condition codes are modified only in long mode */
7011 set_cc_op(s
, CC_OP_EFLAGS
);
7017 case 0x1a2: /* cpuid */
7018 gen_update_cc_op(s
);
7019 gen_jmp_im(pc_start
- s
->cs_base
);
7020 gen_helper_cpuid(cpu_env
);
7022 case 0xf4: /* hlt */
7024 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7026 gen_update_cc_op(s
);
7027 gen_jmp_im(pc_start
- s
->cs_base
);
7028 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7029 s
->is_jmp
= DISAS_TB_JUMP
;
7033 modrm
= cpu_ldub_code(env
, s
->pc
++);
7034 mod
= (modrm
>> 6) & 3;
7035 op
= (modrm
>> 3) & 7;
7038 if (!s
->pe
|| s
->vm86
)
7040 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7041 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7045 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7048 if (!s
->pe
|| s
->vm86
)
7051 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7053 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7054 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7055 gen_jmp_im(pc_start
- s
->cs_base
);
7056 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7057 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7061 if (!s
->pe
|| s
->vm86
)
7063 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7064 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7068 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7071 if (!s
->pe
|| s
->vm86
)
7074 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7076 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7077 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7078 gen_jmp_im(pc_start
- s
->cs_base
);
7079 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7080 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7085 if (!s
->pe
|| s
->vm86
)
7087 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7088 gen_update_cc_op(s
);
7090 gen_helper_verr(cpu_env
, cpu_T
[0]);
7092 gen_helper_verw(cpu_env
, cpu_T
[0]);
7094 set_cc_op(s
, CC_OP_EFLAGS
);
7101 modrm
= cpu_ldub_code(env
, s
->pc
++);
7102 mod
= (modrm
>> 6) & 3;
7103 op
= (modrm
>> 3) & 7;
7109 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7110 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7111 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7112 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7113 gen_add_A0_im(s
, 2);
7114 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7116 gen_op_andl_T0_im(0xffffff);
7117 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7122 case 0: /* monitor */
7123 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7126 gen_update_cc_op(s
);
7127 gen_jmp_im(pc_start
- s
->cs_base
);
7128 #ifdef TARGET_X86_64
7129 if (s
->aflag
== 2) {
7130 gen_op_movq_A0_reg(R_EAX
);
7134 gen_op_movl_A0_reg(R_EAX
);
7136 gen_op_andl_A0_ffff();
7138 gen_add_A0_ds_seg(s
);
7139 gen_helper_monitor(cpu_env
, cpu_A0
);
7142 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7145 gen_update_cc_op(s
);
7146 gen_jmp_im(pc_start
- s
->cs_base
);
7147 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7151 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7155 gen_helper_clac(cpu_env
);
7156 gen_jmp_im(s
->pc
- s
->cs_base
);
7160 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7164 gen_helper_stac(cpu_env
);
7165 gen_jmp_im(s
->pc
- s
->cs_base
);
7172 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7173 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7174 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7175 gen_op_st_T0_A0(OT_WORD
+ s
->mem_index
);
7176 gen_add_A0_im(s
, 2);
7177 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7179 gen_op_andl_T0_im(0xffffff);
7180 gen_op_st_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7186 gen_update_cc_op(s
);
7187 gen_jmp_im(pc_start
- s
->cs_base
);
7190 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7193 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7196 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7197 tcg_const_i32(s
->pc
- pc_start
));
7199 s
->is_jmp
= DISAS_TB_JUMP
;
7202 case 1: /* VMMCALL */
7203 if (!(s
->flags
& HF_SVME_MASK
))
7205 gen_helper_vmmcall(cpu_env
);
7207 case 2: /* VMLOAD */
7208 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7211 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7214 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7217 case 3: /* VMSAVE */
7218 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7221 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7224 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7228 if ((!(s
->flags
& HF_SVME_MASK
) &&
7229 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7233 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7236 gen_helper_stgi(cpu_env
);
7240 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7243 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7246 gen_helper_clgi(cpu_env
);
7249 case 6: /* SKINIT */
7250 if ((!(s
->flags
& HF_SVME_MASK
) &&
7251 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7254 gen_helper_skinit(cpu_env
);
7256 case 7: /* INVLPGA */
7257 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7260 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7263 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7269 } else if (s
->cpl
!= 0) {
7270 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7272 gen_svm_check_intercept(s
, pc_start
,
7273 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7274 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7275 gen_op_ld_T1_A0(OT_WORD
+ s
->mem_index
);
7276 gen_add_A0_im(s
, 2);
7277 gen_op_ld_T0_A0(CODE64(s
) + OT_LONG
+ s
->mem_index
);
7279 gen_op_andl_T0_im(0xffffff);
7281 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7282 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7284 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7285 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7290 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7291 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7292 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7294 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7296 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 1);
7300 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7302 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7303 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7304 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7305 gen_jmp_im(s
->pc
- s
->cs_base
);
7310 if (mod
!= 3) { /* invlpg */
7312 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7314 gen_update_cc_op(s
);
7315 gen_jmp_im(pc_start
- s
->cs_base
);
7316 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7317 gen_helper_invlpg(cpu_env
, cpu_A0
);
7318 gen_jmp_im(s
->pc
- s
->cs_base
);
7323 case 0: /* swapgs */
7324 #ifdef TARGET_X86_64
7327 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7329 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7330 offsetof(CPUX86State
,segs
[R_GS
].base
));
7331 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7332 offsetof(CPUX86State
,kernelgsbase
));
7333 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7334 offsetof(CPUX86State
,segs
[R_GS
].base
));
7335 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7336 offsetof(CPUX86State
,kernelgsbase
));
7344 case 1: /* rdtscp */
7345 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7347 gen_update_cc_op(s
);
7348 gen_jmp_im(pc_start
- s
->cs_base
);
7351 gen_helper_rdtscp(cpu_env
);
7354 gen_jmp(s
, s
->pc
- s
->cs_base
);
7366 case 0x108: /* invd */
7367 case 0x109: /* wbinvd */
7369 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7371 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7375 case 0x63: /* arpl or movslS (x86_64) */
7376 #ifdef TARGET_X86_64
7379 /* d_ot is the size of destination */
7380 d_ot
= dflag
+ OT_WORD
;
7382 modrm
= cpu_ldub_code(env
, s
->pc
++);
7383 reg
= ((modrm
>> 3) & 7) | rex_r
;
7384 mod
= (modrm
>> 6) & 3;
7385 rm
= (modrm
& 7) | REX_B(s
);
7388 gen_op_mov_TN_reg(OT_LONG
, 0, rm
);
7390 if (d_ot
== OT_QUAD
)
7391 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7392 gen_op_mov_reg_T0(d_ot
, reg
);
7394 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7395 if (d_ot
== OT_QUAD
) {
7396 gen_op_lds_T0_A0(OT_LONG
+ s
->mem_index
);
7398 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7400 gen_op_mov_reg_T0(d_ot
, reg
);
7406 TCGv t0
, t1
, t2
, a0
;
7408 if (!s
->pe
|| s
->vm86
)
7410 t0
= tcg_temp_local_new();
7411 t1
= tcg_temp_local_new();
7412 t2
= tcg_temp_local_new();
7414 modrm
= cpu_ldub_code(env
, s
->pc
++);
7415 reg
= (modrm
>> 3) & 7;
7416 mod
= (modrm
>> 6) & 3;
7419 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7420 gen_op_ld_v(ot
+ s
->mem_index
, t0
, cpu_A0
);
7421 a0
= tcg_temp_local_new();
7422 tcg_gen_mov_tl(a0
, cpu_A0
);
7424 gen_op_mov_v_reg(ot
, t0
, rm
);
7427 gen_op_mov_v_reg(ot
, t1
, reg
);
7428 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7429 tcg_gen_andi_tl(t1
, t1
, 3);
7430 tcg_gen_movi_tl(t2
, 0);
7431 label1
= gen_new_label();
7432 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7433 tcg_gen_andi_tl(t0
, t0
, ~3);
7434 tcg_gen_or_tl(t0
, t0
, t1
);
7435 tcg_gen_movi_tl(t2
, CC_Z
);
7436 gen_set_label(label1
);
7438 gen_op_st_v(ot
+ s
->mem_index
, t0
, a0
);
7441 gen_op_mov_reg_v(ot
, rm
, t0
);
7443 gen_compute_eflags(s
);
7444 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7445 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7451 case 0x102: /* lar */
7452 case 0x103: /* lsl */
7456 if (!s
->pe
|| s
->vm86
)
7458 ot
= dflag
? OT_LONG
: OT_WORD
;
7459 modrm
= cpu_ldub_code(env
, s
->pc
++);
7460 reg
= ((modrm
>> 3) & 7) | rex_r
;
7461 gen_ldst_modrm(env
, s
, modrm
, OT_WORD
, OR_TMP0
, 0);
7462 t0
= tcg_temp_local_new();
7463 gen_update_cc_op(s
);
7465 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7467 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7469 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7470 label1
= gen_new_label();
7471 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7472 gen_op_mov_reg_v(ot
, reg
, t0
);
7473 gen_set_label(label1
);
7474 set_cc_op(s
, CC_OP_EFLAGS
);
7479 modrm
= cpu_ldub_code(env
, s
->pc
++);
7480 mod
= (modrm
>> 6) & 3;
7481 op
= (modrm
>> 3) & 7;
7483 case 0: /* prefetchnta */
7484 case 1: /* prefetchnt0 */
7485 case 2: /* prefetchnt0 */
7486 case 3: /* prefetchnt0 */
7489 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7490 /* nothing more to do */
7492 default: /* nop (multi byte) */
7493 gen_nop_modrm(env
, s
, modrm
);
7497 case 0x119 ... 0x11f: /* nop (multi byte) */
7498 modrm
= cpu_ldub_code(env
, s
->pc
++);
7499 gen_nop_modrm(env
, s
, modrm
);
7501 case 0x120: /* mov reg, crN */
7502 case 0x122: /* mov crN, reg */
7504 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7506 modrm
= cpu_ldub_code(env
, s
->pc
++);
7507 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7508 * AMD documentation (24594.pdf) and testing of
7509 * intel 386 and 486 processors all show that the mod bits
7510 * are assumed to be 1's, regardless of actual values.
7512 rm
= (modrm
& 7) | REX_B(s
);
7513 reg
= ((modrm
>> 3) & 7) | rex_r
;
7518 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7519 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7528 gen_update_cc_op(s
);
7529 gen_jmp_im(pc_start
- s
->cs_base
);
7531 gen_op_mov_TN_reg(ot
, 0, rm
);
7532 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7534 gen_jmp_im(s
->pc
- s
->cs_base
);
7537 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7538 gen_op_mov_reg_T0(ot
, rm
);
7546 case 0x121: /* mov reg, drN */
7547 case 0x123: /* mov drN, reg */
7549 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7551 modrm
= cpu_ldub_code(env
, s
->pc
++);
7552 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7553 * AMD documentation (24594.pdf) and testing of
7554 * intel 386 and 486 processors all show that the mod bits
7555 * are assumed to be 1's, regardless of actual values.
7557 rm
= (modrm
& 7) | REX_B(s
);
7558 reg
= ((modrm
>> 3) & 7) | rex_r
;
7563 /* XXX: do it dynamically with CR4.DE bit */
7564 if (reg
== 4 || reg
== 5 || reg
>= 8)
7567 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7568 gen_op_mov_TN_reg(ot
, 0, rm
);
7569 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7570 gen_jmp_im(s
->pc
- s
->cs_base
);
7573 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7574 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7575 gen_op_mov_reg_T0(ot
, rm
);
7579 case 0x106: /* clts */
7581 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7583 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7584 gen_helper_clts(cpu_env
);
7585 /* abort block because static cpu state changed */
7586 gen_jmp_im(s
->pc
- s
->cs_base
);
7590 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7591 case 0x1c3: /* MOVNTI reg, mem */
7592 if (!(s
->cpuid_features
& CPUID_SSE2
))
7594 ot
= s
->dflag
== 2 ? OT_QUAD
: OT_LONG
;
7595 modrm
= cpu_ldub_code(env
, s
->pc
++);
7596 mod
= (modrm
>> 6) & 3;
7599 reg
= ((modrm
>> 3) & 7) | rex_r
;
7600 /* generate a generic store */
7601 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7604 modrm
= cpu_ldub_code(env
, s
->pc
++);
7605 mod
= (modrm
>> 6) & 3;
7606 op
= (modrm
>> 3) & 7;
7608 case 0: /* fxsave */
7609 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7610 (s
->prefix
& PREFIX_LOCK
))
7612 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7613 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7616 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7617 gen_update_cc_op(s
);
7618 gen_jmp_im(pc_start
- s
->cs_base
);
7619 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7621 case 1: /* fxrstor */
7622 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7623 (s
->prefix
& PREFIX_LOCK
))
7625 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7626 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7629 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7630 gen_update_cc_op(s
);
7631 gen_jmp_im(pc_start
- s
->cs_base
);
7632 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7633 tcg_const_i32((s
->dflag
== 2)));
7635 case 2: /* ldmxcsr */
7636 case 3: /* stmxcsr */
7637 if (s
->flags
& HF_TS_MASK
) {
7638 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7641 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7644 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7646 gen_op_ld_T0_A0(OT_LONG
+ s
->mem_index
);
7647 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7648 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7650 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7651 gen_op_st_T0_A0(OT_LONG
+ s
->mem_index
);
7654 case 5: /* lfence */
7655 case 6: /* mfence */
7656 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7659 case 7: /* sfence / clflush */
7660 if ((modrm
& 0xc7) == 0xc0) {
7662 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7663 if (!(s
->cpuid_features
& CPUID_SSE
))
7667 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7669 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7676 case 0x10d: /* 3DNow! prefetch(w) */
7677 modrm
= cpu_ldub_code(env
, s
->pc
++);
7678 mod
= (modrm
>> 6) & 3;
7681 gen_lea_modrm(env
, s
, modrm
, ®_addr
, &offset_addr
);
7682 /* ignore for now */
7684 case 0x1aa: /* rsm */
7685 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7686 if (!(s
->flags
& HF_SMM_MASK
))
7688 gen_update_cc_op(s
);
7689 gen_jmp_im(s
->pc
- s
->cs_base
);
7690 gen_helper_rsm(cpu_env
);
7693 case 0x1b8: /* SSE4.2 popcnt */
7694 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
7697 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
7700 modrm
= cpu_ldub_code(env
, s
->pc
++);
7701 reg
= ((modrm
>> 3) & 7) | rex_r
;
7703 if (s
->prefix
& PREFIX_DATA
)
7705 else if (s
->dflag
!= 2)
7710 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
7711 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
7712 gen_op_mov_reg_T0(ot
, reg
);
7714 set_cc_op(s
, CC_OP_EFLAGS
);
7716 case 0x10e ... 0x10f:
7717 /* 3DNow! instructions, ignore prefixes */
7718 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
7719 case 0x110 ... 0x117:
7720 case 0x128 ... 0x12f:
7721 case 0x138 ... 0x13a:
7722 case 0x150 ... 0x179:
7723 case 0x17c ... 0x17f:
7725 case 0x1c4 ... 0x1c6:
7726 case 0x1d0 ... 0x1fe:
7727 gen_sse(env
, s
, b
, pc_start
, rex_r
);
7732 /* lock generation */
7733 if (s
->prefix
& PREFIX_LOCK
)
7734 gen_helper_unlock();
7737 if (s
->prefix
& PREFIX_LOCK
)
7738 gen_helper_unlock();
7739 /* XXX: ensure that no lock was generated */
7740 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
7744 void optimize_flags_init(void)
7746 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
7747 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
7748 offsetof(CPUX86State
, cc_op
), "cc_op");
7749 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
7751 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
7754 #ifdef TARGET_X86_64
7755 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7756 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
7757 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7758 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
7759 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7760 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
7761 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
7762 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
7763 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7764 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
7765 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
7766 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
7767 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7768 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
7769 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
7770 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
7771 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
7772 offsetof(CPUX86State
, regs
[8]), "r8");
7773 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
7774 offsetof(CPUX86State
, regs
[9]), "r9");
7775 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
7776 offsetof(CPUX86State
, regs
[10]), "r10");
7777 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
7778 offsetof(CPUX86State
, regs
[11]), "r11");
7779 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
7780 offsetof(CPUX86State
, regs
[12]), "r12");
7781 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
7782 offsetof(CPUX86State
, regs
[13]), "r13");
7783 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
7784 offsetof(CPUX86State
, regs
[14]), "r14");
7785 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
7786 offsetof(CPUX86State
, regs
[15]), "r15");
7788 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7789 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
7790 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7791 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
7792 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7793 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
7794 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
7795 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
7796 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7797 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
7798 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
7799 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
7800 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7801 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
7802 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
7803 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
7806 /* register helpers */
7807 #define GEN_HELPER 2
7811 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7812 basic block 'tb'. If search_pc is TRUE, also generate PC
7813 information for each intermediate instruction. */
7814 static inline void gen_intermediate_code_internal(CPUX86State
*env
,
7815 TranslationBlock
*tb
,
7818 DisasContext dc1
, *dc
= &dc1
;
7819 target_ulong pc_ptr
;
7820 uint16_t *gen_opc_end
;
7824 target_ulong pc_start
;
7825 target_ulong cs_base
;
7829 /* generate intermediate code */
7831 cs_base
= tb
->cs_base
;
7834 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
7835 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
7836 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
7837 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
7839 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
7840 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
7841 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
7842 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
7843 dc
->singlestep_enabled
= env
->singlestep_enabled
;
7844 dc
->cc_op
= CC_OP_DYNAMIC
;
7845 dc
->cc_op_dirty
= false;
7846 dc
->cs_base
= cs_base
;
7848 dc
->popl_esp_hack
= 0;
7849 /* select memory access functions */
7851 if (flags
& HF_SOFTMMU_MASK
) {
7852 dc
->mem_index
= (cpu_mmu_index(env
) + 1) << 2;
7854 dc
->cpuid_features
= env
->cpuid_features
;
7855 dc
->cpuid_ext_features
= env
->cpuid_ext_features
;
7856 dc
->cpuid_ext2_features
= env
->cpuid_ext2_features
;
7857 dc
->cpuid_ext3_features
= env
->cpuid_ext3_features
;
7858 dc
->cpuid_7_0_ebx_features
= env
->cpuid_7_0_ebx_features
;
7859 #ifdef TARGET_X86_64
7860 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
7861 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
7864 dc
->jmp_opt
= !(dc
->tf
|| env
->singlestep_enabled
||
7865 (flags
& HF_INHIBIT_IRQ_MASK
)
7866 #ifndef CONFIG_SOFTMMU
7867 || (flags
& HF_SOFTMMU_MASK
)
7871 /* check addseg logic */
7872 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
7873 printf("ERROR addseg\n");
7876 cpu_T
[0] = tcg_temp_new();
7877 cpu_T
[1] = tcg_temp_new();
7878 cpu_A0
= tcg_temp_new();
7880 cpu_tmp0
= tcg_temp_new();
7881 cpu_tmp1_i64
= tcg_temp_new_i64();
7882 cpu_tmp2_i32
= tcg_temp_new_i32();
7883 cpu_tmp3_i32
= tcg_temp_new_i32();
7884 cpu_tmp4
= tcg_temp_new();
7885 cpu_tmp5
= tcg_temp_new();
7886 cpu_ptr0
= tcg_temp_new_ptr();
7887 cpu_ptr1
= tcg_temp_new_ptr();
7889 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
7891 dc
->is_jmp
= DISAS_NEXT
;
7895 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
7897 max_insns
= CF_COUNT_MASK
;
7901 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
7902 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
7903 if (bp
->pc
== pc_ptr
&&
7904 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
7905 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
7911 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7915 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7917 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
7918 gen_opc_cc_op
[lj
] = dc
->cc_op
;
7919 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
7920 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
7922 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
7925 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
7927 /* stop translation if indicated */
7930 /* if single step mode, we generate only one instruction and
7931 generate an exception */
7932 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7933 the flag and abort the translation to give the irqs a
7934 change to be happen */
7935 if (dc
->tf
|| dc
->singlestep_enabled
||
7936 (flags
& HF_INHIBIT_IRQ_MASK
)) {
7937 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7941 /* if too long translation, stop generation too */
7942 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
7943 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
7944 num_insns
>= max_insns
) {
7945 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7950 gen_jmp_im(pc_ptr
- dc
->cs_base
);
7955 if (tb
->cflags
& CF_LAST_IO
)
7957 gen_icount_end(tb
, num_insns
);
7958 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
7959 /* we don't forget to fill the last values */
7961 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
7964 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
7968 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
7970 qemu_log("----------------\n");
7971 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
7972 #ifdef TARGET_X86_64
7977 disas_flags
= !dc
->code32
;
7978 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
7984 tb
->size
= pc_ptr
- pc_start
;
7985 tb
->icount
= num_insns
;
7989 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
7991 gen_intermediate_code_internal(env
, tb
, 0);
7994 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
7996 gen_intermediate_code_internal(env
, tb
, 1);
7999 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8003 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8005 qemu_log("RESTORE:\n");
8006 for(i
= 0;i
<= pc_pos
; i
++) {
8007 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8008 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8009 tcg_ctx
.gen_opc_pc
[i
]);
8012 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8013 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8014 (uint32_t)tb
->cs_base
);
8017 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8018 cc_op
= gen_opc_cc_op
[pc_pos
];
8019 if (cc_op
!= CC_OP_DYNAMIC
)