target-lm32/cpu.h

   1 /*
   2  *  LatticeMico32 virtual CPU header.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef CPU_LM32_H
  21 #define CPU_LM32_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUState struct CPULM32State
  26
  27 #include "config.h"
  28 #include "qemu-common.h"
  29 #include "cpu-defs.h"
  30 struct CPULM32State;
  31
  32 #define TARGET_HAS_ICE 1
  33
  34 #define ELF_MACHINE EM_LATTICEMICO32
  35
  36 #define NB_MMU_MODES 1
  37 #define TARGET_PAGE_BITS 12
  38 static inline int cpu_mmu_index(CPUState *env)
  39 {
  40     return 0;
  41 }
  42
  43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  45
  46 /* Exceptions indices */
  47 enum {
  48     EXCP_RESET = 0,
  49     EXCP_BREAKPOINT,
  50     EXCP_INSN_BUS_ERROR,
  51     EXCP_WATCHPOINT,
  52     EXCP_DATA_BUS_ERROR,
  53     EXCP_DIVIDE_BY_ZERO,
  54     EXCP_IRQ,
  55     EXCP_SYSTEMCALL
  56 };
  57
  58 /* Registers */
  59 enum {
  60     R_R0 = 0, R_R1, R_R2, R_R3, R_R4, R_R5, R_R6, R_R7, R_R8, R_R9, R_R10,
  61     R_R11, R_R12, R_R13, R_R14, R_R15, R_R16, R_R17, R_R18, R_R19, R_R20,
  62     R_R21, R_R22, R_R23, R_R24, R_R25, R_R26, R_R27, R_R28, R_R29, R_R30,
  63     R_R31
  64 };
  65
  66 /* Register aliases */
  67 enum {
  68     R_GP = R_R26,
  69     R_FP = R_R27,
  70     R_SP = R_R28,
  71     R_RA = R_R29,
  72     R_EA = R_R30,
  73     R_BA = R_R31
  74 };
  75
  76 /* IE flags */
  77 enum {
  78     IE_IE  = (1<<0),
  79     IE_EIE = (1<<1),
  80     IE_BIE = (1<<2),
  81 };
  82
  83 /* DC flags */
  84 enum {
  85     DC_SS  = (1<<0),
  86     DC_RE  = (1<<1),
  87     DC_C0  = (1<<2),
  88     DC_C1  = (1<<3),
  89     DC_C2  = (1<<4),
  90     DC_C3  = (1<<5),
  91 };
  92
  93 /* CFG mask */
  94 enum {
  95     CFG_M         = (1<<0),
  96     CFG_D         = (1<<1),
  97     CFG_S         = (1<<2),
  98     CFG_U         = (1<<3),
  99     CFG_X         = (1<<4),
 100     CFG_CC        = (1<<5),
 101     CFG_IC        = (1<<6),
 102     CFG_DC        = (1<<7),
 103     CFG_G         = (1<<8),
 104     CFG_H         = (1<<9),
 105     CFG_R         = (1<<10),
 106     CFG_J         = (1<<11),
 107     CFG_INT_SHIFT = 12,
 108     CFG_BP_SHIFT  = 18,
 109     CFG_WP_SHIFT  = 22,
 110     CFG_REV_SHIFT = 26,
 111 };
 112
 113 /* CSRs */
 114 enum {
 115     CSR_IE   = 0x00,
 116     CSR_IM   = 0x01,
 117     CSR_IP   = 0x02,
 118     CSR_ICC  = 0x03,
 119     CSR_DCC  = 0x04,
 120     CSR_CC   = 0x05,
 121     CSR_CFG  = 0x06,
 122     CSR_EBA  = 0x07,
 123     CSR_DC   = 0x08,
 124     CSR_DEBA = 0x09,
 125     CSR_JTX  = 0x0e,
 126     CSR_JRX  = 0x0f,
 127     CSR_BP0  = 0x10,
 128     CSR_BP1  = 0x11,
 129     CSR_BP2  = 0x12,
 130     CSR_BP3  = 0x13,
 131     CSR_WP0  = 0x18,
 132     CSR_WP1  = 0x19,
 133     CSR_WP2  = 0x1a,
 134     CSR_WP3  = 0x1b,
 135 };
 136
 137 enum {
 138     LM32_FEATURE_MULTIPLY     =  1,
 139     LM32_FEATURE_DIVIDE       =  2,
 140     LM32_FEATURE_SHIFT        =  4,
 141     LM32_FEATURE_SIGN_EXTEND  =  8,
 142     LM32_FEATURE_I_CACHE      = 16,
 143     LM32_FEATURE_D_CACHE      = 32,
 144     LM32_FEATURE_CYCLE_COUNT  = 64,
 145 };
 146
 147 enum {
 148     LM32_FLAG_IGNORE_MSB = 1,
 149 };
 150
 151 typedef struct CPULM32State {
 152     /* general registers */
 153     uint32_t regs[32];
 154
 155     /* special registers */
 156     uint32_t pc;        /* program counter */
 157     uint32_t ie;        /* interrupt enable */
 158     uint32_t icc;       /* instruction cache control */
 159     uint32_t dcc;       /* data cache control */
 160     uint32_t cc;        /* cycle counter */
 161     uint32_t cfg;       /* configuration */
 162
 163     /* debug registers */
 164     uint32_t dc;        /* debug control */
 165     uint32_t bp[4];     /* breakpoint addresses */
 166     uint32_t wp[4];     /* watchpoint addresses */
 167
 168     CPU_COMMON
 169
 170     uint32_t eba;       /* exception base address */
 171     uint32_t deba;      /* debug exception base address */
 172
 173     /* interrupt controller handle for callbacks */
 174     DeviceState *pic_state;
 175     /* JTAG UART handle for callbacks */
 176     DeviceState *juart_state;
 177
 178     /* processor core features */
 179     uint32_t features;
 180     uint32_t flags;
 181     uint8_t num_bps;
 182     uint8_t num_wps;
 183
 184 } CPULM32State;
 185
 186
 187 CPUState *cpu_lm32_init(const char *cpu_model);
 188 void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
 189 int cpu_lm32_exec(CPUState *s);
 190 void cpu_lm32_close(CPUState *s);
 191 void do_interrupt(CPUState *env);
 192 /* you can call this signal handler from your SIGBUS and SIGSEGV
 193    signal handlers to inform the virtual CPU of exceptions. non zero
 194    is returned if the signal was handled by the virtual CPU.  */
 195 int cpu_lm32_signal_handler(int host_signum, void *pinfo,
 196                           void *puc);
 197 void lm32_translate_init(void);
 198 void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
 199
 200 #define cpu_list cpu_lm32_list
 201 #define cpu_init cpu_lm32_init
 202 #define cpu_exec cpu_lm32_exec
 203 #define cpu_gen_code cpu_lm32_gen_code
 204 #define cpu_signal_handler cpu_lm32_signal_handler
 205
 206 #define CPU_SAVE_VERSION 1
 207
 208 int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 209                               int mmu_idx);
 210 #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
 211
 212 #if defined(CONFIG_USER_ONLY)
 213 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 214 {
 215     if (newsp) {
 216         env->regs[R_SP] = newsp;
 217     }
 218     env->regs[R_R1] = 0;
 219 }
 220 #endif
 221
 222 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 223 {
 224 }
 225
 226 static inline int cpu_interrupts_enabled(CPUState *env)
 227 {
 228     return env->ie & IE_IE;
 229 }
 230
 231 #include "cpu-all.h"
 232
 233 static inline target_ulong cpu_get_pc(CPUState *env)
 234 {
 235     return env->pc;
 236 }
 237
 238 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 239                                         target_ulong *cs_base, int *flags)
 240 {
 241     *pc = env->pc;
 242     *cs_base = 0;
 243     *flags = 0;
 244 }
 245
 246 static inline bool cpu_has_work(CPUState *env)
 247 {
 248     return env->interrupt_request & CPU_INTERRUPT_HARD;
 249 }
 250
 251 #include "exec-all.h"
 252
 253 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 254 {
 255     env->pc = tb->pc;
 256 }
 257
 258 #endif