target-lm32/helper.c

   1 /*
   2  *  LatticeMico32 helper routines.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22
  23 int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
  24                               int mmu_idx)
  25 {
  26     int prot;
  27
  28     address &= TARGET_PAGE_MASK;
  29     prot = PAGE_BITS;
  30     if (env->flags & LM32_FLAG_IGNORE_MSB) {
  31         tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
  32                 TARGET_PAGE_SIZE);
  33     } else {
  34         tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
  35     }
  36
  37     return 0;
  38 }
  39
  40 hwaddr cpu_get_phys_page_debug(CPULM32State *env, target_ulong addr)
  41 {
  42     return addr & TARGET_PAGE_MASK;
  43 }
  44
  45 void lm32_cpu_do_interrupt(CPUState *cs)
  46 {
  47     LM32CPU *cpu = LM32_CPU(cs);
  48     CPULM32State *env = &cpu->env;
  49
  50     qemu_log_mask(CPU_LOG_INT,
  51             "exception at pc=%x type=%x\n", env->pc, env->exception_index);
  52
  53     switch (env->exception_index) {
  54     case EXCP_INSN_BUS_ERROR:
  55     case EXCP_DATA_BUS_ERROR:
  56     case EXCP_DIVIDE_BY_ZERO:
  57     case EXCP_IRQ:
  58     case EXCP_SYSTEMCALL:
  59         /* non-debug exceptions */
  60         env->regs[R_EA] = env->pc;
  61         env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
  62         env->ie &= ~IE_IE;
  63         if (env->dc & DC_RE) {
  64             env->pc = env->deba + (env->exception_index * 32);
  65         } else {
  66             env->pc = env->eba + (env->exception_index * 32);
  67         }
  68         log_cpu_state_mask(CPU_LOG_INT, env, 0);
  69         break;
  70     case EXCP_BREAKPOINT:
  71     case EXCP_WATCHPOINT:
  72         /* debug exceptions */
  73         env->regs[R_BA] = env->pc;
  74         env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
  75         env->ie &= ~IE_IE;
  76         env->pc = env->deba + (env->exception_index * 32);
  77         log_cpu_state_mask(CPU_LOG_INT, env, 0);
  78         break;
  79     default:
  80         cpu_abort(env, "unhandled exception type=%d\n",
  81                   env->exception_index);
  82         break;
  83     }
  84 }
  85
  86 typedef struct {
  87     const char *name;
  88     uint32_t revision;
  89     uint8_t num_interrupts;
  90     uint8_t num_breakpoints;
  91     uint8_t num_watchpoints;
  92     uint32_t features;
  93 } LM32Def;
  94
  95 static const LM32Def lm32_defs[] = {
  96     {
  97         .name = "lm32-basic",
  98         .revision = 3,
  99         .num_interrupts = 32,
 100         .num_breakpoints = 4,
 101         .num_watchpoints = 4,
 102         .features = (LM32_FEATURE_SHIFT
 103                      | LM32_FEATURE_SIGN_EXTEND
 104                      | LM32_FEATURE_CYCLE_COUNT),
 105     },
 106     {
 107         .name = "lm32-standard",
 108         .revision = 3,
 109         .num_interrupts = 32,
 110         .num_breakpoints = 4,
 111         .num_watchpoints = 4,
 112         .features = (LM32_FEATURE_MULTIPLY
 113                      | LM32_FEATURE_DIVIDE
 114                      | LM32_FEATURE_SHIFT
 115                      | LM32_FEATURE_SIGN_EXTEND
 116                      | LM32_FEATURE_I_CACHE
 117                      | LM32_FEATURE_CYCLE_COUNT),
 118     },
 119     {
 120         .name = "lm32-full",
 121         .revision = 3,
 122         .num_interrupts = 32,
 123         .num_breakpoints = 4,
 124         .num_watchpoints = 4,
 125         .features = (LM32_FEATURE_MULTIPLY
 126                      | LM32_FEATURE_DIVIDE
 127                      | LM32_FEATURE_SHIFT
 128                      | LM32_FEATURE_SIGN_EXTEND
 129                      | LM32_FEATURE_I_CACHE
 130                      | LM32_FEATURE_D_CACHE
 131                      | LM32_FEATURE_CYCLE_COUNT),
 132     }
 133 };
 134
 135 void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
 136 {
 137     int i;
 138
 139     cpu_fprintf(f, "Available CPUs:\n");
 140     for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
 141         cpu_fprintf(f, "  %s\n", lm32_defs[i].name);
 142     }
 143 }
 144
 145 static const LM32Def *cpu_lm32_find_by_name(const char *name)
 146 {
 147     int i;
 148
 149     for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
 150         if (strcasecmp(name, lm32_defs[i].name) == 0) {
 151             return &lm32_defs[i];
 152         }
 153     }
 154
 155     return NULL;
 156 }
 157
 158 static uint32_t cfg_by_def(const LM32Def *def)
 159 {
 160     uint32_t cfg = 0;
 161
 162     if (def->features & LM32_FEATURE_MULTIPLY) {
 163         cfg |= CFG_M;
 164     }
 165
 166     if (def->features & LM32_FEATURE_DIVIDE) {
 167         cfg |= CFG_D;
 168     }
 169
 170     if (def->features & LM32_FEATURE_SHIFT) {
 171         cfg |= CFG_S;
 172     }
 173
 174     if (def->features & LM32_FEATURE_SIGN_EXTEND) {
 175         cfg |= CFG_X;
 176     }
 177
 178     if (def->features & LM32_FEATURE_I_CACHE) {
 179         cfg |= CFG_IC;
 180     }
 181
 182     if (def->features & LM32_FEATURE_D_CACHE) {
 183         cfg |= CFG_DC;
 184     }
 185
 186     if (def->features & LM32_FEATURE_CYCLE_COUNT) {
 187         cfg |= CFG_CC;
 188     }
 189
 190     cfg |= (def->num_interrupts << CFG_INT_SHIFT);
 191     cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
 192     cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
 193     cfg |= (def->revision << CFG_REV_SHIFT);
 194
 195     return cfg;
 196 }
 197
 198 LM32CPU *cpu_lm32_init(const char *cpu_model)
 199 {
 200     LM32CPU *cpu;
 201     CPULM32State *env;
 202     const LM32Def *def;
 203
 204     def = cpu_lm32_find_by_name(cpu_model);
 205     if (!def) {
 206         return NULL;
 207     }
 208
 209     cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
 210     env = &cpu->env;
 211
 212     env->features = def->features;
 213     env->num_bps = def->num_breakpoints;
 214     env->num_wps = def->num_watchpoints;
 215     env->cfg = cfg_by_def(def);
 216
 217     object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
 218
 219     return cpu;
 220 }
 221
 222 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
 223  * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
 224  * 0x80000000-0xffffffff is not cached and used to access IO devices. */
 225 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
 226 {
 227     if (value) {
 228         env->flags |= LM32_FLAG_IGNORE_MSB;
 229     } else {
 230         env->flags &= ~LM32_FLAG_IGNORE_MSB;
 231     }
 232 }