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git.proxmox.com Git - qemu.git/blob - target-microblaze/helper.c
2 * MicroBlaze helper routines.
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "host-utils.h"
26 #if defined(CONFIG_USER_ONLY)
28 void do_interrupt (CPUState
*env
)
30 env
->exception_index
= -1;
31 env
->regs
[14] = env
->sregs
[SR_PC
];
34 int cpu_mb_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
37 env
->exception_index
= 0xaa;
38 cpu_dump_state(env
, stderr
, fprintf
, 0);
42 #else /* !CONFIG_USER_ONLY */
44 int cpu_mb_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
48 unsigned int mmu_available
;
53 if (env
->pvr
.regs
[0] & PVR0_USE_MMU
) {
55 if ((env
->pvr
.regs
[0] & PVR0_PVR_FULL_MASK
)
56 && (env
->pvr
.regs
[11] & PVR11_USE_MMU
) != PVR11_USE_MMU
) {
61 /* Translate if the MMU is available and enabled. */
62 if (mmu_available
&& (env
->sregs
[SR_MSR
] & MSR_VM
)) {
63 target_ulong vaddr
, paddr
;
64 struct microblaze_mmu_lookup lu
;
66 hit
= mmu_translate(&env
->mmu
, &lu
, address
, rw
, mmu_idx
);
68 vaddr
= address
& TARGET_PAGE_MASK
;
69 paddr
= lu
.paddr
+ vaddr
- lu
.vaddr
;
71 DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
72 mmu_idx
, vaddr
, paddr
, lu
.prot
));
73 tlb_set_page(env
, vaddr
, paddr
, lu
.prot
, mmu_idx
, TARGET_PAGE_SIZE
);
76 env
->sregs
[SR_EAR
] = address
;
77 DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx
, address
));
81 env
->sregs
[SR_ESR
] = rw
== 2 ? 17 : 16;
82 env
->sregs
[SR_ESR
] |= (rw
== 1) << 10;
85 env
->sregs
[SR_ESR
] = rw
== 2 ? 19 : 18;
86 env
->sregs
[SR_ESR
] |= (rw
== 1) << 10;
93 if (env
->exception_index
== EXCP_MMU
) {
94 cpu_abort(env
, "recursive faults\n");
98 env
->exception_index
= EXCP_MMU
;
101 /* MMU disabled or not available. */
102 address
&= TARGET_PAGE_MASK
;
104 tlb_set_page(env
, address
, address
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
110 void do_interrupt(CPUState
*env
)
114 /* IMM flag cannot propagate across a branch and into the dslot. */
115 assert(!((env
->iflags
& D_FLAG
) && (env
->iflags
& IMM_FLAG
)));
116 assert(!(env
->iflags
& (DRTI_FLAG
| DRTE_FLAG
| DRTB_FLAG
)));
117 /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
118 switch (env
->exception_index
) {
120 if (!(env
->pvr
.regs
[0] & PVR0_USE_EXC_MASK
)) {
121 qemu_log("Exception raised on system without exceptions!\n");
125 env
->regs
[17] = env
->sregs
[SR_PC
] + 4;
126 env
->sregs
[SR_ESR
] &= ~(1 << 12);
128 /* Exception breaks branch + dslot sequence? */
129 if (env
->iflags
& D_FLAG
) {
130 env
->sregs
[SR_ESR
] |= 1 << 12 ;
131 env
->sregs
[SR_BTR
] = env
->btarget
;
134 /* Disable the MMU. */
135 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
136 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
137 env
->sregs
[SR_MSR
] |= t
;
138 /* Exception in progress. */
139 env
->sregs
[SR_MSR
] |= MSR_EIP
;
141 qemu_log_mask(CPU_LOG_INT
,
142 "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
143 env
->sregs
[SR_PC
], env
->sregs
[SR_EAR
],
144 env
->sregs
[SR_ESR
], env
->iflags
);
145 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
146 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
147 env
->sregs
[SR_PC
] = 0x20;
151 env
->regs
[17] = env
->sregs
[SR_PC
];
153 env
->sregs
[SR_ESR
] &= ~(1 << 12);
154 /* Exception breaks branch + dslot sequence? */
155 if (env
->iflags
& D_FLAG
) {
156 D(qemu_log("D_FLAG set at exception bimm=%d\n", env
->bimm
));
157 env
->sregs
[SR_ESR
] |= 1 << 12 ;
158 env
->sregs
[SR_BTR
] = env
->btarget
;
160 /* Reexecute the branch. */
162 /* was the branch immprefixed?. */
164 qemu_log_mask(CPU_LOG_INT
,
165 "bimm exception at pc=%x iflags=%x\n",
166 env
->sregs
[SR_PC
], env
->iflags
);
168 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
170 } else if (env
->iflags
& IMM_FLAG
) {
171 D(qemu_log("IMM_FLAG set at exception\n"));
175 /* Disable the MMU. */
176 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
177 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
178 env
->sregs
[SR_MSR
] |= t
;
179 /* Exception in progress. */
180 env
->sregs
[SR_MSR
] |= MSR_EIP
;
182 qemu_log_mask(CPU_LOG_INT
,
183 "exception at pc=%x ear=%x iflags=%x\n",
184 env
->sregs
[SR_PC
], env
->sregs
[SR_EAR
], env
->iflags
);
185 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
186 env
->iflags
&= ~(IMM_FLAG
| D_FLAG
);
187 env
->sregs
[SR_PC
] = 0x20;
191 assert(!(env
->sregs
[SR_MSR
] & (MSR_EIP
| MSR_BIP
)));
192 assert(env
->sregs
[SR_MSR
] & MSR_IE
);
193 assert(!(env
->iflags
& D_FLAG
));
195 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
200 /* Useful instrumentation when debugging interrupt issues in either
201 the models or in sw. */
205 sym
= lookup_symbol(env
->sregs
[SR_PC
]);
207 && (!strcmp("netif_rx", sym
)
208 || !strcmp("process_backlog", sym
))) {
211 "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
212 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
,
215 log_cpu_state(env
, 0);
219 qemu_log_mask(CPU_LOG_INT
,
220 "interrupt at pc=%x msr=%x %x iflags=%x\n",
221 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
);
223 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM \
225 env
->sregs
[SR_MSR
] |= t
;
227 env
->regs
[14] = env
->sregs
[SR_PC
];
228 env
->sregs
[SR_PC
] = 0x10;
229 //log_cpu_state_mask(CPU_LOG_INT, env, 0);
234 assert(!(env
->iflags
& IMM_FLAG
));
235 assert(!(env
->iflags
& D_FLAG
));
236 t
= (env
->sregs
[SR_MSR
] & (MSR_VM
| MSR_UM
)) << 1;
237 qemu_log_mask(CPU_LOG_INT
,
238 "break at pc=%x msr=%x %x iflags=%x\n",
239 env
->sregs
[SR_PC
], env
->sregs
[SR_MSR
], t
, env
->iflags
);
240 log_cpu_state_mask(CPU_LOG_INT
, env
, 0);
241 env
->sregs
[SR_MSR
] &= ~(MSR_VMS
| MSR_UMS
| MSR_VM
| MSR_UM
);
242 env
->sregs
[SR_MSR
] |= t
;
243 env
->sregs
[SR_MSR
] |= MSR_BIP
;
244 if (env
->exception_index
== EXCP_HW_BREAK
) {
245 env
->regs
[16] = env
->sregs
[SR_PC
];
246 env
->sregs
[SR_MSR
] |= MSR_BIP
;
247 env
->sregs
[SR_PC
] = 0x18;
249 env
->sregs
[SR_PC
] = env
->btarget
;
252 cpu_abort(env
, "unhandled exception type=%d\n",
253 env
->exception_index
);
258 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
260 target_ulong vaddr
, paddr
= 0;
261 struct microblaze_mmu_lookup lu
;
264 if (env
->sregs
[SR_MSR
] & MSR_VM
) {
265 hit
= mmu_translate(&env
->mmu
, &lu
, addr
, 0, 0);
267 vaddr
= addr
& TARGET_PAGE_MASK
;
268 paddr
= lu
.paddr
+ vaddr
- lu
.vaddr
;
270 paddr
= 0; /* ???. */
272 paddr
= addr
& TARGET_PAGE_MASK
;