target-microblaze/op_helper.c

   1 /*
   2  *  Microblaze helper routines.
   3  *
   4  *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
   5  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <assert.h>
  22 #include "cpu.h"
  23 #include "dyngen-exec.h"
  24 #include "helper.h"
  25 #include "host-utils.h"
  26
  27 #define D(x)
  28
  29 #if !defined(CONFIG_USER_ONLY)
  30 #include "softmmu_exec.h"
  31
  32 #define MMUSUFFIX _mmu
  33 #define SHIFT 0
  34 #include "softmmu_template.h"
  35 #define SHIFT 1
  36 #include "softmmu_template.h"
  37 #define SHIFT 2
  38 #include "softmmu_template.h"
  39 #define SHIFT 3
  40 #include "softmmu_template.h"
  41
  42 /* Try to fill the TLB and return an exception if error. If retaddr is
  43    NULL, it means that the function was called in C code (i.e. not
  44    from generated code or from helper.c) */
  45 /* XXX: fix it to restore all registers */
  46 void tlb_fill(CPUMBState *env1, target_ulong addr, int is_write, int mmu_idx,
  47               void *retaddr)
  48 {
  49     TranslationBlock *tb;
  50     CPUMBState *saved_env;
  51     unsigned long pc;
  52     int ret;
  53
  54     saved_env = env;
  55     env = env1;
  56
  57     ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
  58     if (unlikely(ret)) {
  59         if (retaddr) {
  60             /* now we have a real cpu fault */
  61             pc = (unsigned long)retaddr;
  62             tb = tb_find_pc(pc);
  63             if (tb) {
  64                 /* the PC is inside the translated code. It means that we have
  65                    a virtual CPU fault */
  66                 cpu_restore_state(tb, env, pc);
  67             }
  68         }
  69         cpu_loop_exit(env);
  70     }
  71     env = saved_env;
  72 }
  73 #endif
  74
  75 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
  76 {
  77     int test = ctrl & STREAM_TEST;
  78     int atomic = ctrl & STREAM_ATOMIC;
  79     int control = ctrl & STREAM_CONTROL;
  80     int nonblock = ctrl & STREAM_NONBLOCK;
  81     int exception = ctrl & STREAM_EXCEPTION;
  82
  83     qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
  84              id, data,
  85              test ? "t" : "",
  86              nonblock ? "n" : "",
  87              exception ? "e" : "",
  88              control ? "c" : "",
  89              atomic ? "a" : "");
  90 }
  91
  92 uint32_t helper_get(uint32_t id, uint32_t ctrl)
  93 {
  94     int test = ctrl & STREAM_TEST;
  95     int atomic = ctrl & STREAM_ATOMIC;
  96     int control = ctrl & STREAM_CONTROL;
  97     int nonblock = ctrl & STREAM_NONBLOCK;
  98     int exception = ctrl & STREAM_EXCEPTION;
  99
 100     qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
 101              id,
 102              test ? "t" : "",
 103              nonblock ? "n" : "",
 104              exception ? "e" : "",
 105              control ? "c" : "",
 106              atomic ? "a" : "");
 107     return 0xdead0000 | id;
 108 }
 109
 110 void helper_raise_exception(uint32_t index)
 111 {
 112     env->exception_index = index;
 113     cpu_loop_exit(env);
 114 }
 115
 116 void helper_debug(void)
 117 {
 118     int i;
 119
 120     qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
 121     qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
 122              env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
 123              env->debug, env->imm, env->iflags);
 124     qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
 125              env->btaken, env->btarget,
 126              (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
 127              (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
 128              (env->sregs[SR_MSR] & MSR_EIP),
 129              (env->sregs[SR_MSR] & MSR_IE));
 130     for (i = 0; i < 32; i++) {
 131         qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
 132         if ((i + 1) % 4 == 0)
 133             qemu_log("\n");
 134     }
 135     qemu_log("\n\n");
 136 }
 137
 138 static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
 139 {
 140     uint32_t cout = 0;
 141
 142     if ((b == ~0) && cin)
 143         cout = 1;
 144     else if ((~0 - a) < (b + cin))
 145         cout = 1;
 146     return cout;
 147 }
 148
 149 uint32_t helper_cmp(uint32_t a, uint32_t b)
 150 {
 151     uint32_t t;
 152
 153     t = b + ~a + 1;
 154     if ((b & 0x80000000) ^ (a & 0x80000000))
 155         t = (t & 0x7fffffff) | (b & 0x80000000);
 156     return t;
 157 }
 158
 159 uint32_t helper_cmpu(uint32_t a, uint32_t b)
 160 {
 161     uint32_t t;
 162
 163     t = b + ~a + 1;
 164     if ((b & 0x80000000) ^ (a & 0x80000000))
 165         t = (t & 0x7fffffff) | (a & 0x80000000);
 166     return t;
 167 }
 168
 169 uint32_t helper_clz(uint32_t t0)
 170 {
 171     return clz32(t0);
 172 }
 173
 174 uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
 175 {
 176     uint32_t ncf;
 177     ncf = compute_carry(a, b, cf);
 178     return ncf;
 179 }
 180
 181 static inline int div_prepare(uint32_t a, uint32_t b)
 182 {
 183     if (b == 0) {
 184         env->sregs[SR_MSR] |= MSR_DZ;
 185
 186         if ((env->sregs[SR_MSR] & MSR_EE)
 187             && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
 188             env->sregs[SR_ESR] = ESR_EC_DIVZERO;
 189             helper_raise_exception(EXCP_HW_EXCP);
 190         }
 191         return 0;
 192     }
 193     env->sregs[SR_MSR] &= ~MSR_DZ;
 194     return 1;
 195 }
 196
 197 uint32_t helper_divs(uint32_t a, uint32_t b)
 198 {
 199     if (!div_prepare(a, b))
 200         return 0;
 201     return (int32_t)a / (int32_t)b;
 202 }
 203
 204 uint32_t helper_divu(uint32_t a, uint32_t b)
 205 {
 206     if (!div_prepare(a, b))
 207         return 0;
 208     return a / b;
 209 }
 210
 211 /* raise FPU exception.  */
 212 static void raise_fpu_exception(void)
 213 {
 214     env->sregs[SR_ESR] = ESR_EC_FPU;
 215     helper_raise_exception(EXCP_HW_EXCP);
 216 }
 217
 218 static void update_fpu_flags(int flags)
 219 {
 220     int raise = 0;
 221
 222     if (flags & float_flag_invalid) {
 223         env->sregs[SR_FSR] |= FSR_IO;
 224         raise = 1;
 225     }
 226     if (flags & float_flag_divbyzero) {
 227         env->sregs[SR_FSR] |= FSR_DZ;
 228         raise = 1;
 229     }
 230     if (flags & float_flag_overflow) {
 231         env->sregs[SR_FSR] |= FSR_OF;
 232         raise = 1;
 233     }
 234     if (flags & float_flag_underflow) {
 235         env->sregs[SR_FSR] |= FSR_UF;
 236         raise = 1;
 237     }
 238     if (raise
 239         && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
 240         && (env->sregs[SR_MSR] & MSR_EE)) {
 241         raise_fpu_exception();
 242     }
 243 }
 244
 245 uint32_t helper_fadd(uint32_t a, uint32_t b)
 246 {
 247     CPU_FloatU fd, fa, fb;
 248     int flags;
 249
 250     set_float_exception_flags(0, &env->fp_status);
 251     fa.l = a;
 252     fb.l = b;
 253     fd.f = float32_add(fa.f, fb.f, &env->fp_status);
 254
 255     flags = get_float_exception_flags(&env->fp_status);
 256     update_fpu_flags(flags);
 257     return fd.l;
 258 }
 259
 260 uint32_t helper_frsub(uint32_t a, uint32_t b)
 261 {
 262     CPU_FloatU fd, fa, fb;
 263     int flags;
 264
 265     set_float_exception_flags(0, &env->fp_status);
 266     fa.l = a;
 267     fb.l = b;
 268     fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
 269     flags = get_float_exception_flags(&env->fp_status);
 270     update_fpu_flags(flags);
 271     return fd.l;
 272 }
 273
 274 uint32_t helper_fmul(uint32_t a, uint32_t b)
 275 {
 276     CPU_FloatU fd, fa, fb;
 277     int flags;
 278
 279     set_float_exception_flags(0, &env->fp_status);
 280     fa.l = a;
 281     fb.l = b;
 282     fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
 283     flags = get_float_exception_flags(&env->fp_status);
 284     update_fpu_flags(flags);
 285
 286     return fd.l;
 287 }
 288
 289 uint32_t helper_fdiv(uint32_t a, uint32_t b)
 290 {
 291     CPU_FloatU fd, fa, fb;
 292     int flags;
 293
 294     set_float_exception_flags(0, &env->fp_status);
 295     fa.l = a;
 296     fb.l = b;
 297     fd.f = float32_div(fb.f, fa.f, &env->fp_status);
 298     flags = get_float_exception_flags(&env->fp_status);
 299     update_fpu_flags(flags);
 300
 301     return fd.l;
 302 }
 303
 304 uint32_t helper_fcmp_un(uint32_t a, uint32_t b)
 305 {
 306     CPU_FloatU fa, fb;
 307     uint32_t r = 0;
 308
 309     fa.l = a;
 310     fb.l = b;
 311
 312     if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
 313         update_fpu_flags(float_flag_invalid);
 314         r = 1;
 315     }
 316
 317     if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
 318         r = 1;
 319     }
 320
 321     return r;
 322 }
 323
 324 uint32_t helper_fcmp_lt(uint32_t a, uint32_t b)
 325 {
 326     CPU_FloatU fa, fb;
 327     int r;
 328     int flags;
 329
 330     set_float_exception_flags(0, &env->fp_status);
 331     fa.l = a;
 332     fb.l = b;
 333     r = float32_lt(fb.f, fa.f, &env->fp_status);
 334     flags = get_float_exception_flags(&env->fp_status);
 335     update_fpu_flags(flags & float_flag_invalid);
 336
 337     return r;
 338 }
 339
 340 uint32_t helper_fcmp_eq(uint32_t a, uint32_t b)
 341 {
 342     CPU_FloatU fa, fb;
 343     int flags;
 344     int r;
 345
 346     set_float_exception_flags(0, &env->fp_status);
 347     fa.l = a;
 348     fb.l = b;
 349     r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 350     flags = get_float_exception_flags(&env->fp_status);
 351     update_fpu_flags(flags & float_flag_invalid);
 352
 353     return r;
 354 }
 355
 356 uint32_t helper_fcmp_le(uint32_t a, uint32_t b)
 357 {
 358     CPU_FloatU fa, fb;
 359     int flags;
 360     int r;
 361
 362     fa.l = a;
 363     fb.l = b;
 364     set_float_exception_flags(0, &env->fp_status);
 365     r = float32_le(fa.f, fb.f, &env->fp_status);
 366     flags = get_float_exception_flags(&env->fp_status);
 367     update_fpu_flags(flags & float_flag_invalid);
 368
 369
 370     return r;
 371 }
 372
 373 uint32_t helper_fcmp_gt(uint32_t a, uint32_t b)
 374 {
 375     CPU_FloatU fa, fb;
 376     int flags, r;
 377
 378     fa.l = a;
 379     fb.l = b;
 380     set_float_exception_flags(0, &env->fp_status);
 381     r = float32_lt(fa.f, fb.f, &env->fp_status);
 382     flags = get_float_exception_flags(&env->fp_status);
 383     update_fpu_flags(flags & float_flag_invalid);
 384     return r;
 385 }
 386
 387 uint32_t helper_fcmp_ne(uint32_t a, uint32_t b)
 388 {
 389     CPU_FloatU fa, fb;
 390     int flags, r;
 391
 392     fa.l = a;
 393     fb.l = b;
 394     set_float_exception_flags(0, &env->fp_status);
 395     r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
 396     flags = get_float_exception_flags(&env->fp_status);
 397     update_fpu_flags(flags & float_flag_invalid);
 398
 399     return r;
 400 }
 401
 402 uint32_t helper_fcmp_ge(uint32_t a, uint32_t b)
 403 {
 404     CPU_FloatU fa, fb;
 405     int flags, r;
 406
 407     fa.l = a;
 408     fb.l = b;
 409     set_float_exception_flags(0, &env->fp_status);
 410     r = !float32_lt(fa.f, fb.f, &env->fp_status);
 411     flags = get_float_exception_flags(&env->fp_status);
 412     update_fpu_flags(flags & float_flag_invalid);
 413
 414     return r;
 415 }
 416
 417 uint32_t helper_flt(uint32_t a)
 418 {
 419     CPU_FloatU fd, fa;
 420
 421     fa.l = a;
 422     fd.f = int32_to_float32(fa.l, &env->fp_status);
 423     return fd.l;
 424 }
 425
 426 uint32_t helper_fint(uint32_t a)
 427 {
 428     CPU_FloatU fa;
 429     uint32_t r;
 430     int flags;
 431
 432     set_float_exception_flags(0, &env->fp_status);
 433     fa.l = a;
 434     r = float32_to_int32(fa.f, &env->fp_status);
 435     flags = get_float_exception_flags(&env->fp_status);
 436     update_fpu_flags(flags);
 437
 438     return r;
 439 }
 440
 441 uint32_t helper_fsqrt(uint32_t a)
 442 {
 443     CPU_FloatU fd, fa;
 444     int flags;
 445
 446     set_float_exception_flags(0, &env->fp_status);
 447     fa.l = a;
 448     fd.l = float32_sqrt(fa.f, &env->fp_status);
 449     flags = get_float_exception_flags(&env->fp_status);
 450     update_fpu_flags(flags);
 451
 452     return fd.l;
 453 }
 454
 455 uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
 456 {
 457     unsigned int i;
 458     uint32_t mask = 0xff000000;
 459
 460     for (i = 0; i < 4; i++) {
 461         if ((a & mask) == (b & mask))
 462             return i + 1;
 463         mask >>= 8;
 464     }
 465     return 0;
 466 }
 467
 468 void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
 469 {
 470     if (addr & mask) {
 471             qemu_log_mask(CPU_LOG_INT,
 472                           "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
 473                           addr, mask, wr, dr);
 474             env->sregs[SR_EAR] = addr;
 475             env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
 476                                  | (dr & 31) << 5;
 477             if (mask == 3) {
 478                 env->sregs[SR_ESR] |= 1 << 11;
 479             }
 480             if (!(env->sregs[SR_MSR] & MSR_EE)) {
 481                 return;
 482             }
 483             helper_raise_exception(EXCP_HW_EXCP);
 484     }
 485 }
 486
 487 void helper_stackprot(uint32_t addr)
 488 {
 489     if (addr < env->slr || addr > env->shr) {
 490             qemu_log("Stack protector violation at %x %x %x\n",
 491                      addr, env->slr, env->shr);
 492             env->sregs[SR_EAR] = addr;
 493             env->sregs[SR_ESR] = ESR_EC_STACKPROT;
 494             helper_raise_exception(EXCP_HW_EXCP);
 495     }
 496 }
 497
 498 #if !defined(CONFIG_USER_ONLY)
 499 /* Writes/reads to the MMU's special regs end up here.  */
 500 uint32_t helper_mmu_read(uint32_t rn)
 501 {
 502     return mmu_read(env, rn);
 503 }
 504
 505 void helper_mmu_write(uint32_t rn, uint32_t v)
 506 {
 507     mmu_write(env, rn, v);
 508 }
 509
 510 void cpu_unassigned_access(CPUMBState *env1, target_phys_addr_t addr,
 511                            int is_write, int is_exec, int is_asi, int size)
 512 {
 513     CPUMBState *saved_env;
 514
 515     saved_env = env;
 516     env = env1;
 517
 518     qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
 519              addr, is_write, is_exec);
 520     if (!(env->sregs[SR_MSR] & MSR_EE)) {
 521         env = saved_env;
 522         return;
 523     }
 524
 525     env->sregs[SR_EAR] = addr;
 526     if (is_exec) {
 527         if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
 528             env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
 529             helper_raise_exception(EXCP_HW_EXCP);
 530         }
 531     } else {
 532         if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
 533             env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
 534             helper_raise_exception(EXCP_HW_EXCP);
 535         }
 536     }
 537     env = saved_env;
 538 }
 539 #endif