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microblaze: Catch illegal insns and privilege violations.
[qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "helper.h"
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
34
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 #define SIM_COMPAT 0
39 #define DISAS_GNU 1
40 #define DISAS_MB 1
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 static TCGv env_debug;
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_R[32];
55 static TCGv cpu_SR[18];
56 static TCGv env_imm;
57 static TCGv env_btaken;
58 static TCGv env_btarget;
59 static TCGv env_iflags;
60
61 #include "gen-icount.h"
62
63 /* This is the state at translation time. */
64 typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc, ppc;
67 target_ulong cache_pc;
68
69 /* Decoder. */
70 int type_b;
71 uint32_t ir;
72 uint8_t opcode;
73 uint8_t rd, ra, rb;
74 uint16_t imm;
75
76 unsigned int cpustate_changed;
77 unsigned int delayed_branch;
78 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
79 unsigned int clear_imm;
80 int is_jmp;
81
82 #define JMP_NOJMP 0
83 #define JMP_DIRECT 1
84 #define JMP_INDIRECT 2
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92 } DisasContext;
93
94 const static char *regnames[] =
95 {
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100 };
101
102 const static char *special_regnames[] =
103 {
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107 };
108
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val, unsigned int width)
111 {
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120 }
121
122 static inline void t_sync_flags(DisasContext *dc)
123 {
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129 }
130
131 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132 {
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140 }
141
142 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143 {
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154 }
155
156 static inline TCGv *dec_alu_op_b(DisasContext *dc)
157 {
158 if (dc->type_b) {
159 if (dc->tb_flags & IMM_FLAG)
160 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
161 else
162 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
163 return &env_imm;
164 } else
165 return &cpu_R[dc->rb];
166 }
167
168 static void dec_add(DisasContext *dc)
169 {
170 unsigned int k, c;
171
172 k = dc->opcode & 4;
173 c = dc->opcode & 2;
174
175 LOG_DIS("add%s%s%s r%d r%d r%d\n",
176 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
177 dc->rd, dc->ra, dc->rb);
178
179 if (k && !c && dc->rd)
180 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
181 else if (dc->rd)
182 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
183 tcg_const_tl(k), tcg_const_tl(c));
184 else {
185 TCGv d = tcg_temp_new();
186 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
187 tcg_const_tl(k), tcg_const_tl(c));
188 tcg_temp_free(d);
189 }
190 }
191
192 static void dec_sub(DisasContext *dc)
193 {
194 unsigned int u, cmp, k, c;
195
196 u = dc->imm & 2;
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199 cmp = (dc->imm & 1) && (!dc->type_b) && k;
200
201 if (cmp) {
202 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
203 if (dc->rd) {
204 if (u)
205 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
206 else
207 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
208 }
209 } else {
210 LOG_DIS("sub%s%s r%d, r%d r%d\n",
211 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
212
213 if (!k || c) {
214 TCGv t;
215 t = tcg_temp_new();
216 if (dc->rd)
217 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
218 tcg_const_tl(k), tcg_const_tl(c));
219 else
220 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
221 tcg_const_tl(k), tcg_const_tl(c));
222 tcg_temp_free(t);
223 }
224 else if (dc->rd)
225 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
226 }
227 }
228
229 static void dec_pattern(DisasContext *dc)
230 {
231 unsigned int mode;
232 int l1;
233
234 if ((dc->tb_flags & MSR_EE_FLAG)
235 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
236 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
237 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
238 t_gen_raise_exception(dc, EXCP_HW_EXCP);
239 }
240
241 mode = dc->opcode & 3;
242 switch (mode) {
243 case 0:
244 /* pcmpbf. */
245 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
246 if (dc->rd)
247 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
248 break;
249 case 2:
250 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
251 if (dc->rd) {
252 TCGv t0 = tcg_temp_local_new();
253 l1 = gen_new_label();
254 tcg_gen_movi_tl(t0, 1);
255 tcg_gen_brcond_tl(TCG_COND_EQ,
256 cpu_R[dc->ra], cpu_R[dc->rb], l1);
257 tcg_gen_movi_tl(t0, 0);
258 gen_set_label(l1);
259 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
260 tcg_temp_free(t0);
261 }
262 break;
263 case 3:
264 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
265 l1 = gen_new_label();
266 if (dc->rd) {
267 TCGv t0 = tcg_temp_local_new();
268 tcg_gen_movi_tl(t0, 1);
269 tcg_gen_brcond_tl(TCG_COND_NE,
270 cpu_R[dc->ra], cpu_R[dc->rb], l1);
271 tcg_gen_movi_tl(t0, 0);
272 gen_set_label(l1);
273 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
274 tcg_temp_free(t0);
275 }
276 break;
277 default:
278 cpu_abort(dc->env,
279 "unsupported pattern insn opcode=%x\n", dc->opcode);
280 break;
281 }
282 }
283
284 static void dec_and(DisasContext *dc)
285 {
286 unsigned int not;
287
288 if (!dc->type_b && (dc->imm & (1 << 10))) {
289 dec_pattern(dc);
290 return;
291 }
292
293 not = dc->opcode & (1 << 1);
294 LOG_DIS("and%s\n", not ? "n" : "");
295
296 if (!dc->rd)
297 return;
298
299 if (not) {
300 TCGv t = tcg_temp_new();
301 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
302 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
303 tcg_temp_free(t);
304 } else
305 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
306 }
307
308 static void dec_or(DisasContext *dc)
309 {
310 if (!dc->type_b && (dc->imm & (1 << 10))) {
311 dec_pattern(dc);
312 return;
313 }
314
315 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
316 if (dc->rd)
317 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
318 }
319
320 static void dec_xor(DisasContext *dc)
321 {
322 if (!dc->type_b && (dc->imm & (1 << 10))) {
323 dec_pattern(dc);
324 return;
325 }
326
327 LOG_DIS("xor r%d\n", dc->rd);
328 if (dc->rd)
329 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
330 }
331
332 static void read_carry(DisasContext *dc, TCGv d)
333 {
334 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
335 }
336
337 static void write_carry(DisasContext *dc, TCGv v)
338 {
339 TCGv t0 = tcg_temp_new();
340 tcg_gen_shli_tl(t0, v, 31);
341 tcg_gen_sari_tl(t0, t0, 31);
342 tcg_gen_mov_tl(env_debug, t0);
343 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
344 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
345 ~(MSR_C | MSR_CC));
346 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
347 tcg_temp_free(t0);
348 }
349
350
351 static inline void msr_read(DisasContext *dc, TCGv d)
352 {
353 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
354 }
355
356 static inline void msr_write(DisasContext *dc, TCGv v)
357 {
358 dc->cpustate_changed = 1;
359 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
360 /* PVR, we have a processor version register. */
361 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
362 }
363
364 static void dec_msr(DisasContext *dc)
365 {
366 TCGv t0, t1;
367 unsigned int sr, to, rn;
368 int mem_index = cpu_mmu_index(dc->env);
369
370 sr = dc->imm & ((1 << 14) - 1);
371 to = dc->imm & (1 << 14);
372 dc->type_b = 1;
373 if (to)
374 dc->cpustate_changed = 1;
375
376 /* msrclr and msrset. */
377 if (!(dc->imm & (1 << 15))) {
378 unsigned int clr = dc->ir & (1 << 16);
379
380 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
381 dc->rd, dc->imm);
382
383 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
384 /* nop??? */
385 return;
386 }
387
388 if ((dc->tb_flags & MSR_EE_FLAG)
389 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
390 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
391 t_gen_raise_exception(dc, EXCP_HW_EXCP);
392 return;
393 }
394
395 if (dc->rd)
396 msr_read(dc, cpu_R[dc->rd]);
397
398 t0 = tcg_temp_new();
399 t1 = tcg_temp_new();
400 msr_read(dc, t0);
401 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
402
403 if (clr) {
404 tcg_gen_not_tl(t1, t1);
405 tcg_gen_and_tl(t0, t0, t1);
406 } else
407 tcg_gen_or_tl(t0, t0, t1);
408 msr_write(dc, t0);
409 tcg_temp_free(t0);
410 tcg_temp_free(t1);
411 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
412 dc->is_jmp = DISAS_UPDATE;
413 return;
414 }
415
416 if (to) {
417 if ((dc->tb_flags & MSR_EE_FLAG)
418 && mem_index == MMU_USER_IDX) {
419 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
420 t_gen_raise_exception(dc, EXCP_HW_EXCP);
421 return;
422 }
423 }
424
425 #if !defined(CONFIG_USER_ONLY)
426 /* Catch read/writes to the mmu block. */
427 if ((sr & ~0xff) == 0x1000) {
428 sr &= 7;
429 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
430 if (to)
431 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
432 else
433 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
434 return;
435 }
436 #endif
437
438 if (to) {
439 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
440 switch (sr) {
441 case 0:
442 break;
443 case 1:
444 msr_write(dc, cpu_R[dc->ra]);
445 break;
446 case 0x3:
447 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
448 break;
449 case 0x5:
450 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
451 break;
452 case 0x7:
453 /* Ignored at the moment. */
454 break;
455 default:
456 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
457 break;
458 }
459 } else {
460 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
461
462 switch (sr) {
463 case 0:
464 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
465 break;
466 case 1:
467 msr_read(dc, cpu_R[dc->rd]);
468 break;
469 case 0x3:
470 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
471 break;
472 case 0x5:
473 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
474 break;
475 case 0x7:
476 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
477 break;
478 case 0xb:
479 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
480 break;
481 case 0x2000:
482 case 0x2001:
483 case 0x2002:
484 case 0x2003:
485 case 0x2004:
486 case 0x2005:
487 case 0x2006:
488 case 0x2007:
489 case 0x2008:
490 case 0x2009:
491 case 0x200a:
492 case 0x200b:
493 case 0x200c:
494 rn = sr & 0xf;
495 tcg_gen_ld_tl(cpu_R[dc->rd],
496 cpu_env, offsetof(CPUState, pvr.regs[rn]));
497 break;
498 default:
499 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
500 break;
501 }
502 }
503 }
504
505 /* 64-bit signed mul, lower result in d and upper in d2. */
506 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
507 {
508 TCGv_i64 t0, t1;
509
510 t0 = tcg_temp_new_i64();
511 t1 = tcg_temp_new_i64();
512
513 tcg_gen_ext_i32_i64(t0, a);
514 tcg_gen_ext_i32_i64(t1, b);
515 tcg_gen_mul_i64(t0, t0, t1);
516
517 tcg_gen_trunc_i64_i32(d, t0);
518 tcg_gen_shri_i64(t0, t0, 32);
519 tcg_gen_trunc_i64_i32(d2, t0);
520
521 tcg_temp_free_i64(t0);
522 tcg_temp_free_i64(t1);
523 }
524
525 /* 64-bit unsigned muls, lower result in d and upper in d2. */
526 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
527 {
528 TCGv_i64 t0, t1;
529
530 t0 = tcg_temp_new_i64();
531 t1 = tcg_temp_new_i64();
532
533 tcg_gen_extu_i32_i64(t0, a);
534 tcg_gen_extu_i32_i64(t1, b);
535 tcg_gen_mul_i64(t0, t0, t1);
536
537 tcg_gen_trunc_i64_i32(d, t0);
538 tcg_gen_shri_i64(t0, t0, 32);
539 tcg_gen_trunc_i64_i32(d2, t0);
540
541 tcg_temp_free_i64(t0);
542 tcg_temp_free_i64(t1);
543 }
544
545 /* Multiplier unit. */
546 static void dec_mul(DisasContext *dc)
547 {
548 TCGv d[2];
549 unsigned int subcode;
550
551 if ((dc->tb_flags & MSR_EE_FLAG)
552 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
553 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
554 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
555 t_gen_raise_exception(dc, EXCP_HW_EXCP);
556 return;
557 }
558
559 subcode = dc->imm & 3;
560 d[0] = tcg_temp_new();
561 d[1] = tcg_temp_new();
562
563 if (dc->type_b) {
564 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
565 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
566 goto done;
567 }
568
569 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
570 if (subcode >= 1 && subcode <= 3
571 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
572 /* nop??? */
573 }
574
575 switch (subcode) {
576 case 0:
577 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
578 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
579 break;
580 case 1:
581 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
582 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
583 break;
584 case 2:
585 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
586 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
587 break;
588 case 3:
589 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
590 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
591 break;
592 default:
593 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
594 break;
595 }
596 done:
597 tcg_temp_free(d[0]);
598 tcg_temp_free(d[1]);
599 }
600
601 /* Div unit. */
602 static void dec_div(DisasContext *dc)
603 {
604 unsigned int u;
605
606 u = dc->imm & 2;
607 LOG_DIS("div\n");
608
609 if (!(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
610 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
611 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
612 t_gen_raise_exception(dc, EXCP_HW_EXCP);
613 }
614
615 /* FIXME: support div by zero exceptions. */
616 if (u)
617 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
618 else
619 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
620 if (!dc->rd)
621 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
622 }
623
624 static void dec_barrel(DisasContext *dc)
625 {
626 TCGv t0;
627 unsigned int s, t;
628
629 if ((dc->tb_flags & MSR_EE_FLAG)
630 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
631 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
632 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
633 t_gen_raise_exception(dc, EXCP_HW_EXCP);
634 return;
635 }
636
637 s = dc->imm & (1 << 10);
638 t = dc->imm & (1 << 9);
639
640 LOG_DIS("bs%s%s r%d r%d r%d\n",
641 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
642
643 t0 = tcg_temp_new();
644
645 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
646 tcg_gen_andi_tl(t0, t0, 31);
647
648 if (s)
649 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
650 else {
651 if (t)
652 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
653 else
654 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
655 }
656 }
657
658 static void dec_bit(DisasContext *dc)
659 {
660 TCGv t0, t1;
661 unsigned int op;
662 int mem_index = cpu_mmu_index(dc->env);
663
664 op = dc->ir & ((1 << 8) - 1);
665 switch (op) {
666 case 0x21:
667 /* src. */
668 t0 = tcg_temp_new();
669
670 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
671 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
672 if (dc->rd) {
673 t1 = tcg_temp_new();
674 read_carry(dc, t1);
675 tcg_gen_shli_tl(t1, t1, 31);
676
677 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
678 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
679 tcg_temp_free(t1);
680 }
681
682 /* Update carry. */
683 write_carry(dc, t0);
684 tcg_temp_free(t0);
685 break;
686
687 case 0x1:
688 case 0x41:
689 /* srl. */
690 t0 = tcg_temp_new();
691 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
692
693 /* Update carry. */
694 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
695 write_carry(dc, t0);
696 tcg_temp_free(t0);
697 if (dc->rd) {
698 if (op == 0x41)
699 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
700 else
701 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
702 }
703 break;
704 case 0x60:
705 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
706 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
707 break;
708 case 0x61:
709 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
710 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
711 break;
712 case 0x64:
713 /* wdc. */
714 LOG_DIS("wdc r%d\n", dc->ra);
715 if ((dc->tb_flags & MSR_EE_FLAG)
716 && mem_index == MMU_USER_IDX) {
717 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
718 t_gen_raise_exception(dc, EXCP_HW_EXCP);
719 return;
720 }
721 break;
722 case 0x68:
723 /* wic. */
724 LOG_DIS("wic r%d\n", dc->ra);
725 if ((dc->tb_flags & MSR_EE_FLAG)
726 && mem_index == MMU_USER_IDX) {
727 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
728 t_gen_raise_exception(dc, EXCP_HW_EXCP);
729 return;
730 }
731 break;
732 default:
733 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
734 dc->pc, op, dc->rd, dc->ra, dc->rb);
735 break;
736 }
737 }
738
739 static inline void sync_jmpstate(DisasContext *dc)
740 {
741 if (dc->jmp == JMP_DIRECT) {
742 dc->jmp = JMP_INDIRECT;
743 tcg_gen_movi_tl(env_btaken, 1);
744 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
745 }
746 }
747
748 static void dec_imm(DisasContext *dc)
749 {
750 LOG_DIS("imm %x\n", dc->imm << 16);
751 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
752 dc->tb_flags |= IMM_FLAG;
753 dc->clear_imm = 0;
754 }
755
756 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
757 unsigned int size)
758 {
759 int mem_index = cpu_mmu_index(dc->env);
760
761 if (size == 1) {
762 tcg_gen_qemu_ld8u(dst, addr, mem_index);
763 } else if (size == 2) {
764 tcg_gen_qemu_ld16u(dst, addr, mem_index);
765 } else if (size == 4) {
766 tcg_gen_qemu_ld32u(dst, addr, mem_index);
767 } else
768 cpu_abort(dc->env, "Incorrect load size %d\n", size);
769 }
770
771 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
772 {
773 unsigned int extimm = dc->tb_flags & IMM_FLAG;
774
775 /* Treat the fast cases first. */
776 if (!dc->type_b) {
777 *t = tcg_temp_new();
778 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
779 return t;
780 }
781 /* Immediate. */
782 if (!extimm) {
783 if (dc->imm == 0) {
784 return &cpu_R[dc->ra];
785 }
786 *t = tcg_temp_new();
787 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
788 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
789 } else {
790 *t = tcg_temp_new();
791 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
792 }
793
794 return t;
795 }
796
797 static void dec_load(DisasContext *dc)
798 {
799 TCGv t, *addr;
800 unsigned int size;
801
802 size = 1 << (dc->opcode & 3);
803
804 LOG_DIS("l %x %d\n", dc->opcode, size);
805 t_sync_flags(dc);
806 addr = compute_ldst_addr(dc, &t);
807
808 /* If we get a fault on a dslot, the jmpstate better be in sync. */
809 sync_jmpstate(dc);
810 if (dc->rd)
811 gen_load(dc, cpu_R[dc->rd], *addr, size);
812 else {
813 gen_load(dc, env_imm, *addr, size);
814 }
815
816 if (addr == &t)
817 tcg_temp_free(t);
818 }
819
820 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
821 unsigned int size)
822 {
823 int mem_index = cpu_mmu_index(dc->env);
824
825 if (size == 1)
826 tcg_gen_qemu_st8(val, addr, mem_index);
827 else if (size == 2) {
828 tcg_gen_qemu_st16(val, addr, mem_index);
829 } else if (size == 4) {
830 tcg_gen_qemu_st32(val, addr, mem_index);
831 } else
832 cpu_abort(dc->env, "Incorrect store size %d\n", size);
833 }
834
835 static void dec_store(DisasContext *dc)
836 {
837 TCGv t, *addr;
838 unsigned int size;
839
840 size = 1 << (dc->opcode & 3);
841
842 LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");
843 t_sync_flags(dc);
844 /* If we get a fault on a dslot, the jmpstate better be in sync. */
845 sync_jmpstate(dc);
846 addr = compute_ldst_addr(dc, &t);
847 gen_store(dc, *addr, cpu_R[dc->rd], size);
848 if (addr == &t)
849 tcg_temp_free(t);
850 }
851
852 static inline void eval_cc(DisasContext *dc, unsigned int cc,
853 TCGv d, TCGv a, TCGv b)
854 {
855 int l1;
856
857 switch (cc) {
858 case CC_EQ:
859 l1 = gen_new_label();
860 tcg_gen_movi_tl(env_btaken, 1);
861 tcg_gen_brcond_tl(TCG_COND_EQ, a, b, l1);
862 tcg_gen_movi_tl(env_btaken, 0);
863 gen_set_label(l1);
864 break;
865 case CC_NE:
866 l1 = gen_new_label();
867 tcg_gen_movi_tl(env_btaken, 1);
868 tcg_gen_brcond_tl(TCG_COND_NE, a, b, l1);
869 tcg_gen_movi_tl(env_btaken, 0);
870 gen_set_label(l1);
871 break;
872 case CC_LT:
873 l1 = gen_new_label();
874 tcg_gen_movi_tl(env_btaken, 1);
875 tcg_gen_brcond_tl(TCG_COND_LT, a, b, l1);
876 tcg_gen_movi_tl(env_btaken, 0);
877 gen_set_label(l1);
878 break;
879 case CC_LE:
880 l1 = gen_new_label();
881 tcg_gen_movi_tl(env_btaken, 1);
882 tcg_gen_brcond_tl(TCG_COND_LE, a, b, l1);
883 tcg_gen_movi_tl(env_btaken, 0);
884 gen_set_label(l1);
885 break;
886 case CC_GE:
887 l1 = gen_new_label();
888 tcg_gen_movi_tl(env_btaken, 1);
889 tcg_gen_brcond_tl(TCG_COND_GE, a, b, l1);
890 tcg_gen_movi_tl(env_btaken, 0);
891 gen_set_label(l1);
892 break;
893 case CC_GT:
894 l1 = gen_new_label();
895 tcg_gen_movi_tl(env_btaken, 1);
896 tcg_gen_brcond_tl(TCG_COND_GT, a, b, l1);
897 tcg_gen_movi_tl(env_btaken, 0);
898 gen_set_label(l1);
899 break;
900 default:
901 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
902 break;
903 }
904 }
905
906 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
907 {
908 int l1;
909
910 l1 = gen_new_label();
911 /* Conditional jmp. */
912 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
913 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
914 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
915 gen_set_label(l1);
916 }
917
918 static void dec_bcc(DisasContext *dc)
919 {
920 unsigned int cc;
921 unsigned int dslot;
922
923 cc = EXTRACT_FIELD(dc->ir, 21, 23);
924 dslot = dc->ir & (1 << 25);
925 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
926
927 dc->delayed_branch = 1;
928 if (dslot) {
929 dc->delayed_branch = 2;
930 dc->tb_flags |= D_FLAG;
931 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
932 cpu_env, offsetof(CPUState, bimm));
933 }
934
935 tcg_gen_movi_tl(env_btarget, dc->pc);
936 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
937 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
938 dc->jmp = JMP_INDIRECT;
939 }
940
941 static void dec_br(DisasContext *dc)
942 {
943 unsigned int dslot, link, abs;
944
945 dslot = dc->ir & (1 << 20);
946 abs = dc->ir & (1 << 19);
947 link = dc->ir & (1 << 18);
948 LOG_DIS("br%s%s%s%s imm=%x\n",
949 abs ? "a" : "", link ? "l" : "",
950 dc->type_b ? "i" : "", dslot ? "d" : "",
951 dc->imm);
952
953 dc->delayed_branch = 1;
954 if (dslot) {
955 dc->delayed_branch = 2;
956 dc->tb_flags |= D_FLAG;
957 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
958 cpu_env, offsetof(CPUState, bimm));
959 }
960 if (link && dc->rd)
961 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
962
963 dc->jmp = JMP_INDIRECT;
964 if (abs) {
965 tcg_gen_movi_tl(env_btaken, 1);
966 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
967 if (link && !(dc->tb_flags & IMM_FLAG)
968 && (dc->imm == 8 || dc->imm == 0x18))
969 t_gen_raise_exception(dc, EXCP_BREAK);
970 if (dc->imm == 0)
971 t_gen_raise_exception(dc, EXCP_DEBUG);
972 } else {
973 if (dc->tb_flags & IMM_FLAG) {
974 tcg_gen_movi_tl(env_btaken, 1);
975 tcg_gen_movi_tl(env_btarget, dc->pc);
976 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
977 } else {
978 dc->jmp = JMP_DIRECT;
979 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
980 }
981 }
982 }
983
984 static inline void do_rti(DisasContext *dc)
985 {
986 TCGv t0, t1;
987 t0 = tcg_temp_new();
988 t1 = tcg_temp_new();
989 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
990 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
991 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
992
993 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
994 tcg_gen_or_tl(t1, t1, t0);
995 msr_write(dc, t1);
996 tcg_temp_free(t1);
997 tcg_temp_free(t0);
998 dc->tb_flags &= ~DRTI_FLAG;
999 }
1000
1001 static inline void do_rtb(DisasContext *dc)
1002 {
1003 TCGv t0, t1;
1004 t0 = tcg_temp_new();
1005 t1 = tcg_temp_new();
1006 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1007 tcg_gen_shri_tl(t0, t1, 1);
1008 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1009
1010 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1011 tcg_gen_or_tl(t1, t1, t0);
1012 msr_write(dc, t1);
1013 tcg_temp_free(t1);
1014 tcg_temp_free(t0);
1015 dc->tb_flags &= ~DRTB_FLAG;
1016 }
1017
1018 static inline void do_rte(DisasContext *dc)
1019 {
1020 TCGv t0, t1;
1021 t0 = tcg_temp_new();
1022 t1 = tcg_temp_new();
1023
1024 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1025 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1026 tcg_gen_shri_tl(t0, t1, 1);
1027 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1028
1029 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1030 tcg_gen_or_tl(t1, t1, t0);
1031 msr_write(dc, t1);
1032 tcg_temp_free(t1);
1033 tcg_temp_free(t0);
1034 dc->tb_flags &= ~DRTE_FLAG;
1035 }
1036
1037 static void dec_rts(DisasContext *dc)
1038 {
1039 unsigned int b_bit, i_bit, e_bit;
1040 int mem_index = cpu_mmu_index(dc->env);
1041
1042 i_bit = dc->ir & (1 << 21);
1043 b_bit = dc->ir & (1 << 22);
1044 e_bit = dc->ir & (1 << 23);
1045
1046 dc->delayed_branch = 2;
1047 dc->tb_flags |= D_FLAG;
1048 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1049 cpu_env, offsetof(CPUState, bimm));
1050
1051 if (i_bit) {
1052 LOG_DIS("rtid ir=%x\n", dc->ir);
1053 if ((dc->tb_flags & MSR_EE_FLAG)
1054 && mem_index == MMU_USER_IDX) {
1055 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1056 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1057 }
1058 dc->tb_flags |= DRTI_FLAG;
1059 } else if (b_bit) {
1060 LOG_DIS("rtbd ir=%x\n", dc->ir);
1061 if ((dc->tb_flags & MSR_EE_FLAG)
1062 && mem_index == MMU_USER_IDX) {
1063 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1064 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1065 }
1066 dc->tb_flags |= DRTB_FLAG;
1067 } else if (e_bit) {
1068 LOG_DIS("rted ir=%x\n", dc->ir);
1069 if ((dc->tb_flags & MSR_EE_FLAG)
1070 && mem_index == MMU_USER_IDX) {
1071 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1072 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1073 }
1074 dc->tb_flags |= DRTE_FLAG;
1075 } else
1076 LOG_DIS("rts ir=%x\n", dc->ir);
1077
1078 tcg_gen_movi_tl(env_btaken, 1);
1079 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1080 }
1081
1082 static void dec_fpu(DisasContext *dc)
1083 {
1084 if ((dc->tb_flags & MSR_EE_FLAG)
1085 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1086 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1087 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1088 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1089 return;
1090 }
1091
1092 qemu_log ("unimplemented FPU insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1093 dc->abort_at_next_insn = 1;
1094 }
1095
1096 static void dec_null(DisasContext *dc)
1097 {
1098 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1099 dc->abort_at_next_insn = 1;
1100 }
1101
1102 static struct decoder_info {
1103 struct {
1104 uint32_t bits;
1105 uint32_t mask;
1106 };
1107 void (*dec)(DisasContext *dc);
1108 } decinfo[] = {
1109 {DEC_ADD, dec_add},
1110 {DEC_SUB, dec_sub},
1111 {DEC_AND, dec_and},
1112 {DEC_XOR, dec_xor},
1113 {DEC_OR, dec_or},
1114 {DEC_BIT, dec_bit},
1115 {DEC_BARREL, dec_barrel},
1116 {DEC_LD, dec_load},
1117 {DEC_ST, dec_store},
1118 {DEC_IMM, dec_imm},
1119 {DEC_BR, dec_br},
1120 {DEC_BCC, dec_bcc},
1121 {DEC_RTS, dec_rts},
1122 {DEC_FPU, dec_fpu},
1123 {DEC_MUL, dec_mul},
1124 {DEC_DIV, dec_div},
1125 {DEC_MSR, dec_msr},
1126 {{0, 0}, dec_null}
1127 };
1128
1129 static inline void decode(DisasContext *dc)
1130 {
1131 uint32_t ir;
1132 int i;
1133
1134 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1135 tcg_gen_debug_insn_start(dc->pc);
1136
1137 dc->ir = ir = ldl_code(dc->pc);
1138 LOG_DIS("%8.8x\t", dc->ir);
1139
1140 if (dc->ir)
1141 dc->nr_nops = 0;
1142 else {
1143 if ((dc->tb_flags & MSR_EE_FLAG)
1144 && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1145 && !(dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1146 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1147 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1148 return;
1149 }
1150
1151 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1152 dc->nr_nops++;
1153 if (dc->nr_nops > 4)
1154 cpu_abort(dc->env, "fetching nop sequence\n");
1155 }
1156 /* bit 2 seems to indicate insn type. */
1157 dc->type_b = ir & (1 << 29);
1158
1159 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1160 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1161 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1162 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1163 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1164
1165 /* Large switch for all insns. */
1166 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1167 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1168 decinfo[i].dec(dc);
1169 break;
1170 }
1171 }
1172 }
1173
1174 static void check_breakpoint(CPUState *env, DisasContext *dc)
1175 {
1176 CPUBreakpoint *bp;
1177
1178 if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
1179 TAILQ_FOREACH(bp, &env->breakpoints, entry) {
1180 if (bp->pc == dc->pc) {
1181 t_gen_raise_exception(dc, EXCP_DEBUG);
1182 dc->is_jmp = DISAS_UPDATE;
1183 }
1184 }
1185 }
1186 }
1187
1188 /* generate intermediate code for basic block 'tb'. */
1189 static void
1190 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1191 int search_pc)
1192 {
1193 uint16_t *gen_opc_end;
1194 uint32_t pc_start;
1195 int j, lj;
1196 struct DisasContext ctx;
1197 struct DisasContext *dc = &ctx;
1198 uint32_t next_page_start, org_flags;
1199 target_ulong npc;
1200 int num_insns;
1201 int max_insns;
1202
1203 qemu_log_try_set_file(stderr);
1204
1205 pc_start = tb->pc;
1206 dc->env = env;
1207 dc->tb = tb;
1208 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1209
1210 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1211
1212 dc->is_jmp = DISAS_NEXT;
1213 dc->jmp = 0;
1214 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1215 dc->ppc = pc_start;
1216 dc->pc = pc_start;
1217 dc->cache_pc = -1;
1218 dc->singlestep_enabled = env->singlestep_enabled;
1219 dc->cpustate_changed = 0;
1220 dc->abort_at_next_insn = 0;
1221 dc->nr_nops = 0;
1222
1223 if (pc_start & 3)
1224 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1225
1226 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1227 #if !SIM_COMPAT
1228 qemu_log("--------------\n");
1229 log_cpu_state(env, 0);
1230 #endif
1231 }
1232
1233 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1234 lj = -1;
1235 num_insns = 0;
1236 max_insns = tb->cflags & CF_COUNT_MASK;
1237 if (max_insns == 0)
1238 max_insns = CF_COUNT_MASK;
1239
1240 gen_icount_start();
1241 do
1242 {
1243 #if SIM_COMPAT
1244 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1245 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1246 gen_helper_debug();
1247 }
1248 #endif
1249 check_breakpoint(env, dc);
1250
1251 if (search_pc) {
1252 j = gen_opc_ptr - gen_opc_buf;
1253 if (lj < j) {
1254 lj++;
1255 while (lj < j)
1256 gen_opc_instr_start[lj++] = 0;
1257 }
1258 gen_opc_pc[lj] = dc->pc;
1259 gen_opc_instr_start[lj] = 1;
1260 gen_opc_icount[lj] = num_insns;
1261 }
1262
1263 /* Pretty disas. */
1264 LOG_DIS("%8.8x:\t", dc->pc);
1265
1266 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1267 gen_io_start();
1268
1269 dc->clear_imm = 1;
1270 decode(dc);
1271 if (dc->clear_imm)
1272 dc->tb_flags &= ~IMM_FLAG;
1273 dc->ppc = dc->pc;
1274 dc->pc += 4;
1275 num_insns++;
1276
1277 if (dc->delayed_branch) {
1278 dc->delayed_branch--;
1279 if (!dc->delayed_branch) {
1280 if (dc->tb_flags & DRTI_FLAG)
1281 do_rti(dc);
1282 if (dc->tb_flags & DRTB_FLAG)
1283 do_rtb(dc);
1284 if (dc->tb_flags & DRTE_FLAG)
1285 do_rte(dc);
1286 /* Clear the delay slot flag. */
1287 dc->tb_flags &= ~D_FLAG;
1288 /* If it is a direct jump, try direct chaining. */
1289 if (dc->jmp != JMP_DIRECT) {
1290 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1291 dc->is_jmp = DISAS_JUMP;
1292 }
1293 break;
1294 }
1295 }
1296 if (env->singlestep_enabled)
1297 break;
1298 } while (!dc->is_jmp && !dc->cpustate_changed
1299 && gen_opc_ptr < gen_opc_end
1300 && !singlestep
1301 && (dc->pc < next_page_start)
1302 && num_insns < max_insns);
1303
1304 npc = dc->pc;
1305 if (dc->jmp == JMP_DIRECT) {
1306 if (dc->tb_flags & D_FLAG) {
1307 dc->is_jmp = DISAS_UPDATE;
1308 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1309 sync_jmpstate(dc);
1310 } else
1311 npc = dc->jmp_pc;
1312 }
1313
1314 if (tb->cflags & CF_LAST_IO)
1315 gen_io_end();
1316 /* Force an update if the per-tb cpu state has changed. */
1317 if (dc->is_jmp == DISAS_NEXT
1318 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1319 dc->is_jmp = DISAS_UPDATE;
1320 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1321 }
1322 t_sync_flags(dc);
1323
1324 if (unlikely(env->singlestep_enabled)) {
1325 t_gen_raise_exception(dc, EXCP_DEBUG);
1326 if (dc->is_jmp == DISAS_NEXT)
1327 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1328 } else {
1329 switch(dc->is_jmp) {
1330 case DISAS_NEXT:
1331 gen_goto_tb(dc, 1, npc);
1332 break;
1333 default:
1334 case DISAS_JUMP:
1335 case DISAS_UPDATE:
1336 /* indicate that the hash table must be used
1337 to find the next TB */
1338 tcg_gen_exit_tb(0);
1339 break;
1340 case DISAS_TB_JUMP:
1341 /* nothing more to generate */
1342 break;
1343 }
1344 }
1345 gen_icount_end(tb, num_insns);
1346 *gen_opc_ptr = INDEX_op_end;
1347 if (search_pc) {
1348 j = gen_opc_ptr - gen_opc_buf;
1349 lj++;
1350 while (lj <= j)
1351 gen_opc_instr_start[lj++] = 0;
1352 } else {
1353 tb->size = dc->pc - pc_start;
1354 tb->icount = num_insns;
1355 }
1356
1357 #ifdef DEBUG_DISAS
1358 #if !SIM_COMPAT
1359 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1360 qemu_log("\n");
1361 #if DISAS_GNU
1362 log_target_disas(pc_start, dc->pc - pc_start, 0);
1363 #endif
1364 qemu_log("\nisize=%d osize=%zd\n",
1365 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1366 }
1367 #endif
1368 #endif
1369 assert(!dc->abort_at_next_insn);
1370 }
1371
1372 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1373 {
1374 gen_intermediate_code_internal(env, tb, 0);
1375 }
1376
1377 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1378 {
1379 gen_intermediate_code_internal(env, tb, 1);
1380 }
1381
1382 void cpu_dump_state (CPUState *env, FILE *f,
1383 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
1384 int flags)
1385 {
1386 int i;
1387
1388 if (!env || !f)
1389 return;
1390
1391 cpu_fprintf(f, "IN: PC=%x %s\n",
1392 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1393 cpu_fprintf(f, "rmsr=%x resr=%x debug[%x] imm=%x iflags=%x\n",
1394 env->sregs[SR_MSR], env->sregs[SR_ESR],
1395 env->debug, env->imm, env->iflags);
1396 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s)\n",
1397 env->btaken, env->btarget,
1398 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1399 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel");
1400 for (i = 0; i < 32; i++) {
1401 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1402 if ((i + 1) % 4 == 0)
1403 cpu_fprintf(f, "\n");
1404 }
1405 cpu_fprintf(f, "\n\n");
1406 }
1407
1408 CPUState *cpu_mb_init (const char *cpu_model)
1409 {
1410 CPUState *env;
1411 static int tcg_initialized = 0;
1412 int i;
1413
1414 env = qemu_mallocz(sizeof(CPUState));
1415
1416 cpu_exec_init(env);
1417 cpu_reset(env);
1418
1419 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1420 | PVR0_USE_BARREL_MASK \
1421 | PVR0_USE_DIV_MASK \
1422 | PVR0_USE_HW_MUL_MASK \
1423 | PVR0_USE_EXC_MASK \
1424 | PVR0_USE_ICACHE_MASK \
1425 | PVR0_USE_DCACHE_MASK \
1426 | PVR0_USE_MMU \
1427 | (0xb << 8);
1428 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1429 | PVR2_D_LMB_MASK \
1430 | PVR2_I_OPB_MASK \
1431 | PVR2_I_LMB_MASK \
1432 | PVR2_USE_MSR_INSTR \
1433 | PVR2_USE_PCMP_INSTR \
1434 | PVR2_USE_BARREL_MASK \
1435 | PVR2_USE_DIV_MASK \
1436 | PVR2_USE_HW_MUL_MASK \
1437 | PVR2_USE_MUL64_MASK \
1438 | 0;
1439 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1440 env->pvr.regs[11] = PVR11_USE_MMU;
1441
1442 if (tcg_initialized)
1443 return env;
1444
1445 tcg_initialized = 1;
1446
1447 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1448
1449 env_debug = tcg_global_mem_new(TCG_AREG0,
1450 offsetof(CPUState, debug),
1451 "debug0");
1452 env_iflags = tcg_global_mem_new(TCG_AREG0,
1453 offsetof(CPUState, iflags),
1454 "iflags");
1455 env_imm = tcg_global_mem_new(TCG_AREG0,
1456 offsetof(CPUState, imm),
1457 "imm");
1458 env_btarget = tcg_global_mem_new(TCG_AREG0,
1459 offsetof(CPUState, btarget),
1460 "btarget");
1461 env_btaken = tcg_global_mem_new(TCG_AREG0,
1462 offsetof(CPUState, btaken),
1463 "btaken");
1464 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1465 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1466 offsetof(CPUState, regs[i]),
1467 regnames[i]);
1468 }
1469 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1470 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1471 offsetof(CPUState, sregs[i]),
1472 special_regnames[i]);
1473 }
1474 #define GEN_HELPER 2
1475 #include "helper.h"
1476
1477 return env;
1478 }
1479
1480 void cpu_reset (CPUState *env)
1481 {
1482 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1483 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1484 log_cpu_state(env, 0);
1485 }
1486
1487 memset(env, 0, offsetof(CPUMBState, breakpoints));
1488 tlb_flush(env, 1);
1489
1490 env->sregs[SR_MSR] = 0;
1491 #if defined(CONFIG_USER_ONLY)
1492 /* start in user mode with interrupts enabled. */
1493 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1494 #else
1495 mmu_init(&env->mmu);
1496 #endif
1497 }
1498
1499 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1500 unsigned long searched_pc, int pc_pos, void *puc)
1501 {
1502 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1503 }
Qemu copy for testing