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microblaze: Remove debug leftovers.
[qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include <stdarg.h>
21 #include <stdlib.h>
22 #include <stdio.h>
23 #include <string.h>
24 #include <inttypes.h>
25 #include <assert.h>
26
27 #include "cpu.h"
28 #include "exec-all.h"
29 #include "disas.h"
30 #include "tcg-op.h"
31 #include "helper.h"
32 #include "microblaze-decode.h"
33 #include "qemu-common.h"
34
35 #define GEN_HELPER 1
36 #include "helper.h"
37
38 #define SIM_COMPAT 0
39 #define DISAS_GNU 1
40 #define DISAS_MB 1
41 #if DISAS_MB && !SIM_COMPAT
42 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DIS(...) do { } while (0)
45 #endif
46
47 #define D(x)
48
49 #define EXTRACT_FIELD(src, start, end) \
50 (((src) >> start) & ((1 << (end - start + 1)) - 1))
51
52 static TCGv env_debug;
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_R[32];
55 static TCGv cpu_SR[18];
56 static TCGv env_imm;
57 static TCGv env_btaken;
58 static TCGv env_btarget;
59 static TCGv env_iflags;
60
61 #include "gen-icount.h"
62
63 /* This is the state at translation time. */
64 typedef struct DisasContext {
65 CPUState *env;
66 target_ulong pc;
67
68 /* Decoder. */
69 int type_b;
70 uint32_t ir;
71 uint8_t opcode;
72 uint8_t rd, ra, rb;
73 uint16_t imm;
74
75 unsigned int cpustate_changed;
76 unsigned int delayed_branch;
77 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
78 unsigned int clear_imm;
79 int is_jmp;
80
81 #define JMP_NOJMP 0
82 #define JMP_DIRECT 1
83 #define JMP_DIRECT_CC 2
84 #define JMP_INDIRECT 3
85 unsigned int jmp;
86 uint32_t jmp_pc;
87
88 int abort_at_next_insn;
89 int nr_nops;
90 struct TranslationBlock *tb;
91 int singlestep_enabled;
92 } DisasContext;
93
94 static const char *regnames[] =
95 {
96 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
97 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
98 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
99 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
100 };
101
102 static const char *special_regnames[] =
103 {
104 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
105 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
106 "sr16", "sr17", "sr18"
107 };
108
109 /* Sign extend at translation time. */
110 static inline int sign_extend(unsigned int val, unsigned int width)
111 {
112 int sval;
113
114 /* LSL. */
115 val <<= 31 - width;
116 sval = val;
117 /* ASR. */
118 sval >>= 31 - width;
119 return sval;
120 }
121
122 static inline void t_sync_flags(DisasContext *dc)
123 {
124 /* Synch the tb dependant flags between translator and runtime. */
125 if (dc->tb_flags != dc->synced_flags) {
126 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
127 dc->synced_flags = dc->tb_flags;
128 }
129 }
130
131 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
132 {
133 TCGv_i32 tmp = tcg_const_i32(index);
134
135 t_sync_flags(dc);
136 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
137 gen_helper_raise_exception(tmp);
138 tcg_temp_free_i32(tmp);
139 dc->is_jmp = DISAS_UPDATE;
140 }
141
142 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
143 {
144 TranslationBlock *tb;
145 tb = dc->tb;
146 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
147 tcg_gen_goto_tb(n);
148 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
149 tcg_gen_exit_tb((long)tb + n);
150 } else {
151 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
152 tcg_gen_exit_tb(0);
153 }
154 }
155
156 static void read_carry(DisasContext *dc, TCGv d)
157 {
158 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
159 }
160
161 static void write_carry(DisasContext *dc, TCGv v)
162 {
163 TCGv t0 = tcg_temp_new();
164 tcg_gen_shli_tl(t0, v, 31);
165 tcg_gen_sari_tl(t0, t0, 31);
166 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
167 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
168 ~(MSR_C | MSR_CC));
169 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
170 tcg_temp_free(t0);
171 }
172
173 /* True if ALU operand b is a small immediate that may deserve
174 faster treatment. */
175 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
176 {
177 /* Immediate insn without the imm prefix ? */
178 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
179 }
180
181 static inline TCGv *dec_alu_op_b(DisasContext *dc)
182 {
183 if (dc->type_b) {
184 if (dc->tb_flags & IMM_FLAG)
185 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
186 else
187 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
188 return &env_imm;
189 } else
190 return &cpu_R[dc->rb];
191 }
192
193 static void dec_add(DisasContext *dc)
194 {
195 unsigned int k, c;
196
197 k = dc->opcode & 4;
198 c = dc->opcode & 2;
199
200 LOG_DIS("add%s%s%s r%d r%d r%d\n",
201 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
202 dc->rd, dc->ra, dc->rb);
203
204 if (k && !c && dc->rd)
205 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
206 else if (dc->rd)
207 gen_helper_addkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
208 tcg_const_tl(k), tcg_const_tl(c));
209 else {
210 TCGv d = tcg_temp_new();
211 gen_helper_addkc(d, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
212 tcg_const_tl(k), tcg_const_tl(c));
213 tcg_temp_free(d);
214 }
215 }
216
217 static void dec_sub(DisasContext *dc)
218 {
219 unsigned int u, cmp, k, c;
220
221 u = dc->imm & 2;
222 k = dc->opcode & 4;
223 c = dc->opcode & 2;
224 cmp = (dc->imm & 1) && (!dc->type_b) && k;
225
226 if (cmp) {
227 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
228 if (dc->rd) {
229 if (u)
230 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
231 else
232 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
233 }
234 } else {
235 LOG_DIS("sub%s%s r%d, r%d r%d\n",
236 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
237
238 if (!k || c) {
239 TCGv t;
240 t = tcg_temp_new();
241 if (dc->rd)
242 gen_helper_subkc(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)),
243 tcg_const_tl(k), tcg_const_tl(c));
244 else
245 gen_helper_subkc(t, cpu_R[dc->ra], *(dec_alu_op_b(dc)),
246 tcg_const_tl(k), tcg_const_tl(c));
247 tcg_temp_free(t);
248 }
249 else if (dc->rd)
250 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
251 }
252 }
253
254 static void dec_pattern(DisasContext *dc)
255 {
256 unsigned int mode;
257 int l1;
258
259 if ((dc->tb_flags & MSR_EE_FLAG)
260 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
261 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
262 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
263 t_gen_raise_exception(dc, EXCP_HW_EXCP);
264 }
265
266 mode = dc->opcode & 3;
267 switch (mode) {
268 case 0:
269 /* pcmpbf. */
270 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
271 if (dc->rd)
272 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
273 break;
274 case 2:
275 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
276 if (dc->rd) {
277 TCGv t0 = tcg_temp_local_new();
278 l1 = gen_new_label();
279 tcg_gen_movi_tl(t0, 1);
280 tcg_gen_brcond_tl(TCG_COND_EQ,
281 cpu_R[dc->ra], cpu_R[dc->rb], l1);
282 tcg_gen_movi_tl(t0, 0);
283 gen_set_label(l1);
284 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
285 tcg_temp_free(t0);
286 }
287 break;
288 case 3:
289 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
290 l1 = gen_new_label();
291 if (dc->rd) {
292 TCGv t0 = tcg_temp_local_new();
293 tcg_gen_movi_tl(t0, 1);
294 tcg_gen_brcond_tl(TCG_COND_NE,
295 cpu_R[dc->ra], cpu_R[dc->rb], l1);
296 tcg_gen_movi_tl(t0, 0);
297 gen_set_label(l1);
298 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
299 tcg_temp_free(t0);
300 }
301 break;
302 default:
303 cpu_abort(dc->env,
304 "unsupported pattern insn opcode=%x\n", dc->opcode);
305 break;
306 }
307 }
308
309 static void dec_and(DisasContext *dc)
310 {
311 unsigned int not;
312
313 if (!dc->type_b && (dc->imm & (1 << 10))) {
314 dec_pattern(dc);
315 return;
316 }
317
318 not = dc->opcode & (1 << 1);
319 LOG_DIS("and%s\n", not ? "n" : "");
320
321 if (!dc->rd)
322 return;
323
324 if (not) {
325 TCGv t = tcg_temp_new();
326 tcg_gen_not_tl(t, *(dec_alu_op_b(dc)));
327 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], t);
328 tcg_temp_free(t);
329 } else
330 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
331 }
332
333 static void dec_or(DisasContext *dc)
334 {
335 if (!dc->type_b && (dc->imm & (1 << 10))) {
336 dec_pattern(dc);
337 return;
338 }
339
340 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
341 if (dc->rd)
342 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
343 }
344
345 static void dec_xor(DisasContext *dc)
346 {
347 if (!dc->type_b && (dc->imm & (1 << 10))) {
348 dec_pattern(dc);
349 return;
350 }
351
352 LOG_DIS("xor r%d\n", dc->rd);
353 if (dc->rd)
354 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
355 }
356
357 static inline void msr_read(DisasContext *dc, TCGv d)
358 {
359 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
360 }
361
362 static inline void msr_write(DisasContext *dc, TCGv v)
363 {
364 dc->cpustate_changed = 1;
365 tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
366 /* PVR, we have a processor version register. */
367 tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
368 }
369
370 static void dec_msr(DisasContext *dc)
371 {
372 TCGv t0, t1;
373 unsigned int sr, to, rn;
374 int mem_index = cpu_mmu_index(dc->env);
375
376 sr = dc->imm & ((1 << 14) - 1);
377 to = dc->imm & (1 << 14);
378 dc->type_b = 1;
379 if (to)
380 dc->cpustate_changed = 1;
381
382 /* msrclr and msrset. */
383 if (!(dc->imm & (1 << 15))) {
384 unsigned int clr = dc->ir & (1 << 16);
385
386 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
387 dc->rd, dc->imm);
388
389 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
390 /* nop??? */
391 return;
392 }
393
394 if ((dc->tb_flags & MSR_EE_FLAG)
395 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
396 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
397 t_gen_raise_exception(dc, EXCP_HW_EXCP);
398 return;
399 }
400
401 if (dc->rd)
402 msr_read(dc, cpu_R[dc->rd]);
403
404 t0 = tcg_temp_new();
405 t1 = tcg_temp_new();
406 msr_read(dc, t0);
407 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
408
409 if (clr) {
410 tcg_gen_not_tl(t1, t1);
411 tcg_gen_and_tl(t0, t0, t1);
412 } else
413 tcg_gen_or_tl(t0, t0, t1);
414 msr_write(dc, t0);
415 tcg_temp_free(t0);
416 tcg_temp_free(t1);
417 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
418 dc->is_jmp = DISAS_UPDATE;
419 return;
420 }
421
422 if (to) {
423 if ((dc->tb_flags & MSR_EE_FLAG)
424 && mem_index == MMU_USER_IDX) {
425 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
426 t_gen_raise_exception(dc, EXCP_HW_EXCP);
427 return;
428 }
429 }
430
431 #if !defined(CONFIG_USER_ONLY)
432 /* Catch read/writes to the mmu block. */
433 if ((sr & ~0xff) == 0x1000) {
434 sr &= 7;
435 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
436 if (to)
437 gen_helper_mmu_write(tcg_const_tl(sr), cpu_R[dc->ra]);
438 else
439 gen_helper_mmu_read(cpu_R[dc->rd], tcg_const_tl(sr));
440 return;
441 }
442 #endif
443
444 if (to) {
445 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
446 switch (sr) {
447 case 0:
448 break;
449 case 1:
450 msr_write(dc, cpu_R[dc->ra]);
451 break;
452 case 0x3:
453 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
454 break;
455 case 0x5:
456 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
457 break;
458 case 0x7:
459 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
460 break;
461 default:
462 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
463 break;
464 }
465 } else {
466 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
467
468 switch (sr) {
469 case 0:
470 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
471 break;
472 case 1:
473 msr_read(dc, cpu_R[dc->rd]);
474 break;
475 case 0x3:
476 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
477 break;
478 case 0x5:
479 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
480 break;
481 case 0x7:
482 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
483 break;
484 case 0xb:
485 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
486 break;
487 case 0x2000:
488 case 0x2001:
489 case 0x2002:
490 case 0x2003:
491 case 0x2004:
492 case 0x2005:
493 case 0x2006:
494 case 0x2007:
495 case 0x2008:
496 case 0x2009:
497 case 0x200a:
498 case 0x200b:
499 case 0x200c:
500 rn = sr & 0xf;
501 tcg_gen_ld_tl(cpu_R[dc->rd],
502 cpu_env, offsetof(CPUState, pvr.regs[rn]));
503 break;
504 default:
505 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
506 break;
507 }
508 }
509
510 if (dc->rd == 0) {
511 tcg_gen_movi_tl(cpu_R[0], 0);
512 }
513 }
514
515 /* 64-bit signed mul, lower result in d and upper in d2. */
516 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
517 {
518 TCGv_i64 t0, t1;
519
520 t0 = tcg_temp_new_i64();
521 t1 = tcg_temp_new_i64();
522
523 tcg_gen_ext_i32_i64(t0, a);
524 tcg_gen_ext_i32_i64(t1, b);
525 tcg_gen_mul_i64(t0, t0, t1);
526
527 tcg_gen_trunc_i64_i32(d, t0);
528 tcg_gen_shri_i64(t0, t0, 32);
529 tcg_gen_trunc_i64_i32(d2, t0);
530
531 tcg_temp_free_i64(t0);
532 tcg_temp_free_i64(t1);
533 }
534
535 /* 64-bit unsigned muls, lower result in d and upper in d2. */
536 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
537 {
538 TCGv_i64 t0, t1;
539
540 t0 = tcg_temp_new_i64();
541 t1 = tcg_temp_new_i64();
542
543 tcg_gen_extu_i32_i64(t0, a);
544 tcg_gen_extu_i32_i64(t1, b);
545 tcg_gen_mul_i64(t0, t0, t1);
546
547 tcg_gen_trunc_i64_i32(d, t0);
548 tcg_gen_shri_i64(t0, t0, 32);
549 tcg_gen_trunc_i64_i32(d2, t0);
550
551 tcg_temp_free_i64(t0);
552 tcg_temp_free_i64(t1);
553 }
554
555 /* Multiplier unit. */
556 static void dec_mul(DisasContext *dc)
557 {
558 TCGv d[2];
559 unsigned int subcode;
560
561 if ((dc->tb_flags & MSR_EE_FLAG)
562 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
563 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
564 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
565 t_gen_raise_exception(dc, EXCP_HW_EXCP);
566 return;
567 }
568
569 subcode = dc->imm & 3;
570 d[0] = tcg_temp_new();
571 d[1] = tcg_temp_new();
572
573 if (dc->type_b) {
574 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
575 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
576 goto done;
577 }
578
579 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
580 if (subcode >= 1 && subcode <= 3
581 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
582 /* nop??? */
583 }
584
585 switch (subcode) {
586 case 0:
587 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
588 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
589 break;
590 case 1:
591 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
592 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
593 break;
594 case 2:
595 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
596 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
597 break;
598 case 3:
599 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
600 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
601 break;
602 default:
603 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
604 break;
605 }
606 done:
607 tcg_temp_free(d[0]);
608 tcg_temp_free(d[1]);
609 }
610
611 /* Div unit. */
612 static void dec_div(DisasContext *dc)
613 {
614 unsigned int u;
615
616 u = dc->imm & 2;
617 LOG_DIS("div\n");
618
619 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
620 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
621 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
622 t_gen_raise_exception(dc, EXCP_HW_EXCP);
623 }
624
625 if (u)
626 gen_helper_divu(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
627 else
628 gen_helper_divs(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
629 if (!dc->rd)
630 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
631 }
632
633 static void dec_barrel(DisasContext *dc)
634 {
635 TCGv t0;
636 unsigned int s, t;
637
638 if ((dc->tb_flags & MSR_EE_FLAG)
639 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
640 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
641 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
642 t_gen_raise_exception(dc, EXCP_HW_EXCP);
643 return;
644 }
645
646 s = dc->imm & (1 << 10);
647 t = dc->imm & (1 << 9);
648
649 LOG_DIS("bs%s%s r%d r%d r%d\n",
650 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
651
652 t0 = tcg_temp_new();
653
654 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
655 tcg_gen_andi_tl(t0, t0, 31);
656
657 if (s)
658 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
659 else {
660 if (t)
661 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
662 else
663 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
664 }
665 }
666
667 static void dec_bit(DisasContext *dc)
668 {
669 TCGv t0, t1;
670 unsigned int op;
671 int mem_index = cpu_mmu_index(dc->env);
672
673 op = dc->ir & ((1 << 8) - 1);
674 switch (op) {
675 case 0x21:
676 /* src. */
677 t0 = tcg_temp_new();
678
679 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
680 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
681 if (dc->rd) {
682 t1 = tcg_temp_new();
683 read_carry(dc, t1);
684 tcg_gen_shli_tl(t1, t1, 31);
685
686 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
687 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1);
688 tcg_temp_free(t1);
689 }
690
691 /* Update carry. */
692 write_carry(dc, t0);
693 tcg_temp_free(t0);
694 break;
695
696 case 0x1:
697 case 0x41:
698 /* srl. */
699 t0 = tcg_temp_new();
700 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
701
702 /* Update carry. */
703 tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1);
704 write_carry(dc, t0);
705 tcg_temp_free(t0);
706 if (dc->rd) {
707 if (op == 0x41)
708 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
709 else
710 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
711 }
712 break;
713 case 0x60:
714 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
715 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
716 break;
717 case 0x61:
718 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
719 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
720 break;
721 case 0x64:
722 case 0x66:
723 case 0x74:
724 case 0x76:
725 /* wdc. */
726 LOG_DIS("wdc r%d\n", dc->ra);
727 if ((dc->tb_flags & MSR_EE_FLAG)
728 && mem_index == MMU_USER_IDX) {
729 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
730 t_gen_raise_exception(dc, EXCP_HW_EXCP);
731 return;
732 }
733 break;
734 case 0x68:
735 /* wic. */
736 LOG_DIS("wic r%d\n", dc->ra);
737 if ((dc->tb_flags & MSR_EE_FLAG)
738 && mem_index == MMU_USER_IDX) {
739 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
740 t_gen_raise_exception(dc, EXCP_HW_EXCP);
741 return;
742 }
743 break;
744 default:
745 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
746 dc->pc, op, dc->rd, dc->ra, dc->rb);
747 break;
748 }
749 }
750
751 static inline void sync_jmpstate(DisasContext *dc)
752 {
753 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
754 if (dc->jmp == JMP_DIRECT) {
755 tcg_gen_movi_tl(env_btaken, 1);
756 }
757 dc->jmp = JMP_INDIRECT;
758 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
759 }
760 }
761
762 static void dec_imm(DisasContext *dc)
763 {
764 LOG_DIS("imm %x\n", dc->imm << 16);
765 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
766 dc->tb_flags |= IMM_FLAG;
767 dc->clear_imm = 0;
768 }
769
770 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
771 unsigned int size)
772 {
773 int mem_index = cpu_mmu_index(dc->env);
774
775 if (size == 1) {
776 tcg_gen_qemu_ld8u(dst, addr, mem_index);
777 } else if (size == 2) {
778 tcg_gen_qemu_ld16u(dst, addr, mem_index);
779 } else if (size == 4) {
780 tcg_gen_qemu_ld32u(dst, addr, mem_index);
781 } else
782 cpu_abort(dc->env, "Incorrect load size %d\n", size);
783 }
784
785 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
786 {
787 unsigned int extimm = dc->tb_flags & IMM_FLAG;
788
789 /* Treat the common cases first. */
790 if (!dc->type_b) {
791 /* If any of the regs is r0, return a ptr to the other. */
792 if (dc->ra == 0) {
793 return &cpu_R[dc->rb];
794 } else if (dc->rb == 0) {
795 return &cpu_R[dc->ra];
796 }
797
798 *t = tcg_temp_new();
799 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
800 return t;
801 }
802 /* Immediate. */
803 if (!extimm) {
804 if (dc->imm == 0) {
805 return &cpu_R[dc->ra];
806 }
807 *t = tcg_temp_new();
808 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
809 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
810 } else {
811 *t = tcg_temp_new();
812 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
813 }
814
815 return t;
816 }
817
818 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
819 {
820 if (size == 4) {
821 tcg_gen_bswap32_tl(dst, src);
822 } else if (size == 2) {
823 TCGv t = tcg_temp_new();
824
825 /* bswap16 assumes the high bits are zero. */
826 tcg_gen_andi_tl(t, src, 0xffff);
827 tcg_gen_bswap16_tl(dst, t);
828 tcg_temp_free(t);
829 } else {
830 /* Ignore.
831 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
832 */
833 }
834 }
835
836 static void dec_load(DisasContext *dc)
837 {
838 TCGv t, *addr;
839 unsigned int size, rev = 0;
840
841 size = 1 << (dc->opcode & 3);
842
843 if (!dc->type_b) {
844 rev = (dc->ir >> 9) & 1;
845 }
846
847 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
848 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
849 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
850 t_gen_raise_exception(dc, EXCP_HW_EXCP);
851 return;
852 }
853
854 LOG_DIS("l%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
855
856 t_sync_flags(dc);
857 addr = compute_ldst_addr(dc, &t);
858
859 /*
860 * When doing reverse accesses we need to do two things.
861 *
862 * 1. Reverse the address wrt endianess.
863 * 2. Byteswap the data lanes on the way back into the CPU core.
864 */
865 if (rev && size != 4) {
866 /* Endian reverse the address. t is addr. */
867 switch (size) {
868 case 1:
869 {
870 /* 00 -> 11
871 01 -> 10
872 10 -> 10
873 11 -> 00 */
874 TCGv low = tcg_temp_new();
875
876 /* Force addr into the temp. */
877 if (addr != &t) {
878 t = tcg_temp_new();
879 tcg_gen_mov_tl(t, *addr);
880 addr = &t;
881 }
882
883 tcg_gen_andi_tl(low, t, 3);
884 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
885 tcg_gen_andi_tl(t, t, ~3);
886 tcg_gen_or_tl(t, t, low);
887 tcg_gen_mov_tl(env_imm, t);
888 tcg_temp_free(low);
889 break;
890 }
891
892 case 2:
893 /* 00 -> 10
894 10 -> 00. */
895 /* Force addr into the temp. */
896 if (addr != &t) {
897 t = tcg_temp_new();
898 tcg_gen_xori_tl(t, *addr, 2);
899 addr = &t;
900 } else {
901 tcg_gen_xori_tl(t, t, 2);
902 }
903 break;
904 default:
905 cpu_abort(dc->env, "Invalid reverse size\n");
906 break;
907 }
908 }
909
910 /* If we get a fault on a dslot, the jmpstate better be in sync. */
911 sync_jmpstate(dc);
912
913 /* Verify alignment if needed. */
914 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
915 TCGv v = tcg_temp_new();
916
917 /*
918 * Microblaze gives MMU faults priority over faults due to
919 * unaligned addresses. That's why we speculatively do the load
920 * into v. If the load succeeds, we verify alignment of the
921 * address and if that succeeds we write into the destination reg.
922 */
923 gen_load(dc, v, *addr, size);
924
925 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
926 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
927 tcg_const_tl(0), tcg_const_tl(size - 1));
928 if (dc->rd) {
929 if (rev) {
930 dec_byteswap(dc, cpu_R[dc->rd], v, size);
931 } else {
932 tcg_gen_mov_tl(cpu_R[dc->rd], v);
933 }
934 }
935 tcg_temp_free(v);
936 } else {
937 if (dc->rd) {
938 gen_load(dc, cpu_R[dc->rd], *addr, size);
939 if (rev) {
940 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
941 }
942 } else {
943 /* We are loading into r0, no need to reverse. */
944 gen_load(dc, env_imm, *addr, size);
945 }
946 }
947
948 if (addr == &t)
949 tcg_temp_free(t);
950 }
951
952 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
953 unsigned int size)
954 {
955 int mem_index = cpu_mmu_index(dc->env);
956
957 if (size == 1)
958 tcg_gen_qemu_st8(val, addr, mem_index);
959 else if (size == 2) {
960 tcg_gen_qemu_st16(val, addr, mem_index);
961 } else if (size == 4) {
962 tcg_gen_qemu_st32(val, addr, mem_index);
963 } else
964 cpu_abort(dc->env, "Incorrect store size %d\n", size);
965 }
966
967 static void dec_store(DisasContext *dc)
968 {
969 TCGv t, *addr;
970 unsigned int size, rev = 0;
971
972 size = 1 << (dc->opcode & 3);
973 if (!dc->type_b) {
974 rev = (dc->ir >> 9) & 1;
975 }
976
977 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
978 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
979 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
980 t_gen_raise_exception(dc, EXCP_HW_EXCP);
981 return;
982 }
983
984 LOG_DIS("s%d%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "");
985 t_sync_flags(dc);
986 /* If we get a fault on a dslot, the jmpstate better be in sync. */
987 sync_jmpstate(dc);
988 addr = compute_ldst_addr(dc, &t);
989
990 if (rev && size != 4) {
991 /* Endian reverse the address. t is addr. */
992 switch (size) {
993 case 1:
994 {
995 /* 00 -> 11
996 01 -> 10
997 10 -> 10
998 11 -> 00 */
999 TCGv low = tcg_temp_new();
1000
1001 /* Force addr into the temp. */
1002 if (addr != &t) {
1003 t = tcg_temp_new();
1004 tcg_gen_mov_tl(t, *addr);
1005 addr = &t;
1006 }
1007
1008 tcg_gen_andi_tl(low, t, 3);
1009 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1010 tcg_gen_andi_tl(t, t, ~3);
1011 tcg_gen_or_tl(t, t, low);
1012 tcg_gen_mov_tl(env_imm, t);
1013 tcg_temp_free(low);
1014 break;
1015 }
1016
1017 case 2:
1018 /* 00 -> 10
1019 10 -> 00. */
1020 /* Force addr into the temp. */
1021 if (addr != &t) {
1022 t = tcg_temp_new();
1023 tcg_gen_xori_tl(t, *addr, 2);
1024 addr = &t;
1025 } else {
1026 tcg_gen_xori_tl(t, t, 2);
1027 }
1028 break;
1029 default:
1030 cpu_abort(dc->env, "Invalid reverse size\n");
1031 break;
1032 }
1033
1034 if (size != 1) {
1035 TCGv bs_data = tcg_temp_new();
1036 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1037 gen_store(dc, *addr, bs_data, size);
1038 tcg_temp_free(bs_data);
1039 } else {
1040 gen_store(dc, *addr, cpu_R[dc->rd], size);
1041 }
1042 } else {
1043 if (rev) {
1044 TCGv bs_data = tcg_temp_new();
1045 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1046 gen_store(dc, *addr, bs_data, size);
1047 tcg_temp_free(bs_data);
1048 } else {
1049 gen_store(dc, *addr, cpu_R[dc->rd], size);
1050 }
1051 }
1052
1053 /* Verify alignment if needed. */
1054 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1055 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1056 /* FIXME: if the alignment is wrong, we should restore the value
1057 * in memory. One possible way to acheive this is to probe
1058 * the MMU prior to the memaccess, thay way we could put
1059 * the alignment checks in between the probe and the mem
1060 * access.
1061 */
1062 gen_helper_memalign(*addr, tcg_const_tl(dc->rd),
1063 tcg_const_tl(1), tcg_const_tl(size - 1));
1064 }
1065
1066 if (addr == &t)
1067 tcg_temp_free(t);
1068 }
1069
1070 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1071 TCGv d, TCGv a, TCGv b)
1072 {
1073 switch (cc) {
1074 case CC_EQ:
1075 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1076 break;
1077 case CC_NE:
1078 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1079 break;
1080 case CC_LT:
1081 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1082 break;
1083 case CC_LE:
1084 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1085 break;
1086 case CC_GE:
1087 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1088 break;
1089 case CC_GT:
1090 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1091 break;
1092 default:
1093 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1094 break;
1095 }
1096 }
1097
1098 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1099 {
1100 int l1;
1101
1102 l1 = gen_new_label();
1103 /* Conditional jmp. */
1104 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1105 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1106 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1107 gen_set_label(l1);
1108 }
1109
1110 static void dec_bcc(DisasContext *dc)
1111 {
1112 unsigned int cc;
1113 unsigned int dslot;
1114
1115 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1116 dslot = dc->ir & (1 << 25);
1117 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1118
1119 dc->delayed_branch = 1;
1120 if (dslot) {
1121 dc->delayed_branch = 2;
1122 dc->tb_flags |= D_FLAG;
1123 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1124 cpu_env, offsetof(CPUState, bimm));
1125 }
1126
1127 if (dec_alu_op_b_is_small_imm(dc)) {
1128 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1129
1130 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1131 dc->jmp = JMP_DIRECT_CC;
1132 dc->jmp_pc = dc->pc + offset;
1133 } else {
1134 dc->jmp = JMP_INDIRECT;
1135 tcg_gen_movi_tl(env_btarget, dc->pc);
1136 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1137 }
1138 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1139 }
1140
1141 static void dec_br(DisasContext *dc)
1142 {
1143 unsigned int dslot, link, abs;
1144 int mem_index = cpu_mmu_index(dc->env);
1145
1146 dslot = dc->ir & (1 << 20);
1147 abs = dc->ir & (1 << 19);
1148 link = dc->ir & (1 << 18);
1149 LOG_DIS("br%s%s%s%s imm=%x\n",
1150 abs ? "a" : "", link ? "l" : "",
1151 dc->type_b ? "i" : "", dslot ? "d" : "",
1152 dc->imm);
1153
1154 dc->delayed_branch = 1;
1155 if (dslot) {
1156 dc->delayed_branch = 2;
1157 dc->tb_flags |= D_FLAG;
1158 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1159 cpu_env, offsetof(CPUState, bimm));
1160 }
1161 if (link && dc->rd)
1162 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1163
1164 dc->jmp = JMP_INDIRECT;
1165 if (abs) {
1166 tcg_gen_movi_tl(env_btaken, 1);
1167 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1168 if (link && !dslot) {
1169 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1170 t_gen_raise_exception(dc, EXCP_BREAK);
1171 if (dc->imm == 0) {
1172 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1173 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1174 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1175 return;
1176 }
1177
1178 t_gen_raise_exception(dc, EXCP_DEBUG);
1179 }
1180 }
1181 } else {
1182 if (dec_alu_op_b_is_small_imm(dc)) {
1183 dc->jmp = JMP_DIRECT;
1184 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1185 } else {
1186 tcg_gen_movi_tl(env_btaken, 1);
1187 tcg_gen_movi_tl(env_btarget, dc->pc);
1188 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1189 }
1190 }
1191 }
1192
1193 static inline void do_rti(DisasContext *dc)
1194 {
1195 TCGv t0, t1;
1196 t0 = tcg_temp_new();
1197 t1 = tcg_temp_new();
1198 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1199 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1200 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1201
1202 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1203 tcg_gen_or_tl(t1, t1, t0);
1204 msr_write(dc, t1);
1205 tcg_temp_free(t1);
1206 tcg_temp_free(t0);
1207 dc->tb_flags &= ~DRTI_FLAG;
1208 }
1209
1210 static inline void do_rtb(DisasContext *dc)
1211 {
1212 TCGv t0, t1;
1213 t0 = tcg_temp_new();
1214 t1 = tcg_temp_new();
1215 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1216 tcg_gen_shri_tl(t0, t1, 1);
1217 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1218
1219 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1220 tcg_gen_or_tl(t1, t1, t0);
1221 msr_write(dc, t1);
1222 tcg_temp_free(t1);
1223 tcg_temp_free(t0);
1224 dc->tb_flags &= ~DRTB_FLAG;
1225 }
1226
1227 static inline void do_rte(DisasContext *dc)
1228 {
1229 TCGv t0, t1;
1230 t0 = tcg_temp_new();
1231 t1 = tcg_temp_new();
1232
1233 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1234 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1235 tcg_gen_shri_tl(t0, t1, 1);
1236 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1237
1238 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1239 tcg_gen_or_tl(t1, t1, t0);
1240 msr_write(dc, t1);
1241 tcg_temp_free(t1);
1242 tcg_temp_free(t0);
1243 dc->tb_flags &= ~DRTE_FLAG;
1244 }
1245
1246 static void dec_rts(DisasContext *dc)
1247 {
1248 unsigned int b_bit, i_bit, e_bit;
1249 int mem_index = cpu_mmu_index(dc->env);
1250
1251 i_bit = dc->ir & (1 << 21);
1252 b_bit = dc->ir & (1 << 22);
1253 e_bit = dc->ir & (1 << 23);
1254
1255 dc->delayed_branch = 2;
1256 dc->tb_flags |= D_FLAG;
1257 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1258 cpu_env, offsetof(CPUState, bimm));
1259
1260 if (i_bit) {
1261 LOG_DIS("rtid ir=%x\n", dc->ir);
1262 if ((dc->tb_flags & MSR_EE_FLAG)
1263 && mem_index == MMU_USER_IDX) {
1264 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1265 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1266 }
1267 dc->tb_flags |= DRTI_FLAG;
1268 } else if (b_bit) {
1269 LOG_DIS("rtbd ir=%x\n", dc->ir);
1270 if ((dc->tb_flags & MSR_EE_FLAG)
1271 && mem_index == MMU_USER_IDX) {
1272 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1273 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1274 }
1275 dc->tb_flags |= DRTB_FLAG;
1276 } else if (e_bit) {
1277 LOG_DIS("rted ir=%x\n", dc->ir);
1278 if ((dc->tb_flags & MSR_EE_FLAG)
1279 && mem_index == MMU_USER_IDX) {
1280 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1281 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1282 }
1283 dc->tb_flags |= DRTE_FLAG;
1284 } else
1285 LOG_DIS("rts ir=%x\n", dc->ir);
1286
1287 dc->jmp = JMP_INDIRECT;
1288 tcg_gen_movi_tl(env_btaken, 1);
1289 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1290 }
1291
1292 static int dec_check_fpuv2(DisasContext *dc)
1293 {
1294 int r;
1295
1296 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1297
1298 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1299 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1300 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1301 }
1302 return r;
1303 }
1304
1305 static void dec_fpu(DisasContext *dc)
1306 {
1307 unsigned int fpu_insn;
1308
1309 if ((dc->tb_flags & MSR_EE_FLAG)
1310 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1311 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1312 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1313 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1314 return;
1315 }
1316
1317 fpu_insn = (dc->ir >> 7) & 7;
1318
1319 switch (fpu_insn) {
1320 case 0:
1321 gen_helper_fadd(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1322 break;
1323
1324 case 1:
1325 gen_helper_frsub(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1326 break;
1327
1328 case 2:
1329 gen_helper_fmul(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1330 break;
1331
1332 case 3:
1333 gen_helper_fdiv(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
1334 break;
1335
1336 case 4:
1337 switch ((dc->ir >> 4) & 7) {
1338 case 0:
1339 gen_helper_fcmp_un(cpu_R[dc->rd],
1340 cpu_R[dc->ra], cpu_R[dc->rb]);
1341 break;
1342 case 1:
1343 gen_helper_fcmp_lt(cpu_R[dc->rd],
1344 cpu_R[dc->ra], cpu_R[dc->rb]);
1345 break;
1346 case 2:
1347 gen_helper_fcmp_eq(cpu_R[dc->rd],
1348 cpu_R[dc->ra], cpu_R[dc->rb]);
1349 break;
1350 case 3:
1351 gen_helper_fcmp_le(cpu_R[dc->rd],
1352 cpu_R[dc->ra], cpu_R[dc->rb]);
1353 break;
1354 case 4:
1355 gen_helper_fcmp_gt(cpu_R[dc->rd],
1356 cpu_R[dc->ra], cpu_R[dc->rb]);
1357 break;
1358 case 5:
1359 gen_helper_fcmp_ne(cpu_R[dc->rd],
1360 cpu_R[dc->ra], cpu_R[dc->rb]);
1361 break;
1362 case 6:
1363 gen_helper_fcmp_ge(cpu_R[dc->rd],
1364 cpu_R[dc->ra], cpu_R[dc->rb]);
1365 break;
1366 default:
1367 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1368 fpu_insn, dc->pc, dc->opcode);
1369 dc->abort_at_next_insn = 1;
1370 break;
1371 }
1372 break;
1373
1374 case 5:
1375 if (!dec_check_fpuv2(dc)) {
1376 return;
1377 }
1378 gen_helper_flt(cpu_R[dc->rd], cpu_R[dc->ra]);
1379 break;
1380
1381 case 6:
1382 if (!dec_check_fpuv2(dc)) {
1383 return;
1384 }
1385 gen_helper_fint(cpu_R[dc->rd], cpu_R[dc->ra]);
1386 break;
1387
1388 case 7:
1389 if (!dec_check_fpuv2(dc)) {
1390 return;
1391 }
1392 gen_helper_fsqrt(cpu_R[dc->rd], cpu_R[dc->ra]);
1393 break;
1394
1395 default:
1396 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1397 fpu_insn, dc->pc, dc->opcode);
1398 dc->abort_at_next_insn = 1;
1399 break;
1400 }
1401 }
1402
1403 static void dec_null(DisasContext *dc)
1404 {
1405 if ((dc->tb_flags & MSR_EE_FLAG)
1406 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1407 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1408 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1409 return;
1410 }
1411 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1412 dc->abort_at_next_insn = 1;
1413 }
1414
1415 static struct decoder_info {
1416 struct {
1417 uint32_t bits;
1418 uint32_t mask;
1419 };
1420 void (*dec)(DisasContext *dc);
1421 } decinfo[] = {
1422 {DEC_ADD, dec_add},
1423 {DEC_SUB, dec_sub},
1424 {DEC_AND, dec_and},
1425 {DEC_XOR, dec_xor},
1426 {DEC_OR, dec_or},
1427 {DEC_BIT, dec_bit},
1428 {DEC_BARREL, dec_barrel},
1429 {DEC_LD, dec_load},
1430 {DEC_ST, dec_store},
1431 {DEC_IMM, dec_imm},
1432 {DEC_BR, dec_br},
1433 {DEC_BCC, dec_bcc},
1434 {DEC_RTS, dec_rts},
1435 {DEC_FPU, dec_fpu},
1436 {DEC_MUL, dec_mul},
1437 {DEC_DIV, dec_div},
1438 {DEC_MSR, dec_msr},
1439 {{0, 0}, dec_null}
1440 };
1441
1442 static inline void decode(DisasContext *dc)
1443 {
1444 uint32_t ir;
1445 int i;
1446
1447 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1448 tcg_gen_debug_insn_start(dc->pc);
1449
1450 dc->ir = ir = ldl_code(dc->pc);
1451 LOG_DIS("%8.8x\t", dc->ir);
1452
1453 if (dc->ir)
1454 dc->nr_nops = 0;
1455 else {
1456 if ((dc->tb_flags & MSR_EE_FLAG)
1457 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1458 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1459 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1460 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1461 return;
1462 }
1463
1464 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1465 dc->nr_nops++;
1466 if (dc->nr_nops > 4)
1467 cpu_abort(dc->env, "fetching nop sequence\n");
1468 }
1469 /* bit 2 seems to indicate insn type. */
1470 dc->type_b = ir & (1 << 29);
1471
1472 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1473 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1474 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1475 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1476 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1477
1478 /* Large switch for all insns. */
1479 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1480 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1481 decinfo[i].dec(dc);
1482 break;
1483 }
1484 }
1485 }
1486
1487 static void check_breakpoint(CPUState *env, DisasContext *dc)
1488 {
1489 CPUBreakpoint *bp;
1490
1491 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1492 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1493 if (bp->pc == dc->pc) {
1494 t_gen_raise_exception(dc, EXCP_DEBUG);
1495 dc->is_jmp = DISAS_UPDATE;
1496 }
1497 }
1498 }
1499 }
1500
1501 /* generate intermediate code for basic block 'tb'. */
1502 static void
1503 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
1504 int search_pc)
1505 {
1506 uint16_t *gen_opc_end;
1507 uint32_t pc_start;
1508 int j, lj;
1509 struct DisasContext ctx;
1510 struct DisasContext *dc = &ctx;
1511 uint32_t next_page_start, org_flags;
1512 target_ulong npc;
1513 int num_insns;
1514 int max_insns;
1515
1516 qemu_log_try_set_file(stderr);
1517
1518 pc_start = tb->pc;
1519 dc->env = env;
1520 dc->tb = tb;
1521 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1522
1523 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
1524
1525 dc->is_jmp = DISAS_NEXT;
1526 dc->jmp = 0;
1527 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1528 if (dc->delayed_branch) {
1529 dc->jmp = JMP_INDIRECT;
1530 }
1531 dc->pc = pc_start;
1532 dc->singlestep_enabled = env->singlestep_enabled;
1533 dc->cpustate_changed = 0;
1534 dc->abort_at_next_insn = 0;
1535 dc->nr_nops = 0;
1536
1537 if (pc_start & 3)
1538 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1539
1540 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1541 #if !SIM_COMPAT
1542 qemu_log("--------------\n");
1543 log_cpu_state(env, 0);
1544 #endif
1545 }
1546
1547 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1548 lj = -1;
1549 num_insns = 0;
1550 max_insns = tb->cflags & CF_COUNT_MASK;
1551 if (max_insns == 0)
1552 max_insns = CF_COUNT_MASK;
1553
1554 gen_icount_start();
1555 do
1556 {
1557 #if SIM_COMPAT
1558 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1559 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1560 gen_helper_debug();
1561 }
1562 #endif
1563 check_breakpoint(env, dc);
1564
1565 if (search_pc) {
1566 j = gen_opc_ptr - gen_opc_buf;
1567 if (lj < j) {
1568 lj++;
1569 while (lj < j)
1570 gen_opc_instr_start[lj++] = 0;
1571 }
1572 gen_opc_pc[lj] = dc->pc;
1573 gen_opc_instr_start[lj] = 1;
1574 gen_opc_icount[lj] = num_insns;
1575 }
1576
1577 /* Pretty disas. */
1578 LOG_DIS("%8.8x:\t", dc->pc);
1579
1580 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1581 gen_io_start();
1582
1583 dc->clear_imm = 1;
1584 decode(dc);
1585 if (dc->clear_imm)
1586 dc->tb_flags &= ~IMM_FLAG;
1587 dc->pc += 4;
1588 num_insns++;
1589
1590 if (dc->delayed_branch) {
1591 dc->delayed_branch--;
1592 if (!dc->delayed_branch) {
1593 if (dc->tb_flags & DRTI_FLAG)
1594 do_rti(dc);
1595 if (dc->tb_flags & DRTB_FLAG)
1596 do_rtb(dc);
1597 if (dc->tb_flags & DRTE_FLAG)
1598 do_rte(dc);
1599 /* Clear the delay slot flag. */
1600 dc->tb_flags &= ~D_FLAG;
1601 /* If it is a direct jump, try direct chaining. */
1602 if (dc->jmp == JMP_INDIRECT) {
1603 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1604 dc->is_jmp = DISAS_JUMP;
1605 } else if (dc->jmp == JMP_DIRECT) {
1606 t_sync_flags(dc);
1607 gen_goto_tb(dc, 0, dc->jmp_pc);
1608 dc->is_jmp = DISAS_TB_JUMP;
1609 } else if (dc->jmp == JMP_DIRECT_CC) {
1610 int l1;
1611
1612 t_sync_flags(dc);
1613 l1 = gen_new_label();
1614 /* Conditional jmp. */
1615 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1616 gen_goto_tb(dc, 1, dc->pc);
1617 gen_set_label(l1);
1618 gen_goto_tb(dc, 0, dc->jmp_pc);
1619
1620 dc->is_jmp = DISAS_TB_JUMP;
1621 }
1622 break;
1623 }
1624 }
1625 if (env->singlestep_enabled)
1626 break;
1627 } while (!dc->is_jmp && !dc->cpustate_changed
1628 && gen_opc_ptr < gen_opc_end
1629 && !singlestep
1630 && (dc->pc < next_page_start)
1631 && num_insns < max_insns);
1632
1633 npc = dc->pc;
1634 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1635 if (dc->tb_flags & D_FLAG) {
1636 dc->is_jmp = DISAS_UPDATE;
1637 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1638 sync_jmpstate(dc);
1639 } else
1640 npc = dc->jmp_pc;
1641 }
1642
1643 if (tb->cflags & CF_LAST_IO)
1644 gen_io_end();
1645 /* Force an update if the per-tb cpu state has changed. */
1646 if (dc->is_jmp == DISAS_NEXT
1647 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1648 dc->is_jmp = DISAS_UPDATE;
1649 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1650 }
1651 t_sync_flags(dc);
1652
1653 if (unlikely(env->singlestep_enabled)) {
1654 t_gen_raise_exception(dc, EXCP_DEBUG);
1655 if (dc->is_jmp == DISAS_NEXT)
1656 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1657 } else {
1658 switch(dc->is_jmp) {
1659 case DISAS_NEXT:
1660 gen_goto_tb(dc, 1, npc);
1661 break;
1662 default:
1663 case DISAS_JUMP:
1664 case DISAS_UPDATE:
1665 /* indicate that the hash table must be used
1666 to find the next TB */
1667 tcg_gen_exit_tb(0);
1668 break;
1669 case DISAS_TB_JUMP:
1670 /* nothing more to generate */
1671 break;
1672 }
1673 }
1674 gen_icount_end(tb, num_insns);
1675 *gen_opc_ptr = INDEX_op_end;
1676 if (search_pc) {
1677 j = gen_opc_ptr - gen_opc_buf;
1678 lj++;
1679 while (lj <= j)
1680 gen_opc_instr_start[lj++] = 0;
1681 } else {
1682 tb->size = dc->pc - pc_start;
1683 tb->icount = num_insns;
1684 }
1685
1686 #ifdef DEBUG_DISAS
1687 #if !SIM_COMPAT
1688 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1689 qemu_log("\n");
1690 #if DISAS_GNU
1691 log_target_disas(pc_start, dc->pc - pc_start, 0);
1692 #endif
1693 qemu_log("\nisize=%d osize=%td\n",
1694 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
1695 }
1696 #endif
1697 #endif
1698 assert(!dc->abort_at_next_insn);
1699 }
1700
1701 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
1702 {
1703 gen_intermediate_code_internal(env, tb, 0);
1704 }
1705
1706 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
1707 {
1708 gen_intermediate_code_internal(env, tb, 1);
1709 }
1710
1711 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
1712 int flags)
1713 {
1714 int i;
1715
1716 if (!env || !f)
1717 return;
1718
1719 cpu_fprintf(f, "IN: PC=%x %s\n",
1720 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1721 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1722 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1723 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1724 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1725 env->btaken, env->btarget,
1726 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1727 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1728 (env->sregs[SR_MSR] & MSR_EIP),
1729 (env->sregs[SR_MSR] & MSR_IE));
1730
1731 for (i = 0; i < 32; i++) {
1732 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1733 if ((i + 1) % 4 == 0)
1734 cpu_fprintf(f, "\n");
1735 }
1736 cpu_fprintf(f, "\n\n");
1737 }
1738
1739 CPUState *cpu_mb_init (const char *cpu_model)
1740 {
1741 CPUState *env;
1742 static int tcg_initialized = 0;
1743 int i;
1744
1745 env = qemu_mallocz(sizeof(CPUState));
1746
1747 cpu_exec_init(env);
1748 cpu_reset(env);
1749 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
1750
1751 if (tcg_initialized)
1752 return env;
1753
1754 tcg_initialized = 1;
1755
1756 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1757
1758 env_debug = tcg_global_mem_new(TCG_AREG0,
1759 offsetof(CPUState, debug),
1760 "debug0");
1761 env_iflags = tcg_global_mem_new(TCG_AREG0,
1762 offsetof(CPUState, iflags),
1763 "iflags");
1764 env_imm = tcg_global_mem_new(TCG_AREG0,
1765 offsetof(CPUState, imm),
1766 "imm");
1767 env_btarget = tcg_global_mem_new(TCG_AREG0,
1768 offsetof(CPUState, btarget),
1769 "btarget");
1770 env_btaken = tcg_global_mem_new(TCG_AREG0,
1771 offsetof(CPUState, btaken),
1772 "btaken");
1773 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
1774 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
1775 offsetof(CPUState, regs[i]),
1776 regnames[i]);
1777 }
1778 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
1779 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
1780 offsetof(CPUState, sregs[i]),
1781 special_regnames[i]);
1782 }
1783 #define GEN_HELPER 2
1784 #include "helper.h"
1785
1786 return env;
1787 }
1788
1789 void cpu_reset (CPUState *env)
1790 {
1791 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1792 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1793 log_cpu_state(env, 0);
1794 }
1795
1796 memset(env, 0, offsetof(CPUMBState, breakpoints));
1797 tlb_flush(env, 1);
1798
1799 env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
1800 | PVR0_USE_BARREL_MASK \
1801 | PVR0_USE_DIV_MASK \
1802 | PVR0_USE_HW_MUL_MASK \
1803 | PVR0_USE_EXC_MASK \
1804 | PVR0_USE_ICACHE_MASK \
1805 | PVR0_USE_DCACHE_MASK \
1806 | PVR0_USE_MMU \
1807 | (0xb << 8);
1808 env->pvr.regs[2] = PVR2_D_OPB_MASK \
1809 | PVR2_D_LMB_MASK \
1810 | PVR2_I_OPB_MASK \
1811 | PVR2_I_LMB_MASK \
1812 | PVR2_USE_MSR_INSTR \
1813 | PVR2_USE_PCMP_INSTR \
1814 | PVR2_USE_BARREL_MASK \
1815 | PVR2_USE_DIV_MASK \
1816 | PVR2_USE_HW_MUL_MASK \
1817 | PVR2_USE_MUL64_MASK \
1818 | PVR2_USE_FPU_MASK \
1819 | PVR2_USE_FPU2_MASK \
1820 | PVR2_FPU_EXC_MASK \
1821 | 0;
1822 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1823 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
1824
1825 #if defined(CONFIG_USER_ONLY)
1826 /* start in user mode with interrupts enabled. */
1827 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
1828 env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */
1829 #else
1830 env->sregs[SR_MSR] = 0;
1831 mmu_init(&env->mmu);
1832 env->mmu.c_mmu = 3;
1833 env->mmu.c_mmu_tlb_access = 3;
1834 env->mmu.c_mmu_zones = 16;
1835 #endif
1836 }
1837
1838 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
1839 unsigned long searched_pc, int pc_pos, void *puc)
1840 {
1841 env->sregs[SR_PC] = gen_opc_pc[pc_pos];
1842 }
Qemu copy for testing