2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
4 * Copyright (c) 2009 Edgar E. Iglesias.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 #include "microblaze-decode.h"
32 #if DISAS_MB && !SIM_COMPAT
33 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35 # define LOG_DIS(...) do { } while (0)
40 #define EXTRACT_FIELD(src, start, end) \
41 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43 static TCGv env_debug
;
44 static TCGv_ptr cpu_env
;
45 static TCGv cpu_R
[32];
46 static TCGv cpu_SR
[18];
48 static TCGv env_btaken
;
49 static TCGv env_btarget
;
50 static TCGv env_iflags
;
52 #include "gen-icount.h"
54 /* This is the state at translation time. */
55 typedef struct DisasContext
{
66 unsigned int cpustate_changed
;
67 unsigned int delayed_branch
;
68 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
69 unsigned int clear_imm
;
74 #define JMP_DIRECT_CC 2
75 #define JMP_INDIRECT 3
79 int abort_at_next_insn
;
81 struct TranslationBlock
*tb
;
82 int singlestep_enabled
;
85 static const char *regnames
[] =
87 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
88 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
89 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
90 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
93 static const char *special_regnames
[] =
95 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
96 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
97 "sr16", "sr17", "sr18"
100 /* Sign extend at translation time. */
101 static inline int sign_extend(unsigned int val
, unsigned int width
)
113 static inline void t_sync_flags(DisasContext
*dc
)
115 /* Synch the tb dependent flags between translator and runtime. */
116 if (dc
->tb_flags
!= dc
->synced_flags
) {
117 tcg_gen_movi_tl(env_iflags
, dc
->tb_flags
);
118 dc
->synced_flags
= dc
->tb_flags
;
122 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
124 TCGv_i32 tmp
= tcg_const_i32(index
);
127 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
128 gen_helper_raise_exception(tmp
);
129 tcg_temp_free_i32(tmp
);
130 dc
->is_jmp
= DISAS_UPDATE
;
133 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
135 TranslationBlock
*tb
;
137 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
139 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
140 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
142 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
147 static void read_carry(DisasContext
*dc
, TCGv d
)
149 tcg_gen_shri_tl(d
, cpu_SR
[SR_MSR
], 31);
152 static void write_carry(DisasContext
*dc
, TCGv v
)
154 TCGv t0
= tcg_temp_new();
155 tcg_gen_shli_tl(t0
, v
, 31);
156 tcg_gen_sari_tl(t0
, t0
, 31);
157 tcg_gen_andi_tl(t0
, t0
, (MSR_C
| MSR_CC
));
158 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
],
160 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], t0
);
164 /* True if ALU operand b is a small immediate that may deserve
166 static inline int dec_alu_op_b_is_small_imm(DisasContext
*dc
)
168 /* Immediate insn without the imm prefix ? */
169 return dc
->type_b
&& !(dc
->tb_flags
& IMM_FLAG
);
172 static inline TCGv
*dec_alu_op_b(DisasContext
*dc
)
175 if (dc
->tb_flags
& IMM_FLAG
)
176 tcg_gen_ori_tl(env_imm
, env_imm
, dc
->imm
);
178 tcg_gen_movi_tl(env_imm
, (int32_t)((int16_t)dc
->imm
));
181 return &cpu_R
[dc
->rb
];
184 static void dec_add(DisasContext
*dc
)
192 LOG_DIS("add%s%s%s r%d r%d r%d\n",
193 dc
->type_b
? "i" : "", k
? "k" : "", c
? "c" : "",
194 dc
->rd
, dc
->ra
, dc
->rb
);
196 /* Take care of the easy cases first. */
198 /* k - keep carry, no need to update MSR. */
199 /* If rd == r0, it's a nop. */
201 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
204 /* c - Add carry into the result. */
208 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
215 /* From now on, we can assume k is zero. So we need to update MSR. */
221 tcg_gen_movi_tl(cf
, 0);
225 TCGv ncf
= tcg_temp_new();
226 gen_helper_carry(ncf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
227 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
228 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
229 write_carry(dc
, ncf
);
232 gen_helper_carry(cf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
238 static void dec_sub(DisasContext
*dc
)
240 unsigned int u
, cmp
, k
, c
;
246 cmp
= (dc
->imm
& 1) && (!dc
->type_b
) && k
;
249 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u
? "u" : "", dc
->rd
, dc
->ra
, dc
->ir
);
252 gen_helper_cmpu(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
254 gen_helper_cmp(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
259 LOG_DIS("sub%s%s r%d, r%d r%d\n",
260 k
? "k" : "", c
? "c" : "", dc
->rd
, dc
->ra
, dc
->rb
);
262 /* Take care of the easy cases first. */
264 /* k - keep carry, no need to update MSR. */
265 /* If rd == r0, it's a nop. */
267 tcg_gen_sub_tl(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
270 /* c - Add carry into the result. */
274 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
281 /* From now on, we can assume k is zero. So we need to update MSR. */
282 /* Extract carry. And complement a into na. */
288 tcg_gen_movi_tl(cf
, 1);
291 /* d = b + ~a + c. carry defaults to 1. */
292 tcg_gen_not_tl(na
, cpu_R
[dc
->ra
]);
295 TCGv ncf
= tcg_temp_new();
296 gen_helper_carry(ncf
, na
, *(dec_alu_op_b(dc
)), cf
);
297 tcg_gen_add_tl(cpu_R
[dc
->rd
], na
, *(dec_alu_op_b(dc
)));
298 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
299 write_carry(dc
, ncf
);
302 gen_helper_carry(cf
, na
, *(dec_alu_op_b(dc
)), cf
);
309 static void dec_pattern(DisasContext
*dc
)
314 if ((dc
->tb_flags
& MSR_EE_FLAG
)
315 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
316 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
317 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
318 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
321 mode
= dc
->opcode
& 3;
325 LOG_DIS("pcmpbf r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
327 gen_helper_pcmpbf(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
330 LOG_DIS("pcmpeq r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
332 TCGv t0
= tcg_temp_local_new();
333 l1
= gen_new_label();
334 tcg_gen_movi_tl(t0
, 1);
335 tcg_gen_brcond_tl(TCG_COND_EQ
,
336 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
337 tcg_gen_movi_tl(t0
, 0);
339 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
344 LOG_DIS("pcmpne r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
345 l1
= gen_new_label();
347 TCGv t0
= tcg_temp_local_new();
348 tcg_gen_movi_tl(t0
, 1);
349 tcg_gen_brcond_tl(TCG_COND_NE
,
350 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
351 tcg_gen_movi_tl(t0
, 0);
353 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
359 "unsupported pattern insn opcode=%x\n", dc
->opcode
);
364 static void dec_and(DisasContext
*dc
)
368 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
373 not = dc
->opcode
& (1 << 1);
374 LOG_DIS("and%s\n", not ? "n" : "");
380 TCGv t
= tcg_temp_new();
381 tcg_gen_not_tl(t
, *(dec_alu_op_b(dc
)));
382 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t
);
385 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
388 static void dec_or(DisasContext
*dc
)
390 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
395 LOG_DIS("or r%d r%d r%d imm=%x\n", dc
->rd
, dc
->ra
, dc
->rb
, dc
->imm
);
397 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
400 static void dec_xor(DisasContext
*dc
)
402 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
407 LOG_DIS("xor r%d\n", dc
->rd
);
409 tcg_gen_xor_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
412 static inline void msr_read(DisasContext
*dc
, TCGv d
)
414 tcg_gen_mov_tl(d
, cpu_SR
[SR_MSR
]);
417 static inline void msr_write(DisasContext
*dc
, TCGv v
)
422 dc
->cpustate_changed
= 1;
423 /* PVR bit is not writable. */
424 tcg_gen_andi_tl(t
, v
, ~MSR_PVR
);
425 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], MSR_PVR
);
426 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], v
);
430 static void dec_msr(DisasContext
*dc
)
433 unsigned int sr
, to
, rn
;
434 int mem_index
= cpu_mmu_index(dc
->env
);
436 sr
= dc
->imm
& ((1 << 14) - 1);
437 to
= dc
->imm
& (1 << 14);
440 dc
->cpustate_changed
= 1;
442 /* msrclr and msrset. */
443 if (!(dc
->imm
& (1 << 15))) {
444 unsigned int clr
= dc
->ir
& (1 << 16);
446 LOG_DIS("msr%s r%d imm=%x\n", clr
? "clr" : "set",
449 if (!(dc
->env
->pvr
.regs
[2] & PVR2_USE_MSR_INSTR
)) {
454 if ((dc
->tb_flags
& MSR_EE_FLAG
)
455 && mem_index
== MMU_USER_IDX
&& (dc
->imm
!= 4 && dc
->imm
!= 0)) {
456 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
457 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
462 msr_read(dc
, cpu_R
[dc
->rd
]);
467 tcg_gen_mov_tl(t1
, *(dec_alu_op_b(dc
)));
470 tcg_gen_not_tl(t1
, t1
);
471 tcg_gen_and_tl(t0
, t0
, t1
);
473 tcg_gen_or_tl(t0
, t0
, t1
);
477 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
478 dc
->is_jmp
= DISAS_UPDATE
;
483 if ((dc
->tb_flags
& MSR_EE_FLAG
)
484 && mem_index
== MMU_USER_IDX
) {
485 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
486 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
491 #if !defined(CONFIG_USER_ONLY)
492 /* Catch read/writes to the mmu block. */
493 if ((sr
& ~0xff) == 0x1000) {
495 LOG_DIS("m%ss sr%d r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
497 gen_helper_mmu_write(tcg_const_tl(sr
), cpu_R
[dc
->ra
]);
499 gen_helper_mmu_read(cpu_R
[dc
->rd
], tcg_const_tl(sr
));
505 LOG_DIS("m%ss sr%x r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
510 msr_write(dc
, cpu_R
[dc
->ra
]);
513 tcg_gen_mov_tl(cpu_SR
[SR_EAR
], cpu_R
[dc
->ra
]);
516 tcg_gen_mov_tl(cpu_SR
[SR_ESR
], cpu_R
[dc
->ra
]);
519 tcg_gen_andi_tl(cpu_SR
[SR_FSR
], cpu_R
[dc
->ra
], 31);
522 tcg_gen_st_tl(cpu_R
[dc
->ra
], cpu_env
, offsetof(CPUMBState
, slr
));
525 tcg_gen_st_tl(cpu_R
[dc
->ra
], cpu_env
, offsetof(CPUMBState
, shr
));
528 cpu_abort(dc
->env
, "unknown mts reg %x\n", sr
);
532 LOG_DIS("m%ss r%d sr%x imm=%x\n", to
? "t" : "f", dc
->rd
, sr
, dc
->imm
);
536 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
539 msr_read(dc
, cpu_R
[dc
->rd
]);
542 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_EAR
]);
545 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_ESR
]);
548 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_FSR
]);
551 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_BTR
]);
554 tcg_gen_ld_tl(cpu_R
[dc
->rd
], cpu_env
, offsetof(CPUMBState
, slr
));
557 tcg_gen_ld_tl(cpu_R
[dc
->rd
], cpu_env
, offsetof(CPUMBState
, shr
));
573 tcg_gen_ld_tl(cpu_R
[dc
->rd
],
574 cpu_env
, offsetof(CPUMBState
, pvr
.regs
[rn
]));
577 cpu_abort(dc
->env
, "unknown mfs reg %x\n", sr
);
583 tcg_gen_movi_tl(cpu_R
[0], 0);
587 /* 64-bit signed mul, lower result in d and upper in d2. */
588 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
592 t0
= tcg_temp_new_i64();
593 t1
= tcg_temp_new_i64();
595 tcg_gen_ext_i32_i64(t0
, a
);
596 tcg_gen_ext_i32_i64(t1
, b
);
597 tcg_gen_mul_i64(t0
, t0
, t1
);
599 tcg_gen_trunc_i64_i32(d
, t0
);
600 tcg_gen_shri_i64(t0
, t0
, 32);
601 tcg_gen_trunc_i64_i32(d2
, t0
);
603 tcg_temp_free_i64(t0
);
604 tcg_temp_free_i64(t1
);
607 /* 64-bit unsigned muls, lower result in d and upper in d2. */
608 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
612 t0
= tcg_temp_new_i64();
613 t1
= tcg_temp_new_i64();
615 tcg_gen_extu_i32_i64(t0
, a
);
616 tcg_gen_extu_i32_i64(t1
, b
);
617 tcg_gen_mul_i64(t0
, t0
, t1
);
619 tcg_gen_trunc_i64_i32(d
, t0
);
620 tcg_gen_shri_i64(t0
, t0
, 32);
621 tcg_gen_trunc_i64_i32(d2
, t0
);
623 tcg_temp_free_i64(t0
);
624 tcg_temp_free_i64(t1
);
627 /* Multiplier unit. */
628 static void dec_mul(DisasContext
*dc
)
631 unsigned int subcode
;
633 if ((dc
->tb_flags
& MSR_EE_FLAG
)
634 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
635 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_HW_MUL_MASK
)) {
636 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
637 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
641 subcode
= dc
->imm
& 3;
642 d
[0] = tcg_temp_new();
643 d
[1] = tcg_temp_new();
646 LOG_DIS("muli r%d r%d %x\n", dc
->rd
, dc
->ra
, dc
->imm
);
647 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
651 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
652 if (subcode
>= 1 && subcode
<= 3
653 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_MUL64_MASK
))) {
659 LOG_DIS("mul r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
660 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
663 LOG_DIS("mulh r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
664 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
667 LOG_DIS("mulhsu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
668 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
671 LOG_DIS("mulhu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
672 t_gen_mulu(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
675 cpu_abort(dc
->env
, "unknown MUL insn %x\n", subcode
);
684 static void dec_div(DisasContext
*dc
)
691 if ((dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
692 && !((dc
->env
->pvr
.regs
[0] & PVR0_USE_DIV_MASK
))) {
693 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
694 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
698 gen_helper_divu(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
700 gen_helper_divs(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
702 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
705 static void dec_barrel(DisasContext
*dc
)
710 if ((dc
->tb_flags
& MSR_EE_FLAG
)
711 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
712 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_BARREL_MASK
)) {
713 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
714 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
718 s
= dc
->imm
& (1 << 10);
719 t
= dc
->imm
& (1 << 9);
721 LOG_DIS("bs%s%s r%d r%d r%d\n",
722 s
? "l" : "r", t
? "a" : "l", dc
->rd
, dc
->ra
, dc
->rb
);
726 tcg_gen_mov_tl(t0
, *(dec_alu_op_b(dc
)));
727 tcg_gen_andi_tl(t0
, t0
, 31);
730 tcg_gen_shl_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
733 tcg_gen_sar_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
735 tcg_gen_shr_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
739 static void dec_bit(DisasContext
*dc
)
743 int mem_index
= cpu_mmu_index(dc
->env
);
745 op
= dc
->ir
& ((1 << 8) - 1);
751 LOG_DIS("src r%d r%d\n", dc
->rd
, dc
->ra
);
752 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
756 tcg_gen_shli_tl(t1
, t1
, 31);
758 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
759 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], t1
);
772 LOG_DIS("srl r%d r%d\n", dc
->rd
, dc
->ra
);
775 tcg_gen_andi_tl(t0
, cpu_R
[dc
->ra
], 1);
780 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
782 tcg_gen_sari_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
786 LOG_DIS("ext8s r%d r%d\n", dc
->rd
, dc
->ra
);
787 tcg_gen_ext8s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
790 LOG_DIS("ext16s r%d r%d\n", dc
->rd
, dc
->ra
);
791 tcg_gen_ext16s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
798 LOG_DIS("wdc r%d\n", dc
->ra
);
799 if ((dc
->tb_flags
& MSR_EE_FLAG
)
800 && mem_index
== MMU_USER_IDX
) {
801 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
802 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
808 LOG_DIS("wic r%d\n", dc
->ra
);
809 if ((dc
->tb_flags
& MSR_EE_FLAG
)
810 && mem_index
== MMU_USER_IDX
) {
811 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
812 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
817 if ((dc
->tb_flags
& MSR_EE_FLAG
)
818 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
819 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
820 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
821 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
823 if (dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
) {
824 gen_helper_clz(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
828 cpu_abort(dc
->env
, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
829 dc
->pc
, op
, dc
->rd
, dc
->ra
, dc
->rb
);
834 static inline void sync_jmpstate(DisasContext
*dc
)
836 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
837 if (dc
->jmp
== JMP_DIRECT
) {
838 tcg_gen_movi_tl(env_btaken
, 1);
840 dc
->jmp
= JMP_INDIRECT
;
841 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
845 static void dec_imm(DisasContext
*dc
)
847 LOG_DIS("imm %x\n", dc
->imm
<< 16);
848 tcg_gen_movi_tl(env_imm
, (dc
->imm
<< 16));
849 dc
->tb_flags
|= IMM_FLAG
;
853 static inline void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
856 int mem_index
= cpu_mmu_index(dc
->env
);
859 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
860 } else if (size
== 2) {
861 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
862 } else if (size
== 4) {
863 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
865 cpu_abort(dc
->env
, "Incorrect load size %d\n", size
);
868 static inline TCGv
*compute_ldst_addr(DisasContext
*dc
, TCGv
*t
)
870 unsigned int extimm
= dc
->tb_flags
& IMM_FLAG
;
871 /* Should be set to one if r1 is used by loadstores. */
874 /* All load/stores use ra. */
879 /* Treat the common cases first. */
881 /* If any of the regs is r0, return a ptr to the other. */
883 return &cpu_R
[dc
->rb
];
884 } else if (dc
->rb
== 0) {
885 return &cpu_R
[dc
->ra
];
893 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
896 gen_helper_stackprot(*t
);
903 return &cpu_R
[dc
->ra
];
906 tcg_gen_movi_tl(*t
, (int32_t)((int16_t)dc
->imm
));
907 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *t
);
910 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
914 gen_helper_stackprot(*t
);
919 static inline void dec_byteswap(DisasContext
*dc
, TCGv dst
, TCGv src
, int size
)
922 tcg_gen_bswap32_tl(dst
, src
);
923 } else if (size
== 2) {
924 TCGv t
= tcg_temp_new();
926 /* bswap16 assumes the high bits are zero. */
927 tcg_gen_andi_tl(t
, src
, 0xffff);
928 tcg_gen_bswap16_tl(dst
, t
);
932 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
937 static void dec_load(DisasContext
*dc
)
940 unsigned int size
, rev
= 0;
942 size
= 1 << (dc
->opcode
& 3);
945 rev
= (dc
->ir
>> 9) & 1;
948 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
949 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
950 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
951 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
955 LOG_DIS("l%d%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "");
958 addr
= compute_ldst_addr(dc
, &t
);
961 * When doing reverse accesses we need to do two things.
963 * 1. Reverse the address wrt endianness.
964 * 2. Byteswap the data lanes on the way back into the CPU core.
966 if (rev
&& size
!= 4) {
967 /* Endian reverse the address. t is addr. */
975 TCGv low
= tcg_temp_new();
977 /* Force addr into the temp. */
980 tcg_gen_mov_tl(t
, *addr
);
984 tcg_gen_andi_tl(low
, t
, 3);
985 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
986 tcg_gen_andi_tl(t
, t
, ~3);
987 tcg_gen_or_tl(t
, t
, low
);
988 tcg_gen_mov_tl(env_imm
, t
);
996 /* Force addr into the temp. */
999 tcg_gen_xori_tl(t
, *addr
, 2);
1002 tcg_gen_xori_tl(t
, t
, 2);
1006 cpu_abort(dc
->env
, "Invalid reverse size\n");
1011 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1014 /* Verify alignment if needed. */
1015 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
1016 TCGv v
= tcg_temp_new();
1019 * Microblaze gives MMU faults priority over faults due to
1020 * unaligned addresses. That's why we speculatively do the load
1021 * into v. If the load succeeds, we verify alignment of the
1022 * address and if that succeeds we write into the destination reg.
1024 gen_load(dc
, v
, *addr
, size
);
1026 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1027 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
1028 tcg_const_tl(0), tcg_const_tl(size
- 1));
1031 dec_byteswap(dc
, cpu_R
[dc
->rd
], v
, size
);
1033 tcg_gen_mov_tl(cpu_R
[dc
->rd
], v
);
1039 gen_load(dc
, cpu_R
[dc
->rd
], *addr
, size
);
1041 dec_byteswap(dc
, cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], size
);
1044 /* We are loading into r0, no need to reverse. */
1045 gen_load(dc
, env_imm
, *addr
, size
);
1053 static void gen_store(DisasContext
*dc
, TCGv addr
, TCGv val
,
1056 int mem_index
= cpu_mmu_index(dc
->env
);
1059 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1060 else if (size
== 2) {
1061 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1062 } else if (size
== 4) {
1063 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1065 cpu_abort(dc
->env
, "Incorrect store size %d\n", size
);
1068 static void dec_store(DisasContext
*dc
)
1071 unsigned int size
, rev
= 0;
1073 size
= 1 << (dc
->opcode
& 3);
1075 rev
= (dc
->ir
>> 9) & 1;
1078 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
1079 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1080 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1081 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1085 LOG_DIS("s%d%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "");
1087 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1089 addr
= compute_ldst_addr(dc
, &t
);
1091 if (rev
&& size
!= 4) {
1092 /* Endian reverse the address. t is addr. */
1100 TCGv low
= tcg_temp_new();
1102 /* Force addr into the temp. */
1105 tcg_gen_mov_tl(t
, *addr
);
1109 tcg_gen_andi_tl(low
, t
, 3);
1110 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
1111 tcg_gen_andi_tl(t
, t
, ~3);
1112 tcg_gen_or_tl(t
, t
, low
);
1113 tcg_gen_mov_tl(env_imm
, t
);
1121 /* Force addr into the temp. */
1124 tcg_gen_xori_tl(t
, *addr
, 2);
1127 tcg_gen_xori_tl(t
, t
, 2);
1131 cpu_abort(dc
->env
, "Invalid reverse size\n");
1136 TCGv bs_data
= tcg_temp_new();
1137 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1138 gen_store(dc
, *addr
, bs_data
, size
);
1139 tcg_temp_free(bs_data
);
1141 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1145 TCGv bs_data
= tcg_temp_new();
1146 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1147 gen_store(dc
, *addr
, bs_data
, size
);
1148 tcg_temp_free(bs_data
);
1150 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1154 /* Verify alignment if needed. */
1155 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
1156 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1157 /* FIXME: if the alignment is wrong, we should restore the value
1158 * in memory. One possible way to achieve this is to probe
1159 * the MMU prior to the memaccess, thay way we could put
1160 * the alignment checks in between the probe and the mem
1163 gen_helper_memalign(*addr
, tcg_const_tl(dc
->rd
),
1164 tcg_const_tl(1), tcg_const_tl(size
- 1));
1171 static inline void eval_cc(DisasContext
*dc
, unsigned int cc
,
1172 TCGv d
, TCGv a
, TCGv b
)
1176 tcg_gen_setcond_tl(TCG_COND_EQ
, d
, a
, b
);
1179 tcg_gen_setcond_tl(TCG_COND_NE
, d
, a
, b
);
1182 tcg_gen_setcond_tl(TCG_COND_LT
, d
, a
, b
);
1185 tcg_gen_setcond_tl(TCG_COND_LE
, d
, a
, b
);
1188 tcg_gen_setcond_tl(TCG_COND_GE
, d
, a
, b
);
1191 tcg_gen_setcond_tl(TCG_COND_GT
, d
, a
, b
);
1194 cpu_abort(dc
->env
, "Unknown condition code %x.\n", cc
);
1199 static void eval_cond_jmp(DisasContext
*dc
, TCGv pc_true
, TCGv pc_false
)
1203 l1
= gen_new_label();
1204 /* Conditional jmp. */
1205 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_false
);
1206 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
1207 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_true
);
1211 static void dec_bcc(DisasContext
*dc
)
1216 cc
= EXTRACT_FIELD(dc
->ir
, 21, 23);
1217 dslot
= dc
->ir
& (1 << 25);
1218 LOG_DIS("bcc%s r%d %x\n", dslot
? "d" : "", dc
->ra
, dc
->imm
);
1220 dc
->delayed_branch
= 1;
1222 dc
->delayed_branch
= 2;
1223 dc
->tb_flags
|= D_FLAG
;
1224 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1225 cpu_env
, offsetof(CPUMBState
, bimm
));
1228 if (dec_alu_op_b_is_small_imm(dc
)) {
1229 int32_t offset
= (int32_t)((int16_t)dc
->imm
); /* sign-extend. */
1231 tcg_gen_movi_tl(env_btarget
, dc
->pc
+ offset
);
1232 dc
->jmp
= JMP_DIRECT_CC
;
1233 dc
->jmp_pc
= dc
->pc
+ offset
;
1235 dc
->jmp
= JMP_INDIRECT
;
1236 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1237 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1239 eval_cc(dc
, cc
, env_btaken
, cpu_R
[dc
->ra
], tcg_const_tl(0));
1242 static void dec_br(DisasContext
*dc
)
1244 unsigned int dslot
, link
, abs
, mbar
;
1245 int mem_index
= cpu_mmu_index(dc
->env
);
1247 dslot
= dc
->ir
& (1 << 20);
1248 abs
= dc
->ir
& (1 << 19);
1249 link
= dc
->ir
& (1 << 18);
1251 /* Memory barrier. */
1252 mbar
= (dc
->ir
>> 16) & 31;
1253 if (mbar
== 2 && dc
->imm
== 4) {
1254 LOG_DIS("mbar %d\n", dc
->rd
);
1256 dc
->cpustate_changed
= 1;
1260 LOG_DIS("br%s%s%s%s imm=%x\n",
1261 abs
? "a" : "", link
? "l" : "",
1262 dc
->type_b
? "i" : "", dslot
? "d" : "",
1265 dc
->delayed_branch
= 1;
1267 dc
->delayed_branch
= 2;
1268 dc
->tb_flags
|= D_FLAG
;
1269 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1270 cpu_env
, offsetof(CPUMBState
, bimm
));
1273 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
1275 dc
->jmp
= JMP_INDIRECT
;
1277 tcg_gen_movi_tl(env_btaken
, 1);
1278 tcg_gen_mov_tl(env_btarget
, *(dec_alu_op_b(dc
)));
1279 if (link
&& !dslot
) {
1280 if (!(dc
->tb_flags
& IMM_FLAG
) && (dc
->imm
== 8 || dc
->imm
== 0x18))
1281 t_gen_raise_exception(dc
, EXCP_BREAK
);
1283 if ((dc
->tb_flags
& MSR_EE_FLAG
) && mem_index
== MMU_USER_IDX
) {
1284 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1285 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1289 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1293 if (dec_alu_op_b_is_small_imm(dc
)) {
1294 dc
->jmp
= JMP_DIRECT
;
1295 dc
->jmp_pc
= dc
->pc
+ (int32_t)((int16_t)dc
->imm
);
1297 tcg_gen_movi_tl(env_btaken
, 1);
1298 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1299 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1304 static inline void do_rti(DisasContext
*dc
)
1307 t0
= tcg_temp_new();
1308 t1
= tcg_temp_new();
1309 tcg_gen_shri_tl(t0
, cpu_SR
[SR_MSR
], 1);
1310 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_IE
);
1311 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1313 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1314 tcg_gen_or_tl(t1
, t1
, t0
);
1318 dc
->tb_flags
&= ~DRTI_FLAG
;
1321 static inline void do_rtb(DisasContext
*dc
)
1324 t0
= tcg_temp_new();
1325 t1
= tcg_temp_new();
1326 tcg_gen_andi_tl(t1
, cpu_SR
[SR_MSR
], ~MSR_BIP
);
1327 tcg_gen_shri_tl(t0
, t1
, 1);
1328 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1330 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1331 tcg_gen_or_tl(t1
, t1
, t0
);
1335 dc
->tb_flags
&= ~DRTB_FLAG
;
1338 static inline void do_rte(DisasContext
*dc
)
1341 t0
= tcg_temp_new();
1342 t1
= tcg_temp_new();
1344 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_EE
);
1345 tcg_gen_andi_tl(t1
, t1
, ~MSR_EIP
);
1346 tcg_gen_shri_tl(t0
, t1
, 1);
1347 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1349 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1350 tcg_gen_or_tl(t1
, t1
, t0
);
1354 dc
->tb_flags
&= ~DRTE_FLAG
;
1357 static void dec_rts(DisasContext
*dc
)
1359 unsigned int b_bit
, i_bit
, e_bit
;
1360 int mem_index
= cpu_mmu_index(dc
->env
);
1362 i_bit
= dc
->ir
& (1 << 21);
1363 b_bit
= dc
->ir
& (1 << 22);
1364 e_bit
= dc
->ir
& (1 << 23);
1366 dc
->delayed_branch
= 2;
1367 dc
->tb_flags
|= D_FLAG
;
1368 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1369 cpu_env
, offsetof(CPUMBState
, bimm
));
1372 LOG_DIS("rtid ir=%x\n", dc
->ir
);
1373 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1374 && mem_index
== MMU_USER_IDX
) {
1375 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1376 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1378 dc
->tb_flags
|= DRTI_FLAG
;
1380 LOG_DIS("rtbd ir=%x\n", dc
->ir
);
1381 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1382 && mem_index
== MMU_USER_IDX
) {
1383 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1384 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1386 dc
->tb_flags
|= DRTB_FLAG
;
1388 LOG_DIS("rted ir=%x\n", dc
->ir
);
1389 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1390 && mem_index
== MMU_USER_IDX
) {
1391 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1392 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1394 dc
->tb_flags
|= DRTE_FLAG
;
1396 LOG_DIS("rts ir=%x\n", dc
->ir
);
1398 dc
->jmp
= JMP_INDIRECT
;
1399 tcg_gen_movi_tl(env_btaken
, 1);
1400 tcg_gen_add_tl(env_btarget
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
1403 static int dec_check_fpuv2(DisasContext
*dc
)
1407 r
= dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU2_MASK
;
1409 if (!r
&& (dc
->tb_flags
& MSR_EE_FLAG
)) {
1410 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_FPU
);
1411 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1416 static void dec_fpu(DisasContext
*dc
)
1418 unsigned int fpu_insn
;
1420 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1421 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1422 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU_MASK
))) {
1423 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1424 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1428 fpu_insn
= (dc
->ir
>> 7) & 7;
1432 gen_helper_fadd(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1436 gen_helper_frsub(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1440 gen_helper_fmul(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1444 gen_helper_fdiv(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1448 switch ((dc
->ir
>> 4) & 7) {
1450 gen_helper_fcmp_un(cpu_R
[dc
->rd
],
1451 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1454 gen_helper_fcmp_lt(cpu_R
[dc
->rd
],
1455 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1458 gen_helper_fcmp_eq(cpu_R
[dc
->rd
],
1459 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1462 gen_helper_fcmp_le(cpu_R
[dc
->rd
],
1463 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1466 gen_helper_fcmp_gt(cpu_R
[dc
->rd
],
1467 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1470 gen_helper_fcmp_ne(cpu_R
[dc
->rd
],
1471 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1474 gen_helper_fcmp_ge(cpu_R
[dc
->rd
],
1475 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1478 qemu_log ("unimplemented fcmp fpu_insn=%x pc=%x opc=%x\n",
1479 fpu_insn
, dc
->pc
, dc
->opcode
);
1480 dc
->abort_at_next_insn
= 1;
1486 if (!dec_check_fpuv2(dc
)) {
1489 gen_helper_flt(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1493 if (!dec_check_fpuv2(dc
)) {
1496 gen_helper_fint(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1500 if (!dec_check_fpuv2(dc
)) {
1503 gen_helper_fsqrt(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
1507 qemu_log ("unimplemented FPU insn fpu_insn=%x pc=%x opc=%x\n",
1508 fpu_insn
, dc
->pc
, dc
->opcode
);
1509 dc
->abort_at_next_insn
= 1;
1514 static void dec_null(DisasContext
*dc
)
1516 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1517 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1518 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1519 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1522 qemu_log ("unknown insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1523 dc
->abort_at_next_insn
= 1;
1526 /* Insns connected to FSL or AXI stream attached devices. */
1527 static void dec_stream(DisasContext
*dc
)
1529 int mem_index
= cpu_mmu_index(dc
->env
);
1530 TCGv_i32 t_id
, t_ctrl
;
1533 LOG_DIS("%s%s imm=%x\n", dc
->rd
? "get" : "put",
1534 dc
->type_b
? "" : "d", dc
->imm
);
1536 if ((dc
->tb_flags
& MSR_EE_FLAG
) && (mem_index
== MMU_USER_IDX
)) {
1537 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1538 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1542 t_id
= tcg_temp_new();
1544 tcg_gen_movi_tl(t_id
, dc
->imm
& 0xf);
1545 ctrl
= dc
->imm
>> 10;
1547 tcg_gen_andi_tl(t_id
, cpu_R
[dc
->rb
], 0xf);
1548 ctrl
= dc
->imm
>> 5;
1551 t_ctrl
= tcg_const_tl(ctrl
);
1554 gen_helper_put(t_id
, t_ctrl
, cpu_R
[dc
->ra
]);
1556 gen_helper_get(cpu_R
[dc
->rd
], t_id
, t_ctrl
);
1558 tcg_temp_free(t_id
);
1559 tcg_temp_free(t_ctrl
);
1562 static struct decoder_info
{
1567 void (*dec
)(DisasContext
*dc
);
1575 {DEC_BARREL
, dec_barrel
},
1577 {DEC_ST
, dec_store
},
1586 {DEC_STREAM
, dec_stream
},
1590 static inline void decode(DisasContext
*dc
)
1595 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
1596 tcg_gen_debug_insn_start(dc
->pc
);
1598 dc
->ir
= ir
= ldl_code(dc
->pc
);
1599 LOG_DIS("%8.8x\t", dc
->ir
);
1604 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1605 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1606 && (dc
->env
->pvr
.regs
[2] & PVR2_OPCODE_0x0_ILL_MASK
)) {
1607 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1608 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1612 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1614 if (dc
->nr_nops
> 4)
1615 cpu_abort(dc
->env
, "fetching nop sequence\n");
1617 /* bit 2 seems to indicate insn type. */
1618 dc
->type_b
= ir
& (1 << 29);
1620 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1621 dc
->rd
= EXTRACT_FIELD(ir
, 21, 25);
1622 dc
->ra
= EXTRACT_FIELD(ir
, 16, 20);
1623 dc
->rb
= EXTRACT_FIELD(ir
, 11, 15);
1624 dc
->imm
= EXTRACT_FIELD(ir
, 0, 15);
1626 /* Large switch for all insns. */
1627 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1628 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1635 static void check_breakpoint(CPUMBState
*env
, DisasContext
*dc
)
1639 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1640 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1641 if (bp
->pc
== dc
->pc
) {
1642 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1643 dc
->is_jmp
= DISAS_UPDATE
;
1649 /* generate intermediate code for basic block 'tb'. */
1651 gen_intermediate_code_internal(CPUMBState
*env
, TranslationBlock
*tb
,
1654 uint16_t *gen_opc_end
;
1657 struct DisasContext ctx
;
1658 struct DisasContext
*dc
= &ctx
;
1659 uint32_t next_page_start
, org_flags
;
1664 qemu_log_try_set_file(stderr
);
1669 org_flags
= dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1671 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1673 dc
->is_jmp
= DISAS_NEXT
;
1675 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1676 if (dc
->delayed_branch
) {
1677 dc
->jmp
= JMP_INDIRECT
;
1680 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1681 dc
->cpustate_changed
= 0;
1682 dc
->abort_at_next_insn
= 0;
1686 cpu_abort(env
, "Microblaze: unaligned PC=%x\n", pc_start
);
1688 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1690 qemu_log("--------------\n");
1691 log_cpu_state(env
, 0);
1695 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1698 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1700 max_insns
= CF_COUNT_MASK
;
1706 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1707 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1711 check_breakpoint(env
, dc
);
1714 j
= gen_opc_ptr
- gen_opc_buf
;
1718 gen_opc_instr_start
[lj
++] = 0;
1720 gen_opc_pc
[lj
] = dc
->pc
;
1721 gen_opc_instr_start
[lj
] = 1;
1722 gen_opc_icount
[lj
] = num_insns
;
1726 LOG_DIS("%8.8x:\t", dc
->pc
);
1728 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1734 dc
->tb_flags
&= ~IMM_FLAG
;
1738 if (dc
->delayed_branch
) {
1739 dc
->delayed_branch
--;
1740 if (!dc
->delayed_branch
) {
1741 if (dc
->tb_flags
& DRTI_FLAG
)
1743 if (dc
->tb_flags
& DRTB_FLAG
)
1745 if (dc
->tb_flags
& DRTE_FLAG
)
1747 /* Clear the delay slot flag. */
1748 dc
->tb_flags
&= ~D_FLAG
;
1749 /* If it is a direct jump, try direct chaining. */
1750 if (dc
->jmp
== JMP_INDIRECT
) {
1751 eval_cond_jmp(dc
, env_btarget
, tcg_const_tl(dc
->pc
));
1752 dc
->is_jmp
= DISAS_JUMP
;
1753 } else if (dc
->jmp
== JMP_DIRECT
) {
1755 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1756 dc
->is_jmp
= DISAS_TB_JUMP
;
1757 } else if (dc
->jmp
== JMP_DIRECT_CC
) {
1761 l1
= gen_new_label();
1762 /* Conditional jmp. */
1763 tcg_gen_brcondi_tl(TCG_COND_NE
, env_btaken
, 0, l1
);
1764 gen_goto_tb(dc
, 1, dc
->pc
);
1766 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1768 dc
->is_jmp
= DISAS_TB_JUMP
;
1773 if (env
->singlestep_enabled
)
1775 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
1776 && gen_opc_ptr
< gen_opc_end
1778 && (dc
->pc
< next_page_start
)
1779 && num_insns
< max_insns
);
1782 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1783 if (dc
->tb_flags
& D_FLAG
) {
1784 dc
->is_jmp
= DISAS_UPDATE
;
1785 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1791 if (tb
->cflags
& CF_LAST_IO
)
1793 /* Force an update if the per-tb cpu state has changed. */
1794 if (dc
->is_jmp
== DISAS_NEXT
1795 && (dc
->cpustate_changed
|| org_flags
!= dc
->tb_flags
)) {
1796 dc
->is_jmp
= DISAS_UPDATE
;
1797 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1801 if (unlikely(env
->singlestep_enabled
)) {
1802 TCGv_i32 tmp
= tcg_const_i32(EXCP_DEBUG
);
1804 if (dc
->is_jmp
!= DISAS_JUMP
) {
1805 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1807 gen_helper_raise_exception(tmp
);
1808 tcg_temp_free_i32(tmp
);
1810 switch(dc
->is_jmp
) {
1812 gen_goto_tb(dc
, 1, npc
);
1817 /* indicate that the hash table must be used
1818 to find the next TB */
1822 /* nothing more to generate */
1826 gen_icount_end(tb
, num_insns
);
1827 *gen_opc_ptr
= INDEX_op_end
;
1829 j
= gen_opc_ptr
- gen_opc_buf
;
1832 gen_opc_instr_start
[lj
++] = 0;
1834 tb
->size
= dc
->pc
- pc_start
;
1835 tb
->icount
= num_insns
;
1840 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1843 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
1845 qemu_log("\nisize=%d osize=%td\n",
1846 dc
->pc
- pc_start
, gen_opc_ptr
- gen_opc_buf
);
1850 assert(!dc
->abort_at_next_insn
);
1853 void gen_intermediate_code (CPUMBState
*env
, struct TranslationBlock
*tb
)
1855 gen_intermediate_code_internal(env
, tb
, 0);
1858 void gen_intermediate_code_pc (CPUMBState
*env
, struct TranslationBlock
*tb
)
1860 gen_intermediate_code_internal(env
, tb
, 1);
1863 void cpu_dump_state (CPUMBState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1871 cpu_fprintf(f
, "IN: PC=%x %s\n",
1872 env
->sregs
[SR_PC
], lookup_symbol(env
->sregs
[SR_PC
]));
1873 cpu_fprintf(f
, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1874 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
1875 env
->debug
, env
->imm
, env
->iflags
, env
->sregs
[SR_FSR
]);
1876 cpu_fprintf(f
, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1877 env
->btaken
, env
->btarget
,
1878 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
1879 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
1880 (env
->sregs
[SR_MSR
] & MSR_EIP
),
1881 (env
->sregs
[SR_MSR
] & MSR_IE
));
1883 for (i
= 0; i
< 32; i
++) {
1884 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1885 if ((i
+ 1) % 4 == 0)
1886 cpu_fprintf(f
, "\n");
1888 cpu_fprintf(f
, "\n\n");
1891 CPUMBState
*cpu_mb_init (const char *cpu_model
)
1894 static int tcg_initialized
= 0;
1897 env
= g_malloc0(sizeof(CPUMBState
));
1900 cpu_state_reset(env
);
1901 qemu_init_vcpu(env
);
1902 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
1904 if (tcg_initialized
)
1907 tcg_initialized
= 1;
1909 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1911 env_debug
= tcg_global_mem_new(TCG_AREG0
,
1912 offsetof(CPUMBState
, debug
),
1914 env_iflags
= tcg_global_mem_new(TCG_AREG0
,
1915 offsetof(CPUMBState
, iflags
),
1917 env_imm
= tcg_global_mem_new(TCG_AREG0
,
1918 offsetof(CPUMBState
, imm
),
1920 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
1921 offsetof(CPUMBState
, btarget
),
1923 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
1924 offsetof(CPUMBState
, btaken
),
1926 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
1927 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
1928 offsetof(CPUMBState
, regs
[i
]),
1931 for (i
= 0; i
< ARRAY_SIZE(cpu_SR
); i
++) {
1932 cpu_SR
[i
] = tcg_global_mem_new(TCG_AREG0
,
1933 offsetof(CPUMBState
, sregs
[i
]),
1934 special_regnames
[i
]);
1936 #define GEN_HELPER 2
1942 void cpu_state_reset(CPUMBState
*env
)
1944 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1945 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1946 log_cpu_state(env
, 0);
1949 memset(env
, 0, offsetof(CPUMBState
, breakpoints
));
1952 /* Disable stack protector. */
1955 env
->pvr
.regs
[0] = PVR0_PVR_FULL_MASK \
1956 | PVR0_USE_BARREL_MASK \
1957 | PVR0_USE_DIV_MASK \
1958 | PVR0_USE_HW_MUL_MASK \
1959 | PVR0_USE_EXC_MASK \
1960 | PVR0_USE_ICACHE_MASK \
1961 | PVR0_USE_DCACHE_MASK \
1964 env
->pvr
.regs
[2] = PVR2_D_OPB_MASK \
1968 | PVR2_USE_MSR_INSTR \
1969 | PVR2_USE_PCMP_INSTR \
1970 | PVR2_USE_BARREL_MASK \
1971 | PVR2_USE_DIV_MASK \
1972 | PVR2_USE_HW_MUL_MASK \
1973 | PVR2_USE_MUL64_MASK \
1974 | PVR2_USE_FPU_MASK \
1975 | PVR2_USE_FPU2_MASK \
1976 | PVR2_FPU_EXC_MASK \
1978 env
->pvr
.regs
[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
1979 env
->pvr
.regs
[11] = PVR11_USE_MMU
| (16 << 17);
1981 #if defined(CONFIG_USER_ONLY)
1982 /* start in user mode with interrupts enabled. */
1983 env
->sregs
[SR_MSR
] = MSR_EE
| MSR_IE
| MSR_VM
| MSR_UM
;
1984 env
->pvr
.regs
[10] = 0x0c000000; /* Spartan 3a dsp. */
1986 env
->sregs
[SR_MSR
] = 0;
1987 mmu_init(&env
->mmu
);
1989 env
->mmu
.c_mmu_tlb_access
= 3;
1990 env
->mmu
.c_mmu_zones
= 16;
1994 void restore_state_to_opc(CPUMBState
*env
, TranslationBlock
*tb
, int pc_pos
)
1996 env
->sregs
[SR_PC
] = gen_opc_pc
[pc_pos
];