2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "disas/disas.h"
25 #include "microblaze-decode.h"
33 #if DISAS_MB && !SIM_COMPAT
34 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
36 # define LOG_DIS(...) do { } while (0)
41 #define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
44 static TCGv env_debug
;
45 static TCGv_ptr cpu_env
;
46 static TCGv cpu_R
[32];
47 static TCGv cpu_SR
[18];
49 static TCGv env_btaken
;
50 static TCGv env_btarget
;
51 static TCGv env_iflags
;
52 static TCGv env_res_addr
;
54 #include "exec/gen-icount.h"
56 /* This is the state at translation time. */
57 typedef struct DisasContext
{
68 unsigned int cpustate_changed
;
69 unsigned int delayed_branch
;
70 unsigned int tb_flags
, synced_flags
; /* tb dependent flags. */
71 unsigned int clear_imm
;
76 #define JMP_DIRECT_CC 2
77 #define JMP_INDIRECT 3
81 int abort_at_next_insn
;
83 struct TranslationBlock
*tb
;
84 int singlestep_enabled
;
87 static const char *regnames
[] =
89 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
90 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
91 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
92 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
95 static const char *special_regnames
[] =
97 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
98 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
99 "sr16", "sr17", "sr18"
102 /* Sign extend at translation time. */
103 static inline int sign_extend(unsigned int val
, unsigned int width
)
115 static inline void t_sync_flags(DisasContext
*dc
)
117 /* Synch the tb dependent flags between translator and runtime. */
118 if (dc
->tb_flags
!= dc
->synced_flags
) {
119 tcg_gen_movi_tl(env_iflags
, dc
->tb_flags
);
120 dc
->synced_flags
= dc
->tb_flags
;
124 static inline void t_gen_raise_exception(DisasContext
*dc
, uint32_t index
)
126 TCGv_i32 tmp
= tcg_const_i32(index
);
129 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
130 gen_helper_raise_exception(cpu_env
, tmp
);
131 tcg_temp_free_i32(tmp
);
132 dc
->is_jmp
= DISAS_UPDATE
;
135 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
137 TranslationBlock
*tb
;
139 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
141 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
142 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
144 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dest
);
149 static void read_carry(DisasContext
*dc
, TCGv d
)
151 tcg_gen_shri_tl(d
, cpu_SR
[SR_MSR
], 31);
155 * write_carry sets the carry bits in MSR based on bit 0 of v.
156 * v[31:1] are ignored.
158 static void write_carry(DisasContext
*dc
, TCGv v
)
160 TCGv t0
= tcg_temp_new();
161 tcg_gen_shli_tl(t0
, v
, 31);
162 tcg_gen_sari_tl(t0
, t0
, 31);
163 tcg_gen_andi_tl(t0
, t0
, (MSR_C
| MSR_CC
));
164 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
],
166 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], t0
);
170 static void write_carryi(DisasContext
*dc
, bool carry
)
172 TCGv t0
= tcg_temp_new();
173 tcg_gen_movi_tl(t0
, carry
);
178 /* True if ALU operand b is a small immediate that may deserve
180 static inline int dec_alu_op_b_is_small_imm(DisasContext
*dc
)
182 /* Immediate insn without the imm prefix ? */
183 return dc
->type_b
&& !(dc
->tb_flags
& IMM_FLAG
);
186 static inline TCGv
*dec_alu_op_b(DisasContext
*dc
)
189 if (dc
->tb_flags
& IMM_FLAG
)
190 tcg_gen_ori_tl(env_imm
, env_imm
, dc
->imm
);
192 tcg_gen_movi_tl(env_imm
, (int32_t)((int16_t)dc
->imm
));
195 return &cpu_R
[dc
->rb
];
198 static void dec_add(DisasContext
*dc
)
206 LOG_DIS("add%s%s%s r%d r%d r%d\n",
207 dc
->type_b
? "i" : "", k
? "k" : "", c
? "c" : "",
208 dc
->rd
, dc
->ra
, dc
->rb
);
210 /* Take care of the easy cases first. */
212 /* k - keep carry, no need to update MSR. */
213 /* If rd == r0, it's a nop. */
215 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
218 /* c - Add carry into the result. */
222 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
229 /* From now on, we can assume k is zero. So we need to update MSR. */
235 tcg_gen_movi_tl(cf
, 0);
239 TCGv ncf
= tcg_temp_new();
240 gen_helper_carry(ncf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
241 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
242 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
243 write_carry(dc
, ncf
);
246 gen_helper_carry(cf
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)), cf
);
252 static void dec_sub(DisasContext
*dc
)
254 unsigned int u
, cmp
, k
, c
;
260 cmp
= (dc
->imm
& 1) && (!dc
->type_b
) && k
;
263 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u
? "u" : "", dc
->rd
, dc
->ra
, dc
->ir
);
266 gen_helper_cmpu(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
268 gen_helper_cmp(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
273 LOG_DIS("sub%s%s r%d, r%d r%d\n",
274 k
? "k" : "", c
? "c" : "", dc
->rd
, dc
->ra
, dc
->rb
);
276 /* Take care of the easy cases first. */
278 /* k - keep carry, no need to update MSR. */
279 /* If rd == r0, it's a nop. */
281 tcg_gen_sub_tl(cpu_R
[dc
->rd
], *(dec_alu_op_b(dc
)), cpu_R
[dc
->ra
]);
284 /* c - Add carry into the result. */
288 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
295 /* From now on, we can assume k is zero. So we need to update MSR. */
296 /* Extract carry. And complement a into na. */
302 tcg_gen_movi_tl(cf
, 1);
305 /* d = b + ~a + c. carry defaults to 1. */
306 tcg_gen_not_tl(na
, cpu_R
[dc
->ra
]);
309 TCGv ncf
= tcg_temp_new();
310 gen_helper_carry(ncf
, na
, *(dec_alu_op_b(dc
)), cf
);
311 tcg_gen_add_tl(cpu_R
[dc
->rd
], na
, *(dec_alu_op_b(dc
)));
312 tcg_gen_add_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], cf
);
313 write_carry(dc
, ncf
);
316 gen_helper_carry(cf
, na
, *(dec_alu_op_b(dc
)), cf
);
323 static void dec_pattern(DisasContext
*dc
)
328 if ((dc
->tb_flags
& MSR_EE_FLAG
)
329 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
330 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
331 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
332 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
335 mode
= dc
->opcode
& 3;
339 LOG_DIS("pcmpbf r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
341 gen_helper_pcmpbf(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
344 LOG_DIS("pcmpeq r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
346 TCGv t0
= tcg_temp_local_new();
347 l1
= gen_new_label();
348 tcg_gen_movi_tl(t0
, 1);
349 tcg_gen_brcond_tl(TCG_COND_EQ
,
350 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
351 tcg_gen_movi_tl(t0
, 0);
353 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
358 LOG_DIS("pcmpne r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
359 l1
= gen_new_label();
361 TCGv t0
= tcg_temp_local_new();
362 tcg_gen_movi_tl(t0
, 1);
363 tcg_gen_brcond_tl(TCG_COND_NE
,
364 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
], l1
);
365 tcg_gen_movi_tl(t0
, 0);
367 tcg_gen_mov_tl(cpu_R
[dc
->rd
], t0
);
373 "unsupported pattern insn opcode=%x\n", dc
->opcode
);
378 static void dec_and(DisasContext
*dc
)
382 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
387 not = dc
->opcode
& (1 << 1);
388 LOG_DIS("and%s\n", not ? "n" : "");
394 tcg_gen_andc_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
396 tcg_gen_and_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
399 static void dec_or(DisasContext
*dc
)
401 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
406 LOG_DIS("or r%d r%d r%d imm=%x\n", dc
->rd
, dc
->ra
, dc
->rb
, dc
->imm
);
408 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
411 static void dec_xor(DisasContext
*dc
)
413 if (!dc
->type_b
&& (dc
->imm
& (1 << 10))) {
418 LOG_DIS("xor r%d\n", dc
->rd
);
420 tcg_gen_xor_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
423 static inline void msr_read(DisasContext
*dc
, TCGv d
)
425 tcg_gen_mov_tl(d
, cpu_SR
[SR_MSR
]);
428 static inline void msr_write(DisasContext
*dc
, TCGv v
)
433 dc
->cpustate_changed
= 1;
434 /* PVR bit is not writable. */
435 tcg_gen_andi_tl(t
, v
, ~MSR_PVR
);
436 tcg_gen_andi_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], MSR_PVR
);
437 tcg_gen_or_tl(cpu_SR
[SR_MSR
], cpu_SR
[SR_MSR
], v
);
441 static void dec_msr(DisasContext
*dc
)
444 unsigned int sr
, to
, rn
;
445 int mem_index
= cpu_mmu_index(dc
->env
);
447 sr
= dc
->imm
& ((1 << 14) - 1);
448 to
= dc
->imm
& (1 << 14);
451 dc
->cpustate_changed
= 1;
453 /* msrclr and msrset. */
454 if (!(dc
->imm
& (1 << 15))) {
455 unsigned int clr
= dc
->ir
& (1 << 16);
457 LOG_DIS("msr%s r%d imm=%x\n", clr
? "clr" : "set",
460 if (!(dc
->env
->pvr
.regs
[2] & PVR2_USE_MSR_INSTR
)) {
465 if ((dc
->tb_flags
& MSR_EE_FLAG
)
466 && mem_index
== MMU_USER_IDX
&& (dc
->imm
!= 4 && dc
->imm
!= 0)) {
467 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
468 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
473 msr_read(dc
, cpu_R
[dc
->rd
]);
478 tcg_gen_mov_tl(t1
, *(dec_alu_op_b(dc
)));
481 tcg_gen_not_tl(t1
, t1
);
482 tcg_gen_and_tl(t0
, t0
, t1
);
484 tcg_gen_or_tl(t0
, t0
, t1
);
488 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
489 dc
->is_jmp
= DISAS_UPDATE
;
494 if ((dc
->tb_flags
& MSR_EE_FLAG
)
495 && mem_index
== MMU_USER_IDX
) {
496 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
497 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
502 #if !defined(CONFIG_USER_ONLY)
503 /* Catch read/writes to the mmu block. */
504 if ((sr
& ~0xff) == 0x1000) {
506 LOG_DIS("m%ss sr%d r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
508 gen_helper_mmu_write(cpu_env
, tcg_const_tl(sr
), cpu_R
[dc
->ra
]);
510 gen_helper_mmu_read(cpu_R
[dc
->rd
], cpu_env
, tcg_const_tl(sr
));
516 LOG_DIS("m%ss sr%x r%d imm=%x\n", to
? "t" : "f", sr
, dc
->ra
, dc
->imm
);
521 msr_write(dc
, cpu_R
[dc
->ra
]);
524 tcg_gen_mov_tl(cpu_SR
[SR_EAR
], cpu_R
[dc
->ra
]);
527 tcg_gen_mov_tl(cpu_SR
[SR_ESR
], cpu_R
[dc
->ra
]);
530 tcg_gen_andi_tl(cpu_SR
[SR_FSR
], cpu_R
[dc
->ra
], 31);
533 tcg_gen_st_tl(cpu_R
[dc
->ra
], cpu_env
, offsetof(CPUMBState
, slr
));
536 tcg_gen_st_tl(cpu_R
[dc
->ra
], cpu_env
, offsetof(CPUMBState
, shr
));
539 cpu_abort(dc
->env
, "unknown mts reg %x\n", sr
);
543 LOG_DIS("m%ss r%d sr%x imm=%x\n", to
? "t" : "f", dc
->rd
, sr
, dc
->imm
);
547 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
550 msr_read(dc
, cpu_R
[dc
->rd
]);
553 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_EAR
]);
556 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_ESR
]);
559 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_FSR
]);
562 tcg_gen_mov_tl(cpu_R
[dc
->rd
], cpu_SR
[SR_BTR
]);
565 tcg_gen_ld_tl(cpu_R
[dc
->rd
], cpu_env
, offsetof(CPUMBState
, slr
));
568 tcg_gen_ld_tl(cpu_R
[dc
->rd
], cpu_env
, offsetof(CPUMBState
, shr
));
584 tcg_gen_ld_tl(cpu_R
[dc
->rd
],
585 cpu_env
, offsetof(CPUMBState
, pvr
.regs
[rn
]));
588 cpu_abort(dc
->env
, "unknown mfs reg %x\n", sr
);
594 tcg_gen_movi_tl(cpu_R
[0], 0);
598 /* 64-bit signed mul, lower result in d and upper in d2. */
599 static void t_gen_muls(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
603 t0
= tcg_temp_new_i64();
604 t1
= tcg_temp_new_i64();
606 tcg_gen_ext_i32_i64(t0
, a
);
607 tcg_gen_ext_i32_i64(t1
, b
);
608 tcg_gen_mul_i64(t0
, t0
, t1
);
610 tcg_gen_trunc_i64_i32(d
, t0
);
611 tcg_gen_shri_i64(t0
, t0
, 32);
612 tcg_gen_trunc_i64_i32(d2
, t0
);
614 tcg_temp_free_i64(t0
);
615 tcg_temp_free_i64(t1
);
618 /* 64-bit unsigned muls, lower result in d and upper in d2. */
619 static void t_gen_mulu(TCGv d
, TCGv d2
, TCGv a
, TCGv b
)
623 t0
= tcg_temp_new_i64();
624 t1
= tcg_temp_new_i64();
626 tcg_gen_extu_i32_i64(t0
, a
);
627 tcg_gen_extu_i32_i64(t1
, b
);
628 tcg_gen_mul_i64(t0
, t0
, t1
);
630 tcg_gen_trunc_i64_i32(d
, t0
);
631 tcg_gen_shri_i64(t0
, t0
, 32);
632 tcg_gen_trunc_i64_i32(d2
, t0
);
634 tcg_temp_free_i64(t0
);
635 tcg_temp_free_i64(t1
);
638 /* Multiplier unit. */
639 static void dec_mul(DisasContext
*dc
)
642 unsigned int subcode
;
644 if ((dc
->tb_flags
& MSR_EE_FLAG
)
645 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
646 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_HW_MUL_MASK
)) {
647 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
648 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
652 subcode
= dc
->imm
& 3;
653 d
[0] = tcg_temp_new();
654 d
[1] = tcg_temp_new();
657 LOG_DIS("muli r%d r%d %x\n", dc
->rd
, dc
->ra
, dc
->imm
);
658 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
662 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
663 if (subcode
>= 1 && subcode
<= 3
664 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_MUL64_MASK
))) {
670 LOG_DIS("mul r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
671 t_gen_mulu(cpu_R
[dc
->rd
], d
[1], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
674 LOG_DIS("mulh r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
675 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
678 LOG_DIS("mulhsu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
679 t_gen_muls(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
682 LOG_DIS("mulhu r%d r%d r%d\n", dc
->rd
, dc
->ra
, dc
->rb
);
683 t_gen_mulu(d
[0], cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
686 cpu_abort(dc
->env
, "unknown MUL insn %x\n", subcode
);
695 static void dec_div(DisasContext
*dc
)
702 if ((dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
703 && !((dc
->env
->pvr
.regs
[0] & PVR0_USE_DIV_MASK
))) {
704 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
705 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
709 gen_helper_divu(cpu_R
[dc
->rd
], cpu_env
, *(dec_alu_op_b(dc
)),
712 gen_helper_divs(cpu_R
[dc
->rd
], cpu_env
, *(dec_alu_op_b(dc
)),
715 tcg_gen_movi_tl(cpu_R
[dc
->rd
], 0);
718 static void dec_barrel(DisasContext
*dc
)
723 if ((dc
->tb_flags
& MSR_EE_FLAG
)
724 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
725 && !(dc
->env
->pvr
.regs
[0] & PVR0_USE_BARREL_MASK
)) {
726 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
727 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
731 s
= dc
->imm
& (1 << 10);
732 t
= dc
->imm
& (1 << 9);
734 LOG_DIS("bs%s%s r%d r%d r%d\n",
735 s
? "l" : "r", t
? "a" : "l", dc
->rd
, dc
->ra
, dc
->rb
);
739 tcg_gen_mov_tl(t0
, *(dec_alu_op_b(dc
)));
740 tcg_gen_andi_tl(t0
, t0
, 31);
743 tcg_gen_shl_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
746 tcg_gen_sar_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
748 tcg_gen_shr_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], t0
);
752 static void dec_bit(DisasContext
*dc
)
756 int mem_index
= cpu_mmu_index(dc
->env
);
758 op
= dc
->ir
& ((1 << 9) - 1);
764 LOG_DIS("src r%d r%d\n", dc
->rd
, dc
->ra
);
765 tcg_gen_andi_tl(t0
, cpu_SR
[SR_MSR
], MSR_CC
);
766 write_carry(dc
, cpu_R
[dc
->ra
]);
768 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
769 tcg_gen_or_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], t0
);
777 LOG_DIS("srl r%d r%d\n", dc
->rd
, dc
->ra
);
779 /* Update carry. Note that write carry only looks at the LSB. */
780 write_carry(dc
, cpu_R
[dc
->ra
]);
783 tcg_gen_shri_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
785 tcg_gen_sari_tl(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 1);
789 LOG_DIS("ext8s r%d r%d\n", dc
->rd
, dc
->ra
);
790 tcg_gen_ext8s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
793 LOG_DIS("ext16s r%d r%d\n", dc
->rd
, dc
->ra
);
794 tcg_gen_ext16s_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
801 LOG_DIS("wdc r%d\n", dc
->ra
);
802 if ((dc
->tb_flags
& MSR_EE_FLAG
)
803 && mem_index
== MMU_USER_IDX
) {
804 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
805 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
811 LOG_DIS("wic r%d\n", dc
->ra
);
812 if ((dc
->tb_flags
& MSR_EE_FLAG
)
813 && mem_index
== MMU_USER_IDX
) {
814 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
815 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
820 if ((dc
->tb_flags
& MSR_EE_FLAG
)
821 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
822 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
))) {
823 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
824 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
826 if (dc
->env
->pvr
.regs
[2] & PVR2_USE_PCMP_INSTR
) {
827 gen_helper_clz(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
832 LOG_DIS("swapb r%d r%d\n", dc
->rd
, dc
->ra
);
833 tcg_gen_bswap32_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
]);
837 LOG_DIS("swaph r%d r%d\n", dc
->rd
, dc
->ra
);
838 tcg_gen_rotri_i32(cpu_R
[dc
->rd
], cpu_R
[dc
->ra
], 16);
841 cpu_abort(dc
->env
, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
842 dc
->pc
, op
, dc
->rd
, dc
->ra
, dc
->rb
);
847 static inline void sync_jmpstate(DisasContext
*dc
)
849 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
850 if (dc
->jmp
== JMP_DIRECT
) {
851 tcg_gen_movi_tl(env_btaken
, 1);
853 dc
->jmp
= JMP_INDIRECT
;
854 tcg_gen_movi_tl(env_btarget
, dc
->jmp_pc
);
858 static void dec_imm(DisasContext
*dc
)
860 LOG_DIS("imm %x\n", dc
->imm
<< 16);
861 tcg_gen_movi_tl(env_imm
, (dc
->imm
<< 16));
862 dc
->tb_flags
|= IMM_FLAG
;
866 static inline void gen_load(DisasContext
*dc
, TCGv dst
, TCGv addr
,
867 unsigned int size
, bool exclusive
)
869 int mem_index
= cpu_mmu_index(dc
->env
);
872 tcg_gen_qemu_ld8u(dst
, addr
, mem_index
);
873 } else if (size
== 2) {
874 tcg_gen_qemu_ld16u(dst
, addr
, mem_index
);
875 } else if (size
== 4) {
876 tcg_gen_qemu_ld32u(dst
, addr
, mem_index
);
878 cpu_abort(dc
->env
, "Incorrect load size %d\n", size
);
881 tcg_gen_mov_tl(env_res_addr
, addr
);
885 static inline TCGv
*compute_ldst_addr(DisasContext
*dc
, TCGv
*t
)
887 unsigned int extimm
= dc
->tb_flags
& IMM_FLAG
;
888 /* Should be set to one if r1 is used by loadstores. */
891 /* All load/stores use ra. */
896 /* Treat the common cases first. */
898 /* If any of the regs is r0, return a ptr to the other. */
900 return &cpu_R
[dc
->rb
];
901 } else if (dc
->rb
== 0) {
902 return &cpu_R
[dc
->ra
];
910 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
913 gen_helper_stackprot(cpu_env
, *t
);
920 return &cpu_R
[dc
->ra
];
923 tcg_gen_movi_tl(*t
, (int32_t)((int16_t)dc
->imm
));
924 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *t
);
927 tcg_gen_add_tl(*t
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
931 gen_helper_stackprot(cpu_env
, *t
);
936 static inline void dec_byteswap(DisasContext
*dc
, TCGv dst
, TCGv src
, int size
)
939 tcg_gen_bswap32_tl(dst
, src
);
940 } else if (size
== 2) {
941 TCGv t
= tcg_temp_new();
943 /* bswap16 assumes the high bits are zero. */
944 tcg_gen_andi_tl(t
, src
, 0xffff);
945 tcg_gen_bswap16_tl(dst
, t
);
949 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
954 static void dec_load(DisasContext
*dc
)
957 unsigned int size
, rev
= 0, ex
= 0;
959 size
= 1 << (dc
->opcode
& 3);
962 rev
= (dc
->ir
>> 9) & 1;
963 ex
= (dc
->ir
>> 10) & 1;
966 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
967 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
968 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
969 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
973 LOG_DIS("l%d%s%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "",
977 addr
= compute_ldst_addr(dc
, &t
);
980 * When doing reverse accesses we need to do two things.
982 * 1. Reverse the address wrt endianness.
983 * 2. Byteswap the data lanes on the way back into the CPU core.
985 if (rev
&& size
!= 4) {
986 /* Endian reverse the address. t is addr. */
994 TCGv low
= tcg_temp_new();
996 /* Force addr into the temp. */
999 tcg_gen_mov_tl(t
, *addr
);
1003 tcg_gen_andi_tl(low
, t
, 3);
1004 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
1005 tcg_gen_andi_tl(t
, t
, ~3);
1006 tcg_gen_or_tl(t
, t
, low
);
1007 tcg_gen_mov_tl(env_imm
, t
);
1015 /* Force addr into the temp. */
1018 tcg_gen_xori_tl(t
, *addr
, 2);
1021 tcg_gen_xori_tl(t
, t
, 2);
1025 cpu_abort(dc
->env
, "Invalid reverse size\n");
1030 /* lwx does not throw unaligned access errors, so force alignment */
1032 /* Force addr into the temp. */
1035 tcg_gen_mov_tl(t
, *addr
);
1038 tcg_gen_andi_tl(t
, t
, ~3);
1041 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1044 /* Verify alignment if needed. */
1045 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
1046 TCGv v
= tcg_temp_new();
1049 * Microblaze gives MMU faults priority over faults due to
1050 * unaligned addresses. That's why we speculatively do the load
1051 * into v. If the load succeeds, we verify alignment of the
1052 * address and if that succeeds we write into the destination reg.
1054 gen_load(dc
, v
, *addr
, size
, ex
);
1056 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1057 gen_helper_memalign(cpu_env
, *addr
, tcg_const_tl(dc
->rd
),
1058 tcg_const_tl(0), tcg_const_tl(size
- 1));
1061 dec_byteswap(dc
, cpu_R
[dc
->rd
], v
, size
);
1063 tcg_gen_mov_tl(cpu_R
[dc
->rd
], v
);
1069 gen_load(dc
, cpu_R
[dc
->rd
], *addr
, size
, ex
);
1071 dec_byteswap(dc
, cpu_R
[dc
->rd
], cpu_R
[dc
->rd
], size
);
1074 /* We are loading into r0, no need to reverse. */
1075 gen_load(dc
, env_imm
, *addr
, size
, ex
);
1080 /* no support for for AXI exclusive so always clear C */
1081 write_carryi(dc
, 0);
1088 static void gen_store(DisasContext
*dc
, TCGv addr
, TCGv val
,
1091 int mem_index
= cpu_mmu_index(dc
->env
);
1094 tcg_gen_qemu_st8(val
, addr
, mem_index
);
1095 else if (size
== 2) {
1096 tcg_gen_qemu_st16(val
, addr
, mem_index
);
1097 } else if (size
== 4) {
1098 tcg_gen_qemu_st32(val
, addr
, mem_index
);
1100 cpu_abort(dc
->env
, "Incorrect store size %d\n", size
);
1103 static void dec_store(DisasContext
*dc
)
1105 TCGv t
, *addr
, swx_addr
;
1107 unsigned int size
, rev
= 0, ex
= 0;
1109 size
= 1 << (dc
->opcode
& 3);
1111 rev
= (dc
->ir
>> 9) & 1;
1112 ex
= (dc
->ir
>> 10) & 1;
1115 if (size
> 4 && (dc
->tb_flags
& MSR_EE_FLAG
)
1116 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1117 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1118 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1122 LOG_DIS("s%d%s%s%s\n", size
, dc
->type_b
? "i" : "", rev
? "r" : "",
1125 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1127 addr
= compute_ldst_addr(dc
, &t
);
1129 swx_addr
= tcg_temp_local_new();
1132 /* Force addr into the swx_addr. */
1133 tcg_gen_mov_tl(swx_addr
, *addr
);
1135 /* swx does not throw unaligned access errors, so force alignment */
1136 tcg_gen_andi_tl(swx_addr
, swx_addr
, ~3);
1138 write_carryi(dc
, 1);
1139 swx_skip
= gen_new_label();
1140 tcg_gen_brcond_tl(TCG_COND_NE
, env_res_addr
, swx_addr
, swx_skip
);
1141 write_carryi(dc
, 0);
1144 if (rev
&& size
!= 4) {
1145 /* Endian reverse the address. t is addr. */
1153 TCGv low
= tcg_temp_new();
1155 /* Force addr into the temp. */
1158 tcg_gen_mov_tl(t
, *addr
);
1162 tcg_gen_andi_tl(low
, t
, 3);
1163 tcg_gen_sub_tl(low
, tcg_const_tl(3), low
);
1164 tcg_gen_andi_tl(t
, t
, ~3);
1165 tcg_gen_or_tl(t
, t
, low
);
1166 tcg_gen_mov_tl(env_imm
, t
);
1174 /* Force addr into the temp. */
1177 tcg_gen_xori_tl(t
, *addr
, 2);
1180 tcg_gen_xori_tl(t
, t
, 2);
1184 cpu_abort(dc
->env
, "Invalid reverse size\n");
1189 TCGv bs_data
= tcg_temp_new();
1190 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1191 gen_store(dc
, *addr
, bs_data
, size
);
1192 tcg_temp_free(bs_data
);
1194 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1198 TCGv bs_data
= tcg_temp_new();
1199 dec_byteswap(dc
, bs_data
, cpu_R
[dc
->rd
], size
);
1200 gen_store(dc
, *addr
, bs_data
, size
);
1201 tcg_temp_free(bs_data
);
1203 gen_store(dc
, *addr
, cpu_R
[dc
->rd
], size
);
1207 /* Verify alignment if needed. */
1208 if ((dc
->env
->pvr
.regs
[2] & PVR2_UNALIGNED_EXC_MASK
) && size
> 1) {
1209 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1210 /* FIXME: if the alignment is wrong, we should restore the value
1211 * in memory. One possible way to achieve this is to probe
1212 * the MMU prior to the memaccess, thay way we could put
1213 * the alignment checks in between the probe and the mem
1216 gen_helper_memalign(cpu_env
, *addr
, tcg_const_tl(dc
->rd
),
1217 tcg_const_tl(1), tcg_const_tl(size
- 1));
1221 gen_set_label(swx_skip
);
1223 tcg_temp_free(swx_addr
);
1229 static inline void eval_cc(DisasContext
*dc
, unsigned int cc
,
1230 TCGv d
, TCGv a
, TCGv b
)
1234 tcg_gen_setcond_tl(TCG_COND_EQ
, d
, a
, b
);
1237 tcg_gen_setcond_tl(TCG_COND_NE
, d
, a
, b
);
1240 tcg_gen_setcond_tl(TCG_COND_LT
, d
, a
, b
);
1243 tcg_gen_setcond_tl(TCG_COND_LE
, d
, a
, b
);
1246 tcg_gen_setcond_tl(TCG_COND_GE
, d
, a
, b
);
1249 tcg_gen_setcond_tl(TCG_COND_GT
, d
, a
, b
);
1252 cpu_abort(dc
->env
, "Unknown condition code %x.\n", cc
);
1257 static void eval_cond_jmp(DisasContext
*dc
, TCGv pc_true
, TCGv pc_false
)
1261 l1
= gen_new_label();
1262 /* Conditional jmp. */
1263 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_false
);
1264 tcg_gen_brcondi_tl(TCG_COND_EQ
, env_btaken
, 0, l1
);
1265 tcg_gen_mov_tl(cpu_SR
[SR_PC
], pc_true
);
1269 static void dec_bcc(DisasContext
*dc
)
1274 cc
= EXTRACT_FIELD(dc
->ir
, 21, 23);
1275 dslot
= dc
->ir
& (1 << 25);
1276 LOG_DIS("bcc%s r%d %x\n", dslot
? "d" : "", dc
->ra
, dc
->imm
);
1278 dc
->delayed_branch
= 1;
1280 dc
->delayed_branch
= 2;
1281 dc
->tb_flags
|= D_FLAG
;
1282 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1283 cpu_env
, offsetof(CPUMBState
, bimm
));
1286 if (dec_alu_op_b_is_small_imm(dc
)) {
1287 int32_t offset
= (int32_t)((int16_t)dc
->imm
); /* sign-extend. */
1289 tcg_gen_movi_tl(env_btarget
, dc
->pc
+ offset
);
1290 dc
->jmp
= JMP_DIRECT_CC
;
1291 dc
->jmp_pc
= dc
->pc
+ offset
;
1293 dc
->jmp
= JMP_INDIRECT
;
1294 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1295 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1297 eval_cc(dc
, cc
, env_btaken
, cpu_R
[dc
->ra
], tcg_const_tl(0));
1300 static void dec_br(DisasContext
*dc
)
1302 unsigned int dslot
, link
, abs
, mbar
;
1303 int mem_index
= cpu_mmu_index(dc
->env
);
1305 dslot
= dc
->ir
& (1 << 20);
1306 abs
= dc
->ir
& (1 << 19);
1307 link
= dc
->ir
& (1 << 18);
1309 /* Memory barrier. */
1310 mbar
= (dc
->ir
>> 16) & 31;
1311 if (mbar
== 2 && dc
->imm
== 4) {
1312 /* mbar IMM & 16 decodes to sleep. */
1314 TCGv_i32 tmp_hlt
= tcg_const_i32(EXCP_HLT
);
1315 TCGv_i32 tmp_1
= tcg_const_i32(1);
1320 tcg_gen_st_i32(tmp_1
, cpu_env
,
1321 -offsetof(MicroBlazeCPU
, env
)
1322 +offsetof(CPUState
, halted
));
1323 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
+ 4);
1324 gen_helper_raise_exception(cpu_env
, tmp_hlt
);
1325 tcg_temp_free_i32(tmp_hlt
);
1326 tcg_temp_free_i32(tmp_1
);
1329 LOG_DIS("mbar %d\n", dc
->rd
);
1331 dc
->cpustate_changed
= 1;
1335 LOG_DIS("br%s%s%s%s imm=%x\n",
1336 abs
? "a" : "", link
? "l" : "",
1337 dc
->type_b
? "i" : "", dslot
? "d" : "",
1340 dc
->delayed_branch
= 1;
1342 dc
->delayed_branch
= 2;
1343 dc
->tb_flags
|= D_FLAG
;
1344 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1345 cpu_env
, offsetof(CPUMBState
, bimm
));
1348 tcg_gen_movi_tl(cpu_R
[dc
->rd
], dc
->pc
);
1350 dc
->jmp
= JMP_INDIRECT
;
1352 tcg_gen_movi_tl(env_btaken
, 1);
1353 tcg_gen_mov_tl(env_btarget
, *(dec_alu_op_b(dc
)));
1354 if (link
&& !dslot
) {
1355 if (!(dc
->tb_flags
& IMM_FLAG
) && (dc
->imm
== 8 || dc
->imm
== 0x18))
1356 t_gen_raise_exception(dc
, EXCP_BREAK
);
1358 if ((dc
->tb_flags
& MSR_EE_FLAG
) && mem_index
== MMU_USER_IDX
) {
1359 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1360 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1364 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1368 if (dec_alu_op_b_is_small_imm(dc
)) {
1369 dc
->jmp
= JMP_DIRECT
;
1370 dc
->jmp_pc
= dc
->pc
+ (int32_t)((int16_t)dc
->imm
);
1372 tcg_gen_movi_tl(env_btaken
, 1);
1373 tcg_gen_movi_tl(env_btarget
, dc
->pc
);
1374 tcg_gen_add_tl(env_btarget
, env_btarget
, *(dec_alu_op_b(dc
)));
1379 static inline void do_rti(DisasContext
*dc
)
1382 t0
= tcg_temp_new();
1383 t1
= tcg_temp_new();
1384 tcg_gen_shri_tl(t0
, cpu_SR
[SR_MSR
], 1);
1385 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_IE
);
1386 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1388 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1389 tcg_gen_or_tl(t1
, t1
, t0
);
1393 dc
->tb_flags
&= ~DRTI_FLAG
;
1396 static inline void do_rtb(DisasContext
*dc
)
1399 t0
= tcg_temp_new();
1400 t1
= tcg_temp_new();
1401 tcg_gen_andi_tl(t1
, cpu_SR
[SR_MSR
], ~MSR_BIP
);
1402 tcg_gen_shri_tl(t0
, t1
, 1);
1403 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1405 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1406 tcg_gen_or_tl(t1
, t1
, t0
);
1410 dc
->tb_flags
&= ~DRTB_FLAG
;
1413 static inline void do_rte(DisasContext
*dc
)
1416 t0
= tcg_temp_new();
1417 t1
= tcg_temp_new();
1419 tcg_gen_ori_tl(t1
, cpu_SR
[SR_MSR
], MSR_EE
);
1420 tcg_gen_andi_tl(t1
, t1
, ~MSR_EIP
);
1421 tcg_gen_shri_tl(t0
, t1
, 1);
1422 tcg_gen_andi_tl(t0
, t0
, (MSR_VM
| MSR_UM
));
1424 tcg_gen_andi_tl(t1
, t1
, ~(MSR_VM
| MSR_UM
));
1425 tcg_gen_or_tl(t1
, t1
, t0
);
1429 dc
->tb_flags
&= ~DRTE_FLAG
;
1432 static void dec_rts(DisasContext
*dc
)
1434 unsigned int b_bit
, i_bit
, e_bit
;
1435 int mem_index
= cpu_mmu_index(dc
->env
);
1437 i_bit
= dc
->ir
& (1 << 21);
1438 b_bit
= dc
->ir
& (1 << 22);
1439 e_bit
= dc
->ir
& (1 << 23);
1441 dc
->delayed_branch
= 2;
1442 dc
->tb_flags
|= D_FLAG
;
1443 tcg_gen_st_tl(tcg_const_tl(dc
->type_b
&& (dc
->tb_flags
& IMM_FLAG
)),
1444 cpu_env
, offsetof(CPUMBState
, bimm
));
1447 LOG_DIS("rtid ir=%x\n", dc
->ir
);
1448 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1449 && mem_index
== MMU_USER_IDX
) {
1450 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1451 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1453 dc
->tb_flags
|= DRTI_FLAG
;
1455 LOG_DIS("rtbd ir=%x\n", dc
->ir
);
1456 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1457 && mem_index
== MMU_USER_IDX
) {
1458 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1459 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1461 dc
->tb_flags
|= DRTB_FLAG
;
1463 LOG_DIS("rted ir=%x\n", dc
->ir
);
1464 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1465 && mem_index
== MMU_USER_IDX
) {
1466 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1467 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1469 dc
->tb_flags
|= DRTE_FLAG
;
1471 LOG_DIS("rts ir=%x\n", dc
->ir
);
1473 dc
->jmp
= JMP_INDIRECT
;
1474 tcg_gen_movi_tl(env_btaken
, 1);
1475 tcg_gen_add_tl(env_btarget
, cpu_R
[dc
->ra
], *(dec_alu_op_b(dc
)));
1478 static int dec_check_fpuv2(DisasContext
*dc
)
1482 r
= dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU2_MASK
;
1484 if (!r
&& (dc
->tb_flags
& MSR_EE_FLAG
)) {
1485 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_FPU
);
1486 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1491 static void dec_fpu(DisasContext
*dc
)
1493 unsigned int fpu_insn
;
1495 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1496 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1497 && !((dc
->env
->pvr
.regs
[2] & PVR2_USE_FPU_MASK
))) {
1498 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1499 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1503 fpu_insn
= (dc
->ir
>> 7) & 7;
1507 gen_helper_fadd(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
],
1512 gen_helper_frsub(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
],
1517 gen_helper_fmul(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
],
1522 gen_helper_fdiv(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
],
1527 switch ((dc
->ir
>> 4) & 7) {
1529 gen_helper_fcmp_un(cpu_R
[dc
->rd
], cpu_env
,
1530 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1533 gen_helper_fcmp_lt(cpu_R
[dc
->rd
], cpu_env
,
1534 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1537 gen_helper_fcmp_eq(cpu_R
[dc
->rd
], cpu_env
,
1538 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1541 gen_helper_fcmp_le(cpu_R
[dc
->rd
], cpu_env
,
1542 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1545 gen_helper_fcmp_gt(cpu_R
[dc
->rd
], cpu_env
,
1546 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1549 gen_helper_fcmp_ne(cpu_R
[dc
->rd
], cpu_env
,
1550 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1553 gen_helper_fcmp_ge(cpu_R
[dc
->rd
], cpu_env
,
1554 cpu_R
[dc
->ra
], cpu_R
[dc
->rb
]);
1557 qemu_log_mask(LOG_UNIMP
,
1558 "unimplemented fcmp fpu_insn=%x pc=%x"
1560 fpu_insn
, dc
->pc
, dc
->opcode
);
1561 dc
->abort_at_next_insn
= 1;
1567 if (!dec_check_fpuv2(dc
)) {
1570 gen_helper_flt(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
]);
1574 if (!dec_check_fpuv2(dc
)) {
1577 gen_helper_fint(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
]);
1581 if (!dec_check_fpuv2(dc
)) {
1584 gen_helper_fsqrt(cpu_R
[dc
->rd
], cpu_env
, cpu_R
[dc
->ra
]);
1588 qemu_log_mask(LOG_UNIMP
, "unimplemented FPU insn fpu_insn=%x pc=%x"
1590 fpu_insn
, dc
->pc
, dc
->opcode
);
1591 dc
->abort_at_next_insn
= 1;
1596 static void dec_null(DisasContext
*dc
)
1598 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1599 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)) {
1600 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1601 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1604 qemu_log ("unknown insn pc=%x opc=%x\n", dc
->pc
, dc
->opcode
);
1605 dc
->abort_at_next_insn
= 1;
1608 /* Insns connected to FSL or AXI stream attached devices. */
1609 static void dec_stream(DisasContext
*dc
)
1611 int mem_index
= cpu_mmu_index(dc
->env
);
1612 TCGv_i32 t_id
, t_ctrl
;
1615 LOG_DIS("%s%s imm=%x\n", dc
->rd
? "get" : "put",
1616 dc
->type_b
? "" : "d", dc
->imm
);
1618 if ((dc
->tb_flags
& MSR_EE_FLAG
) && (mem_index
== MMU_USER_IDX
)) {
1619 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_PRIVINSN
);
1620 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1624 t_id
= tcg_temp_new();
1626 tcg_gen_movi_tl(t_id
, dc
->imm
& 0xf);
1627 ctrl
= dc
->imm
>> 10;
1629 tcg_gen_andi_tl(t_id
, cpu_R
[dc
->rb
], 0xf);
1630 ctrl
= dc
->imm
>> 5;
1633 t_ctrl
= tcg_const_tl(ctrl
);
1636 gen_helper_put(t_id
, t_ctrl
, cpu_R
[dc
->ra
]);
1638 gen_helper_get(cpu_R
[dc
->rd
], t_id
, t_ctrl
);
1640 tcg_temp_free(t_id
);
1641 tcg_temp_free(t_ctrl
);
1644 static struct decoder_info
{
1649 void (*dec
)(DisasContext
*dc
);
1657 {DEC_BARREL
, dec_barrel
},
1659 {DEC_ST
, dec_store
},
1668 {DEC_STREAM
, dec_stream
},
1672 static inline void decode(DisasContext
*dc
, uint32_t ir
)
1676 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
1677 tcg_gen_debug_insn_start(dc
->pc
);
1681 LOG_DIS("%8.8x\t", dc
->ir
);
1686 if ((dc
->tb_flags
& MSR_EE_FLAG
)
1687 && (dc
->env
->pvr
.regs
[2] & PVR2_ILL_OPCODE_EXC_MASK
)
1688 && (dc
->env
->pvr
.regs
[2] & PVR2_OPCODE_0x0_ILL_MASK
)) {
1689 tcg_gen_movi_tl(cpu_SR
[SR_ESR
], ESR_EC_ILLEGAL_OP
);
1690 t_gen_raise_exception(dc
, EXCP_HW_EXCP
);
1694 LOG_DIS("nr_nops=%d\t", dc
->nr_nops
);
1696 if (dc
->nr_nops
> 4)
1697 cpu_abort(dc
->env
, "fetching nop sequence\n");
1699 /* bit 2 seems to indicate insn type. */
1700 dc
->type_b
= ir
& (1 << 29);
1702 dc
->opcode
= EXTRACT_FIELD(ir
, 26, 31);
1703 dc
->rd
= EXTRACT_FIELD(ir
, 21, 25);
1704 dc
->ra
= EXTRACT_FIELD(ir
, 16, 20);
1705 dc
->rb
= EXTRACT_FIELD(ir
, 11, 15);
1706 dc
->imm
= EXTRACT_FIELD(ir
, 0, 15);
1708 /* Large switch for all insns. */
1709 for (i
= 0; i
< ARRAY_SIZE(decinfo
); i
++) {
1710 if ((dc
->opcode
& decinfo
[i
].mask
) == decinfo
[i
].bits
) {
1717 static void check_breakpoint(CPUMBState
*env
, DisasContext
*dc
)
1721 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1722 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1723 if (bp
->pc
== dc
->pc
) {
1724 t_gen_raise_exception(dc
, EXCP_DEBUG
);
1725 dc
->is_jmp
= DISAS_UPDATE
;
1731 /* generate intermediate code for basic block 'tb'. */
1733 gen_intermediate_code_internal(MicroBlazeCPU
*cpu
, TranslationBlock
*tb
,
1736 CPUState
*cs
= CPU(cpu
);
1737 CPUMBState
*env
= &cpu
->env
;
1738 uint16_t *gen_opc_end
;
1741 struct DisasContext ctx
;
1742 struct DisasContext
*dc
= &ctx
;
1743 uint32_t next_page_start
, org_flags
;
1751 org_flags
= dc
->synced_flags
= dc
->tb_flags
= tb
->flags
;
1753 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
1755 dc
->is_jmp
= DISAS_NEXT
;
1757 dc
->delayed_branch
= !!(dc
->tb_flags
& D_FLAG
);
1758 if (dc
->delayed_branch
) {
1759 dc
->jmp
= JMP_INDIRECT
;
1762 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1763 dc
->cpustate_changed
= 0;
1764 dc
->abort_at_next_insn
= 0;
1768 cpu_abort(env
, "Microblaze: unaligned PC=%x\n", pc_start
);
1770 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1772 qemu_log("--------------\n");
1773 log_cpu_state(CPU(cpu
), 0);
1777 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1780 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1782 max_insns
= CF_COUNT_MASK
;
1788 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1789 tcg_gen_movi_tl(cpu_SR
[SR_PC
], dc
->pc
);
1793 check_breakpoint(env
, dc
);
1796 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
1800 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
1802 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
1803 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
1804 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
1808 LOG_DIS("%8.8x:\t", dc
->pc
);
1810 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
1814 decode(dc
, cpu_ldl_code(env
, dc
->pc
));
1816 dc
->tb_flags
&= ~IMM_FLAG
;
1820 if (dc
->delayed_branch
) {
1821 dc
->delayed_branch
--;
1822 if (!dc
->delayed_branch
) {
1823 if (dc
->tb_flags
& DRTI_FLAG
)
1825 if (dc
->tb_flags
& DRTB_FLAG
)
1827 if (dc
->tb_flags
& DRTE_FLAG
)
1829 /* Clear the delay slot flag. */
1830 dc
->tb_flags
&= ~D_FLAG
;
1831 /* If it is a direct jump, try direct chaining. */
1832 if (dc
->jmp
== JMP_INDIRECT
) {
1833 eval_cond_jmp(dc
, env_btarget
, tcg_const_tl(dc
->pc
));
1834 dc
->is_jmp
= DISAS_JUMP
;
1835 } else if (dc
->jmp
== JMP_DIRECT
) {
1837 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1838 dc
->is_jmp
= DISAS_TB_JUMP
;
1839 } else if (dc
->jmp
== JMP_DIRECT_CC
) {
1843 l1
= gen_new_label();
1844 /* Conditional jmp. */
1845 tcg_gen_brcondi_tl(TCG_COND_NE
, env_btaken
, 0, l1
);
1846 gen_goto_tb(dc
, 1, dc
->pc
);
1848 gen_goto_tb(dc
, 0, dc
->jmp_pc
);
1850 dc
->is_jmp
= DISAS_TB_JUMP
;
1855 if (cs
->singlestep_enabled
) {
1858 } while (!dc
->is_jmp
&& !dc
->cpustate_changed
1859 && tcg_ctx
.gen_opc_ptr
< gen_opc_end
1861 && (dc
->pc
< next_page_start
)
1862 && num_insns
< max_insns
);
1865 if (dc
->jmp
== JMP_DIRECT
|| dc
->jmp
== JMP_DIRECT_CC
) {
1866 if (dc
->tb_flags
& D_FLAG
) {
1867 dc
->is_jmp
= DISAS_UPDATE
;
1868 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1874 if (tb
->cflags
& CF_LAST_IO
)
1876 /* Force an update if the per-tb cpu state has changed. */
1877 if (dc
->is_jmp
== DISAS_NEXT
1878 && (dc
->cpustate_changed
|| org_flags
!= dc
->tb_flags
)) {
1879 dc
->is_jmp
= DISAS_UPDATE
;
1880 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1884 if (unlikely(cs
->singlestep_enabled
)) {
1885 TCGv_i32 tmp
= tcg_const_i32(EXCP_DEBUG
);
1887 if (dc
->is_jmp
!= DISAS_JUMP
) {
1888 tcg_gen_movi_tl(cpu_SR
[SR_PC
], npc
);
1890 gen_helper_raise_exception(cpu_env
, tmp
);
1891 tcg_temp_free_i32(tmp
);
1893 switch(dc
->is_jmp
) {
1895 gen_goto_tb(dc
, 1, npc
);
1900 /* indicate that the hash table must be used
1901 to find the next TB */
1905 /* nothing more to generate */
1909 gen_tb_end(tb
, num_insns
);
1910 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
1912 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
1915 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
1917 tb
->size
= dc
->pc
- pc_start
;
1918 tb
->icount
= num_insns
;
1923 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
1926 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
, 0);
1928 qemu_log("\nisize=%d osize=%td\n",
1929 dc
->pc
- pc_start
, tcg_ctx
.gen_opc_ptr
-
1930 tcg_ctx
.gen_opc_buf
);
1934 assert(!dc
->abort_at_next_insn
);
1937 void gen_intermediate_code (CPUMBState
*env
, struct TranslationBlock
*tb
)
1939 gen_intermediate_code_internal(mb_env_get_cpu(env
), tb
, false);
1942 void gen_intermediate_code_pc (CPUMBState
*env
, struct TranslationBlock
*tb
)
1944 gen_intermediate_code_internal(mb_env_get_cpu(env
), tb
, true);
1947 void mb_cpu_dump_state(CPUState
*cs
, FILE *f
, fprintf_function cpu_fprintf
,
1950 MicroBlazeCPU
*cpu
= MICROBLAZE_CPU(cs
);
1951 CPUMBState
*env
= &cpu
->env
;
1957 cpu_fprintf(f
, "IN: PC=%x %s\n",
1958 env
->sregs
[SR_PC
], lookup_symbol(env
->sregs
[SR_PC
]));
1959 cpu_fprintf(f
, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1960 env
->sregs
[SR_MSR
], env
->sregs
[SR_ESR
], env
->sregs
[SR_EAR
],
1961 env
->debug
, env
->imm
, env
->iflags
, env
->sregs
[SR_FSR
]);
1962 cpu_fprintf(f
, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1963 env
->btaken
, env
->btarget
,
1964 (env
->sregs
[SR_MSR
] & MSR_UM
) ? "user" : "kernel",
1965 (env
->sregs
[SR_MSR
] & MSR_UMS
) ? "user" : "kernel",
1966 (env
->sregs
[SR_MSR
] & MSR_EIP
),
1967 (env
->sregs
[SR_MSR
] & MSR_IE
));
1969 for (i
= 0; i
< 32; i
++) {
1970 cpu_fprintf(f
, "r%2.2d=%8.8x ", i
, env
->regs
[i
]);
1971 if ((i
+ 1) % 4 == 0)
1972 cpu_fprintf(f
, "\n");
1974 cpu_fprintf(f
, "\n\n");
1977 MicroBlazeCPU
*cpu_mb_init(const char *cpu_model
)
1981 cpu
= MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU
));
1983 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
1988 void mb_tcg_init(void)
1992 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
1994 env_debug
= tcg_global_mem_new(TCG_AREG0
,
1995 offsetof(CPUMBState
, debug
),
1997 env_iflags
= tcg_global_mem_new(TCG_AREG0
,
1998 offsetof(CPUMBState
, iflags
),
2000 env_imm
= tcg_global_mem_new(TCG_AREG0
,
2001 offsetof(CPUMBState
, imm
),
2003 env_btarget
= tcg_global_mem_new(TCG_AREG0
,
2004 offsetof(CPUMBState
, btarget
),
2006 env_btaken
= tcg_global_mem_new(TCG_AREG0
,
2007 offsetof(CPUMBState
, btaken
),
2009 env_res_addr
= tcg_global_mem_new(TCG_AREG0
,
2010 offsetof(CPUMBState
, res_addr
),
2012 for (i
= 0; i
< ARRAY_SIZE(cpu_R
); i
++) {
2013 cpu_R
[i
] = tcg_global_mem_new(TCG_AREG0
,
2014 offsetof(CPUMBState
, regs
[i
]),
2017 for (i
= 0; i
< ARRAY_SIZE(cpu_SR
); i
++) {
2018 cpu_SR
[i
] = tcg_global_mem_new(TCG_AREG0
,
2019 offsetof(CPUMBState
, sregs
[i
]),
2020 special_regnames
[i
]);
2024 void restore_state_to_opc(CPUMBState
*env
, TranslationBlock
*tb
, int pc_pos
)
2026 env
->sregs
[SR_PC
] = tcg_ctx
.gen_opc_pc
[pc_pos
];