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microblaze: Move the saving of the reservation addr into gen_load
[qemu.git] / target-microblaze / translate.c
1 /*
2 * Xilinx MicroBlaze emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "helper.h"
25 #include "microblaze-decode.h"
26
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define SIM_COMPAT 0
31 #define DISAS_GNU 1
32 #define DISAS_MB 1
33 #if DISAS_MB && !SIM_COMPAT
34 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
35 #else
36 # define LOG_DIS(...) do { } while (0)
37 #endif
38
39 #define D(x)
40
41 #define EXTRACT_FIELD(src, start, end) \
42 (((src) >> start) & ((1 << (end - start + 1)) - 1))
43
44 static TCGv env_debug;
45 static TCGv_ptr cpu_env;
46 static TCGv cpu_R[32];
47 static TCGv cpu_SR[18];
48 static TCGv env_imm;
49 static TCGv env_btaken;
50 static TCGv env_btarget;
51 static TCGv env_iflags;
52
53 #include "exec/gen-icount.h"
54
55 /* This is the state at translation time. */
56 typedef struct DisasContext {
57 CPUMBState *env;
58 target_ulong pc;
59
60 /* Decoder. */
61 int type_b;
62 uint32_t ir;
63 uint8_t opcode;
64 uint8_t rd, ra, rb;
65 uint16_t imm;
66
67 unsigned int cpustate_changed;
68 unsigned int delayed_branch;
69 unsigned int tb_flags, synced_flags; /* tb dependent flags. */
70 unsigned int clear_imm;
71 int is_jmp;
72
73 #define JMP_NOJMP 0
74 #define JMP_DIRECT 1
75 #define JMP_DIRECT_CC 2
76 #define JMP_INDIRECT 3
77 unsigned int jmp;
78 uint32_t jmp_pc;
79
80 int abort_at_next_insn;
81 int nr_nops;
82 struct TranslationBlock *tb;
83 int singlestep_enabled;
84 } DisasContext;
85
86 static const char *regnames[] =
87 {
88 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
89 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
90 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
91 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
92 };
93
94 static const char *special_regnames[] =
95 {
96 "rpc", "rmsr", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
97 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
98 "sr16", "sr17", "sr18"
99 };
100
101 /* Sign extend at translation time. */
102 static inline int sign_extend(unsigned int val, unsigned int width)
103 {
104 int sval;
105
106 /* LSL. */
107 val <<= 31 - width;
108 sval = val;
109 /* ASR. */
110 sval >>= 31 - width;
111 return sval;
112 }
113
114 static inline void t_sync_flags(DisasContext *dc)
115 {
116 /* Synch the tb dependent flags between translator and runtime. */
117 if (dc->tb_flags != dc->synced_flags) {
118 tcg_gen_movi_tl(env_iflags, dc->tb_flags);
119 dc->synced_flags = dc->tb_flags;
120 }
121 }
122
123 static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
124 {
125 TCGv_i32 tmp = tcg_const_i32(index);
126
127 t_sync_flags(dc);
128 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
129 gen_helper_raise_exception(cpu_env, tmp);
130 tcg_temp_free_i32(tmp);
131 dc->is_jmp = DISAS_UPDATE;
132 }
133
134 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
135 {
136 TranslationBlock *tb;
137 tb = dc->tb;
138 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
139 tcg_gen_goto_tb(n);
140 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
141 tcg_gen_exit_tb((uintptr_t)tb + n);
142 } else {
143 tcg_gen_movi_tl(cpu_SR[SR_PC], dest);
144 tcg_gen_exit_tb(0);
145 }
146 }
147
148 static void read_carry(DisasContext *dc, TCGv d)
149 {
150 tcg_gen_shri_tl(d, cpu_SR[SR_MSR], 31);
151 }
152
153 /*
154 * write_carry sets the carry bits in MSR based on bit 0 of v.
155 * v[31:1] are ignored.
156 */
157 static void write_carry(DisasContext *dc, TCGv v)
158 {
159 TCGv t0 = tcg_temp_new();
160 tcg_gen_shli_tl(t0, v, 31);
161 tcg_gen_sari_tl(t0, t0, 31);
162 tcg_gen_andi_tl(t0, t0, (MSR_C | MSR_CC));
163 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR],
164 ~(MSR_C | MSR_CC));
165 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0);
166 tcg_temp_free(t0);
167 }
168
169 static void write_carryi(DisasContext *dc, bool carry)
170 {
171 TCGv t0 = tcg_temp_new();
172 tcg_gen_movi_tl(t0, carry);
173 write_carry(dc, t0);
174 tcg_temp_free(t0);
175 }
176
177 /* True if ALU operand b is a small immediate that may deserve
178 faster treatment. */
179 static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
180 {
181 /* Immediate insn without the imm prefix ? */
182 return dc->type_b && !(dc->tb_flags & IMM_FLAG);
183 }
184
185 static inline TCGv *dec_alu_op_b(DisasContext *dc)
186 {
187 if (dc->type_b) {
188 if (dc->tb_flags & IMM_FLAG)
189 tcg_gen_ori_tl(env_imm, env_imm, dc->imm);
190 else
191 tcg_gen_movi_tl(env_imm, (int32_t)((int16_t)dc->imm));
192 return &env_imm;
193 } else
194 return &cpu_R[dc->rb];
195 }
196
197 static void dec_add(DisasContext *dc)
198 {
199 unsigned int k, c;
200 TCGv cf;
201
202 k = dc->opcode & 4;
203 c = dc->opcode & 2;
204
205 LOG_DIS("add%s%s%s r%d r%d r%d\n",
206 dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
207 dc->rd, dc->ra, dc->rb);
208
209 /* Take care of the easy cases first. */
210 if (k) {
211 /* k - keep carry, no need to update MSR. */
212 /* If rd == r0, it's a nop. */
213 if (dc->rd) {
214 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
215
216 if (c) {
217 /* c - Add carry into the result. */
218 cf = tcg_temp_new();
219
220 read_carry(dc, cf);
221 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
222 tcg_temp_free(cf);
223 }
224 }
225 return;
226 }
227
228 /* From now on, we can assume k is zero. So we need to update MSR. */
229 /* Extract carry. */
230 cf = tcg_temp_new();
231 if (c) {
232 read_carry(dc, cf);
233 } else {
234 tcg_gen_movi_tl(cf, 0);
235 }
236
237 if (dc->rd) {
238 TCGv ncf = tcg_temp_new();
239 gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
240 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
241 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
242 write_carry(dc, ncf);
243 tcg_temp_free(ncf);
244 } else {
245 gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
246 write_carry(dc, cf);
247 }
248 tcg_temp_free(cf);
249 }
250
251 static void dec_sub(DisasContext *dc)
252 {
253 unsigned int u, cmp, k, c;
254 TCGv cf, na;
255
256 u = dc->imm & 2;
257 k = dc->opcode & 4;
258 c = dc->opcode & 2;
259 cmp = (dc->imm & 1) && (!dc->type_b) && k;
260
261 if (cmp) {
262 LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
263 if (dc->rd) {
264 if (u)
265 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
266 else
267 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
268 }
269 return;
270 }
271
272 LOG_DIS("sub%s%s r%d, r%d r%d\n",
273 k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb);
274
275 /* Take care of the easy cases first. */
276 if (k) {
277 /* k - keep carry, no need to update MSR. */
278 /* If rd == r0, it's a nop. */
279 if (dc->rd) {
280 tcg_gen_sub_tl(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
281
282 if (c) {
283 /* c - Add carry into the result. */
284 cf = tcg_temp_new();
285
286 read_carry(dc, cf);
287 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
288 tcg_temp_free(cf);
289 }
290 }
291 return;
292 }
293
294 /* From now on, we can assume k is zero. So we need to update MSR. */
295 /* Extract carry. And complement a into na. */
296 cf = tcg_temp_new();
297 na = tcg_temp_new();
298 if (c) {
299 read_carry(dc, cf);
300 } else {
301 tcg_gen_movi_tl(cf, 1);
302 }
303
304 /* d = b + ~a + c. carry defaults to 1. */
305 tcg_gen_not_tl(na, cpu_R[dc->ra]);
306
307 if (dc->rd) {
308 TCGv ncf = tcg_temp_new();
309 gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf);
310 tcg_gen_add_tl(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
311 tcg_gen_add_tl(cpu_R[dc->rd], cpu_R[dc->rd], cf);
312 write_carry(dc, ncf);
313 tcg_temp_free(ncf);
314 } else {
315 gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf);
316 write_carry(dc, cf);
317 }
318 tcg_temp_free(cf);
319 tcg_temp_free(na);
320 }
321
322 static void dec_pattern(DisasContext *dc)
323 {
324 unsigned int mode;
325 int l1;
326
327 if ((dc->tb_flags & MSR_EE_FLAG)
328 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
329 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
330 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
331 t_gen_raise_exception(dc, EXCP_HW_EXCP);
332 }
333
334 mode = dc->opcode & 3;
335 switch (mode) {
336 case 0:
337 /* pcmpbf. */
338 LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
339 if (dc->rd)
340 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
341 break;
342 case 2:
343 LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
344 if (dc->rd) {
345 TCGv t0 = tcg_temp_local_new();
346 l1 = gen_new_label();
347 tcg_gen_movi_tl(t0, 1);
348 tcg_gen_brcond_tl(TCG_COND_EQ,
349 cpu_R[dc->ra], cpu_R[dc->rb], l1);
350 tcg_gen_movi_tl(t0, 0);
351 gen_set_label(l1);
352 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
353 tcg_temp_free(t0);
354 }
355 break;
356 case 3:
357 LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
358 l1 = gen_new_label();
359 if (dc->rd) {
360 TCGv t0 = tcg_temp_local_new();
361 tcg_gen_movi_tl(t0, 1);
362 tcg_gen_brcond_tl(TCG_COND_NE,
363 cpu_R[dc->ra], cpu_R[dc->rb], l1);
364 tcg_gen_movi_tl(t0, 0);
365 gen_set_label(l1);
366 tcg_gen_mov_tl(cpu_R[dc->rd], t0);
367 tcg_temp_free(t0);
368 }
369 break;
370 default:
371 cpu_abort(dc->env,
372 "unsupported pattern insn opcode=%x\n", dc->opcode);
373 break;
374 }
375 }
376
377 static void dec_and(DisasContext *dc)
378 {
379 unsigned int not;
380
381 if (!dc->type_b && (dc->imm & (1 << 10))) {
382 dec_pattern(dc);
383 return;
384 }
385
386 not = dc->opcode & (1 << 1);
387 LOG_DIS("and%s\n", not ? "n" : "");
388
389 if (!dc->rd)
390 return;
391
392 if (not) {
393 tcg_gen_andc_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
394 } else
395 tcg_gen_and_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
396 }
397
398 static void dec_or(DisasContext *dc)
399 {
400 if (!dc->type_b && (dc->imm & (1 << 10))) {
401 dec_pattern(dc);
402 return;
403 }
404
405 LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
406 if (dc->rd)
407 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
408 }
409
410 static void dec_xor(DisasContext *dc)
411 {
412 if (!dc->type_b && (dc->imm & (1 << 10))) {
413 dec_pattern(dc);
414 return;
415 }
416
417 LOG_DIS("xor r%d\n", dc->rd);
418 if (dc->rd)
419 tcg_gen_xor_tl(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
420 }
421
422 static inline void msr_read(DisasContext *dc, TCGv d)
423 {
424 tcg_gen_mov_tl(d, cpu_SR[SR_MSR]);
425 }
426
427 static inline void msr_write(DisasContext *dc, TCGv v)
428 {
429 TCGv t;
430
431 t = tcg_temp_new();
432 dc->cpustate_changed = 1;
433 /* PVR bit is not writable. */
434 tcg_gen_andi_tl(t, v, ~MSR_PVR);
435 tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
436 tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
437 tcg_temp_free(t);
438 }
439
440 static void dec_msr(DisasContext *dc)
441 {
442 TCGv t0, t1;
443 unsigned int sr, to, rn;
444 int mem_index = cpu_mmu_index(dc->env);
445
446 sr = dc->imm & ((1 << 14) - 1);
447 to = dc->imm & (1 << 14);
448 dc->type_b = 1;
449 if (to)
450 dc->cpustate_changed = 1;
451
452 /* msrclr and msrset. */
453 if (!(dc->imm & (1 << 15))) {
454 unsigned int clr = dc->ir & (1 << 16);
455
456 LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
457 dc->rd, dc->imm);
458
459 if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
460 /* nop??? */
461 return;
462 }
463
464 if ((dc->tb_flags & MSR_EE_FLAG)
465 && mem_index == MMU_USER_IDX && (dc->imm != 4 && dc->imm != 0)) {
466 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
467 t_gen_raise_exception(dc, EXCP_HW_EXCP);
468 return;
469 }
470
471 if (dc->rd)
472 msr_read(dc, cpu_R[dc->rd]);
473
474 t0 = tcg_temp_new();
475 t1 = tcg_temp_new();
476 msr_read(dc, t0);
477 tcg_gen_mov_tl(t1, *(dec_alu_op_b(dc)));
478
479 if (clr) {
480 tcg_gen_not_tl(t1, t1);
481 tcg_gen_and_tl(t0, t0, t1);
482 } else
483 tcg_gen_or_tl(t0, t0, t1);
484 msr_write(dc, t0);
485 tcg_temp_free(t0);
486 tcg_temp_free(t1);
487 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
488 dc->is_jmp = DISAS_UPDATE;
489 return;
490 }
491
492 if (to) {
493 if ((dc->tb_flags & MSR_EE_FLAG)
494 && mem_index == MMU_USER_IDX) {
495 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
496 t_gen_raise_exception(dc, EXCP_HW_EXCP);
497 return;
498 }
499 }
500
501 #if !defined(CONFIG_USER_ONLY)
502 /* Catch read/writes to the mmu block. */
503 if ((sr & ~0xff) == 0x1000) {
504 sr &= 7;
505 LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
506 if (to)
507 gen_helper_mmu_write(cpu_env, tcg_const_tl(sr), cpu_R[dc->ra]);
508 else
509 gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tcg_const_tl(sr));
510 return;
511 }
512 #endif
513
514 if (to) {
515 LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
516 switch (sr) {
517 case 0:
518 break;
519 case 1:
520 msr_write(dc, cpu_R[dc->ra]);
521 break;
522 case 0x3:
523 tcg_gen_mov_tl(cpu_SR[SR_EAR], cpu_R[dc->ra]);
524 break;
525 case 0x5:
526 tcg_gen_mov_tl(cpu_SR[SR_ESR], cpu_R[dc->ra]);
527 break;
528 case 0x7:
529 tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
530 break;
531 case 0x800:
532 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, slr));
533 break;
534 case 0x802:
535 tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
536 break;
537 default:
538 cpu_abort(dc->env, "unknown mts reg %x\n", sr);
539 break;
540 }
541 } else {
542 LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
543
544 switch (sr) {
545 case 0:
546 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
547 break;
548 case 1:
549 msr_read(dc, cpu_R[dc->rd]);
550 break;
551 case 0x3:
552 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_EAR]);
553 break;
554 case 0x5:
555 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_ESR]);
556 break;
557 case 0x7:
558 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_FSR]);
559 break;
560 case 0xb:
561 tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]);
562 break;
563 case 0x800:
564 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, slr));
565 break;
566 case 0x802:
567 tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUMBState, shr));
568 break;
569 case 0x2000:
570 case 0x2001:
571 case 0x2002:
572 case 0x2003:
573 case 0x2004:
574 case 0x2005:
575 case 0x2006:
576 case 0x2007:
577 case 0x2008:
578 case 0x2009:
579 case 0x200a:
580 case 0x200b:
581 case 0x200c:
582 rn = sr & 0xf;
583 tcg_gen_ld_tl(cpu_R[dc->rd],
584 cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
585 break;
586 default:
587 cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
588 break;
589 }
590 }
591
592 if (dc->rd == 0) {
593 tcg_gen_movi_tl(cpu_R[0], 0);
594 }
595 }
596
597 /* 64-bit signed mul, lower result in d and upper in d2. */
598 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
599 {
600 TCGv_i64 t0, t1;
601
602 t0 = tcg_temp_new_i64();
603 t1 = tcg_temp_new_i64();
604
605 tcg_gen_ext_i32_i64(t0, a);
606 tcg_gen_ext_i32_i64(t1, b);
607 tcg_gen_mul_i64(t0, t0, t1);
608
609 tcg_gen_trunc_i64_i32(d, t0);
610 tcg_gen_shri_i64(t0, t0, 32);
611 tcg_gen_trunc_i64_i32(d2, t0);
612
613 tcg_temp_free_i64(t0);
614 tcg_temp_free_i64(t1);
615 }
616
617 /* 64-bit unsigned muls, lower result in d and upper in d2. */
618 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
619 {
620 TCGv_i64 t0, t1;
621
622 t0 = tcg_temp_new_i64();
623 t1 = tcg_temp_new_i64();
624
625 tcg_gen_extu_i32_i64(t0, a);
626 tcg_gen_extu_i32_i64(t1, b);
627 tcg_gen_mul_i64(t0, t0, t1);
628
629 tcg_gen_trunc_i64_i32(d, t0);
630 tcg_gen_shri_i64(t0, t0, 32);
631 tcg_gen_trunc_i64_i32(d2, t0);
632
633 tcg_temp_free_i64(t0);
634 tcg_temp_free_i64(t1);
635 }
636
637 /* Multiplier unit. */
638 static void dec_mul(DisasContext *dc)
639 {
640 TCGv d[2];
641 unsigned int subcode;
642
643 if ((dc->tb_flags & MSR_EE_FLAG)
644 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
645 && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
646 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
647 t_gen_raise_exception(dc, EXCP_HW_EXCP);
648 return;
649 }
650
651 subcode = dc->imm & 3;
652 d[0] = tcg_temp_new();
653 d[1] = tcg_temp_new();
654
655 if (dc->type_b) {
656 LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
657 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
658 goto done;
659 }
660
661 /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
662 if (subcode >= 1 && subcode <= 3
663 && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
664 /* nop??? */
665 }
666
667 switch (subcode) {
668 case 0:
669 LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
670 t_gen_mulu(cpu_R[dc->rd], d[1], cpu_R[dc->ra], cpu_R[dc->rb]);
671 break;
672 case 1:
673 LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
674 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
675 break;
676 case 2:
677 LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
678 t_gen_muls(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
679 break;
680 case 3:
681 LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
682 t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
683 break;
684 default:
685 cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
686 break;
687 }
688 done:
689 tcg_temp_free(d[0]);
690 tcg_temp_free(d[1]);
691 }
692
693 /* Div unit. */
694 static void dec_div(DisasContext *dc)
695 {
696 unsigned int u;
697
698 u = dc->imm & 2;
699 LOG_DIS("div\n");
700
701 if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
702 && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
703 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
704 t_gen_raise_exception(dc, EXCP_HW_EXCP);
705 }
706
707 if (u)
708 gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
709 cpu_R[dc->ra]);
710 else
711 gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
712 cpu_R[dc->ra]);
713 if (!dc->rd)
714 tcg_gen_movi_tl(cpu_R[dc->rd], 0);
715 }
716
717 static void dec_barrel(DisasContext *dc)
718 {
719 TCGv t0;
720 unsigned int s, t;
721
722 if ((dc->tb_flags & MSR_EE_FLAG)
723 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
724 && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
725 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
726 t_gen_raise_exception(dc, EXCP_HW_EXCP);
727 return;
728 }
729
730 s = dc->imm & (1 << 10);
731 t = dc->imm & (1 << 9);
732
733 LOG_DIS("bs%s%s r%d r%d r%d\n",
734 s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
735
736 t0 = tcg_temp_new();
737
738 tcg_gen_mov_tl(t0, *(dec_alu_op_b(dc)));
739 tcg_gen_andi_tl(t0, t0, 31);
740
741 if (s)
742 tcg_gen_shl_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
743 else {
744 if (t)
745 tcg_gen_sar_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
746 else
747 tcg_gen_shr_tl(cpu_R[dc->rd], cpu_R[dc->ra], t0);
748 }
749 }
750
751 static void dec_bit(DisasContext *dc)
752 {
753 TCGv t0;
754 unsigned int op;
755 int mem_index = cpu_mmu_index(dc->env);
756
757 op = dc->ir & ((1 << 9) - 1);
758 switch (op) {
759 case 0x21:
760 /* src. */
761 t0 = tcg_temp_new();
762
763 LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
764 tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC);
765 write_carry(dc, cpu_R[dc->ra]);
766 if (dc->rd) {
767 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
768 tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0);
769 }
770 tcg_temp_free(t0);
771 break;
772
773 case 0x1:
774 case 0x41:
775 /* srl. */
776 LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
777
778 /* Update carry. Note that write carry only looks at the LSB. */
779 write_carry(dc, cpu_R[dc->ra]);
780 if (dc->rd) {
781 if (op == 0x41)
782 tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
783 else
784 tcg_gen_sari_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1);
785 }
786 break;
787 case 0x60:
788 LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
789 tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
790 break;
791 case 0x61:
792 LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
793 tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
794 break;
795 case 0x64:
796 case 0x66:
797 case 0x74:
798 case 0x76:
799 /* wdc. */
800 LOG_DIS("wdc r%d\n", dc->ra);
801 if ((dc->tb_flags & MSR_EE_FLAG)
802 && mem_index == MMU_USER_IDX) {
803 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
804 t_gen_raise_exception(dc, EXCP_HW_EXCP);
805 return;
806 }
807 break;
808 case 0x68:
809 /* wic. */
810 LOG_DIS("wic r%d\n", dc->ra);
811 if ((dc->tb_flags & MSR_EE_FLAG)
812 && mem_index == MMU_USER_IDX) {
813 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
814 t_gen_raise_exception(dc, EXCP_HW_EXCP);
815 return;
816 }
817 break;
818 case 0xe0:
819 if ((dc->tb_flags & MSR_EE_FLAG)
820 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
821 && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
822 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
823 t_gen_raise_exception(dc, EXCP_HW_EXCP);
824 }
825 if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
826 gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
827 }
828 break;
829 case 0x1e0:
830 /* swapb */
831 LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
832 tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
833 break;
834 case 0x1e2:
835 /*swaph */
836 LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
837 tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
838 break;
839 default:
840 cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
841 dc->pc, op, dc->rd, dc->ra, dc->rb);
842 break;
843 }
844 }
845
846 static inline void sync_jmpstate(DisasContext *dc)
847 {
848 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
849 if (dc->jmp == JMP_DIRECT) {
850 tcg_gen_movi_tl(env_btaken, 1);
851 }
852 dc->jmp = JMP_INDIRECT;
853 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
854 }
855 }
856
857 static void dec_imm(DisasContext *dc)
858 {
859 LOG_DIS("imm %x\n", dc->imm << 16);
860 tcg_gen_movi_tl(env_imm, (dc->imm << 16));
861 dc->tb_flags |= IMM_FLAG;
862 dc->clear_imm = 0;
863 }
864
865 static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
866 unsigned int size, bool exclusive)
867 {
868 int mem_index = cpu_mmu_index(dc->env);
869
870 if (size == 1) {
871 tcg_gen_qemu_ld8u(dst, addr, mem_index);
872 } else if (size == 2) {
873 tcg_gen_qemu_ld16u(dst, addr, mem_index);
874 } else if (size == 4) {
875 tcg_gen_qemu_ld32u(dst, addr, mem_index);
876 } else
877 cpu_abort(dc->env, "Incorrect load size %d\n", size);
878
879 if (exclusive) {
880 tcg_gen_st_tl(addr, cpu_env, offsetof(CPUMBState, res_addr));
881 }
882 }
883
884 static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
885 {
886 unsigned int extimm = dc->tb_flags & IMM_FLAG;
887 /* Should be set to one if r1 is used by loadstores. */
888 int stackprot = 0;
889
890 /* All load/stores use ra. */
891 if (dc->ra == 1) {
892 stackprot = 1;
893 }
894
895 /* Treat the common cases first. */
896 if (!dc->type_b) {
897 /* If any of the regs is r0, return a ptr to the other. */
898 if (dc->ra == 0) {
899 return &cpu_R[dc->rb];
900 } else if (dc->rb == 0) {
901 return &cpu_R[dc->ra];
902 }
903
904 if (dc->rb == 1) {
905 stackprot = 1;
906 }
907
908 *t = tcg_temp_new();
909 tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
910
911 if (stackprot) {
912 gen_helper_stackprot(cpu_env, *t);
913 }
914 return t;
915 }
916 /* Immediate. */
917 if (!extimm) {
918 if (dc->imm == 0) {
919 return &cpu_R[dc->ra];
920 }
921 *t = tcg_temp_new();
922 tcg_gen_movi_tl(*t, (int32_t)((int16_t)dc->imm));
923 tcg_gen_add_tl(*t, cpu_R[dc->ra], *t);
924 } else {
925 *t = tcg_temp_new();
926 tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
927 }
928
929 if (stackprot) {
930 gen_helper_stackprot(cpu_env, *t);
931 }
932 return t;
933 }
934
935 static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
936 {
937 if (size == 4) {
938 tcg_gen_bswap32_tl(dst, src);
939 } else if (size == 2) {
940 TCGv t = tcg_temp_new();
941
942 /* bswap16 assumes the high bits are zero. */
943 tcg_gen_andi_tl(t, src, 0xffff);
944 tcg_gen_bswap16_tl(dst, t);
945 tcg_temp_free(t);
946 } else {
947 /* Ignore.
948 cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
949 */
950 }
951 }
952
953 static void dec_load(DisasContext *dc)
954 {
955 TCGv t, *addr;
956 unsigned int size, rev = 0, ex = 0;
957
958 size = 1 << (dc->opcode & 3);
959
960 if (!dc->type_b) {
961 rev = (dc->ir >> 9) & 1;
962 ex = (dc->ir >> 10) & 1;
963 }
964
965 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
966 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
967 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
968 t_gen_raise_exception(dc, EXCP_HW_EXCP);
969 return;
970 }
971
972 LOG_DIS("l%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
973 ex ? "x" : "");
974
975 t_sync_flags(dc);
976 addr = compute_ldst_addr(dc, &t);
977
978 /*
979 * When doing reverse accesses we need to do two things.
980 *
981 * 1. Reverse the address wrt endianness.
982 * 2. Byteswap the data lanes on the way back into the CPU core.
983 */
984 if (rev && size != 4) {
985 /* Endian reverse the address. t is addr. */
986 switch (size) {
987 case 1:
988 {
989 /* 00 -> 11
990 01 -> 10
991 10 -> 10
992 11 -> 00 */
993 TCGv low = tcg_temp_new();
994
995 /* Force addr into the temp. */
996 if (addr != &t) {
997 t = tcg_temp_new();
998 tcg_gen_mov_tl(t, *addr);
999 addr = &t;
1000 }
1001
1002 tcg_gen_andi_tl(low, t, 3);
1003 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1004 tcg_gen_andi_tl(t, t, ~3);
1005 tcg_gen_or_tl(t, t, low);
1006 tcg_gen_mov_tl(env_imm, t);
1007 tcg_temp_free(low);
1008 break;
1009 }
1010
1011 case 2:
1012 /* 00 -> 10
1013 10 -> 00. */
1014 /* Force addr into the temp. */
1015 if (addr != &t) {
1016 t = tcg_temp_new();
1017 tcg_gen_xori_tl(t, *addr, 2);
1018 addr = &t;
1019 } else {
1020 tcg_gen_xori_tl(t, t, 2);
1021 }
1022 break;
1023 default:
1024 cpu_abort(dc->env, "Invalid reverse size\n");
1025 break;
1026 }
1027 }
1028
1029 /* lwx does not throw unaligned access errors, so force alignment */
1030 if (ex) {
1031 /* Force addr into the temp. */
1032 if (addr != &t) {
1033 t = tcg_temp_new();
1034 tcg_gen_mov_tl(t, *addr);
1035 addr = &t;
1036 }
1037 tcg_gen_andi_tl(t, t, ~3);
1038 }
1039
1040 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1041 sync_jmpstate(dc);
1042
1043 /* Verify alignment if needed. */
1044 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1045 TCGv v = tcg_temp_new();
1046
1047 /*
1048 * Microblaze gives MMU faults priority over faults due to
1049 * unaligned addresses. That's why we speculatively do the load
1050 * into v. If the load succeeds, we verify alignment of the
1051 * address and if that succeeds we write into the destination reg.
1052 */
1053 gen_load(dc, v, *addr, size, ex);
1054
1055 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1056 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1057 tcg_const_tl(0), tcg_const_tl(size - 1));
1058 if (dc->rd) {
1059 if (rev) {
1060 dec_byteswap(dc, cpu_R[dc->rd], v, size);
1061 } else {
1062 tcg_gen_mov_tl(cpu_R[dc->rd], v);
1063 }
1064 }
1065 tcg_temp_free(v);
1066 } else {
1067 if (dc->rd) {
1068 gen_load(dc, cpu_R[dc->rd], *addr, size, ex);
1069 if (rev) {
1070 dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size);
1071 }
1072 } else {
1073 /* We are loading into r0, no need to reverse. */
1074 gen_load(dc, env_imm, *addr, size, ex);
1075 }
1076 }
1077
1078 if (ex) { /* lwx */
1079 /* no support for for AXI exclusive so always clear C */
1080 write_carryi(dc, 0);
1081 }
1082
1083 if (addr == &t)
1084 tcg_temp_free(t);
1085 }
1086
1087 static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
1088 unsigned int size)
1089 {
1090 int mem_index = cpu_mmu_index(dc->env);
1091
1092 if (size == 1)
1093 tcg_gen_qemu_st8(val, addr, mem_index);
1094 else if (size == 2) {
1095 tcg_gen_qemu_st16(val, addr, mem_index);
1096 } else if (size == 4) {
1097 tcg_gen_qemu_st32(val, addr, mem_index);
1098 } else
1099 cpu_abort(dc->env, "Incorrect store size %d\n", size);
1100 }
1101
1102 static void dec_store(DisasContext *dc)
1103 {
1104 TCGv t, *addr, swx_addr, r_check;
1105 int swx_skip = 0;
1106 unsigned int size, rev = 0, ex = 0;
1107
1108 size = 1 << (dc->opcode & 3);
1109 if (!dc->type_b) {
1110 rev = (dc->ir >> 9) & 1;
1111 ex = (dc->ir >> 10) & 1;
1112 }
1113
1114 if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
1115 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1116 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1117 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1118 return;
1119 }
1120
1121 LOG_DIS("s%d%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1122 ex ? "x" : "");
1123 t_sync_flags(dc);
1124 /* If we get a fault on a dslot, the jmpstate better be in sync. */
1125 sync_jmpstate(dc);
1126 addr = compute_ldst_addr(dc, &t);
1127
1128 r_check = tcg_temp_new();
1129 swx_addr = tcg_temp_local_new();
1130 if (ex) { /* swx */
1131
1132 /* Force addr into the swx_addr. */
1133 tcg_gen_mov_tl(swx_addr, *addr);
1134 addr = &swx_addr;
1135 /* swx does not throw unaligned access errors, so force alignment */
1136 tcg_gen_andi_tl(swx_addr, swx_addr, ~3);
1137
1138 tcg_gen_ld_tl(r_check, cpu_env, offsetof(CPUMBState, res_addr));
1139 write_carryi(dc, 1);
1140 swx_skip = gen_new_label();
1141 tcg_gen_brcond_tl(TCG_COND_NE, r_check, swx_addr, swx_skip);
1142 write_carryi(dc, 0);
1143 }
1144
1145 if (rev && size != 4) {
1146 /* Endian reverse the address. t is addr. */
1147 switch (size) {
1148 case 1:
1149 {
1150 /* 00 -> 11
1151 01 -> 10
1152 10 -> 10
1153 11 -> 00 */
1154 TCGv low = tcg_temp_new();
1155
1156 /* Force addr into the temp. */
1157 if (addr != &t) {
1158 t = tcg_temp_new();
1159 tcg_gen_mov_tl(t, *addr);
1160 addr = &t;
1161 }
1162
1163 tcg_gen_andi_tl(low, t, 3);
1164 tcg_gen_sub_tl(low, tcg_const_tl(3), low);
1165 tcg_gen_andi_tl(t, t, ~3);
1166 tcg_gen_or_tl(t, t, low);
1167 tcg_gen_mov_tl(env_imm, t);
1168 tcg_temp_free(low);
1169 break;
1170 }
1171
1172 case 2:
1173 /* 00 -> 10
1174 10 -> 00. */
1175 /* Force addr into the temp. */
1176 if (addr != &t) {
1177 t = tcg_temp_new();
1178 tcg_gen_xori_tl(t, *addr, 2);
1179 addr = &t;
1180 } else {
1181 tcg_gen_xori_tl(t, t, 2);
1182 }
1183 break;
1184 default:
1185 cpu_abort(dc->env, "Invalid reverse size\n");
1186 break;
1187 }
1188
1189 if (size != 1) {
1190 TCGv bs_data = tcg_temp_new();
1191 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1192 gen_store(dc, *addr, bs_data, size);
1193 tcg_temp_free(bs_data);
1194 } else {
1195 gen_store(dc, *addr, cpu_R[dc->rd], size);
1196 }
1197 } else {
1198 if (rev) {
1199 TCGv bs_data = tcg_temp_new();
1200 dec_byteswap(dc, bs_data, cpu_R[dc->rd], size);
1201 gen_store(dc, *addr, bs_data, size);
1202 tcg_temp_free(bs_data);
1203 } else {
1204 gen_store(dc, *addr, cpu_R[dc->rd], size);
1205 }
1206 }
1207
1208 /* Verify alignment if needed. */
1209 if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
1210 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1211 /* FIXME: if the alignment is wrong, we should restore the value
1212 * in memory. One possible way to achieve this is to probe
1213 * the MMU prior to the memaccess, thay way we could put
1214 * the alignment checks in between the probe and the mem
1215 * access.
1216 */
1217 gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd),
1218 tcg_const_tl(1), tcg_const_tl(size - 1));
1219 }
1220
1221 if (ex) {
1222 gen_set_label(swx_skip);
1223 }
1224 tcg_temp_free(r_check);
1225 tcg_temp_free(swx_addr);
1226
1227 if (addr == &t)
1228 tcg_temp_free(t);
1229 }
1230
1231 static inline void eval_cc(DisasContext *dc, unsigned int cc,
1232 TCGv d, TCGv a, TCGv b)
1233 {
1234 switch (cc) {
1235 case CC_EQ:
1236 tcg_gen_setcond_tl(TCG_COND_EQ, d, a, b);
1237 break;
1238 case CC_NE:
1239 tcg_gen_setcond_tl(TCG_COND_NE, d, a, b);
1240 break;
1241 case CC_LT:
1242 tcg_gen_setcond_tl(TCG_COND_LT, d, a, b);
1243 break;
1244 case CC_LE:
1245 tcg_gen_setcond_tl(TCG_COND_LE, d, a, b);
1246 break;
1247 case CC_GE:
1248 tcg_gen_setcond_tl(TCG_COND_GE, d, a, b);
1249 break;
1250 case CC_GT:
1251 tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
1252 break;
1253 default:
1254 cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
1255 break;
1256 }
1257 }
1258
1259 static void eval_cond_jmp(DisasContext *dc, TCGv pc_true, TCGv pc_false)
1260 {
1261 int l1;
1262
1263 l1 = gen_new_label();
1264 /* Conditional jmp. */
1265 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_false);
1266 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
1267 tcg_gen_mov_tl(cpu_SR[SR_PC], pc_true);
1268 gen_set_label(l1);
1269 }
1270
1271 static void dec_bcc(DisasContext *dc)
1272 {
1273 unsigned int cc;
1274 unsigned int dslot;
1275
1276 cc = EXTRACT_FIELD(dc->ir, 21, 23);
1277 dslot = dc->ir & (1 << 25);
1278 LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
1279
1280 dc->delayed_branch = 1;
1281 if (dslot) {
1282 dc->delayed_branch = 2;
1283 dc->tb_flags |= D_FLAG;
1284 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1285 cpu_env, offsetof(CPUMBState, bimm));
1286 }
1287
1288 if (dec_alu_op_b_is_small_imm(dc)) {
1289 int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */
1290
1291 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
1292 dc->jmp = JMP_DIRECT_CC;
1293 dc->jmp_pc = dc->pc + offset;
1294 } else {
1295 dc->jmp = JMP_INDIRECT;
1296 tcg_gen_movi_tl(env_btarget, dc->pc);
1297 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1298 }
1299 eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_tl(0));
1300 }
1301
1302 static void dec_br(DisasContext *dc)
1303 {
1304 unsigned int dslot, link, abs, mbar;
1305 int mem_index = cpu_mmu_index(dc->env);
1306
1307 dslot = dc->ir & (1 << 20);
1308 abs = dc->ir & (1 << 19);
1309 link = dc->ir & (1 << 18);
1310
1311 /* Memory barrier. */
1312 mbar = (dc->ir >> 16) & 31;
1313 if (mbar == 2 && dc->imm == 4) {
1314 /* mbar IMM & 16 decodes to sleep. */
1315 if (dc->rd & 16) {
1316 TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
1317 TCGv_i32 tmp_1 = tcg_const_i32(1);
1318
1319 LOG_DIS("sleep\n");
1320
1321 t_sync_flags(dc);
1322 tcg_gen_st_i32(tmp_1, cpu_env,
1323 -offsetof(MicroBlazeCPU, env)
1324 +offsetof(CPUState, halted));
1325 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc + 4);
1326 gen_helper_raise_exception(cpu_env, tmp_hlt);
1327 tcg_temp_free_i32(tmp_hlt);
1328 tcg_temp_free_i32(tmp_1);
1329 return;
1330 }
1331 LOG_DIS("mbar %d\n", dc->rd);
1332 /* Break the TB. */
1333 dc->cpustate_changed = 1;
1334 return;
1335 }
1336
1337 LOG_DIS("br%s%s%s%s imm=%x\n",
1338 abs ? "a" : "", link ? "l" : "",
1339 dc->type_b ? "i" : "", dslot ? "d" : "",
1340 dc->imm);
1341
1342 dc->delayed_branch = 1;
1343 if (dslot) {
1344 dc->delayed_branch = 2;
1345 dc->tb_flags |= D_FLAG;
1346 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1347 cpu_env, offsetof(CPUMBState, bimm));
1348 }
1349 if (link && dc->rd)
1350 tcg_gen_movi_tl(cpu_R[dc->rd], dc->pc);
1351
1352 dc->jmp = JMP_INDIRECT;
1353 if (abs) {
1354 tcg_gen_movi_tl(env_btaken, 1);
1355 tcg_gen_mov_tl(env_btarget, *(dec_alu_op_b(dc)));
1356 if (link && !dslot) {
1357 if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18))
1358 t_gen_raise_exception(dc, EXCP_BREAK);
1359 if (dc->imm == 0) {
1360 if ((dc->tb_flags & MSR_EE_FLAG) && mem_index == MMU_USER_IDX) {
1361 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1362 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1363 return;
1364 }
1365
1366 t_gen_raise_exception(dc, EXCP_DEBUG);
1367 }
1368 }
1369 } else {
1370 if (dec_alu_op_b_is_small_imm(dc)) {
1371 dc->jmp = JMP_DIRECT;
1372 dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
1373 } else {
1374 tcg_gen_movi_tl(env_btaken, 1);
1375 tcg_gen_movi_tl(env_btarget, dc->pc);
1376 tcg_gen_add_tl(env_btarget, env_btarget, *(dec_alu_op_b(dc)));
1377 }
1378 }
1379 }
1380
1381 static inline void do_rti(DisasContext *dc)
1382 {
1383 TCGv t0, t1;
1384 t0 = tcg_temp_new();
1385 t1 = tcg_temp_new();
1386 tcg_gen_shri_tl(t0, cpu_SR[SR_MSR], 1);
1387 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_IE);
1388 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1389
1390 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1391 tcg_gen_or_tl(t1, t1, t0);
1392 msr_write(dc, t1);
1393 tcg_temp_free(t1);
1394 tcg_temp_free(t0);
1395 dc->tb_flags &= ~DRTI_FLAG;
1396 }
1397
1398 static inline void do_rtb(DisasContext *dc)
1399 {
1400 TCGv t0, t1;
1401 t0 = tcg_temp_new();
1402 t1 = tcg_temp_new();
1403 tcg_gen_andi_tl(t1, cpu_SR[SR_MSR], ~MSR_BIP);
1404 tcg_gen_shri_tl(t0, t1, 1);
1405 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1406
1407 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1408 tcg_gen_or_tl(t1, t1, t0);
1409 msr_write(dc, t1);
1410 tcg_temp_free(t1);
1411 tcg_temp_free(t0);
1412 dc->tb_flags &= ~DRTB_FLAG;
1413 }
1414
1415 static inline void do_rte(DisasContext *dc)
1416 {
1417 TCGv t0, t1;
1418 t0 = tcg_temp_new();
1419 t1 = tcg_temp_new();
1420
1421 tcg_gen_ori_tl(t1, cpu_SR[SR_MSR], MSR_EE);
1422 tcg_gen_andi_tl(t1, t1, ~MSR_EIP);
1423 tcg_gen_shri_tl(t0, t1, 1);
1424 tcg_gen_andi_tl(t0, t0, (MSR_VM | MSR_UM));
1425
1426 tcg_gen_andi_tl(t1, t1, ~(MSR_VM | MSR_UM));
1427 tcg_gen_or_tl(t1, t1, t0);
1428 msr_write(dc, t1);
1429 tcg_temp_free(t1);
1430 tcg_temp_free(t0);
1431 dc->tb_flags &= ~DRTE_FLAG;
1432 }
1433
1434 static void dec_rts(DisasContext *dc)
1435 {
1436 unsigned int b_bit, i_bit, e_bit;
1437 int mem_index = cpu_mmu_index(dc->env);
1438
1439 i_bit = dc->ir & (1 << 21);
1440 b_bit = dc->ir & (1 << 22);
1441 e_bit = dc->ir & (1 << 23);
1442
1443 dc->delayed_branch = 2;
1444 dc->tb_flags |= D_FLAG;
1445 tcg_gen_st_tl(tcg_const_tl(dc->type_b && (dc->tb_flags & IMM_FLAG)),
1446 cpu_env, offsetof(CPUMBState, bimm));
1447
1448 if (i_bit) {
1449 LOG_DIS("rtid ir=%x\n", dc->ir);
1450 if ((dc->tb_flags & MSR_EE_FLAG)
1451 && mem_index == MMU_USER_IDX) {
1452 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1453 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1454 }
1455 dc->tb_flags |= DRTI_FLAG;
1456 } else if (b_bit) {
1457 LOG_DIS("rtbd ir=%x\n", dc->ir);
1458 if ((dc->tb_flags & MSR_EE_FLAG)
1459 && mem_index == MMU_USER_IDX) {
1460 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1461 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1462 }
1463 dc->tb_flags |= DRTB_FLAG;
1464 } else if (e_bit) {
1465 LOG_DIS("rted ir=%x\n", dc->ir);
1466 if ((dc->tb_flags & MSR_EE_FLAG)
1467 && mem_index == MMU_USER_IDX) {
1468 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1469 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1470 }
1471 dc->tb_flags |= DRTE_FLAG;
1472 } else
1473 LOG_DIS("rts ir=%x\n", dc->ir);
1474
1475 dc->jmp = JMP_INDIRECT;
1476 tcg_gen_movi_tl(env_btaken, 1);
1477 tcg_gen_add_tl(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
1478 }
1479
1480 static int dec_check_fpuv2(DisasContext *dc)
1481 {
1482 int r;
1483
1484 r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
1485
1486 if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
1487 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
1488 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1489 }
1490 return r;
1491 }
1492
1493 static void dec_fpu(DisasContext *dc)
1494 {
1495 unsigned int fpu_insn;
1496
1497 if ((dc->tb_flags & MSR_EE_FLAG)
1498 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1499 && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
1500 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1501 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1502 return;
1503 }
1504
1505 fpu_insn = (dc->ir >> 7) & 7;
1506
1507 switch (fpu_insn) {
1508 case 0:
1509 gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1510 cpu_R[dc->rb]);
1511 break;
1512
1513 case 1:
1514 gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1515 cpu_R[dc->rb]);
1516 break;
1517
1518 case 2:
1519 gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1520 cpu_R[dc->rb]);
1521 break;
1522
1523 case 3:
1524 gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
1525 cpu_R[dc->rb]);
1526 break;
1527
1528 case 4:
1529 switch ((dc->ir >> 4) & 7) {
1530 case 0:
1531 gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
1532 cpu_R[dc->ra], cpu_R[dc->rb]);
1533 break;
1534 case 1:
1535 gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
1536 cpu_R[dc->ra], cpu_R[dc->rb]);
1537 break;
1538 case 2:
1539 gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
1540 cpu_R[dc->ra], cpu_R[dc->rb]);
1541 break;
1542 case 3:
1543 gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
1544 cpu_R[dc->ra], cpu_R[dc->rb]);
1545 break;
1546 case 4:
1547 gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
1548 cpu_R[dc->ra], cpu_R[dc->rb]);
1549 break;
1550 case 5:
1551 gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
1552 cpu_R[dc->ra], cpu_R[dc->rb]);
1553 break;
1554 case 6:
1555 gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
1556 cpu_R[dc->ra], cpu_R[dc->rb]);
1557 break;
1558 default:
1559 qemu_log_mask(LOG_UNIMP,
1560 "unimplemented fcmp fpu_insn=%x pc=%x"
1561 " opc=%x\n",
1562 fpu_insn, dc->pc, dc->opcode);
1563 dc->abort_at_next_insn = 1;
1564 break;
1565 }
1566 break;
1567
1568 case 5:
1569 if (!dec_check_fpuv2(dc)) {
1570 return;
1571 }
1572 gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1573 break;
1574
1575 case 6:
1576 if (!dec_check_fpuv2(dc)) {
1577 return;
1578 }
1579 gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1580 break;
1581
1582 case 7:
1583 if (!dec_check_fpuv2(dc)) {
1584 return;
1585 }
1586 gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
1587 break;
1588
1589 default:
1590 qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
1591 " opc=%x\n",
1592 fpu_insn, dc->pc, dc->opcode);
1593 dc->abort_at_next_insn = 1;
1594 break;
1595 }
1596 }
1597
1598 static void dec_null(DisasContext *dc)
1599 {
1600 if ((dc->tb_flags & MSR_EE_FLAG)
1601 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
1602 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1603 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1604 return;
1605 }
1606 qemu_log ("unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
1607 dc->abort_at_next_insn = 1;
1608 }
1609
1610 /* Insns connected to FSL or AXI stream attached devices. */
1611 static void dec_stream(DisasContext *dc)
1612 {
1613 int mem_index = cpu_mmu_index(dc->env);
1614 TCGv_i32 t_id, t_ctrl;
1615 int ctrl;
1616
1617 LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
1618 dc->type_b ? "" : "d", dc->imm);
1619
1620 if ((dc->tb_flags & MSR_EE_FLAG) && (mem_index == MMU_USER_IDX)) {
1621 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
1622 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1623 return;
1624 }
1625
1626 t_id = tcg_temp_new();
1627 if (dc->type_b) {
1628 tcg_gen_movi_tl(t_id, dc->imm & 0xf);
1629 ctrl = dc->imm >> 10;
1630 } else {
1631 tcg_gen_andi_tl(t_id, cpu_R[dc->rb], 0xf);
1632 ctrl = dc->imm >> 5;
1633 }
1634
1635 t_ctrl = tcg_const_tl(ctrl);
1636
1637 if (dc->rd == 0) {
1638 gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
1639 } else {
1640 gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
1641 }
1642 tcg_temp_free(t_id);
1643 tcg_temp_free(t_ctrl);
1644 }
1645
1646 static struct decoder_info {
1647 struct {
1648 uint32_t bits;
1649 uint32_t mask;
1650 };
1651 void (*dec)(DisasContext *dc);
1652 } decinfo[] = {
1653 {DEC_ADD, dec_add},
1654 {DEC_SUB, dec_sub},
1655 {DEC_AND, dec_and},
1656 {DEC_XOR, dec_xor},
1657 {DEC_OR, dec_or},
1658 {DEC_BIT, dec_bit},
1659 {DEC_BARREL, dec_barrel},
1660 {DEC_LD, dec_load},
1661 {DEC_ST, dec_store},
1662 {DEC_IMM, dec_imm},
1663 {DEC_BR, dec_br},
1664 {DEC_BCC, dec_bcc},
1665 {DEC_RTS, dec_rts},
1666 {DEC_FPU, dec_fpu},
1667 {DEC_MUL, dec_mul},
1668 {DEC_DIV, dec_div},
1669 {DEC_MSR, dec_msr},
1670 {DEC_STREAM, dec_stream},
1671 {{0, 0}, dec_null}
1672 };
1673
1674 static inline void decode(DisasContext *dc, uint32_t ir)
1675 {
1676 int i;
1677
1678 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1679 tcg_gen_debug_insn_start(dc->pc);
1680 }
1681
1682 dc->ir = ir;
1683 LOG_DIS("%8.8x\t", dc->ir);
1684
1685 if (dc->ir)
1686 dc->nr_nops = 0;
1687 else {
1688 if ((dc->tb_flags & MSR_EE_FLAG)
1689 && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
1690 && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
1691 tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
1692 t_gen_raise_exception(dc, EXCP_HW_EXCP);
1693 return;
1694 }
1695
1696 LOG_DIS("nr_nops=%d\t", dc->nr_nops);
1697 dc->nr_nops++;
1698 if (dc->nr_nops > 4)
1699 cpu_abort(dc->env, "fetching nop sequence\n");
1700 }
1701 /* bit 2 seems to indicate insn type. */
1702 dc->type_b = ir & (1 << 29);
1703
1704 dc->opcode = EXTRACT_FIELD(ir, 26, 31);
1705 dc->rd = EXTRACT_FIELD(ir, 21, 25);
1706 dc->ra = EXTRACT_FIELD(ir, 16, 20);
1707 dc->rb = EXTRACT_FIELD(ir, 11, 15);
1708 dc->imm = EXTRACT_FIELD(ir, 0, 15);
1709
1710 /* Large switch for all insns. */
1711 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
1712 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
1713 decinfo[i].dec(dc);
1714 break;
1715 }
1716 }
1717 }
1718
1719 static void check_breakpoint(CPUMBState *env, DisasContext *dc)
1720 {
1721 CPUBreakpoint *bp;
1722
1723 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
1724 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1725 if (bp->pc == dc->pc) {
1726 t_gen_raise_exception(dc, EXCP_DEBUG);
1727 dc->is_jmp = DISAS_UPDATE;
1728 }
1729 }
1730 }
1731 }
1732
1733 /* generate intermediate code for basic block 'tb'. */
1734 static inline void
1735 gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
1736 bool search_pc)
1737 {
1738 CPUState *cs = CPU(cpu);
1739 CPUMBState *env = &cpu->env;
1740 uint16_t *gen_opc_end;
1741 uint32_t pc_start;
1742 int j, lj;
1743 struct DisasContext ctx;
1744 struct DisasContext *dc = &ctx;
1745 uint32_t next_page_start, org_flags;
1746 target_ulong npc;
1747 int num_insns;
1748 int max_insns;
1749
1750 pc_start = tb->pc;
1751 dc->env = env;
1752 dc->tb = tb;
1753 org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
1754
1755 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1756
1757 dc->is_jmp = DISAS_NEXT;
1758 dc->jmp = 0;
1759 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1760 if (dc->delayed_branch) {
1761 dc->jmp = JMP_INDIRECT;
1762 }
1763 dc->pc = pc_start;
1764 dc->singlestep_enabled = cs->singlestep_enabled;
1765 dc->cpustate_changed = 0;
1766 dc->abort_at_next_insn = 0;
1767 dc->nr_nops = 0;
1768
1769 if (pc_start & 3)
1770 cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
1771
1772 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1773 #if !SIM_COMPAT
1774 qemu_log("--------------\n");
1775 log_cpu_state(CPU(cpu), 0);
1776 #endif
1777 }
1778
1779 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1780 lj = -1;
1781 num_insns = 0;
1782 max_insns = tb->cflags & CF_COUNT_MASK;
1783 if (max_insns == 0)
1784 max_insns = CF_COUNT_MASK;
1785
1786 gen_tb_start();
1787 do
1788 {
1789 #if SIM_COMPAT
1790 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1791 tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
1792 gen_helper_debug();
1793 }
1794 #endif
1795 check_breakpoint(env, dc);
1796
1797 if (search_pc) {
1798 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1799 if (lj < j) {
1800 lj++;
1801 while (lj < j)
1802 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1803 }
1804 tcg_ctx.gen_opc_pc[lj] = dc->pc;
1805 tcg_ctx.gen_opc_instr_start[lj] = 1;
1806 tcg_ctx.gen_opc_icount[lj] = num_insns;
1807 }
1808
1809 /* Pretty disas. */
1810 LOG_DIS("%8.8x:\t", dc->pc);
1811
1812 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
1813 gen_io_start();
1814
1815 dc->clear_imm = 1;
1816 decode(dc, cpu_ldl_code(env, dc->pc));
1817 if (dc->clear_imm)
1818 dc->tb_flags &= ~IMM_FLAG;
1819 dc->pc += 4;
1820 num_insns++;
1821
1822 if (dc->delayed_branch) {
1823 dc->delayed_branch--;
1824 if (!dc->delayed_branch) {
1825 if (dc->tb_flags & DRTI_FLAG)
1826 do_rti(dc);
1827 if (dc->tb_flags & DRTB_FLAG)
1828 do_rtb(dc);
1829 if (dc->tb_flags & DRTE_FLAG)
1830 do_rte(dc);
1831 /* Clear the delay slot flag. */
1832 dc->tb_flags &= ~D_FLAG;
1833 /* If it is a direct jump, try direct chaining. */
1834 if (dc->jmp == JMP_INDIRECT) {
1835 eval_cond_jmp(dc, env_btarget, tcg_const_tl(dc->pc));
1836 dc->is_jmp = DISAS_JUMP;
1837 } else if (dc->jmp == JMP_DIRECT) {
1838 t_sync_flags(dc);
1839 gen_goto_tb(dc, 0, dc->jmp_pc);
1840 dc->is_jmp = DISAS_TB_JUMP;
1841 } else if (dc->jmp == JMP_DIRECT_CC) {
1842 int l1;
1843
1844 t_sync_flags(dc);
1845 l1 = gen_new_label();
1846 /* Conditional jmp. */
1847 tcg_gen_brcondi_tl(TCG_COND_NE, env_btaken, 0, l1);
1848 gen_goto_tb(dc, 1, dc->pc);
1849 gen_set_label(l1);
1850 gen_goto_tb(dc, 0, dc->jmp_pc);
1851
1852 dc->is_jmp = DISAS_TB_JUMP;
1853 }
1854 break;
1855 }
1856 }
1857 if (cs->singlestep_enabled) {
1858 break;
1859 }
1860 } while (!dc->is_jmp && !dc->cpustate_changed
1861 && tcg_ctx.gen_opc_ptr < gen_opc_end
1862 && !singlestep
1863 && (dc->pc < next_page_start)
1864 && num_insns < max_insns);
1865
1866 npc = dc->pc;
1867 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1868 if (dc->tb_flags & D_FLAG) {
1869 dc->is_jmp = DISAS_UPDATE;
1870 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1871 sync_jmpstate(dc);
1872 } else
1873 npc = dc->jmp_pc;
1874 }
1875
1876 if (tb->cflags & CF_LAST_IO)
1877 gen_io_end();
1878 /* Force an update if the per-tb cpu state has changed. */
1879 if (dc->is_jmp == DISAS_NEXT
1880 && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
1881 dc->is_jmp = DISAS_UPDATE;
1882 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1883 }
1884 t_sync_flags(dc);
1885
1886 if (unlikely(cs->singlestep_enabled)) {
1887 TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
1888
1889 if (dc->is_jmp != DISAS_JUMP) {
1890 tcg_gen_movi_tl(cpu_SR[SR_PC], npc);
1891 }
1892 gen_helper_raise_exception(cpu_env, tmp);
1893 tcg_temp_free_i32(tmp);
1894 } else {
1895 switch(dc->is_jmp) {
1896 case DISAS_NEXT:
1897 gen_goto_tb(dc, 1, npc);
1898 break;
1899 default:
1900 case DISAS_JUMP:
1901 case DISAS_UPDATE:
1902 /* indicate that the hash table must be used
1903 to find the next TB */
1904 tcg_gen_exit_tb(0);
1905 break;
1906 case DISAS_TB_JUMP:
1907 /* nothing more to generate */
1908 break;
1909 }
1910 }
1911 gen_tb_end(tb, num_insns);
1912 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1913 if (search_pc) {
1914 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1915 lj++;
1916 while (lj <= j)
1917 tcg_ctx.gen_opc_instr_start[lj++] = 0;
1918 } else {
1919 tb->size = dc->pc - pc_start;
1920 tb->icount = num_insns;
1921 }
1922
1923 #ifdef DEBUG_DISAS
1924 #if !SIM_COMPAT
1925 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1926 qemu_log("\n");
1927 #if DISAS_GNU
1928 log_target_disas(env, pc_start, dc->pc - pc_start, 0);
1929 #endif
1930 qemu_log("\nisize=%d osize=%td\n",
1931 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1932 tcg_ctx.gen_opc_buf);
1933 }
1934 #endif
1935 #endif
1936 assert(!dc->abort_at_next_insn);
1937 }
1938
1939 void gen_intermediate_code (CPUMBState *env, struct TranslationBlock *tb)
1940 {
1941 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, false);
1942 }
1943
1944 void gen_intermediate_code_pc (CPUMBState *env, struct TranslationBlock *tb)
1945 {
1946 gen_intermediate_code_internal(mb_env_get_cpu(env), tb, true);
1947 }
1948
1949 void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1950 int flags)
1951 {
1952 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1953 CPUMBState *env = &cpu->env;
1954 int i;
1955
1956 if (!env || !f)
1957 return;
1958
1959 cpu_fprintf(f, "IN: PC=%x %s\n",
1960 env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
1961 cpu_fprintf(f, "rmsr=%x resr=%x rear=%x debug=%x imm=%x iflags=%x fsr=%x\n",
1962 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
1963 env->debug, env->imm, env->iflags, env->sregs[SR_FSR]);
1964 cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
1965 env->btaken, env->btarget,
1966 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
1967 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
1968 (env->sregs[SR_MSR] & MSR_EIP),
1969 (env->sregs[SR_MSR] & MSR_IE));
1970
1971 for (i = 0; i < 32; i++) {
1972 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
1973 if ((i + 1) % 4 == 0)
1974 cpu_fprintf(f, "\n");
1975 }
1976 cpu_fprintf(f, "\n\n");
1977 }
1978
1979 MicroBlazeCPU *cpu_mb_init(const char *cpu_model)
1980 {
1981 MicroBlazeCPU *cpu;
1982
1983 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
1984
1985 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
1986
1987 return cpu;
1988 }
1989
1990 void mb_tcg_init(void)
1991 {
1992 int i;
1993
1994 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
1995
1996 env_debug = tcg_global_mem_new(TCG_AREG0,
1997 offsetof(CPUMBState, debug),
1998 "debug0");
1999 env_iflags = tcg_global_mem_new(TCG_AREG0,
2000 offsetof(CPUMBState, iflags),
2001 "iflags");
2002 env_imm = tcg_global_mem_new(TCG_AREG0,
2003 offsetof(CPUMBState, imm),
2004 "imm");
2005 env_btarget = tcg_global_mem_new(TCG_AREG0,
2006 offsetof(CPUMBState, btarget),
2007 "btarget");
2008 env_btaken = tcg_global_mem_new(TCG_AREG0,
2009 offsetof(CPUMBState, btaken),
2010 "btaken");
2011 for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
2012 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
2013 offsetof(CPUMBState, regs[i]),
2014 regnames[i]);
2015 }
2016 for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
2017 cpu_SR[i] = tcg_global_mem_new(TCG_AREG0,
2018 offsetof(CPUMBState, sregs[i]),
2019 special_regnames[i]);
2020 }
2021 }
2022
2023 void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
2024 {
2025 env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos];
2026 }
Qemu copy for testing