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target-mips: Add ASE DSP multiply instructions
[qemu.git] / target-mips / cpu.c
1 /*
2 * QEMU MIPS CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "cpu.h"
22 #include "qemu-common.h"
23
24
25 /* CPUClass::reset() */
26 static void mips_cpu_reset(CPUState *s)
27 {
28 MIPSCPU *cpu = MIPS_CPU(s);
29 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
30 CPUMIPSState *env = &cpu->env;
31
32 mcc->parent_reset(s);
33
34 cpu_state_reset(env);
35 }
36
37 static void mips_cpu_initfn(Object *obj)
38 {
39 MIPSCPU *cpu = MIPS_CPU(obj);
40 CPUMIPSState *env = &cpu->env;
41
42 cpu_exec_init(env);
43 }
44
45 static void mips_cpu_class_init(ObjectClass *c, void *data)
46 {
47 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
48 CPUClass *cc = CPU_CLASS(c);
49
50 mcc->parent_reset = cc->reset;
51 cc->reset = mips_cpu_reset;
52 }
53
54 static const TypeInfo mips_cpu_type_info = {
55 .name = TYPE_MIPS_CPU,
56 .parent = TYPE_CPU,
57 .instance_size = sizeof(MIPSCPU),
58 .instance_init = mips_cpu_initfn,
59 .abstract = false,
60 .class_size = sizeof(MIPSCPUClass),
61 .class_init = mips_cpu_class_init,
62 };
63
64 static void mips_cpu_register_types(void)
65 {
66 type_register_static(&mips_cpu_type_info);
67 }
68
69 type_init(mips_cpu_register_types)