1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
22 typedef struct r4k_tlb_t r4k_tlb_t
;
37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
38 struct CPUMIPSTLBContext
{
41 int (*map_address
) (struct CPUMIPSState
*env
, target_ulong
*physical
, int *prot
, target_ulong address
, int rw
, int access_type
);
42 void (*do_tlbwi
) (void);
43 void (*do_tlbwr
) (void);
44 void (*do_tlbp
) (void);
45 void (*do_tlbr
) (void);
48 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
53 typedef union fpr_t fpr_t
;
55 float64 fd
; /* ieee double precision */
56 float32 fs
[2];/* ieee single precision */
57 uint64_t d
; /* binary double fixed-point */
58 uint32_t w
[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianess
63 #if defined(WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
70 struct CPUMIPSFPUContext
{
71 /* Floating point registers */
73 #ifndef USE_HOST_FLOAT_REGS
78 float_status fp_status
;
79 /* fpu implementation/revision register (fir) */
92 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
93 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
94 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
95 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
96 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
97 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
98 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
99 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
100 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
101 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
103 #define FP_UNDERFLOW 2
104 #define FP_OVERFLOW 4
106 #define FP_INVALID 16
107 #define FP_UNIMPLEMENTED 32
110 #define NB_MMU_MODES 3
112 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
113 struct CPUMIPSMVPContext
{
114 int32_t CP0_MVPControl
;
115 #define CP0MVPCo_CPA 3
116 #define CP0MVPCo_STLB 2
117 #define CP0MVPCo_VPC 1
118 #define CP0MVPCo_EVP 0
119 int32_t CP0_MVPConf0
;
120 #define CP0MVPC0_M 31
121 #define CP0MVPC0_TLBS 29
122 #define CP0MVPC0_GS 28
123 #define CP0MVPC0_PCP 27
124 #define CP0MVPC0_PTLBE 16
125 #define CP0MVPC0_TCA 15
126 #define CP0MVPC0_PVPE 10
127 #define CP0MVPC0_PTC 0
128 int32_t CP0_MVPConf1
;
129 #define CP0MVPC1_CIM 31
130 #define CP0MVPC1_CIF 30
131 #define CP0MVPC1_PCX 20
132 #define CP0MVPC1_PCP2 10
133 #define CP0MVPC1_PCP1 0
136 typedef struct mips_def_t mips_def_t
;
138 #define MIPS_SHADOW_SET_MAX 16
139 #define MIPS_TC_MAX 5
140 #define MIPS_DSP_ACC 4
142 typedef struct CPUMIPSState CPUMIPSState
;
143 struct CPUMIPSState
{
144 /* General integer registers */
145 target_ulong gpr
[MIPS_SHADOW_SET_MAX
][32];
146 /* Special registers */
147 target_ulong PC
[MIPS_TC_MAX
];
148 #if TARGET_LONG_BITS > HOST_LONG_BITS
152 target_ulong HI
[MIPS_TC_MAX
][MIPS_DSP_ACC
];
153 target_ulong LO
[MIPS_TC_MAX
][MIPS_DSP_ACC
];
154 target_ulong ACX
[MIPS_TC_MAX
][MIPS_DSP_ACC
];
155 target_ulong DSPControl
[MIPS_TC_MAX
];
157 CPUMIPSMVPContext
*mvp
;
158 CPUMIPSTLBContext
*tlb
;
159 CPUMIPSFPUContext
*fpu
;
161 target_ulong
*current_tc_gprs
;
162 target_ulong
*current_tc_hi
;
165 target_ulong SEGMask
;
170 /* CP0_MVP* are per MVP registers. */
172 int32_t CP0_VPEControl
;
173 #define CP0VPECo_YSI 21
174 #define CP0VPECo_GSI 20
175 #define CP0VPECo_EXCPT 16
176 #define CP0VPECo_TE 15
177 #define CP0VPECo_TargTC 0
178 int32_t CP0_VPEConf0
;
179 #define CP0VPEC0_M 31
180 #define CP0VPEC0_XTC 21
181 #define CP0VPEC0_TCS 19
182 #define CP0VPEC0_SCS 18
183 #define CP0VPEC0_DSC 17
184 #define CP0VPEC0_ICS 16
185 #define CP0VPEC0_MVP 1
186 #define CP0VPEC0_VPA 0
187 int32_t CP0_VPEConf1
;
188 #define CP0VPEC1_NCX 20
189 #define CP0VPEC1_NCP2 10
190 #define CP0VPEC1_NCP1 0
191 target_ulong CP0_YQMask
;
192 target_ulong CP0_VPESchedule
;
193 target_ulong CP0_VPEScheFBack
;
195 #define CP0VPEOpt_IWX7 15
196 #define CP0VPEOpt_IWX6 14
197 #define CP0VPEOpt_IWX5 13
198 #define CP0VPEOpt_IWX4 12
199 #define CP0VPEOpt_IWX3 11
200 #define CP0VPEOpt_IWX2 10
201 #define CP0VPEOpt_IWX1 9
202 #define CP0VPEOpt_IWX0 8
203 #define CP0VPEOpt_DWX7 7
204 #define CP0VPEOpt_DWX6 6
205 #define CP0VPEOpt_DWX5 5
206 #define CP0VPEOpt_DWX4 4
207 #define CP0VPEOpt_DWX3 3
208 #define CP0VPEOpt_DWX2 2
209 #define CP0VPEOpt_DWX1 1
210 #define CP0VPEOpt_DWX0 0
211 target_ulong CP0_EntryLo0
;
212 int32_t CP0_TCStatus
[MIPS_TC_MAX
];
213 #define CP0TCSt_TCU3 31
214 #define CP0TCSt_TCU2 30
215 #define CP0TCSt_TCU1 29
216 #define CP0TCSt_TCU0 28
217 #define CP0TCSt_TMX 27
218 #define CP0TCSt_RNST 23
219 #define CP0TCSt_TDS 21
220 #define CP0TCSt_DT 20
221 #define CP0TCSt_DA 15
223 #define CP0TCSt_TKSU 11
224 #define CP0TCSt_IXMT 10
225 #define CP0TCSt_TASID 0
226 int32_t CP0_TCBind
[MIPS_TC_MAX
];
227 #define CP0TCBd_CurTC 21
228 #define CP0TCBd_TBE 17
229 #define CP0TCBd_CurVPE 0
230 target_ulong CP0_TCHalt
[MIPS_TC_MAX
];
231 target_ulong CP0_TCContext
[MIPS_TC_MAX
];
232 target_ulong CP0_TCSchedule
[MIPS_TC_MAX
];
233 target_ulong CP0_TCScheFBack
[MIPS_TC_MAX
];
234 target_ulong CP0_EntryLo1
;
235 target_ulong CP0_Context
;
236 int32_t CP0_PageMask
;
237 int32_t CP0_PageGrain
;
239 int32_t CP0_SRSConf0_rw_bitmask
;
240 int32_t CP0_SRSConf0
;
241 #define CP0SRSC0_M 31
242 #define CP0SRSC0_SRS3 20
243 #define CP0SRSC0_SRS2 10
244 #define CP0SRSC0_SRS1 0
245 int32_t CP0_SRSConf1_rw_bitmask
;
246 int32_t CP0_SRSConf1
;
247 #define CP0SRSC1_M 31
248 #define CP0SRSC1_SRS6 20
249 #define CP0SRSC1_SRS5 10
250 #define CP0SRSC1_SRS4 0
251 int32_t CP0_SRSConf2_rw_bitmask
;
252 int32_t CP0_SRSConf2
;
253 #define CP0SRSC2_M 31
254 #define CP0SRSC2_SRS9 20
255 #define CP0SRSC2_SRS8 10
256 #define CP0SRSC2_SRS7 0
257 int32_t CP0_SRSConf3_rw_bitmask
;
258 int32_t CP0_SRSConf3
;
259 #define CP0SRSC3_M 31
260 #define CP0SRSC3_SRS12 20
261 #define CP0SRSC3_SRS11 10
262 #define CP0SRSC3_SRS10 0
263 int32_t CP0_SRSConf4_rw_bitmask
;
264 int32_t CP0_SRSConf4
;
265 #define CP0SRSC4_SRS15 20
266 #define CP0SRSC4_SRS14 10
267 #define CP0SRSC4_SRS13 0
269 target_ulong CP0_BadVAddr
;
271 target_ulong CP0_EntryHi
;
296 #define CP0IntCtl_IPTI 29
297 #define CP0IntCtl_IPPC1 26
298 #define CP0IntCtl_VS 5
300 #define CP0SRSCtl_HSS 26
301 #define CP0SRSCtl_EICSS 18
302 #define CP0SRSCtl_ESS 12
303 #define CP0SRSCtl_PSS 6
304 #define CP0SRSCtl_CSS 0
306 #define CP0SRSMap_SSV7 28
307 #define CP0SRSMap_SSV6 24
308 #define CP0SRSMap_SSV5 20
309 #define CP0SRSMap_SSV4 16
310 #define CP0SRSMap_SSV3 12
311 #define CP0SRSMap_SSV2 8
312 #define CP0SRSMap_SSV1 4
313 #define CP0SRSMap_SSV0 0
323 #define CP0Ca_IP_mask 0x0000FF00
325 target_ulong CP0_EPC
;
369 #define CP0C3_DSPP 10
379 /* XXX: Maybe make LLAddr per-TC? */
380 target_ulong CP0_LLAddr
;
381 target_ulong CP0_WatchLo
[8];
382 int32_t CP0_WatchHi
[8];
383 target_ulong CP0_XContext
;
384 int32_t CP0_Framemask
;
388 #define CP0DB_LSNM 28
389 #define CP0DB_Doze 27
390 #define CP0DB_Halt 26
392 #define CP0DB_IBEP 24
393 #define CP0DB_DBEP 21
394 #define CP0DB_IEXI 20
404 int32_t CP0_Debug_tcstatus
[MIPS_TC_MAX
];
405 target_ulong CP0_DEPC
;
406 int32_t CP0_Performance0
;
411 target_ulong CP0_ErrorEPC
;
414 int interrupt_request
;
416 int user_mode_only
; /* user mode only simulation */
417 uint32_t hflags
; /* CPU State */
418 /* TMASK defines different execution modes */
419 #define MIPS_HFLAG_TMASK 0x01FF
420 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
421 /* The KSU flags must be the lowest bits in hflags. The flag order
422 must be the same as defined for CP0 Status. This allows to use
423 the bits as the value of mmu_idx. */
424 #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
425 #define MIPS_HFLAG_UM 0x0002 /* user mode flag */
426 #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
427 #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
428 #define MIPS_HFLAG_DM 0x0004 /* Debug mode */
429 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
430 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
431 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
432 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
433 /* True if the MIPS IV COP1X instructions can be used. This also
434 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
436 #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
437 #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
438 /* If translation is interrupted between the branch instruction and
439 * the delay slot, record what type of branch it is so that we can
440 * resume translation properly. It might be possible to reduce
441 * this from three bits to two. */
442 #define MIPS_HFLAG_BMASK 0x0e00
443 #define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
444 #define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
445 #define MIPS_HFLAG_BL 0x0600 /* Likely branch */
446 #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
447 target_ulong btarget
; /* Jump / branch target */
448 int bcond
; /* Branch condition (if needed) */
450 int SYNCI_Step
; /* Address step size for SYNCI */
451 int CCRes
; /* Cycle count resolution/divisor */
452 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
453 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
454 int insn_flags
; /* Supported instruction set */
456 #ifdef CONFIG_USER_ONLY
457 target_ulong tls_value
;
462 const mips_def_t
*cpu_model
;
463 #ifndef CONFIG_USER_ONLY
467 struct QEMUTimer
*timer
; /* Internal timer */
470 int no_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
471 target_ulong address
, int rw
, int access_type
);
472 int fixed_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
473 target_ulong address
, int rw
, int access_type
);
474 int r4k_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
475 target_ulong address
, int rw
, int access_type
);
476 void r4k_do_tlbwi (void);
477 void r4k_do_tlbwr (void);
478 void r4k_do_tlbp (void);
479 void r4k_do_tlbr (void);
480 void mips_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
482 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
485 #define CPUState CPUMIPSState
486 #define cpu_init cpu_mips_init
487 #define cpu_exec cpu_mips_exec
488 #define cpu_gen_code cpu_mips_gen_code
489 #define cpu_signal_handler cpu_mips_signal_handler
490 #define cpu_list mips_cpu_list
492 /* MMU modes definitions. We carefully match the indices with our
494 #define MMU_MODE0_SUFFIX _kernel
495 #define MMU_MODE1_SUFFIX _super
496 #define MMU_MODE2_SUFFIX _user
497 #define MMU_USER_IDX 2
498 static inline int cpu_mmu_index (CPUState
*env
)
500 return env
->hflags
& MIPS_HFLAG_KSU
;
505 /* Memory access type :
506 * may be needed for precise access rights control and precise exceptions.
509 /* 1 bit to define user level / supervisor access */
512 /* 1 bit to indicate direction */
514 /* Type of instruction that generated the access */
515 ACCESS_CODE
= 0x10, /* Code fetch access */
516 ACCESS_INT
= 0x20, /* Integer load/store access */
517 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
531 EXCP_EXT_INTERRUPT
, /* 8 */
547 EXCP_DWATCH
, /* 24 */
557 EXCP_LAST
= EXCP_CACHE
,
560 int cpu_mips_exec(CPUMIPSState
*s
);
561 CPUMIPSState
*cpu_mips_init(const char *cpu_model
);
562 uint32_t cpu_mips_get_clock (void);
563 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
565 #endif /* !defined (__MIPS_CPU_H__) */