1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
22 typedef struct r4k_tlb_t r4k_tlb_t
;
37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
38 struct CPUMIPSTLBContext
{
41 int (*map_address
) (struct CPUMIPSState
*env
, target_ulong
*physical
, int *prot
, target_ulong address
, int rw
, int access_type
);
42 void (*do_tlbwi
) (void);
43 void (*do_tlbwr
) (void);
44 void (*do_tlbp
) (void);
45 void (*do_tlbr
) (void);
48 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
53 typedef union fpr_t fpr_t
;
55 float64 fd
; /* ieee double precision */
56 float32 fs
[2];/* ieee single precision */
57 uint64_t d
; /* binary double fixed-point */
58 uint32_t w
[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianess
63 #if defined(WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
70 struct CPUMIPSFPUContext
{
71 /* Floating point registers */
73 float_status fp_status
;
74 /* fpu implementation/revision register (fir) */
87 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
88 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
89 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
90 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
91 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
92 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
93 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
94 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
95 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
96 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
98 #define FP_UNDERFLOW 2
101 #define FP_INVALID 16
102 #define FP_UNIMPLEMENTED 32
105 #define NB_MMU_MODES 3
107 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
108 struct CPUMIPSMVPContext
{
109 int32_t CP0_MVPControl
;
110 #define CP0MVPCo_CPA 3
111 #define CP0MVPCo_STLB 2
112 #define CP0MVPCo_VPC 1
113 #define CP0MVPCo_EVP 0
114 int32_t CP0_MVPConf0
;
115 #define CP0MVPC0_M 31
116 #define CP0MVPC0_TLBS 29
117 #define CP0MVPC0_GS 28
118 #define CP0MVPC0_PCP 27
119 #define CP0MVPC0_PTLBE 16
120 #define CP0MVPC0_TCA 15
121 #define CP0MVPC0_PVPE 10
122 #define CP0MVPC0_PTC 0
123 int32_t CP0_MVPConf1
;
124 #define CP0MVPC1_CIM 31
125 #define CP0MVPC1_CIF 30
126 #define CP0MVPC1_PCX 20
127 #define CP0MVPC1_PCP2 10
128 #define CP0MVPC1_PCP1 0
131 typedef struct mips_def_t mips_def_t
;
133 #define MIPS_SHADOW_SET_MAX 16
134 #define MIPS_TC_MAX 5
135 #define MIPS_DSP_ACC 4
137 typedef struct TCState TCState
;
139 target_ulong gpr
[32];
141 target_ulong HI
[MIPS_DSP_ACC
];
142 target_ulong LO
[MIPS_DSP_ACC
];
143 target_ulong ACX
[MIPS_DSP_ACC
];
144 target_ulong DSPControl
;
145 int32_t CP0_TCStatus
;
146 #define CP0TCSt_TCU3 31
147 #define CP0TCSt_TCU2 30
148 #define CP0TCSt_TCU1 29
149 #define CP0TCSt_TCU0 28
150 #define CP0TCSt_TMX 27
151 #define CP0TCSt_RNST 23
152 #define CP0TCSt_TDS 21
153 #define CP0TCSt_DT 20
154 #define CP0TCSt_DA 15
156 #define CP0TCSt_TKSU 11
157 #define CP0TCSt_IXMT 10
158 #define CP0TCSt_TASID 0
160 #define CP0TCBd_CurTC 21
161 #define CP0TCBd_TBE 17
162 #define CP0TCBd_CurVPE 0
163 target_ulong CP0_TCHalt
;
164 target_ulong CP0_TCContext
;
165 target_ulong CP0_TCSchedule
;
166 target_ulong CP0_TCScheFBack
;
167 int32_t CP0_Debug_tcstatus
;
170 typedef struct CPUMIPSState CPUMIPSState
;
171 struct CPUMIPSState
{
174 /* temporary hack for FP globals */
175 #ifndef USE_HOST_FLOAT_REGS
180 CPUMIPSMVPContext
*mvp
;
181 CPUMIPSTLBContext
*tlb
;
182 CPUMIPSFPUContext
*fpu
;
186 target_ulong SEGMask
;
191 /* CP0_MVP* are per MVP registers. */
193 int32_t CP0_VPEControl
;
194 #define CP0VPECo_YSI 21
195 #define CP0VPECo_GSI 20
196 #define CP0VPECo_EXCPT 16
197 #define CP0VPECo_TE 15
198 #define CP0VPECo_TargTC 0
199 int32_t CP0_VPEConf0
;
200 #define CP0VPEC0_M 31
201 #define CP0VPEC0_XTC 21
202 #define CP0VPEC0_TCS 19
203 #define CP0VPEC0_SCS 18
204 #define CP0VPEC0_DSC 17
205 #define CP0VPEC0_ICS 16
206 #define CP0VPEC0_MVP 1
207 #define CP0VPEC0_VPA 0
208 int32_t CP0_VPEConf1
;
209 #define CP0VPEC1_NCX 20
210 #define CP0VPEC1_NCP2 10
211 #define CP0VPEC1_NCP1 0
212 target_ulong CP0_YQMask
;
213 target_ulong CP0_VPESchedule
;
214 target_ulong CP0_VPEScheFBack
;
216 #define CP0VPEOpt_IWX7 15
217 #define CP0VPEOpt_IWX6 14
218 #define CP0VPEOpt_IWX5 13
219 #define CP0VPEOpt_IWX4 12
220 #define CP0VPEOpt_IWX3 11
221 #define CP0VPEOpt_IWX2 10
222 #define CP0VPEOpt_IWX1 9
223 #define CP0VPEOpt_IWX0 8
224 #define CP0VPEOpt_DWX7 7
225 #define CP0VPEOpt_DWX6 6
226 #define CP0VPEOpt_DWX5 5
227 #define CP0VPEOpt_DWX4 4
228 #define CP0VPEOpt_DWX3 3
229 #define CP0VPEOpt_DWX2 2
230 #define CP0VPEOpt_DWX1 1
231 #define CP0VPEOpt_DWX0 0
232 target_ulong CP0_EntryLo0
;
233 target_ulong CP0_EntryLo1
;
234 target_ulong CP0_Context
;
235 int32_t CP0_PageMask
;
236 int32_t CP0_PageGrain
;
238 int32_t CP0_SRSConf0_rw_bitmask
;
239 int32_t CP0_SRSConf0
;
240 #define CP0SRSC0_M 31
241 #define CP0SRSC0_SRS3 20
242 #define CP0SRSC0_SRS2 10
243 #define CP0SRSC0_SRS1 0
244 int32_t CP0_SRSConf1_rw_bitmask
;
245 int32_t CP0_SRSConf1
;
246 #define CP0SRSC1_M 31
247 #define CP0SRSC1_SRS6 20
248 #define CP0SRSC1_SRS5 10
249 #define CP0SRSC1_SRS4 0
250 int32_t CP0_SRSConf2_rw_bitmask
;
251 int32_t CP0_SRSConf2
;
252 #define CP0SRSC2_M 31
253 #define CP0SRSC2_SRS9 20
254 #define CP0SRSC2_SRS8 10
255 #define CP0SRSC2_SRS7 0
256 int32_t CP0_SRSConf3_rw_bitmask
;
257 int32_t CP0_SRSConf3
;
258 #define CP0SRSC3_M 31
259 #define CP0SRSC3_SRS12 20
260 #define CP0SRSC3_SRS11 10
261 #define CP0SRSC3_SRS10 0
262 int32_t CP0_SRSConf4_rw_bitmask
;
263 int32_t CP0_SRSConf4
;
264 #define CP0SRSC4_SRS15 20
265 #define CP0SRSC4_SRS14 10
266 #define CP0SRSC4_SRS13 0
268 target_ulong CP0_BadVAddr
;
270 target_ulong CP0_EntryHi
;
295 #define CP0IntCtl_IPTI 29
296 #define CP0IntCtl_IPPC1 26
297 #define CP0IntCtl_VS 5
299 #define CP0SRSCtl_HSS 26
300 #define CP0SRSCtl_EICSS 18
301 #define CP0SRSCtl_ESS 12
302 #define CP0SRSCtl_PSS 6
303 #define CP0SRSCtl_CSS 0
305 #define CP0SRSMap_SSV7 28
306 #define CP0SRSMap_SSV6 24
307 #define CP0SRSMap_SSV5 20
308 #define CP0SRSMap_SSV4 16
309 #define CP0SRSMap_SSV3 12
310 #define CP0SRSMap_SSV2 8
311 #define CP0SRSMap_SSV1 4
312 #define CP0SRSMap_SSV0 0
322 #define CP0Ca_IP_mask 0x0000FF00
324 target_ulong CP0_EPC
;
368 #define CP0C3_DSPP 10
378 /* XXX: Maybe make LLAddr per-TC? */
379 target_ulong CP0_LLAddr
;
380 target_ulong CP0_WatchLo
[8];
381 int32_t CP0_WatchHi
[8];
382 target_ulong CP0_XContext
;
383 int32_t CP0_Framemask
;
387 #define CP0DB_LSNM 28
388 #define CP0DB_Doze 27
389 #define CP0DB_Halt 26
391 #define CP0DB_IBEP 24
392 #define CP0DB_DBEP 21
393 #define CP0DB_IEXI 20
403 target_ulong CP0_DEPC
;
404 int32_t CP0_Performance0
;
409 target_ulong CP0_ErrorEPC
;
411 /* We waste some space so we can handle shadow registers like TCs. */
412 TCState tcs
[MIPS_SHADOW_SET_MAX
];
415 uint32_t hflags
; /* CPU State */
416 /* TMASK defines different execution modes */
417 #define MIPS_HFLAG_TMASK 0x01FF
418 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
419 /* The KSU flags must be the lowest bits in hflags. The flag order
420 must be the same as defined for CP0 Status. This allows to use
421 the bits as the value of mmu_idx. */
422 #define MIPS_HFLAG_KSU 0x0003 /* kernel/supervisor/user mode mask */
423 #define MIPS_HFLAG_UM 0x0002 /* user mode flag */
424 #define MIPS_HFLAG_SM 0x0001 /* supervisor mode flag */
425 #define MIPS_HFLAG_KM 0x0000 /* kernel mode flag */
426 #define MIPS_HFLAG_DM 0x0004 /* Debug mode */
427 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
428 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
429 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
430 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
431 /* True if the MIPS IV COP1X instructions can be used. This also
432 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
434 #define MIPS_HFLAG_COP1X 0x0080 /* COP1X instructions enabled */
435 #define MIPS_HFLAG_RE 0x0100 /* Reversed endianness */
436 /* If translation is interrupted between the branch instruction and
437 * the delay slot, record what type of branch it is so that we can
438 * resume translation properly. It might be possible to reduce
439 * this from three bits to two. */
440 #define MIPS_HFLAG_BMASK 0x0e00
441 #define MIPS_HFLAG_B 0x0200 /* Unconditional branch */
442 #define MIPS_HFLAG_BC 0x0400 /* Conditional branch */
443 #define MIPS_HFLAG_BL 0x0600 /* Likely branch */
444 #define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
445 target_ulong btarget
; /* Jump / branch target */
446 int bcond
; /* Branch condition (if needed) */
448 int SYNCI_Step
; /* Address step size for SYNCI */
449 int CCRes
; /* Cycle count resolution/divisor */
450 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
451 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
452 int insn_flags
; /* Supported instruction set */
454 #ifdef CONFIG_USER_ONLY
455 target_ulong tls_value
;
460 const mips_def_t
*cpu_model
;
461 #ifndef CONFIG_USER_ONLY
465 struct QEMUTimer
*timer
; /* Internal timer */
468 int no_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
469 target_ulong address
, int rw
, int access_type
);
470 int fixed_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
471 target_ulong address
, int rw
, int access_type
);
472 int r4k_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
473 target_ulong address
, int rw
, int access_type
);
474 void r4k_do_tlbwi (void);
475 void r4k_do_tlbwr (void);
476 void r4k_do_tlbp (void);
477 void r4k_do_tlbr (void);
478 void mips_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
480 void do_unassigned_access(target_phys_addr_t addr
, int is_write
, int is_exec
,
483 #define CPUState CPUMIPSState
484 #define cpu_init cpu_mips_init
485 #define cpu_exec cpu_mips_exec
486 #define cpu_gen_code cpu_mips_gen_code
487 #define cpu_signal_handler cpu_mips_signal_handler
488 #define cpu_list mips_cpu_list
490 #define CPU_SAVE_VERSION 3
492 /* MMU modes definitions. We carefully match the indices with our
494 #define MMU_MODE0_SUFFIX _kernel
495 #define MMU_MODE1_SUFFIX _super
496 #define MMU_MODE2_SUFFIX _user
497 #define MMU_USER_IDX 2
498 static inline int cpu_mmu_index (CPUState
*env
)
500 return env
->hflags
& MIPS_HFLAG_KSU
;
503 #if defined(CONFIG_USER_ONLY)
504 static inline void cpu_clone_regs(CPUState
*env
, target_ulong newsp
)
507 env
->active_tc
.gpr
[29] = newsp
;
508 env
->active_tc
.gpr
[7] = 0;
509 env
->active_tc
.gpr
[2] = 0;
515 /* Memory access type :
516 * may be needed for precise access rights control and precise exceptions.
519 /* 1 bit to define user level / supervisor access */
522 /* 1 bit to indicate direction */
524 /* Type of instruction that generated the access */
525 ACCESS_CODE
= 0x10, /* Code fetch access */
526 ACCESS_INT
= 0x20, /* Integer load/store access */
527 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
541 EXCP_EXT_INTERRUPT
, /* 8 */
557 EXCP_DWATCH
, /* 24 */
567 EXCP_LAST
= EXCP_CACHE
,
570 int cpu_mips_exec(CPUMIPSState
*s
);
571 CPUMIPSState
*cpu_mips_init(const char *cpu_model
);
572 uint32_t cpu_mips_get_clock (void);
573 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
575 #define CPU_PC_FROM_TB(env, tb) do { \
576 env->active_tc.PC = tb->pc; \
577 env->hflags &= ~MIPS_HFLAG_BMASK; \
578 env->hflags |= tb->flags & MIPS_HFLAG_BMASK; \
581 #endif /* !defined (__MIPS_CPU_H__) */