1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
11 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
12 // XXX: move that elsewhere
13 #if defined(HOST_SOLARIS) && SOLARISREV < 10
14 typedef unsigned char uint_fast8_t;
15 typedef unsigned int uint_fast16_t;
18 typedef union fpr_t fpr_t
;
20 float64 fd
; /* ieee double precision */
21 float32 fs
[2];/* ieee single precision */
22 uint64_t d
; /* binary single fixed-point */
23 uint32_t w
[2]; /* binary single fixed-point */
25 /* define FP_ENDIAN_IDX to access the same location
26 * in the fpr_t union regardless of the host endianess
28 #if defined(WORDS_BIGENDIAN)
29 # define FP_ENDIAN_IDX 1
31 # define FP_ENDIAN_IDX 0
34 #if defined(MIPS_USES_R4K_TLB)
35 typedef struct tlb_t tlb_t
;
52 typedef struct CPUMIPSState CPUMIPSState
;
54 /* General integer registers */
56 /* Special registers */
60 #if defined(MIPS_USES_FPU)
61 /* Floating point registers */
63 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
64 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
65 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
66 #define FPR_D(cpu, n) (FPR(cpu, n)->d)
67 #define FPR_W(cpu, n) (FPR(cpu, n)->w[((n) & 1) ^ FP_ENDIAN_IDX])
69 #ifndef USE_HOST_FLOAT_REGS
74 float_status fp_status
;
75 /* fpu implementation/revision register */
79 #define SET_FP_COND(reg) do { (reg) |= (1<<23); } while(0)
80 #define CLEAR_FP_COND(reg) do { (reg) &= ~(1<<23); } while(0)
81 #define IS_FP_COND_SET(reg) (((reg) & (1<<23)) != 0)
82 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
83 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
84 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
85 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v) << 12); } while(0)
86 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v) << 7); } while(0)
87 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v) << 2); } while(0)
89 #define FP_UNDERFLOW 2
93 #define FP_UNIMPLEMENTED 32
96 #if defined(MIPS_USES_R4K_TLB)
97 tlb_t tlb
[MIPS_TLB_MAX
];
102 uint32_t CP0_EntryLo0
;
103 uint32_t CP0_EntryLo1
;
104 uint32_t CP0_Context
;
105 uint32_t CP0_PageMask
;
107 uint32_t CP0_BadVAddr
;
109 uint32_t CP0_EntryHi
;
110 uint32_t CP0_Compare
;
132 uint32_t CP0_Config0
;
144 uint32_t CP0_Config1
;
158 uint32_t CP0_WatchLo
;
159 uint32_t CP0_WatchHi
;
163 #define CP0DB_LSNM 28
164 #define CP0DB_Doze 27
165 #define CP0DB_Halt 26
167 #define CP0DB_IBEP 24
168 #define CP0DB_DBEP 21
169 #define CP0DB_IEXI 20
182 uint32_t CP0_ErrorEPC
;
185 int interrupt_request
;
189 int user_mode_only
; /* user mode only simulation */
190 uint32_t hflags
; /* CPU State */
191 /* TMASK defines different execution modes */
192 #define MIPS_HFLAG_TMASK 0x007F
193 #define MIPS_HFLAG_MODE 0x001F /* execution modes */
194 #define MIPS_HFLAG_UM 0x0001 /* user mode */
195 #define MIPS_HFLAG_ERL 0x0002 /* Error mode */
196 #define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
197 #define MIPS_HFLAG_DM 0x0008 /* Debug mode */
198 #define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
199 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
200 /* If translation is interrupted between the branch instruction and
201 * the delay slot, record what type of branch it is so that we can
202 * resume translation properly. It might be possible to reduce
203 * this from three bits to two. */
204 #define MIPS_HFLAG_BMASK 0x0380
205 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
206 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
207 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
208 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
209 target_ulong btarget
; /* Jump / branch target */
210 int bcond
; /* Branch condition (if needed) */
212 int halted
; /* TRUE if the CPU is in suspend state */
217 const char *kernel_filename
;
218 const char *kernel_cmdline
;
219 const char *initrd_filename
;
221 struct QEMUTimer
*timer
; /* Internal timer */
226 /* Memory access type :
227 * may be needed for precise access rights control and precise exceptions.
230 /* 1 bit to define user level / supervisor access */
233 /* 1 bit to indicate direction */
235 /* Type of instruction that generated the access */
236 ACCESS_CODE
= 0x10, /* Code fetch access */
237 ACCESS_INT
= 0x20, /* Integer load/store access */
238 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
274 EXCP_MTCP0
= 0x104, /* mtmsr instruction: */
275 /* may change privilege level */
276 EXCP_BRANCH
= 0x108, /* branch instruction */
277 EXCP_ERET
= 0x10C, /* return from interrupt */
278 EXCP_SYSCALL_USER
= 0x110, /* System call in user mode only */
282 int cpu_mips_exec(CPUMIPSState
*s
);
283 CPUMIPSState
*cpu_mips_init(void);
284 uint32_t cpu_mips_get_clock (void);
286 #endif /* !defined (__MIPS_CPU_H__) */