1 #if !defined (__MIPS_CPU_H__)
4 #define TARGET_HAS_ICE 1
6 #define ELF_MACHINE EM_MIPS
11 #include "softfloat.h"
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
22 typedef struct r4k_tlb_t r4k_tlb_t
;
37 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext
;
38 struct CPUMIPSTLBContext
{
41 int (*map_address
) (struct CPUMIPSState
*env
, target_ulong
*physical
, int *prot
, target_ulong address
, int rw
, int access_type
);
42 void (*do_tlbwi
) (void);
43 void (*do_tlbwr
) (void);
44 void (*do_tlbp
) (void);
45 void (*do_tlbr
) (void);
48 r4k_tlb_t tlb
[MIPS_TLB_MAX
];
53 typedef union fpr_t fpr_t
;
55 float64 fd
; /* ieee double precision */
56 float32 fs
[2];/* ieee single precision */
57 uint64_t d
; /* binary double fixed-point */
58 uint32_t w
[2]; /* binary single fixed-point */
60 /* define FP_ENDIAN_IDX to access the same location
61 * in the fpr_t union regardless of the host endianess
63 #if defined(WORDS_BIGENDIAN)
64 # define FP_ENDIAN_IDX 1
66 # define FP_ENDIAN_IDX 0
69 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext
;
70 struct CPUMIPSFPUContext
{
71 /* Floating point registers */
73 #ifndef USE_HOST_FLOAT_REGS
78 float_status fp_status
;
79 /* fpu implementation/revision register (fir) */
92 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
93 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
94 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
95 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
96 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
97 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
98 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
99 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
100 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
101 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
103 #define FP_UNDERFLOW 2
104 #define FP_OVERFLOW 4
106 #define FP_INVALID 16
107 #define FP_UNIMPLEMENTED 32
110 #define NB_MMU_MODES 2
112 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext
;
113 struct CPUMIPSMVPContext
{
114 int32_t CP0_MVPControl
;
115 #define CP0MVPCo_CPA 3
116 #define CP0MVPCo_STLB 2
117 #define CP0MVPCo_VPC 1
118 #define CP0MVPCo_EVP 0
119 int32_t CP0_MVPConf0
;
120 #define CP0MVPC0_M 31
121 #define CP0MVPC0_TLBS 29
122 #define CP0MVPC0_GS 28
123 #define CP0MVPC0_PCP 27
124 #define CP0MVPC0_PTLBE 16
125 #define CP0MVPC0_TCA 15
126 #define CP0MVPC0_PVPE 10
127 #define CP0MVPC0_PTC 0
128 int32_t CP0_MVPConf1
;
129 #define CP0MVPC1_CIM 31
130 #define CP0MVPC1_CIF 30
131 #define CP0MVPC1_PCX 20
132 #define CP0MVPC1_PCP2 10
133 #define CP0MVPC1_PCP1 0
136 typedef struct mips_def_t mips_def_t
;
138 #define MIPS_SHADOW_SET_MAX 16
139 #define MIPS_TC_MAX 5
140 #define MIPS_DSP_ACC 4
142 typedef struct CPUMIPSState CPUMIPSState
;
143 struct CPUMIPSState
{
144 /* General integer registers */
145 target_ulong gpr
[32][MIPS_SHADOW_SET_MAX
];
146 /* Special registers */
147 target_ulong PC
[MIPS_TC_MAX
];
148 #if TARGET_LONG_BITS > HOST_LONG_BITS
153 target_ulong HI
[MIPS_DSP_ACC
][MIPS_TC_MAX
];
154 target_ulong LO
[MIPS_DSP_ACC
][MIPS_TC_MAX
];
155 target_ulong ACX
[MIPS_DSP_ACC
][MIPS_TC_MAX
];
156 target_ulong DSPControl
[MIPS_TC_MAX
];
158 CPUMIPSMVPContext
*mvp
;
159 CPUMIPSTLBContext
*tlb
;
160 CPUMIPSFPUContext
*fpu
;
164 target_ulong SEGMask
;
167 /* CP0_MVP* are per MVP registers. */
169 int32_t CP0_VPEControl
;
170 #define CP0VPECo_YSI 21
171 #define CP0VPECo_GSI 20
172 #define CP0VPECo_EXCPT 16
173 #define CP0VPECo_TE 15
174 #define CP0VPECo_TargTC 0
175 int32_t CP0_VPEConf0
;
176 #define CP0VPEC0_M 31
177 #define CP0VPEC0_XTC 21
178 #define CP0VPEC0_TCS 19
179 #define CP0VPEC0_SCS 18
180 #define CP0VPEC0_DSC 17
181 #define CP0VPEC0_ICS 16
182 #define CP0VPEC0_MVP 1
183 #define CP0VPEC0_VPA 0
184 int32_t CP0_VPEConf1
;
185 #define CP0VPEC1_NCX 20
186 #define CP0VPEC1_NCP2 10
187 #define CP0VPEC1_NCP1 0
188 target_ulong CP0_YQMask
;
189 target_ulong CP0_VPESchedule
;
190 target_ulong CP0_VPEScheFBack
;
192 #define CP0VPEOpt_IWX7 15
193 #define CP0VPEOpt_IWX6 14
194 #define CP0VPEOpt_IWX5 13
195 #define CP0VPEOpt_IWX4 12
196 #define CP0VPEOpt_IWX3 11
197 #define CP0VPEOpt_IWX2 10
198 #define CP0VPEOpt_IWX1 9
199 #define CP0VPEOpt_IWX0 8
200 #define CP0VPEOpt_DWX7 7
201 #define CP0VPEOpt_DWX6 6
202 #define CP0VPEOpt_DWX5 5
203 #define CP0VPEOpt_DWX4 4
204 #define CP0VPEOpt_DWX3 3
205 #define CP0VPEOpt_DWX2 2
206 #define CP0VPEOpt_DWX1 1
207 #define CP0VPEOpt_DWX0 0
208 target_ulong CP0_EntryLo0
;
209 int32_t CP0_TCStatus
[MIPS_TC_MAX
];
210 #define CP0TCSt_TCU3 31
211 #define CP0TCSt_TCU2 30
212 #define CP0TCSt_TCU1 29
213 #define CP0TCSt_TCU0 28
214 #define CP0TCSt_TMX 27
215 #define CP0TCSt_RNST 23
216 #define CP0TCSt_TDS 21
217 #define CP0TCSt_DT 20
218 #define CP0TCSt_DA 15
220 #define CP0TCSt_TKSU 11
221 #define CP0TCSt_IXMT 10
222 #define CP0TCSt_TASID 0
223 int32_t CP0_TCBind
[MIPS_TC_MAX
];
224 #define CP0TCBd_CurTC 21
225 #define CP0TCBd_TBE 17
226 #define CP0TCBd_CurVPE 0
227 target_ulong CP0_TCHalt
[MIPS_TC_MAX
];
228 target_ulong CP0_TCContext
[MIPS_TC_MAX
];
229 target_ulong CP0_TCSchedule
[MIPS_TC_MAX
];
230 target_ulong CP0_TCScheFBack
[MIPS_TC_MAX
];
231 target_ulong CP0_EntryLo1
;
232 target_ulong CP0_Context
;
233 int32_t CP0_PageMask
;
234 int32_t CP0_PageGrain
;
236 int32_t CP0_SRSConf0_rw_bitmask
;
237 int32_t CP0_SRSConf0
;
238 #define CP0SRSC0_M 31
239 #define CP0SRSC0_SRS3 20
240 #define CP0SRSC0_SRS2 10
241 #define CP0SRSC0_SRS1 0
242 int32_t CP0_SRSConf1_rw_bitmask
;
243 int32_t CP0_SRSConf1
;
244 #define CP0SRSC1_M 31
245 #define CP0SRSC1_SRS6 20
246 #define CP0SRSC1_SRS5 10
247 #define CP0SRSC1_SRS4 0
248 int32_t CP0_SRSConf2_rw_bitmask
;
249 int32_t CP0_SRSConf2
;
250 #define CP0SRSC2_M 31
251 #define CP0SRSC2_SRS9 20
252 #define CP0SRSC2_SRS8 10
253 #define CP0SRSC2_SRS7 0
254 int32_t CP0_SRSConf3_rw_bitmask
;
255 int32_t CP0_SRSConf3
;
256 #define CP0SRSC3_M 31
257 #define CP0SRSC3_SRS12 20
258 #define CP0SRSC3_SRS11 10
259 #define CP0SRSC3_SRS10 0
260 int32_t CP0_SRSConf4_rw_bitmask
;
261 int32_t CP0_SRSConf4
;
262 #define CP0SRSC4_SRS15 20
263 #define CP0SRSC4_SRS14 10
264 #define CP0SRSC4_SRS13 0
266 target_ulong CP0_BadVAddr
;
268 target_ulong CP0_EntryHi
;
294 #define CP0IntCtl_IPTI 29
295 #define CP0IntCtl_IPPC1 26
296 #define CP0IntCtl_VS 5
298 #define CP0SRSCtl_HSS 26
299 #define CP0SRSCtl_EICSS 18
300 #define CP0SRSCtl_ESS 12
301 #define CP0SRSCtl_PSS 6
302 #define CP0SRSCtl_CSS 0
304 #define CP0SRSMap_SSV7 28
305 #define CP0SRSMap_SSV6 24
306 #define CP0SRSMap_SSV5 20
307 #define CP0SRSMap_SSV4 16
308 #define CP0SRSMap_SSV3 12
309 #define CP0SRSMap_SSV2 8
310 #define CP0SRSMap_SSV1 4
311 #define CP0SRSMap_SSV0 0
321 #define CP0Ca_IP_mask 0x0000FF00
323 target_ulong CP0_EPC
;
367 #define CP0C3_DSPP 10
377 /* XXX: Maybe make LLAddr per-TC? */
378 target_ulong CP0_LLAddr
;
379 target_ulong CP0_WatchLo
[8];
380 int32_t CP0_WatchHi
[8];
381 target_ulong CP0_XContext
;
382 int32_t CP0_Framemask
;
386 #define CP0DB_LSNM 28
387 #define CP0DB_Doze 27
388 #define CP0DB_Halt 26
390 #define CP0DB_IBEP 24
391 #define CP0DB_DBEP 21
392 #define CP0DB_IEXI 20
402 int32_t CP0_Debug_tcstatus
[MIPS_TC_MAX
];
403 target_ulong CP0_DEPC
;
404 int32_t CP0_Performance0
;
409 target_ulong CP0_ErrorEPC
;
412 int interrupt_request
;
416 int user_mode_only
; /* user mode only simulation */
417 uint32_t hflags
; /* CPU State */
418 /* TMASK defines different execution modes */
419 #define MIPS_HFLAG_TMASK 0x00FF
420 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
421 #define MIPS_HFLAG_UM 0x0001 /* user mode */
422 #define MIPS_HFLAG_DM 0x0002 /* Debug mode */
423 #define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
424 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
425 #define MIPS_HFLAG_CP0 0x0010 /* CP0 enabled */
426 #define MIPS_HFLAG_FPU 0x0020 /* FPU enabled */
427 #define MIPS_HFLAG_F64 0x0040 /* 64-bit FPU enabled */
428 #define MIPS_HFLAG_RE 0x0080 /* Reversed endianness */
429 /* If translation is interrupted between the branch instruction and
430 * the delay slot, record what type of branch it is so that we can
431 * resume translation properly. It might be possible to reduce
432 * this from three bits to two. */
433 #define MIPS_HFLAG_BMASK 0x0700
434 #define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
435 #define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
436 #define MIPS_HFLAG_BL 0x0300 /* Likely branch */
437 #define MIPS_HFLAG_BR 0x0400 /* branch to register (can't link TB) */
438 target_ulong btarget
; /* Jump / branch target */
439 int bcond
; /* Branch condition (if needed) */
441 int halted
; /* TRUE if the CPU is in suspend state */
443 int SYNCI_Step
; /* Address step size for SYNCI */
444 int CCRes
; /* Cycle count resolution/divisor */
445 uint32_t CP0_Status_rw_bitmask
; /* Read/write bits in CP0_Status */
446 uint32_t CP0_TCStatus_rw_bitmask
; /* Read/write bits in CP0_TCStatus */
447 int insn_flags
; /* Supported instruction set */
449 #ifdef CONFIG_USER_ONLY
450 target_ulong tls_value
;
456 const char *kernel_filename
;
457 const char *kernel_cmdline
;
458 const char *initrd_filename
;
460 mips_def_t
*cpu_model
;
461 #ifndef CONFIG_USER_ONLY
465 struct QEMUTimer
*timer
; /* Internal timer */
468 int no_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
469 target_ulong address
, int rw
, int access_type
);
470 int fixed_mmu_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
471 target_ulong address
, int rw
, int access_type
);
472 int r4k_map_address (CPUMIPSState
*env
, target_ulong
*physical
, int *prot
,
473 target_ulong address
, int rw
, int access_type
);
474 void r4k_do_tlbwi (void);
475 void r4k_do_tlbwr (void);
476 void r4k_do_tlbp (void);
477 void r4k_do_tlbr (void);
478 int mips_find_by_name (const unsigned char *name
, mips_def_t
**def
);
479 void mips_cpu_list (FILE *f
, int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...));
480 int cpu_mips_register (CPUMIPSState
*env
, mips_def_t
*def
);
482 #define CPUState CPUMIPSState
483 #define cpu_init cpu_mips_init
484 #define cpu_exec cpu_mips_exec
485 #define cpu_gen_code cpu_mips_gen_code
486 #define cpu_signal_handler cpu_mips_signal_handler
487 #define cpu_list mips_cpu_list
489 /* MMU modes definitions */
490 #define MMU_MODE0_SUFFIX _kernel
491 #define MMU_MODE1_SUFFIX _user
492 #define MMU_USER_IDX 1
493 static inline int cpu_mmu_index (CPUState
*env
)
495 return (env
->hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
? 1 : 0;
500 /* Memory access type :
501 * may be needed for precise access rights control and precise exceptions.
504 /* 1 bit to define user level / supervisor access */
507 /* 1 bit to indicate direction */
509 /* Type of instruction that generated the access */
510 ACCESS_CODE
= 0x10, /* Code fetch access */
511 ACCESS_INT
= 0x20, /* Integer load/store access */
512 ACCESS_FLOAT
= 0x30, /* floating point load/store access */
550 EXCP_MTCP0
= 0x104, /* mtmsr instruction: */
551 /* may change privilege level */
552 EXCP_BRANCH
= 0x108, /* branch instruction */
553 EXCP_ERET
= 0x10C, /* return from interrupt */
554 EXCP_SYSCALL_USER
= 0x110, /* System call in user mode only */
558 int cpu_mips_exec(CPUMIPSState
*s
);
559 CPUMIPSState
*cpu_mips_init(void);
560 uint32_t cpu_mips_get_clock (void);
561 int cpu_mips_signal_handler(int host_signum
, void *pinfo
, void *puc
);
563 #endif /* !defined (__MIPS_CPU_H__) */