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Fix usermode check, thanks Aurelien Jarno.
[qemu.git] / target-mips / cpu.h
1 #if !defined (__MIPS_CPU_H__)
2 #define __MIPS_CPU_H__
3
4 #define TARGET_HAS_ICE 1
5
6 #define ELF_MACHINE EM_MIPS
7
8 #include "config.h"
9 #include "mips-defs.h"
10 #include "cpu-defs.h"
11 #include "softfloat.h"
12
13 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
14 // XXX: move that elsewhere
15 #if defined(HOST_SOLARIS) && HOST_SOLARIS < 10
16 typedef unsigned char uint_fast8_t;
17 typedef unsigned int uint_fast16_t;
18 #endif
19
20 typedef union fpr_t fpr_t;
21 union fpr_t {
22 float64 fd; /* ieee double precision */
23 float32 fs[2];/* ieee single precision */
24 uint64_t d; /* binary double fixed-point */
25 uint32_t w[2]; /* binary single fixed-point */
26 };
27 /* define FP_ENDIAN_IDX to access the same location
28 * in the fpr_t union regardless of the host endianess
29 */
30 #if defined(WORDS_BIGENDIAN)
31 # define FP_ENDIAN_IDX 1
32 #else
33 # define FP_ENDIAN_IDX 0
34 #endif
35
36 typedef struct r4k_tlb_t r4k_tlb_t;
37 struct r4k_tlb_t {
38 target_ulong VPN;
39 uint32_t PageMask;
40 uint_fast8_t ASID;
41 uint_fast16_t G:1;
42 uint_fast16_t C0:3;
43 uint_fast16_t C1:3;
44 uint_fast16_t V0:1;
45 uint_fast16_t V1:1;
46 uint_fast16_t D0:1;
47 uint_fast16_t D1:1;
48 target_ulong PFN[2];
49 };
50
51 typedef struct CPUMIPSState CPUMIPSState;
52 struct CPUMIPSState {
53 /* General integer registers */
54 target_ulong gpr[32];
55 /* Special registers */
56 target_ulong PC;
57 #if TARGET_LONG_BITS > HOST_LONG_BITS
58 target_ulong t0;
59 target_ulong t1;
60 target_ulong t2;
61 #endif
62 target_ulong HI, LO;
63 /* Floating point registers */
64 fpr_t fpr[32];
65 #ifndef USE_HOST_FLOAT_REGS
66 fpr_t ft0;
67 fpr_t ft1;
68 fpr_t ft2;
69 #endif
70 float_status fp_status;
71 /* fpu implementation/revision register (fir) */
72 uint32_t fcr0;
73 #define FCR0_F64 22
74 #define FCR0_L 21
75 #define FCR0_W 20
76 #define FCR0_3D 19
77 #define FCR0_PS 18
78 #define FCR0_D 17
79 #define FCR0_S 16
80 #define FCR0_PRID 8
81 #define FCR0_REV 0
82 /* fcsr */
83 uint32_t fcr31;
84 #define SET_FP_COND(num,env) do { ((env)->fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
85 #define CLEAR_FP_COND(num,env) do { ((env)->fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
86 #define GET_FP_COND(env) ((((env)->fcr31 >> 24) & 0xfe) | (((env)->fcr31 >> 23) & 0x1))
87 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
88 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
89 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
90 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
91 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
92 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
93 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
94 #define FP_INEXACT 1
95 #define FP_UNDERFLOW 2
96 #define FP_OVERFLOW 4
97 #define FP_DIV0 8
98 #define FP_INVALID 16
99 #define FP_UNIMPLEMENTED 32
100
101 uint32_t nb_tlb;
102 uint32_t tlb_in_use;
103 int (*map_address) (CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
104 void (*do_tlbwi) (void);
105 void (*do_tlbwr) (void);
106 void (*do_tlbp) (void);
107 void (*do_tlbr) (void);
108 union {
109 struct {
110 r4k_tlb_t tlb[MIPS_TLB_MAX];
111 } r4k;
112 } mmu;
113
114 int32_t CP0_Index;
115 int32_t CP0_Random;
116 target_ulong CP0_EntryLo0;
117 target_ulong CP0_EntryLo1;
118 target_ulong CP0_Context;
119 int32_t CP0_PageMask;
120 int32_t CP0_PageGrain;
121 int32_t CP0_Wired;
122 int32_t CP0_HWREna;
123 target_ulong CP0_BadVAddr;
124 int32_t CP0_Count;
125 target_ulong CP0_EntryHi;
126 int32_t CP0_Compare;
127 int32_t CP0_Status;
128 #define CP0St_CU3 31
129 #define CP0St_CU2 30
130 #define CP0St_CU1 29
131 #define CP0St_CU0 28
132 #define CP0St_RP 27
133 #define CP0St_FR 26
134 #define CP0St_RE 25
135 #define CP0St_MX 24
136 #define CP0St_PX 23
137 #define CP0St_BEV 22
138 #define CP0St_TS 21
139 #define CP0St_SR 20
140 #define CP0St_NMI 19
141 #define CP0St_IM 8
142 #define CP0St_KX 7
143 #define CP0St_SX 6
144 #define CP0St_UX 5
145 #define CP0St_UM 4
146 #define CP0St_R0 3
147 #define CP0St_ERL 2
148 #define CP0St_EXL 1
149 #define CP0St_IE 0
150 int32_t CP0_IntCtl;
151 int32_t CP0_SRSCtl;
152 int32_t CP0_SRSMap;
153 int32_t CP0_Cause;
154 #define CP0Ca_BD 31
155 #define CP0Ca_TI 30
156 #define CP0Ca_CE 28
157 #define CP0Ca_DC 27
158 #define CP0Ca_PCI 26
159 #define CP0Ca_IV 23
160 #define CP0Ca_WP 22
161 #define CP0Ca_IP 8
162 #define CP0Ca_IP_mask 0x0000FF00
163 #define CP0Ca_EC 2
164 target_ulong CP0_EPC;
165 int32_t CP0_PRid;
166 int32_t CP0_EBase;
167 int32_t CP0_Config0;
168 #define CP0C0_M 31
169 #define CP0C0_K23 28
170 #define CP0C0_KU 25
171 #define CP0C0_MDU 20
172 #define CP0C0_MM 17
173 #define CP0C0_BM 16
174 #define CP0C0_BE 15
175 #define CP0C0_AT 13
176 #define CP0C0_AR 10
177 #define CP0C0_MT 7
178 #define CP0C0_VI 3
179 #define CP0C0_K0 0
180 int32_t CP0_Config1;
181 #define CP0C1_M 31
182 #define CP0C1_MMU 25
183 #define CP0C1_IS 22
184 #define CP0C1_IL 19
185 #define CP0C1_IA 16
186 #define CP0C1_DS 13
187 #define CP0C1_DL 10
188 #define CP0C1_DA 7
189 #define CP0C1_C2 6
190 #define CP0C1_MD 5
191 #define CP0C1_PC 4
192 #define CP0C1_WR 3
193 #define CP0C1_CA 2
194 #define CP0C1_EP 1
195 #define CP0C1_FP 0
196 int32_t CP0_Config2;
197 #define CP0C2_M 31
198 #define CP0C2_TU 28
199 #define CP0C2_TS 24
200 #define CP0C2_TL 20
201 #define CP0C2_TA 16
202 #define CP0C2_SU 12
203 #define CP0C2_SS 8
204 #define CP0C2_SL 4
205 #define CP0C2_SA 0
206 int32_t CP0_Config3;
207 #define CP0C3_M 31
208 #define CP0C3_DSPP 10
209 #define CP0C3_LPA 7
210 #define CP0C3_VEIC 6
211 #define CP0C3_VInt 5
212 #define CP0C3_SP 4
213 #define CP0C3_MT 2
214 #define CP0C3_SM 1
215 #define CP0C3_TL 0
216 int32_t CP0_Config6;
217 int32_t CP0_Config7;
218 target_ulong CP0_LLAddr;
219 target_ulong CP0_WatchLo[8];
220 int32_t CP0_WatchHi[8];
221 target_ulong CP0_XContext;
222 int32_t CP0_Framemask;
223 int32_t CP0_Debug;
224 #define CPDB_DBD 31
225 #define CP0DB_DM 30
226 #define CP0DB_LSNM 28
227 #define CP0DB_Doze 27
228 #define CP0DB_Halt 26
229 #define CP0DB_CNT 25
230 #define CP0DB_IBEP 24
231 #define CP0DB_DBEP 21
232 #define CP0DB_IEXI 20
233 #define CP0DB_VER 15
234 #define CP0DB_DEC 10
235 #define CP0DB_SSt 8
236 #define CP0DB_DINT 5
237 #define CP0DB_DIB 4
238 #define CP0DB_DDBS 3
239 #define CP0DB_DDBL 2
240 #define CP0DB_DBp 1
241 #define CP0DB_DSS 0
242 target_ulong CP0_DEPC;
243 int32_t CP0_Performance0;
244 int32_t CP0_TagLo;
245 int32_t CP0_DataLo;
246 int32_t CP0_TagHi;
247 int32_t CP0_DataHi;
248 target_ulong CP0_ErrorEPC;
249 int32_t CP0_DESAVE;
250 /* Qemu */
251 int interrupt_request;
252 jmp_buf jmp_env;
253 int exception_index;
254 int error_code;
255 int user_mode_only; /* user mode only simulation */
256 uint32_t hflags; /* CPU State */
257 /* TMASK defines different execution modes */
258 #define MIPS_HFLAG_TMASK 0x007F
259 #define MIPS_HFLAG_MODE 0x0007 /* execution modes */
260 #define MIPS_HFLAG_UM 0x0001 /* user mode */
261 #define MIPS_HFLAG_DM 0x0002 /* Debug mode */
262 #define MIPS_HFLAG_SM 0x0004 /* Supervisor mode */
263 #define MIPS_HFLAG_64 0x0008 /* 64-bit instructions enabled */
264 #define MIPS_HFLAG_FPU 0x0010 /* FPU enabled */
265 #define MIPS_HFLAG_F64 0x0020 /* 64-bit FPU enabled */
266 #define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
267 /* If translation is interrupted between the branch instruction and
268 * the delay slot, record what type of branch it is so that we can
269 * resume translation properly. It might be possible to reduce
270 * this from three bits to two. */
271 #define MIPS_HFLAG_BMASK 0x0380
272 #define MIPS_HFLAG_B 0x0080 /* Unconditional branch */
273 #define MIPS_HFLAG_BC 0x0100 /* Conditional branch */
274 #define MIPS_HFLAG_BL 0x0180 /* Likely branch */
275 #define MIPS_HFLAG_BR 0x0200 /* branch to register (can't link TB) */
276 target_ulong btarget; /* Jump / branch target */
277 int bcond; /* Branch condition (if needed) */
278
279 int halted; /* TRUE if the CPU is in suspend state */
280
281 int SYNCI_Step; /* Address step size for SYNCI */
282 int CCRes; /* Cycle count resolution/divisor */
283 int Status_rw_bitmask; /* Read/write bits in CP0_Status */
284
285 #if defined(CONFIG_USER_ONLY)
286 target_ulong tls_value;
287 #else
288 void *irq[8];
289 #endif
290
291 CPU_COMMON
292
293 int ram_size;
294 const char *kernel_filename;
295 const char *kernel_cmdline;
296 const char *initrd_filename;
297
298 struct QEMUTimer *timer; /* Internal timer */
299 };
300
301 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
302 target_ulong address, int rw, int access_type);
303 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
304 target_ulong address, int rw, int access_type);
305 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
306 target_ulong address, int rw, int access_type);
307 void r4k_do_tlbwi (void);
308 void r4k_do_tlbwr (void);
309 void r4k_do_tlbp (void);
310 void r4k_do_tlbr (void);
311 typedef struct mips_def_t mips_def_t;
312 int mips_find_by_name (const unsigned char *name, mips_def_t **def);
313 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
314 int cpu_mips_register (CPUMIPSState *env, mips_def_t *def);
315
316 #include "cpu-all.h"
317
318 /* Memory access type :
319 * may be needed for precise access rights control and precise exceptions.
320 */
321 enum {
322 /* 1 bit to define user level / supervisor access */
323 ACCESS_USER = 0x00,
324 ACCESS_SUPER = 0x01,
325 /* 1 bit to indicate direction */
326 ACCESS_STORE = 0x02,
327 /* Type of instruction that generated the access */
328 ACCESS_CODE = 0x10, /* Code fetch access */
329 ACCESS_INT = 0x20, /* Integer load/store access */
330 ACCESS_FLOAT = 0x30, /* floating point load/store access */
331 };
332
333 /* Exceptions */
334 enum {
335 EXCP_NONE = -1,
336 EXCP_RESET = 0,
337 EXCP_SRESET,
338 EXCP_DSS,
339 EXCP_DINT,
340 EXCP_NMI,
341 EXCP_MCHECK,
342 EXCP_EXT_INTERRUPT,
343 EXCP_DFWATCH,
344 EXCP_DIB, /* 8 */
345 EXCP_IWATCH,
346 EXCP_AdEL,
347 EXCP_AdES,
348 EXCP_TLBF,
349 EXCP_IBE,
350 EXCP_DBp,
351 EXCP_SYSCALL,
352 EXCP_BREAK, /* 16 */
353 EXCP_CpU,
354 EXCP_RI,
355 EXCP_OVERFLOW,
356 EXCP_TRAP,
357 EXCP_FPE,
358 EXCP_DDBS,
359 EXCP_DWATCH,
360 EXCP_LAE, /* 24 */
361 EXCP_SAE,
362 EXCP_LTLBL,
363 EXCP_TLBL,
364 EXCP_TLBS,
365 EXCP_DBE,
366 EXCP_DDBL,
367 EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
368 /* may change privilege level */
369 EXCP_BRANCH = 0x108, /* branch instruction */
370 EXCP_ERET = 0x10C, /* return from interrupt */
371 EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
372 EXCP_FLUSH = 0x109,
373 };
374
375 int cpu_mips_exec(CPUMIPSState *s);
376 CPUMIPSState *cpu_mips_init(void);
377 uint32_t cpu_mips_get_clock (void);
378 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
379
380 #endif /* !defined (__MIPS_CPU_H__) */
Qemu copy for testing