target-mips/cpu.h

   1 #if !defined (__MIPS_CPU_H__)
   2 #define __MIPS_CPU_H__
   3
   4 #define TARGET_HAS_ICE 1
   5
   6 #define ELF_MACHINE     EM_MIPS
   7
   8 #define CPUState struct CPUMIPSState
   9
  10 #include "config.h"
  11 #include "mips-defs.h"
  12 #include "cpu-defs.h"
  13 #include "softfloat.h"
  14
  15 // uint_fast8_t and uint_fast16_t not in <sys/int_types.h>
  16 // XXX: move that elsewhere
  17 #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10
  18 typedef unsigned char           uint_fast8_t;
  19 typedef unsigned int            uint_fast16_t;
  20 #endif
  21
  22 struct CPUMIPSState;
  23
  24 typedef struct r4k_tlb a_r4k_tlb;
  25 struct r4k_tlb {
  26     target_ulong VPN;
  27     uint32_t PageMask;
  28     uint_fast8_t ASID;
  29     uint_fast16_t G:1;
  30     uint_fast16_t C0:3;
  31     uint_fast16_t C1:3;
  32     uint_fast16_t V0:1;
  33     uint_fast16_t V1:1;
  34     uint_fast16_t D0:1;
  35     uint_fast16_t D1:1;
  36     target_ulong PFN[2];
  37 };
  38
  39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  40 struct CPUMIPSTLBContext {
  41     uint32_t nb_tlb;
  42     uint32_t tlb_in_use;
  43     int (*map_address) (struct CPUMIPSState *env, target_ulong *physical, int *prot, target_ulong address, int rw, int access_type);
  44     void (*helper_tlbwi) (void);
  45     void (*helper_tlbwr) (void);
  46     void (*helper_tlbp) (void);
  47     void (*helper_tlbr) (void);
  48     union {
  49         struct {
  50             a_r4k_tlb tlb[MIPS_TLB_MAX];
  51         } r4k;
  52     } mmu;
  53 };
  54
  55 union fpr {
  56     float64  fd;   /* ieee double precision */
  57     float32  fs[2];/* ieee single precision */
  58     uint64_t d;    /* binary double fixed-point */
  59     uint32_t w[2]; /* binary single fixed-point */
  60 };
  61 /* define FP_ENDIAN_IDX to access the same location
  62  * in the fpr_t union regardless of the host endianess
  63  */
  64 #if defined(HOST_WORDS_BIGENDIAN)
  65 #  define FP_ENDIAN_IDX 1
  66 #else
  67 #  define FP_ENDIAN_IDX 0
  68 #endif
  69
  70 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  71 struct CPUMIPSFPUContext {
  72     /* Floating point registers */
  73     union fpr fpr[32];
  74     float_status fp_status;
  75     /* fpu implementation/revision register (fir) */
  76     uint32_t fcr0;
  77 #define FCR0_F64 22
  78 #define FCR0_L 21
  79 #define FCR0_W 20
  80 #define FCR0_3D 19
  81 #define FCR0_PS 18
  82 #define FCR0_D 17
  83 #define FCR0_S 16
  84 #define FCR0_PRID 8
  85 #define FCR0_REV 0
  86     /* fcsr */
  87     uint32_t fcr31;
  88 #define SET_FP_COND(num,env)     do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  89 #define CLEAR_FP_COND(num,env)   do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
  90 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
  91 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  92 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  93 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  94 #define SET_FP_CAUSE(reg,v)      do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
  95 #define SET_FP_ENABLE(reg,v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | ((v & 0x1f) << 7); } while(0)
  96 #define SET_FP_FLAGS(reg,v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | ((v & 0x1f) << 2); } while(0)
  97 #define UPDATE_FP_FLAGS(reg,v)   do { (reg) |= ((v & 0x1f) << 2); } while(0)
  98 #define FP_INEXACT        1
  99 #define FP_UNDERFLOW      2
 100 #define FP_OVERFLOW       4
 101 #define FP_DIV0           8
 102 #define FP_INVALID        16
 103 #define FP_UNIMPLEMENTED  32
 104 };
 105
 106 #define NB_MMU_MODES 3
 107
 108 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 109 struct CPUMIPSMVPContext {
 110     int32_t CP0_MVPControl;
 111 #define CP0MVPCo_CPA    3
 112 #define CP0MVPCo_STLB   2
 113 #define CP0MVPCo_VPC    1
 114 #define CP0MVPCo_EVP    0
 115     int32_t CP0_MVPConf0;
 116 #define CP0MVPC0_M      31
 117 #define CP0MVPC0_TLBS   29
 118 #define CP0MVPC0_GS     28
 119 #define CP0MVPC0_PCP    27
 120 #define CP0MVPC0_PTLBE  16
 121 #define CP0MVPC0_TCA    15
 122 #define CP0MVPC0_PVPE   10
 123 #define CP0MVPC0_PTC    0
 124     int32_t CP0_MVPConf1;
 125 #define CP0MVPC1_CIM    31
 126 #define CP0MVPC1_CIF    30
 127 #define CP0MVPC1_PCX    20
 128 #define CP0MVPC1_PCP2   10
 129 #define CP0MVPC1_PCP1   0
 130 };
 131
 132 typedef struct mips_def a_mips_def;
 133
 134 #define MIPS_SHADOW_SET_MAX 16
 135 #define MIPS_TC_MAX 5
 136 #define MIPS_FPU_MAX 1
 137 #define MIPS_DSP_ACC 4
 138
 139 typedef struct TCState TCState;
 140 struct TCState {
 141     target_ulong gpr[32];
 142     target_ulong PC;
 143     target_ulong HI[MIPS_DSP_ACC];
 144     target_ulong LO[MIPS_DSP_ACC];
 145     target_ulong ACX[MIPS_DSP_ACC];
 146     target_ulong DSPControl;
 147     int32_t CP0_TCStatus;
 148 #define CP0TCSt_TCU3    31
 149 #define CP0TCSt_TCU2    30
 150 #define CP0TCSt_TCU1    29
 151 #define CP0TCSt_TCU0    28
 152 #define CP0TCSt_TMX     27
 153 #define CP0TCSt_RNST    23
 154 #define CP0TCSt_TDS     21
 155 #define CP0TCSt_DT      20
 156 #define CP0TCSt_DA      15
 157 #define CP0TCSt_A       13
 158 #define CP0TCSt_TKSU    11
 159 #define CP0TCSt_IXMT    10
 160 #define CP0TCSt_TASID   0
 161     int32_t CP0_TCBind;
 162 #define CP0TCBd_CurTC   21
 163 #define CP0TCBd_TBE     17
 164 #define CP0TCBd_CurVPE  0
 165     target_ulong CP0_TCHalt;
 166     target_ulong CP0_TCContext;
 167     target_ulong CP0_TCSchedule;
 168     target_ulong CP0_TCScheFBack;
 169     int32_t CP0_Debug_tcstatus;
 170 };
 171
 172 typedef struct CPUMIPSState CPUMIPSState;
 173 struct CPUMIPSState {
 174     TCState active_tc;
 175     CPUMIPSFPUContext active_fpu;
 176
 177     CPUMIPSMVPContext *mvp;
 178     CPUMIPSTLBContext *tlb;
 179     uint32_t current_tc;
 180     uint32_t current_fpu;
 181
 182     uint32_t SEGBITS;
 183     uint32_t PABITS;
 184     target_ulong SEGMask;
 185     target_ulong PAMask;
 186
 187     int32_t CP0_Index;
 188     /* CP0_MVP* are per MVP registers. */
 189     int32_t CP0_Random;
 190     int32_t CP0_VPEControl;
 191 #define CP0VPECo_YSI    21
 192 #define CP0VPECo_GSI    20
 193 #define CP0VPECo_EXCPT  16
 194 #define CP0VPECo_TE     15
 195 #define CP0VPECo_TargTC 0
 196     int32_t CP0_VPEConf0;
 197 #define CP0VPEC0_M      31
 198 #define CP0VPEC0_XTC    21
 199 #define CP0VPEC0_TCS    19
 200 #define CP0VPEC0_SCS    18
 201 #define CP0VPEC0_DSC    17
 202 #define CP0VPEC0_ICS    16
 203 #define CP0VPEC0_MVP    1
 204 #define CP0VPEC0_VPA    0
 205     int32_t CP0_VPEConf1;
 206 #define CP0VPEC1_NCX    20
 207 #define CP0VPEC1_NCP2   10
 208 #define CP0VPEC1_NCP1   0
 209     target_ulong CP0_YQMask;
 210     target_ulong CP0_VPESchedule;
 211     target_ulong CP0_VPEScheFBack;
 212     int32_t CP0_VPEOpt;
 213 #define CP0VPEOpt_IWX7  15
 214 #define CP0VPEOpt_IWX6  14
 215 #define CP0VPEOpt_IWX5  13
 216 #define CP0VPEOpt_IWX4  12
 217 #define CP0VPEOpt_IWX3  11
 218 #define CP0VPEOpt_IWX2  10
 219 #define CP0VPEOpt_IWX1  9
 220 #define CP0VPEOpt_IWX0  8
 221 #define CP0VPEOpt_DWX7  7
 222 #define CP0VPEOpt_DWX6  6
 223 #define CP0VPEOpt_DWX5  5
 224 #define CP0VPEOpt_DWX4  4
 225 #define CP0VPEOpt_DWX3  3
 226 #define CP0VPEOpt_DWX2  2
 227 #define CP0VPEOpt_DWX1  1
 228 #define CP0VPEOpt_DWX0  0
 229     target_ulong CP0_EntryLo0;
 230     target_ulong CP0_EntryLo1;
 231     target_ulong CP0_Context;
 232     int32_t CP0_PageMask;
 233     int32_t CP0_PageGrain;
 234     int32_t CP0_Wired;
 235     int32_t CP0_SRSConf0_rw_bitmask;
 236     int32_t CP0_SRSConf0;
 237 #define CP0SRSC0_M      31
 238 #define CP0SRSC0_SRS3   20
 239 #define CP0SRSC0_SRS2   10
 240 #define CP0SRSC0_SRS1   0
 241     int32_t CP0_SRSConf1_rw_bitmask;
 242     int32_t CP0_SRSConf1;
 243 #define CP0SRSC1_M      31
 244 #define CP0SRSC1_SRS6   20
 245 #define CP0SRSC1_SRS5   10
 246 #define CP0SRSC1_SRS4   0
 247     int32_t CP0_SRSConf2_rw_bitmask;
 248     int32_t CP0_SRSConf2;
 249 #define CP0SRSC2_M      31
 250 #define CP0SRSC2_SRS9   20
 251 #define CP0SRSC2_SRS8   10
 252 #define CP0SRSC2_SRS7   0
 253     int32_t CP0_SRSConf3_rw_bitmask;
 254     int32_t CP0_SRSConf3;
 255 #define CP0SRSC3_M      31
 256 #define CP0SRSC3_SRS12  20
 257 #define CP0SRSC3_SRS11  10
 258 #define CP0SRSC3_SRS10  0
 259     int32_t CP0_SRSConf4_rw_bitmask;
 260     int32_t CP0_SRSConf4;
 261 #define CP0SRSC4_SRS15  20
 262 #define CP0SRSC4_SRS14  10
 263 #define CP0SRSC4_SRS13  0
 264     int32_t CP0_HWREna;
 265     target_ulong CP0_BadVAddr;
 266     int32_t CP0_Count;
 267     target_ulong CP0_EntryHi;
 268     int32_t CP0_Compare;
 269     int32_t CP0_Status;
 270 #define CP0St_CU3   31
 271 #define CP0St_CU2   30
 272 #define CP0St_CU1   29
 273 #define CP0St_CU0   28
 274 #define CP0St_RP    27
 275 #define CP0St_FR    26
 276 #define CP0St_RE    25
 277 #define CP0St_MX    24
 278 #define CP0St_PX    23
 279 #define CP0St_BEV   22
 280 #define CP0St_TS    21
 281 #define CP0St_SR    20
 282 #define CP0St_NMI   19
 283 #define CP0St_IM    8
 284 #define CP0St_KX    7
 285 #define CP0St_SX    6
 286 #define CP0St_UX    5
 287 #define CP0St_KSU   3
 288 #define CP0St_ERL   2
 289 #define CP0St_EXL   1
 290 #define CP0St_IE    0
 291     int32_t CP0_IntCtl;
 292 #define CP0IntCtl_IPTI 29
 293 #define CP0IntCtl_IPPC1 26
 294 #define CP0IntCtl_VS 5
 295     int32_t CP0_SRSCtl;
 296 #define CP0SRSCtl_HSS 26
 297 #define CP0SRSCtl_EICSS 18
 298 #define CP0SRSCtl_ESS 12
 299 #define CP0SRSCtl_PSS 6
 300 #define CP0SRSCtl_CSS 0
 301     int32_t CP0_SRSMap;
 302 #define CP0SRSMap_SSV7 28
 303 #define CP0SRSMap_SSV6 24
 304 #define CP0SRSMap_SSV5 20
 305 #define CP0SRSMap_SSV4 16
 306 #define CP0SRSMap_SSV3 12
 307 #define CP0SRSMap_SSV2 8
 308 #define CP0SRSMap_SSV1 4
 309 #define CP0SRSMap_SSV0 0
 310     int32_t CP0_Cause;
 311 #define CP0Ca_BD   31
 312 #define CP0Ca_TI   30
 313 #define CP0Ca_CE   28
 314 #define CP0Ca_DC   27
 315 #define CP0Ca_PCI  26
 316 #define CP0Ca_IV   23
 317 #define CP0Ca_WP   22
 318 #define CP0Ca_IP    8
 319 #define CP0Ca_IP_mask 0x0000FF00
 320 #define CP0Ca_EC    2
 321     target_ulong CP0_EPC;
 322     int32_t CP0_PRid;
 323     int32_t CP0_EBase;
 324     int32_t CP0_Config0;
 325 #define CP0C0_M    31
 326 #define CP0C0_K23  28
 327 #define CP0C0_KU   25
 328 #define CP0C0_MDU  20
 329 #define CP0C0_MM   17
 330 #define CP0C0_BM   16
 331 #define CP0C0_BE   15
 332 #define CP0C0_AT   13
 333 #define CP0C0_AR   10
 334 #define CP0C0_MT   7
 335 #define CP0C0_VI   3
 336 #define CP0C0_K0   0
 337     int32_t CP0_Config1;
 338 #define CP0C1_M    31
 339 #define CP0C1_MMU  25
 340 #define CP0C1_IS   22
 341 #define CP0C1_IL   19
 342 #define CP0C1_IA   16
 343 #define CP0C1_DS   13
 344 #define CP0C1_DL   10
 345 #define CP0C1_DA   7
 346 #define CP0C1_C2   6
 347 #define CP0C1_MD   5
 348 #define CP0C1_PC   4
 349 #define CP0C1_WR   3
 350 #define CP0C1_CA   2
 351 #define CP0C1_EP   1
 352 #define CP0C1_FP   0
 353     int32_t CP0_Config2;
 354 #define CP0C2_M    31
 355 #define CP0C2_TU   28
 356 #define CP0C2_TS   24
 357 #define CP0C2_TL   20
 358 #define CP0C2_TA   16
 359 #define CP0C2_SU   12
 360 #define CP0C2_SS   8
 361 #define CP0C2_SL   4
 362 #define CP0C2_SA   0
 363     int32_t CP0_Config3;
 364 #define CP0C3_M    31
 365 #define CP0C3_DSPP 10
 366 #define CP0C3_LPA  7
 367 #define CP0C3_VEIC 6
 368 #define CP0C3_VInt 5
 369 #define CP0C3_SP   4
 370 #define CP0C3_MT   2
 371 #define CP0C3_SM   1
 372 #define CP0C3_TL   0
 373     int32_t CP0_Config6;
 374     int32_t CP0_Config7;
 375     /* XXX: Maybe make LLAddr per-TC? */
 376     target_ulong CP0_LLAddr;
 377     target_ulong llval;
 378     target_ulong llnewval;
 379     target_ulong llreg;
 380     target_ulong CP0_WatchLo[8];
 381     int32_t CP0_WatchHi[8];
 382     target_ulong CP0_XContext;
 383     int32_t CP0_Framemask;
 384     int32_t CP0_Debug;
 385 #define CP0DB_DBD  31
 386 #define CP0DB_DM   30
 387 #define CP0DB_LSNM 28
 388 #define CP0DB_Doze 27
 389 #define CP0DB_Halt 26
 390 #define CP0DB_CNT  25
 391 #define CP0DB_IBEP 24
 392 #define CP0DB_DBEP 21
 393 #define CP0DB_IEXI 20
 394 #define CP0DB_VER  15
 395 #define CP0DB_DEC  10
 396 #define CP0DB_SSt  8
 397 #define CP0DB_DINT 5
 398 #define CP0DB_DIB  4
 399 #define CP0DB_DDBS 3
 400 #define CP0DB_DDBL 2
 401 #define CP0DB_DBp  1
 402 #define CP0DB_DSS  0
 403     target_ulong CP0_DEPC;
 404     int32_t CP0_Performance0;
 405     int32_t CP0_TagLo;
 406     int32_t CP0_DataLo;
 407     int32_t CP0_TagHi;
 408     int32_t CP0_DataHi;
 409     target_ulong CP0_ErrorEPC;
 410     int32_t CP0_DESAVE;
 411     /* We waste some space so we can handle shadow registers like TCs. */
 412     TCState tcs[MIPS_SHADOW_SET_MAX];
 413     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 414     /* Qemu */
 415     int error_code;
 416     uint32_t hflags;    /* CPU State */
 417     /* TMASK defines different execution modes */
 418 #define MIPS_HFLAG_TMASK  0x03FF
 419 #define MIPS_HFLAG_MODE   0x0007 /* execution modes                    */
 420     /* The KSU flags must be the lowest bits in hflags. The flag order
 421        must be the same as defined for CP0 Status. This allows to use
 422        the bits as the value of mmu_idx. */
 423 #define MIPS_HFLAG_KSU    0x0003 /* kernel/supervisor/user mode mask   */
 424 #define MIPS_HFLAG_UM       0x0002 /* user mode flag */
 425 #define MIPS_HFLAG_SM       0x0001 /* supervisor mode flag */
 426 #define MIPS_HFLAG_KM       0x0000 /* kernel mode flag */
 427 #define MIPS_HFLAG_DM     0x0004 /* Debug mode                         */
 428 #define MIPS_HFLAG_64     0x0008 /* 64-bit instructions enabled        */
 429 #define MIPS_HFLAG_CP0    0x0010 /* CP0 enabled                        */
 430 #define MIPS_HFLAG_FPU    0x0020 /* FPU enabled                        */
 431 #define MIPS_HFLAG_F64    0x0040 /* 64-bit FPU enabled                 */
 432     /* True if the MIPS IV COP1X instructions can be used.  This also
 433        controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
 434        and RSQRT.D.  */
 435 #define MIPS_HFLAG_COP1X  0x0080 /* COP1X instructions enabled         */
 436 #define MIPS_HFLAG_RE     0x0100 /* Reversed endianness                */
 437 #define MIPS_HFLAG_UX     0x0200 /* 64-bit user mode                   */
 438     /* If translation is interrupted between the branch instruction and
 439      * the delay slot, record what type of branch it is so that we can
 440      * resume translation properly.  It might be possible to reduce
 441      * this from three bits to two.  */
 442 #define MIPS_HFLAG_BMASK  0x1C00
 443 #define MIPS_HFLAG_B      0x0400 /* Unconditional branch               */
 444 #define MIPS_HFLAG_BC     0x0800 /* Conditional branch                 */
 445 #define MIPS_HFLAG_BL     0x0C00 /* Likely branch                      */
 446 #define MIPS_HFLAG_BR     0x1000 /* branch to register (can't link TB) */
 447     target_ulong btarget;        /* Jump / branch target               */
 448     target_ulong bcond;          /* Branch condition (if needed)       */
 449
 450     int SYNCI_Step; /* Address step size for SYNCI */
 451     int CCRes; /* Cycle count resolution/divisor */
 452     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
 453     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
 454     int insn_flags; /* Supported instruction set */
 455
 456     target_ulong tls_value; /* For usermode emulation */
 457
 458     CPU_COMMON
 459
 460     const a_mips_def *cpu_model;
 461     void *irq[8];
 462     struct QEMUTimer *timer; /* Internal timer */
 463 };
 464
 465 int no_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 466                         target_ulong address, int rw, int access_type);
 467 int fixed_mmu_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 468                            target_ulong address, int rw, int access_type);
 469 int r4k_map_address (CPUMIPSState *env, target_ulong *physical, int *prot,
 470                      target_ulong address, int rw, int access_type);
 471 void r4k_helper_tlbwi (void);
 472 void r4k_helper_tlbwr (void);
 473 void r4k_helper_tlbp (void);
 474 void r4k_helper_tlbr (void);
 475 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 476
 477 void do_unassigned_access(a_target_phys_addr addr, int is_write, int is_exec,
 478                           int unused, int size);
 479
 480 #define cpu_init cpu_mips_init
 481 #define cpu_exec cpu_mips_exec
 482 #define cpu_gen_code cpu_mips_gen_code
 483 #define cpu_signal_handler cpu_mips_signal_handler
 484 #define cpu_list mips_cpu_list
 485
 486 #define CPU_SAVE_VERSION 3
 487
 488 /* MMU modes definitions. We carefully match the indices with our
 489    hflags layout. */
 490 #define MMU_MODE0_SUFFIX _kernel
 491 #define MMU_MODE1_SUFFIX _super
 492 #define MMU_MODE2_SUFFIX _user
 493 #define MMU_USER_IDX 2
 494 static inline int cpu_mmu_index (CPUState *env)
 495 {
 496     return env->hflags & MIPS_HFLAG_KSU;
 497 }
 498
 499 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 500 {
 501     if (newsp)
 502         env->active_tc.gpr[29] = newsp;
 503     env->active_tc.gpr[7] = 0;
 504     env->active_tc.gpr[2] = 0;
 505 }
 506
 507 #include "cpu-all.h"
 508 #include "exec-all.h"
 509
 510 /* Memory access type :
 511  * may be needed for precise access rights control and precise exceptions.
 512  */
 513 enum {
 514     /* 1 bit to define user level / supervisor access */
 515     ACCESS_USER  = 0x00,
 516     ACCESS_SUPER = 0x01,
 517     /* 1 bit to indicate direction */
 518     ACCESS_STORE = 0x02,
 519     /* Type of instruction that generated the access */
 520     ACCESS_CODE  = 0x10, /* Code fetch access                */
 521     ACCESS_INT   = 0x20, /* Integer load/store access        */
 522     ACCESS_FLOAT = 0x30, /* floating point load/store access */
 523 };
 524
 525 /* Exceptions */
 526 enum {
 527     EXCP_NONE          = -1,
 528     EXCP_RESET         = 0,
 529     EXCP_SRESET,
 530     EXCP_DSS,
 531     EXCP_DINT,
 532     EXCP_DDBL,
 533     EXCP_DDBS,
 534     EXCP_NMI,
 535     EXCP_MCHECK,
 536     EXCP_EXT_INTERRUPT, /* 8 */
 537     EXCP_DFWATCH,
 538     EXCP_DIB,
 539     EXCP_IWATCH,
 540     EXCP_AdEL,
 541     EXCP_AdES,
 542     EXCP_TLBF,
 543     EXCP_IBE,
 544     EXCP_DBp, /* 16 */
 545     EXCP_SYSCALL,
 546     EXCP_BREAK,
 547     EXCP_CpU,
 548     EXCP_RI,
 549     EXCP_OVERFLOW,
 550     EXCP_TRAP,
 551     EXCP_FPE,
 552     EXCP_DWATCH, /* 24 */
 553     EXCP_LTLBL,
 554     EXCP_TLBL,
 555     EXCP_TLBS,
 556     EXCP_DBE,
 557     EXCP_THREAD,
 558     EXCP_MDMX,
 559     EXCP_C2E,
 560     EXCP_CACHE, /* 32 */
 561
 562     EXCP_LAST = EXCP_CACHE,
 563 };
 564 /* Dummy exception for conditional stores.  */
 565 #define EXCP_SC 0x100
 566
 567 int cpu_mips_exec(CPUMIPSState *s);
 568 CPUMIPSState *cpu_mips_init(const char *cpu_model);
 569 //~ uint32_t cpu_mips_get_clock (void);
 570 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
 571
 572 /* mips_timer.c */
 573 uint32_t cpu_mips_get_random (CPUState *env);
 574 uint32_t cpu_mips_get_count (CPUState *env);
 575 void cpu_mips_store_count (CPUState *env, uint32_t value);
 576 void cpu_mips_store_compare (CPUState *env, uint32_t value);
 577 void cpu_mips_start_count(CPUState *env);
 578 void cpu_mips_stop_count(CPUState *env);
 579
 580 /* mips_int.c */
 581 void cpu_mips_update_irq (CPUState *env);
 582
 583 /* helper.c */
 584 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 585                                int mmu_idx, int is_softmmu);
 586 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
 587 void do_interrupt (CPUState *env);
 588 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
 589
 590 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 591 {
 592     env->active_tc.PC = tb->pc;
 593     env->hflags &= ~MIPS_HFLAG_BMASK;
 594     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
 595 }
 596
 597 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 598                                         target_ulong *cs_base, int *flags)
 599 {
 600     *pc = env->active_tc.PC;
 601     *cs_base = 0;
 602     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
 603 }
 604
 605 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 606 {
 607     env->tls_value = newtls;
 608 }
 609
 610 #endif /* !defined (__MIPS_CPU_H__) */