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target-mips: use DSP unions for binary DSP operators
[qemu.git] / target-mips / dsp_helper.c
1 /*
2 * MIPS ASE DSP Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 * Dongxue Zhang <elta.era@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 /* As the byte ordering doesn't matter, i.e. all columns are treated
24 identically, these unions can be used directly. */
25 typedef union {
26 uint8_t ub[4];
27 int8_t sb[4];
28 uint16_t uh[2];
29 int16_t sh[2];
30 uint32_t uw[1];
31 int32_t sw[1];
32 } DSP32Value;
33
34 typedef union {
35 uint8_t ub[8];
36 int8_t sb[8];
37 uint16_t uh[4];
38 int16_t sh[4];
39 uint32_t uw[2];
40 int32_t sw[2];
41 uint64_t ul[1];
42 int64_t sl[1];
43 } DSP64Value;
44
45 /*** MIPS DSP internal functions begin ***/
46 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
47 #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
48
49 static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
50 CPUMIPSState *env)
51 {
52 env->active_tc.DSPControl |= (target_ulong)flag << position;
53 }
54
55 static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
56 {
57 env->active_tc.DSPControl |= (target_ulong)flag << 13;
58 }
59
60 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
61 {
62 return (env->active_tc.DSPControl >> 13) & 0x01;
63 }
64
65 static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
66 {
67 uint32_t filter;
68
69 filter = ((0x01 << len) - 1) << 24;
70 filter = ~filter;
71
72 env->active_tc.DSPControl &= filter;
73 env->active_tc.DSPControl |= (target_ulong)flag << 24;
74 }
75
76 static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
77 {
78 uint32_t filter;
79
80 filter = (0x01 << len) - 1;
81
82 return (env->active_tc.DSPControl >> 24) & filter;
83 }
84
85 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
86 {
87 target_ulong dspc;
88
89 dspc = env->active_tc.DSPControl;
90 #ifndef TARGET_MIPS64
91 dspc = dspc & 0xFFFFFFC0;
92 dspc |= pos;
93 #else
94 dspc = dspc & 0xFFFFFF80;
95 dspc |= pos;
96 #endif
97 env->active_tc.DSPControl = dspc;
98 }
99
100 static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
101 {
102 target_ulong dspc;
103 uint32_t pos;
104
105 dspc = env->active_tc.DSPControl;
106
107 #ifndef TARGET_MIPS64
108 pos = dspc & 0x3F;
109 #else
110 pos = dspc & 0x7F;
111 #endif
112
113 return pos;
114 }
115
116 static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
117 {
118 env->active_tc.DSPControl &= 0xFFFFBFFF;
119 env->active_tc.DSPControl |= (target_ulong)flag << 14;
120 }
121
122 #define DO_MIPS_SAT_ABS(size) \
123 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
124 CPUMIPSState *env) \
125 { \
126 if (a == INT##size##_MIN) { \
127 set_DSPControl_overflow_flag(1, 20, env); \
128 return INT##size##_MAX; \
129 } else { \
130 return MIPSDSP_ABS(a); \
131 } \
132 }
133 DO_MIPS_SAT_ABS(8)
134 DO_MIPS_SAT_ABS(16)
135 DO_MIPS_SAT_ABS(32)
136 #undef DO_MIPS_SAT_ABS
137
138 /* get sum value */
139 static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
140 {
141 int16_t tempI;
142
143 tempI = a + b;
144
145 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x8000)) {
146 set_DSPControl_overflow_flag(1, 20, env);
147 }
148
149 return tempI;
150 }
151
152 static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
153 CPUMIPSState *env)
154 {
155 int16_t tempS;
156
157 tempS = a + b;
158
159 if (MIPSDSP_OVERFLOW(a, b, tempS, 0x8000)) {
160 if (a > 0) {
161 tempS = 0x7FFF;
162 } else {
163 tempS = 0x8000;
164 }
165 set_DSPControl_overflow_flag(1, 20, env);
166 }
167
168 return tempS;
169 }
170
171 static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
172 CPUMIPSState *env)
173 {
174 int32_t tempI;
175
176 tempI = a + b;
177
178 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x80000000)) {
179 if (a > 0) {
180 tempI = 0x7FFFFFFF;
181 } else {
182 tempI = 0x80000000;
183 }
184 set_DSPControl_overflow_flag(1, 20, env);
185 }
186
187 return tempI;
188 }
189
190 static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
191 {
192 uint16_t temp;
193
194 temp = (uint16_t)a + (uint16_t)b;
195
196 if (temp & 0x0100) {
197 set_DSPControl_overflow_flag(1, 20, env);
198 }
199
200 return temp & 0xFF;
201 }
202
203 static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
204 CPUMIPSState *env)
205 {
206 uint32_t temp;
207
208 temp = (uint32_t)a + (uint32_t)b;
209
210 if (temp & 0x00010000) {
211 set_DSPControl_overflow_flag(1, 20, env);
212 }
213
214 return temp & 0xFFFF;
215 }
216
217 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
218 CPUMIPSState *env)
219 {
220 uint8_t result;
221 uint16_t temp;
222
223 temp = (uint16_t)a + (uint16_t)b;
224 result = temp & 0xFF;
225
226 if (0x0100 & temp) {
227 result = 0xFF;
228 set_DSPControl_overflow_flag(1, 20, env);
229 }
230
231 return result;
232 }
233
234 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
235 CPUMIPSState *env)
236 {
237 uint16_t result;
238 uint32_t temp;
239
240 temp = (uint32_t)a + (uint32_t)b;
241 result = temp & 0xFFFF;
242
243 if (0x00010000 & temp) {
244 result = 0xFFFF;
245 set_DSPControl_overflow_flag(1, 20, env);
246 }
247
248 return result;
249 }
250
251 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
252 CPUMIPSState *env)
253 {
254 int64_t temp;
255 int32_t temp32, temp31, result;
256 int64_t temp_sum;
257
258 #ifndef TARGET_MIPS64
259 temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
260 (uint64_t)env->active_tc.LO[acc];
261 #else
262 temp = (uint64_t)env->active_tc.LO[acc];
263 #endif
264
265 temp_sum = (int64_t)a + temp;
266
267 temp32 = (temp_sum >> 32) & 0x01;
268 temp31 = (temp_sum >> 31) & 0x01;
269 result = temp_sum & 0xFFFFFFFF;
270
271 /* FIXME
272 This sat function may wrong, because user manual wrote:
273 temp127..0 ← temp + ( (signA) || a31..0
274 if ( temp32 ≠ temp31 ) then
275 if ( temp32 = 0 ) then
276 temp31..0 ← 0x80000000
277 else
278 temp31..0 ← 0x7FFFFFFF
279 endif
280 DSPControlouflag:16+acc ← 1
281 endif
282 */
283 if (temp32 != temp31) {
284 if (temp32 == 0) {
285 result = 0x7FFFFFFF;
286 } else {
287 result = 0x80000000;
288 }
289 set_DSPControl_overflow_flag(1, 16 + acc, env);
290 }
291
292 return result;
293 }
294
295 /* a[0] is LO, a[1] is HI. */
296 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
297 int32_t ac,
298 int64_t *a,
299 CPUMIPSState *env)
300 {
301 bool temp64;
302
303 ret[0] = env->active_tc.LO[ac] + a[0];
304 ret[1] = env->active_tc.HI[ac] + a[1];
305
306 if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
307 ((uint64_t)ret[0] < (uint64_t)a[0])) {
308 ret[1] += 1;
309 }
310 temp64 = ret[1] & 1;
311 if (temp64 != ((ret[0] >> 63) & 0x01)) {
312 if (temp64) {
313 ret[0] = (0x01ull << 63);
314 ret[1] = ~0ull;
315 } else {
316 ret[0] = (0x01ull << 63) - 1;
317 ret[1] = 0x00;
318 }
319 set_DSPControl_overflow_flag(1, 16 + ac, env);
320 }
321 }
322
323 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
324 int32_t ac,
325 int64_t *a,
326 CPUMIPSState *env)
327 {
328 bool temp64;
329
330 ret[0] = env->active_tc.LO[ac] - a[0];
331 ret[1] = env->active_tc.HI[ac] - a[1];
332
333 if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
334 ret[1] -= 1;
335 }
336 temp64 = ret[1] & 1;
337 if (temp64 != ((ret[0] >> 63) & 0x01)) {
338 if (temp64) {
339 ret[0] = (0x01ull << 63);
340 ret[1] = ~0ull;
341 } else {
342 ret[0] = (0x01ull << 63) - 1;
343 ret[1] = 0x00;
344 }
345 set_DSPControl_overflow_flag(1, 16 + ac, env);
346 }
347 }
348
349 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
350 CPUMIPSState *env)
351 {
352 int32_t temp;
353
354 temp = (int32_t)a * (int32_t)b;
355
356 if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
357 set_DSPControl_overflow_flag(1, 21, env);
358 }
359 temp &= 0x0000FFFF;
360
361 return temp;
362 }
363
364 static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
365 {
366 return a * b;
367 }
368
369 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
370 {
371 return a * b;
372 }
373
374 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
375 CPUMIPSState *env)
376 {
377 int32_t temp;
378
379 temp = (int32_t)a * (int32_t)b;
380
381 if (temp > (int)0x7FFF) {
382 temp = 0x00007FFF;
383 set_DSPControl_overflow_flag(1, 21, env);
384 } else if (temp < (int)0xffff8000) {
385 temp = 0xFFFF8000;
386 set_DSPControl_overflow_flag(1, 21, env);
387 }
388 temp &= 0x0000FFFF;
389
390 return temp;
391 }
392
393 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
394 CPUMIPSState *env)
395 {
396 int32_t temp;
397
398 if ((a == 0x8000) && (b == 0x8000)) {
399 temp = 0x7FFFFFFF;
400 set_DSPControl_overflow_flag(1, 21, env);
401 } else {
402 temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
403 }
404
405 return temp;
406 }
407
408 /* right shift */
409 static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
410 {
411 return a >> mov;
412 }
413
414 static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
415 {
416 return a >> mov;
417 }
418
419 static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
420 {
421 return a >> mov;
422 }
423
424 static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
425 {
426 return a >> mov;
427 }
428
429 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
430 {
431 return a >> mov;
432 }
433
434 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
435 {
436 int32_t temp;
437
438 temp = (int32_t)a + (int32_t)b;
439
440 return (temp >> 1) & 0xFFFF;
441 }
442
443 /* round right shift */
444 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
445 {
446 int32_t temp;
447
448 temp = (int32_t)a + (int32_t)b;
449 temp += 1;
450
451 return (temp >> 1) & 0xFFFF;
452 }
453
454 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
455 {
456 int64_t temp;
457
458 temp = (int64_t)a + (int64_t)b;
459
460 return (temp >> 1) & 0xFFFFFFFF;
461 }
462
463 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
464 {
465 int64_t temp;
466
467 temp = (int64_t)a + (int64_t)b;
468 temp += 1;
469
470 return (temp >> 1) & 0xFFFFFFFF;
471 }
472
473 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
474 {
475 uint16_t temp;
476
477 temp = (uint16_t)a + (uint16_t)b;
478
479 return (temp >> 1) & 0x00FF;
480 }
481
482 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
483 {
484 uint16_t temp;
485
486 temp = (uint16_t)a + (uint16_t)b + 1;
487
488 return (temp >> 1) & 0x00FF;
489 }
490
491 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
492 {
493 uint16_t temp;
494
495 temp = (uint16_t)a - (uint16_t)b;
496
497 return (temp >> 1) & 0x00FF;
498 }
499
500 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
501 {
502 uint16_t temp;
503
504 temp = (uint16_t)a - (uint16_t)b + 1;
505
506 return (temp >> 1) & 0x00FF;
507 }
508
509 /* 128 bits long. p[0] is LO, p[1] is HI. */
510 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
511 int32_t ac,
512 int32_t shift,
513 CPUMIPSState *env)
514 {
515 int64_t acc;
516
517 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
518 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
519 if (shift == 0) {
520 p[0] = acc << 1;
521 p[1] = (acc >> 63) & 0x01;
522 } else {
523 p[0] = acc >> (shift - 1);
524 p[1] = 0;
525 }
526 }
527
528 /* 128 bits long. p[0] is LO, p[1] is HI */
529 static inline void mipsdsp_rashift_acc(uint64_t *p,
530 uint32_t ac,
531 uint32_t shift,
532 CPUMIPSState *env)
533 {
534 uint64_t tempB, tempA;
535
536 tempB = env->active_tc.HI[ac];
537 tempA = env->active_tc.LO[ac];
538 shift = shift & 0x1F;
539
540 if (shift == 0) {
541 p[1] = tempB;
542 p[0] = tempA;
543 } else {
544 p[0] = (tempB << (64 - shift)) | (tempA >> shift);
545 p[1] = (int64_t)tempB >> shift;
546 }
547 }
548
549 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
550 static inline void mipsdsp_rndrashift_acc(uint64_t *p,
551 uint32_t ac,
552 uint32_t shift,
553 CPUMIPSState *env)
554 {
555 int64_t tempB, tempA;
556
557 tempB = env->active_tc.HI[ac];
558 tempA = env->active_tc.LO[ac];
559 shift = shift & 0x3F;
560
561 if (shift == 0) {
562 p[2] = tempB >> 63;
563 p[1] = (tempB << 1) | (tempA >> 63);
564 p[0] = tempA << 1;
565 } else {
566 p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
567 p[1] = (int64_t)tempB >> (shift - 1);
568 if (tempB >= 0) {
569 p[2] = 0x0;
570 } else {
571 p[2] = ~0ull;
572 }
573 }
574 }
575
576 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
577 CPUMIPSState *env)
578 {
579 int32_t temp;
580
581 if ((a == 0x8000) && (b == 0x8000)) {
582 temp = 0x7FFFFFFF;
583 set_DSPControl_overflow_flag(1, 16 + ac, env);
584 } else {
585 temp = ((uint32_t)a * (uint32_t)b) << 1;
586 }
587
588 return temp;
589 }
590
591 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
592 CPUMIPSState *env)
593 {
594 uint64_t temp;
595
596 if ((a == 0x80000000) && (b == 0x80000000)) {
597 temp = (0x01ull << 63) - 1;
598 set_DSPControl_overflow_flag(1, 16 + ac, env);
599 } else {
600 temp = ((uint64_t)a * (uint64_t)b) << 1;
601 }
602
603 return temp;
604 }
605
606 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
607 {
608 return (uint16_t)a * (uint16_t)b;
609 }
610
611 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
612 CPUMIPSState *env)
613 {
614 uint32_t tempI;
615
616 tempI = (uint32_t)a * (uint32_t)b;
617 if (tempI > 0x0000FFFF) {
618 tempI = 0x0000FFFF;
619 set_DSPControl_overflow_flag(1, 21, env);
620 }
621
622 return tempI & 0x0000FFFF;
623 }
624
625 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
626 {
627 return (uint64_t)a * (uint64_t)b;
628 }
629
630 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
631 CPUMIPSState *env)
632 {
633 uint32_t temp;
634
635 if ((a == 0x8000) && (b == 0x8000)) {
636 temp = 0x7FFF0000;
637 set_DSPControl_overflow_flag(1, 21, env);
638 } else {
639 temp = (a * b) << 1;
640 temp = temp + 0x00008000;
641 }
642
643 return (temp & 0xFFFF0000) >> 16;
644 }
645
646 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
647 CPUMIPSState *env)
648 {
649 int32_t temp;
650
651 if ((a == 0x8000) && (b == 0x8000)) {
652 temp = 0x7FFF0000;
653 set_DSPControl_overflow_flag(1, 21, env);
654 } else {
655 temp = ((uint32_t)a * (uint32_t)b);
656 temp = temp << 1;
657 }
658
659 return (temp >> 16) & 0x0000FFFF;
660 }
661
662 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
663 CPUMIPSState *env)
664 {
665 int64_t temp;
666
667 temp = (int32_t)a + 0x00008000;
668
669 if (a > (int)0x7fff8000) {
670 temp = 0x7FFFFFFF;
671 set_DSPControl_overflow_flag(1, 22, env);
672 }
673
674 return (temp >> 16) & 0xFFFF;
675 }
676
677 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
678 CPUMIPSState *env)
679 {
680 uint16_t mag;
681 uint32_t sign;
682
683 sign = (a >> 15) & 0x01;
684 mag = a & 0x7FFF;
685
686 if (sign == 0) {
687 if (mag > 0x7F80) {
688 set_DSPControl_overflow_flag(1, 22, env);
689 return 0xFF;
690 } else {
691 return (mag >> 7) & 0xFFFF;
692 }
693 } else {
694 set_DSPControl_overflow_flag(1, 22, env);
695 return 0x00;
696 }
697 }
698
699 static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
700 {
701 uint8_t sign;
702 uint8_t discard;
703
704 if (s == 0) {
705 return a;
706 } else {
707 sign = (a >> 7) & 0x01;
708 if (sign != 0) {
709 discard = (((0x01 << (8 - s)) - 1) << s) |
710 ((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
711 } else {
712 discard = a >> (6 - (s - 1));
713 }
714
715 if (discard != 0x00) {
716 set_DSPControl_overflow_flag(1, 22, env);
717 }
718 return a << s;
719 }
720 }
721
722 static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
723 CPUMIPSState *env)
724 {
725 uint8_t sign;
726 uint16_t discard;
727
728 if (s == 0) {
729 return a;
730 } else {
731 sign = (a >> 15) & 0x01;
732 if (sign != 0) {
733 discard = (((0x01 << (16 - s)) - 1) << s) |
734 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
735 } else {
736 discard = a >> (14 - (s - 1));
737 }
738
739 if ((discard != 0x0000) && (discard != 0xFFFF)) {
740 set_DSPControl_overflow_flag(1, 22, env);
741 }
742 return a << s;
743 }
744 }
745
746
747 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
748 CPUMIPSState *env)
749 {
750 uint32_t discard;
751
752 if (s == 0) {
753 return a;
754 } else {
755 discard = (int32_t)a >> (31 - (s - 1));
756
757 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
758 set_DSPControl_overflow_flag(1, 22, env);
759 }
760 return a << s;
761 }
762 }
763
764 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
765 CPUMIPSState *env)
766 {
767 uint8_t sign;
768 uint16_t discard;
769
770 if (s == 0) {
771 return a;
772 } else {
773 sign = (a >> 15) & 0x01;
774 if (sign != 0) {
775 discard = (((0x01 << (16 - s)) - 1) << s) |
776 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
777 } else {
778 discard = a >> (14 - (s - 1));
779 }
780
781 if ((discard != 0x0000) && (discard != 0xFFFF)) {
782 set_DSPControl_overflow_flag(1, 22, env);
783 return (sign == 0) ? 0x7FFF : 0x8000;
784 } else {
785 return a << s;
786 }
787 }
788 }
789
790 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
791 CPUMIPSState *env)
792 {
793 uint8_t sign;
794 uint32_t discard;
795
796 if (s == 0) {
797 return a;
798 } else {
799 sign = (a >> 31) & 0x01;
800 if (sign != 0) {
801 discard = (((0x01 << (32 - s)) - 1) << s) |
802 ((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
803 } else {
804 discard = a >> (30 - (s - 1));
805 }
806
807 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
808 set_DSPControl_overflow_flag(1, 22, env);
809 return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
810 } else {
811 return a << s;
812 }
813 }
814 }
815
816 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
817 {
818 uint32_t temp;
819
820 if (s == 0) {
821 temp = (uint32_t)a << 1;
822 } else {
823 temp = (int32_t)(int8_t)a >> (s - 1);
824 }
825
826 return (temp + 1) >> 1;
827 }
828
829 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
830 {
831 uint32_t temp;
832
833 if (s == 0) {
834 temp = (uint32_t)a << 1;
835 } else {
836 temp = (int32_t)(int16_t)a >> (s - 1);
837 }
838
839 return (temp + 1) >> 1;
840 }
841
842 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
843 {
844 int64_t temp;
845
846 if (s == 0) {
847 temp = (uint64_t)a << 1;
848 } else {
849 temp = (int64_t)(int32_t)a >> (s - 1);
850 }
851 temp += 1;
852
853 return (temp >> 1) & 0xFFFFFFFFull;
854 }
855
856 static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
857 {
858 int16_t temp;
859
860 temp = a - b;
861 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
862 set_DSPControl_overflow_flag(1, 20, env);
863 }
864
865 return temp;
866 }
867
868 static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
869 CPUMIPSState *env)
870 {
871 int16_t temp;
872
873 temp = a - b;
874 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
875 if (a > 0) {
876 temp = 0x7FFF;
877 } else {
878 temp = 0x8000;
879 }
880 set_DSPControl_overflow_flag(1, 20, env);
881 }
882
883 return temp;
884 }
885
886 static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
887 CPUMIPSState *env)
888 {
889 int32_t temp;
890
891 temp = a - b;
892 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
893 if (a > 0) {
894 temp = 0x7FFFFFFF;
895 } else {
896 temp = 0x80000000;
897 }
898 set_DSPControl_overflow_flag(1, 20, env);
899 }
900
901 return temp & 0xFFFFFFFFull;
902 }
903
904 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
905 {
906 int32_t temp;
907
908 temp = (int32_t)a - (int32_t)b;
909
910 return (temp >> 1) & 0x0000FFFF;
911 }
912
913 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
914 {
915 int32_t temp;
916
917 temp = (int32_t)a - (int32_t)b;
918 temp += 1;
919
920 return (temp >> 1) & 0x0000FFFF;
921 }
922
923 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
924 {
925 int64_t temp;
926
927 temp = (int64_t)a - (int64_t)b;
928
929 return (temp >> 1) & 0xFFFFFFFFull;
930 }
931
932 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
933 {
934 int64_t temp;
935
936 temp = (int64_t)a - (int64_t)b;
937 temp += 1;
938
939 return (temp >> 1) & 0xFFFFFFFFull;
940 }
941
942 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
943 CPUMIPSState *env)
944 {
945 uint8_t temp16;
946 uint32_t temp;
947
948 temp = (uint32_t)a - (uint32_t)b;
949 temp16 = (temp >> 16) & 0x01;
950 if (temp16 == 1) {
951 set_DSPControl_overflow_flag(1, 20, env);
952 }
953 return temp & 0x0000FFFF;
954 }
955
956 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
957 CPUMIPSState *env)
958 {
959 uint8_t temp16;
960 uint32_t temp;
961
962 temp = (uint32_t)a - (uint32_t)b;
963 temp16 = (temp >> 16) & 0x01;
964
965 if (temp16 == 1) {
966 temp = 0x0000;
967 set_DSPControl_overflow_flag(1, 20, env);
968 }
969
970 return temp & 0x0000FFFF;
971 }
972
973 static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
974 {
975 uint8_t temp8;
976 uint16_t temp;
977
978 temp = (uint16_t)a - (uint16_t)b;
979 temp8 = (temp >> 8) & 0x01;
980 if (temp8 == 1) {
981 set_DSPControl_overflow_flag(1, 20, env);
982 }
983
984 return temp & 0x00FF;
985 }
986
987 static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
988 {
989 uint8_t temp8;
990 uint16_t temp;
991
992 temp = (uint16_t)a - (uint16_t)b;
993 temp8 = (temp >> 8) & 0x01;
994 if (temp8 == 1) {
995 temp = 0x00;
996 set_DSPControl_overflow_flag(1, 20, env);
997 }
998
999 return temp & 0x00FF;
1000 }
1001
1002 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
1003 {
1004 int32_t temp;
1005
1006 temp = a - b;
1007 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
1008 set_DSPControl_overflow_flag(1, 20, env);
1009 }
1010
1011 return temp;
1012 }
1013
1014 static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
1015 {
1016 int32_t temp;
1017
1018 temp = a + b;
1019
1020 if (MIPSDSP_OVERFLOW(a, b, temp, 0x80000000)) {
1021 set_DSPControl_overflow_flag(1, 20, env);
1022 }
1023
1024 return temp;
1025 }
1026
1027 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
1028 {
1029 return a == b;
1030 }
1031
1032 static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
1033 {
1034 return a <= b;
1035 }
1036
1037 static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
1038 {
1039 return a < b;
1040 }
1041
1042 static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
1043 {
1044 return a == b;
1045 }
1046
1047 static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
1048 {
1049 return a <= b;
1050 }
1051
1052 static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
1053 {
1054 return a < b;
1055 }
1056 /*** MIPS DSP internal functions end ***/
1057
1058 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1059 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1060 #define MIPSDSP_HI 0xFFFF0000
1061 #define MIPSDSP_LO 0x0000FFFF
1062 #define MIPSDSP_Q3 0xFF000000
1063 #define MIPSDSP_Q2 0x00FF0000
1064 #define MIPSDSP_Q1 0x0000FF00
1065 #define MIPSDSP_Q0 0x000000FF
1066
1067 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
1068 do { \
1069 a = (num >> 24) & MIPSDSP_Q0; \
1070 b = (num >> 16) & MIPSDSP_Q0; \
1071 c = (num >> 8) & MIPSDSP_Q0; \
1072 d = num & MIPSDSP_Q0; \
1073 } while (0)
1074
1075 #define MIPSDSP_SPLIT32_16(num, a, b) \
1076 do { \
1077 a = (num >> 16) & MIPSDSP_LO; \
1078 b = num & MIPSDSP_LO; \
1079 } while (0)
1080
1081 #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
1082 (((uint32_t)a << 24) | \
1083 (((uint32_t)b << 16) | \
1084 (((uint32_t)c << 8) | \
1085 ((uint32_t)d & 0xFF)))))
1086 #define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
1087 (((uint32_t)a << 16) | \
1088 ((uint32_t)b & 0xFFFF)))
1089
1090 #ifdef TARGET_MIPS64
1091 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
1092 do { \
1093 a = (num >> 48) & MIPSDSP_LO; \
1094 b = (num >> 32) & MIPSDSP_LO; \
1095 c = (num >> 16) & MIPSDSP_LO; \
1096 d = num & MIPSDSP_LO; \
1097 } while (0)
1098
1099 #define MIPSDSP_SPLIT64_32(num, a, b) \
1100 do { \
1101 a = (num >> 32) & MIPSDSP_LLO; \
1102 b = num & MIPSDSP_LLO; \
1103 } while (0)
1104
1105 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1106 ((uint64_t)b << 32) | \
1107 ((uint64_t)c << 16) | \
1108 (uint64_t)d)
1109 #define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
1110 #endif
1111
1112 /** DSP Arithmetic Sub-class insns **/
1113 #define MIPSDSP32_BINOP(name, func, element) \
1114 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1115 { \
1116 DSP32Value ds, dt; \
1117 unsigned int i, n; \
1118 \
1119 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1120 ds.sw[0] = rs; \
1121 dt.sw[0] = rt; \
1122 \
1123 for (i = 0; i < n; i++) { \
1124 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1125 } \
1126 \
1127 return (target_long)ds.sw[0]; \
1128 }
1129 MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh);
1130 MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh);
1131 MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw);
1132 MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw);
1133 MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub);
1134 MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub);
1135 MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh);
1136 MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh);
1137 MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw);
1138 MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw);
1139 #undef MIPSDSP32_BINOP
1140
1141 #define MIPSDSP32_BINOP_ENV(name, func, element) \
1142 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1143 CPUMIPSState *env) \
1144 { \
1145 DSP32Value ds, dt; \
1146 unsigned int i, n; \
1147 \
1148 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1149 ds.sw[0] = rs; \
1150 dt.sw[0] = rt; \
1151 \
1152 for (i = 0 ; i < n ; i++) { \
1153 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1154 } \
1155 \
1156 return (target_long)ds.sw[0]; \
1157 }
1158 MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh)
1159 MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh)
1160 MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw);
1161 MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh)
1162 MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub);
1163 MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh)
1164 MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub);
1165 MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh);
1166 MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh);
1167 MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw);
1168 MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh);
1169 MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub);
1170 MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh);
1171 MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub);
1172 #undef MIPSDSP32_BINOP_ENV
1173
1174 #ifdef TARGET_MIPS64
1175 #define MIPSDSP64_BINOP(name, func, element) \
1176 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1177 { \
1178 DSP64Value ds, dt; \
1179 unsigned int i, n; \
1180 \
1181 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1182 ds.sl[0] = rs; \
1183 dt.sl[0] = rt; \
1184 \
1185 for (i = 0 ; i < n ; i++) { \
1186 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1187 } \
1188 \
1189 return ds.sl[0]; \
1190 }
1191 MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub);
1192 MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub);
1193 MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub);
1194 MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub);
1195 #undef MIPSDSP64_BINOP
1196
1197 #define MIPSDSP64_BINOP_ENV(name, func, element) \
1198 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1199 CPUMIPSState *env) \
1200 { \
1201 DSP64Value ds, dt; \
1202 unsigned int i, n; \
1203 \
1204 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1205 ds.sl[0] = rs; \
1206 dt.sl[0] = rt; \
1207 \
1208 for (i = 0 ; i < n ; i++) { \
1209 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1210 } \
1211 \
1212 return ds.sl[0]; \
1213 }
1214 MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw);
1215 MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh);
1216 MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw);
1217 MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh);
1218 MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh);
1219 MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh);
1220 MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh);
1221 MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh);
1222 MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw);
1223 MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh);
1224 MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw);
1225 MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh);
1226 MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh);
1227 MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh);
1228 MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh);
1229 MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh);
1230 #undef MIPSDSP64_BINOP_ENV
1231
1232 #endif
1233
1234 target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env)
1235 {
1236 uint32_t rd;
1237
1238 rd = mipsdsp_sat_abs32(rt, env);
1239
1240 return (target_ulong)rd;
1241 }
1242
1243
1244 #define SUBUH_QB(name, var) \
1245 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1246 { \
1247 uint8_t rs3, rs2, rs1, rs0; \
1248 uint8_t rt3, rt2, rt1, rt0; \
1249 uint8_t tempD, tempC, tempB, tempA; \
1250 \
1251 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1252 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1253 \
1254 tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
1255 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1256 tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
1257 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1258 \
1259 return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
1260 ((uint32_t)tempB << 8) | ((uint32_t)tempA); \
1261 }
1262
1263 SUBUH_QB(subuh, 0);
1264 SUBUH_QB(subuh_r, 1);
1265
1266 #undef SUBUH_QB
1267
1268 target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1269 {
1270 uint64_t temp, tempRs, tempRt;
1271 int32_t flag;
1272
1273 tempRs = (uint64_t)rs & MIPSDSP_LLO;
1274 tempRt = (uint64_t)rt & MIPSDSP_LLO;
1275
1276 temp = tempRs + tempRt;
1277 flag = (temp & 0x0100000000ull) >> 32;
1278 set_DSPControl_carryflag(flag, env);
1279
1280 return (target_long)(int32_t)(temp & MIPSDSP_LLO);
1281 }
1282
1283 target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1284 {
1285 uint32_t rd;
1286 int32_t temp32, temp31;
1287 int64_t tempL;
1288
1289 tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt +
1290 get_DSPControl_carryflag(env);
1291 temp31 = (tempL >> 31) & 0x01;
1292 temp32 = (tempL >> 32) & 0x01;
1293
1294 if (temp31 != temp32) {
1295 set_DSPControl_overflow_flag(1, 20, env);
1296 }
1297
1298 rd = tempL & MIPSDSP_LLO;
1299
1300 return (target_long)(int32_t)rd;
1301 }
1302
1303 target_ulong helper_modsub(target_ulong rs, target_ulong rt)
1304 {
1305 int32_t decr;
1306 uint16_t lastindex;
1307 target_ulong rd;
1308
1309 decr = rt & MIPSDSP_Q0;
1310 lastindex = (rt >> 8) & MIPSDSP_LO;
1311
1312 if ((rs & MIPSDSP_LLO) == 0x00000000) {
1313 rd = (target_ulong)lastindex;
1314 } else {
1315 rd = rs - decr;
1316 }
1317
1318 return rd;
1319 }
1320
1321 target_ulong helper_raddu_w_qb(target_ulong rs)
1322 {
1323 uint8_t rs3, rs2, rs1, rs0;
1324 uint16_t temp;
1325
1326 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
1327
1328 temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
1329
1330 return (target_ulong)temp;
1331 }
1332
1333 #if defined(TARGET_MIPS64)
1334 target_ulong helper_raddu_l_ob(target_ulong rs)
1335 {
1336 int i;
1337 uint16_t rs_t[8];
1338 uint64_t temp;
1339
1340 temp = 0;
1341
1342 for (i = 0; i < 8; i++) {
1343 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
1344 temp += (uint64_t)rs_t[i];
1345 }
1346
1347 return temp;
1348 }
1349 #endif
1350
1351 target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env)
1352 {
1353 uint8_t tempD, tempC, tempB, tempA;
1354
1355 MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA);
1356
1357 tempD = mipsdsp_sat_abs8(tempD, env);
1358 tempC = mipsdsp_sat_abs8(tempC, env);
1359 tempB = mipsdsp_sat_abs8(tempB, env);
1360 tempA = mipsdsp_sat_abs8(tempA, env);
1361
1362 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1363 }
1364
1365 target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env)
1366 {
1367 uint16_t tempB, tempA;
1368
1369 MIPSDSP_SPLIT32_16(rt, tempB, tempA);
1370
1371 tempB = mipsdsp_sat_abs16 (tempB, env);
1372 tempA = mipsdsp_sat_abs16 (tempA, env);
1373
1374 return MIPSDSP_RETURN32_16(tempB, tempA);
1375 }
1376
1377 #if defined(TARGET_MIPS64)
1378 target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env)
1379 {
1380 int i;
1381 int8_t temp[8];
1382 uint64_t result;
1383
1384 for (i = 0; i < 8; i++) {
1385 temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0;
1386 temp[i] = mipsdsp_sat_abs8(temp[i], env);
1387 }
1388
1389 for (i = 0; i < 8; i++) {
1390 result = (uint64_t)(uint8_t)temp[i] << (8 * i);
1391 }
1392
1393 return result;
1394 }
1395
1396 target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env)
1397 {
1398 int16_t tempD, tempC, tempB, tempA;
1399
1400 MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA);
1401
1402 tempD = mipsdsp_sat_abs16(tempD, env);
1403 tempC = mipsdsp_sat_abs16(tempC, env);
1404 tempB = mipsdsp_sat_abs16(tempB, env);
1405 tempA = mipsdsp_sat_abs16(tempA, env);
1406
1407 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1408 }
1409
1410 target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env)
1411 {
1412 int32_t tempB, tempA;
1413
1414 MIPSDSP_SPLIT64_32(rt, tempB, tempA);
1415
1416 tempB = mipsdsp_sat_abs32(tempB, env);
1417 tempA = mipsdsp_sat_abs32(tempA, env);
1418
1419 return MIPSDSP_RETURN64_32(tempB, tempA);
1420 }
1421 #endif
1422
1423 #define PRECR_QB_PH(name, a, b)\
1424 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1425 { \
1426 uint8_t tempD, tempC, tempB, tempA; \
1427 \
1428 tempD = (rs >> a) & MIPSDSP_Q0; \
1429 tempC = (rs >> b) & MIPSDSP_Q0; \
1430 tempB = (rt >> a) & MIPSDSP_Q0; \
1431 tempA = (rt >> b) & MIPSDSP_Q0; \
1432 \
1433 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1434 }
1435
1436 PRECR_QB_PH(precr, 16, 0);
1437 PRECR_QB_PH(precrq, 24, 8);
1438
1439 #undef PRECR_QB_OH
1440
1441 target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
1442 target_ulong rt)
1443 {
1444 uint16_t tempB, tempA;
1445
1446 tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
1447 tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
1448
1449 return MIPSDSP_RETURN32_16(tempB, tempA);
1450 }
1451
1452 target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
1453 target_ulong rs, target_ulong rt)
1454 {
1455 uint64_t tempB, tempA;
1456
1457 /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1458 if (sa == 0) {
1459 tempB = (rt & MIPSDSP_LO) << 1;
1460 tempA = (rs & MIPSDSP_LO) << 1;
1461 } else {
1462 tempB = ((int32_t)rt >> (sa - 1)) + 1;
1463 tempA = ((int32_t)rs >> (sa - 1)) + 1;
1464 }
1465 rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
1466
1467 return (target_long)(int32_t)rt;
1468 }
1469
1470 target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
1471 {
1472 uint16_t tempB, tempA;
1473
1474 tempB = (rs & MIPSDSP_HI) >> 16;
1475 tempA = (rt & MIPSDSP_HI) >> 16;
1476
1477 return MIPSDSP_RETURN32_16(tempB, tempA);
1478 }
1479
1480 target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
1481 CPUMIPSState *env)
1482 {
1483 uint16_t tempB, tempA;
1484
1485 tempB = mipsdsp_trunc16_sat16_round(rs, env);
1486 tempA = mipsdsp_trunc16_sat16_round(rt, env);
1487
1488 return MIPSDSP_RETURN32_16(tempB, tempA);
1489 }
1490
1491 #if defined(TARGET_MIPS64)
1492 target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
1493 {
1494 uint8_t rs6, rs4, rs2, rs0;
1495 uint8_t rt6, rt4, rt2, rt0;
1496 uint64_t temp;
1497
1498 rs6 = (rs >> 48) & MIPSDSP_Q0;
1499 rs4 = (rs >> 32) & MIPSDSP_Q0;
1500 rs2 = (rs >> 16) & MIPSDSP_Q0;
1501 rs0 = rs & MIPSDSP_Q0;
1502 rt6 = (rt >> 48) & MIPSDSP_Q0;
1503 rt4 = (rt >> 32) & MIPSDSP_Q0;
1504 rt2 = (rt >> 16) & MIPSDSP_Q0;
1505 rt0 = rt & MIPSDSP_Q0;
1506
1507 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1508 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1509 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1510 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1511
1512 return temp;
1513 }
1514
1515 #define PRECR_QH_PW(name, var) \
1516 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1517 uint32_t sa) \
1518 { \
1519 uint16_t rs3, rs2, rs1, rs0; \
1520 uint16_t rt3, rt2, rt1, rt0; \
1521 uint16_t tempD, tempC, tempB, tempA; \
1522 \
1523 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1524 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1525 \
1526 /* When sa = 0, we use rt2, rt0, rs2, rs0; \
1527 * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
1528 if (sa == 0) { \
1529 tempD = rt2 << var; \
1530 tempC = rt0 << var; \
1531 tempB = rs2 << var; \
1532 tempA = rs0 << var; \
1533 } else { \
1534 tempD = (((int16_t)rt3 >> sa) + var) >> var; \
1535 tempC = (((int16_t)rt1 >> sa) + var) >> var; \
1536 tempB = (((int16_t)rs3 >> sa) + var) >> var; \
1537 tempA = (((int16_t)rs1 >> sa) + var) >> var; \
1538 } \
1539 \
1540 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1541 }
1542
1543 PRECR_QH_PW(sra, 0);
1544 PRECR_QH_PW(sra_r, 1);
1545
1546 #undef PRECR_QH_PW
1547
1548 target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
1549 {
1550 uint8_t rs6, rs4, rs2, rs0;
1551 uint8_t rt6, rt4, rt2, rt0;
1552 uint64_t temp;
1553
1554 rs6 = (rs >> 56) & MIPSDSP_Q0;
1555 rs4 = (rs >> 40) & MIPSDSP_Q0;
1556 rs2 = (rs >> 24) & MIPSDSP_Q0;
1557 rs0 = (rs >> 8) & MIPSDSP_Q0;
1558 rt6 = (rt >> 56) & MIPSDSP_Q0;
1559 rt4 = (rt >> 40) & MIPSDSP_Q0;
1560 rt2 = (rt >> 24) & MIPSDSP_Q0;
1561 rt0 = (rt >> 8) & MIPSDSP_Q0;
1562
1563 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1564 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1565 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1566 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1567
1568 return temp;
1569 }
1570
1571 target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
1572 {
1573 uint16_t tempD, tempC, tempB, tempA;
1574
1575 tempD = (rs >> 48) & MIPSDSP_LO;
1576 tempC = (rs >> 16) & MIPSDSP_LO;
1577 tempB = (rt >> 48) & MIPSDSP_LO;
1578 tempA = (rt >> 16) & MIPSDSP_LO;
1579
1580 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1581 }
1582
1583 target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
1584 CPUMIPSState *env)
1585 {
1586 uint32_t rs2, rs0;
1587 uint32_t rt2, rt0;
1588 uint16_t tempD, tempC, tempB, tempA;
1589
1590 rs2 = (rs >> 32) & MIPSDSP_LLO;
1591 rs0 = rs & MIPSDSP_LLO;
1592 rt2 = (rt >> 32) & MIPSDSP_LLO;
1593 rt0 = rt & MIPSDSP_LLO;
1594
1595 tempD = mipsdsp_trunc16_sat16_round(rs2, env);
1596 tempC = mipsdsp_trunc16_sat16_round(rs0, env);
1597 tempB = mipsdsp_trunc16_sat16_round(rt2, env);
1598 tempA = mipsdsp_trunc16_sat16_round(rt0, env);
1599
1600 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1601 }
1602
1603 target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
1604 {
1605 uint32_t tempB, tempA;
1606
1607 tempB = (rs >> 32) & MIPSDSP_LLO;
1608 tempA = (rt >> 32) & MIPSDSP_LLO;
1609
1610 return MIPSDSP_RETURN64_32(tempB, tempA);
1611 }
1612 #endif
1613
1614 target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
1615 CPUMIPSState *env)
1616 {
1617 uint8_t tempD, tempC, tempB, tempA;
1618 uint16_t rsh, rsl, rth, rtl;
1619
1620 rsh = (rs & MIPSDSP_HI) >> 16;
1621 rsl = rs & MIPSDSP_LO;
1622 rth = (rt & MIPSDSP_HI) >> 16;
1623 rtl = rt & MIPSDSP_LO;
1624
1625 tempD = mipsdsp_sat8_reduce_precision(rsh, env);
1626 tempC = mipsdsp_sat8_reduce_precision(rsl, env);
1627 tempB = mipsdsp_sat8_reduce_precision(rth, env);
1628 tempA = mipsdsp_sat8_reduce_precision(rtl, env);
1629
1630 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1631 }
1632
1633 #if defined(TARGET_MIPS64)
1634 target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
1635 CPUMIPSState *env)
1636 {
1637 int i;
1638 uint16_t rs3, rs2, rs1, rs0;
1639 uint16_t rt3, rt2, rt1, rt0;
1640 uint8_t temp[8];
1641 uint64_t result;
1642
1643 result = 0;
1644
1645 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
1646 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
1647
1648 temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
1649 temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
1650 temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
1651 temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
1652 temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
1653 temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
1654 temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
1655 temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
1656
1657 for (i = 0; i < 8; i++) {
1658 result |= (uint64_t)temp[i] << (8 * i);
1659 }
1660
1661 return result;
1662 }
1663
1664 #define PRECEQ_PW(name, a, b) \
1665 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1666 { \
1667 uint16_t tempB, tempA; \
1668 uint32_t tempBI, tempAI; \
1669 \
1670 tempB = (rt >> a) & MIPSDSP_LO; \
1671 tempA = (rt >> b) & MIPSDSP_LO; \
1672 \
1673 tempBI = (uint32_t)tempB << 16; \
1674 tempAI = (uint32_t)tempA << 16; \
1675 \
1676 return MIPSDSP_RETURN64_32(tempBI, tempAI); \
1677 }
1678
1679 PRECEQ_PW(qhl, 48, 32);
1680 PRECEQ_PW(qhr, 16, 0);
1681 PRECEQ_PW(qhla, 48, 16);
1682 PRECEQ_PW(qhra, 32, 0);
1683
1684 #undef PRECEQ_PW
1685
1686 #endif
1687
1688 #define PRECEQU_PH(name, a, b) \
1689 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1690 { \
1691 uint16_t tempB, tempA; \
1692 \
1693 tempB = (rt >> a) & MIPSDSP_Q0; \
1694 tempA = (rt >> b) & MIPSDSP_Q0; \
1695 \
1696 tempB = tempB << 7; \
1697 tempA = tempA << 7; \
1698 \
1699 return MIPSDSP_RETURN32_16(tempB, tempA); \
1700 }
1701
1702 PRECEQU_PH(qbl, 24, 16);
1703 PRECEQU_PH(qbr, 8, 0);
1704 PRECEQU_PH(qbla, 24, 8);
1705 PRECEQU_PH(qbra, 16, 0);
1706
1707 #undef PRECEQU_PH
1708
1709 #if defined(TARGET_MIPS64)
1710 #define PRECEQU_QH(name, a, b, c, d) \
1711 target_ulong helper_precequ_qh_##name(target_ulong rt) \
1712 { \
1713 uint16_t tempD, tempC, tempB, tempA; \
1714 \
1715 tempD = (rt >> a) & MIPSDSP_Q0; \
1716 tempC = (rt >> b) & MIPSDSP_Q0; \
1717 tempB = (rt >> c) & MIPSDSP_Q0; \
1718 tempA = (rt >> d) & MIPSDSP_Q0; \
1719 \
1720 tempD = tempD << 7; \
1721 tempC = tempC << 7; \
1722 tempB = tempB << 7; \
1723 tempA = tempA << 7; \
1724 \
1725 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1726 }
1727
1728 PRECEQU_QH(obl, 56, 48, 40, 32);
1729 PRECEQU_QH(obr, 24, 16, 8, 0);
1730 PRECEQU_QH(obla, 56, 40, 24, 8);
1731 PRECEQU_QH(obra, 48, 32, 16, 0);
1732
1733 #undef PRECEQU_QH
1734
1735 #endif
1736
1737 #define PRECEU_PH(name, a, b) \
1738 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1739 { \
1740 uint16_t tempB, tempA; \
1741 \
1742 tempB = (rt >> a) & MIPSDSP_Q0; \
1743 tempA = (rt >> b) & MIPSDSP_Q0; \
1744 \
1745 return MIPSDSP_RETURN32_16(tempB, tempA); \
1746 }
1747
1748 PRECEU_PH(qbl, 24, 16);
1749 PRECEU_PH(qbr, 8, 0);
1750 PRECEU_PH(qbla, 24, 8);
1751 PRECEU_PH(qbra, 16, 0);
1752
1753 #undef PRECEU_PH
1754
1755 #if defined(TARGET_MIPS64)
1756 #define PRECEU_QH(name, a, b, c, d) \
1757 target_ulong helper_preceu_qh_##name(target_ulong rt) \
1758 { \
1759 uint16_t tempD, tempC, tempB, tempA; \
1760 \
1761 tempD = (rt >> a) & MIPSDSP_Q0; \
1762 tempC = (rt >> b) & MIPSDSP_Q0; \
1763 tempB = (rt >> c) & MIPSDSP_Q0; \
1764 tempA = (rt >> d) & MIPSDSP_Q0; \
1765 \
1766 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1767 }
1768
1769 PRECEU_QH(obl, 56, 48, 40, 32);
1770 PRECEU_QH(obr, 24, 16, 8, 0);
1771 PRECEU_QH(obla, 56, 40, 24, 8);
1772 PRECEU_QH(obra, 48, 32, 16, 0);
1773
1774 #undef PRECEU_QH
1775
1776 #endif
1777
1778 /** DSP GPR-Based Shift Sub-class insns **/
1779 #define SHIFT_QB(name, func) \
1780 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1781 { \
1782 uint8_t rt3, rt2, rt1, rt0; \
1783 \
1784 sa = sa & 0x07; \
1785 \
1786 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1787 \
1788 rt3 = mipsdsp_##func(rt3, sa); \
1789 rt2 = mipsdsp_##func(rt2, sa); \
1790 rt1 = mipsdsp_##func(rt1, sa); \
1791 rt0 = mipsdsp_##func(rt0, sa); \
1792 \
1793 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1794 }
1795
1796 #define SHIFT_QB_ENV(name, func) \
1797 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1798 CPUMIPSState *env) \
1799 { \
1800 uint8_t rt3, rt2, rt1, rt0; \
1801 \
1802 sa = sa & 0x07; \
1803 \
1804 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1805 \
1806 rt3 = mipsdsp_##func(rt3, sa, env); \
1807 rt2 = mipsdsp_##func(rt2, sa, env); \
1808 rt1 = mipsdsp_##func(rt1, sa, env); \
1809 rt0 = mipsdsp_##func(rt0, sa, env); \
1810 \
1811 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1812 }
1813
1814 SHIFT_QB_ENV(shll, lshift8);
1815 SHIFT_QB(shrl, rshift_u8);
1816
1817 SHIFT_QB(shra, rashift8);
1818 SHIFT_QB(shra_r, rnd8_rashift);
1819
1820 #undef SHIFT_QB
1821 #undef SHIFT_QB_ENV
1822
1823 #if defined(TARGET_MIPS64)
1824 #define SHIFT_OB(name, func) \
1825 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1826 { \
1827 int i; \
1828 uint8_t rt_t[8]; \
1829 uint64_t temp; \
1830 \
1831 sa = sa & 0x07; \
1832 temp = 0; \
1833 \
1834 for (i = 0; i < 8; i++) { \
1835 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1836 rt_t[i] = mipsdsp_##func(rt_t[i], sa); \
1837 temp |= (uint64_t)rt_t[i] << (8 * i); \
1838 } \
1839 \
1840 return temp; \
1841 }
1842
1843 #define SHIFT_OB_ENV(name, func) \
1844 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
1845 CPUMIPSState *env) \
1846 { \
1847 int i; \
1848 uint8_t rt_t[8]; \
1849 uint64_t temp; \
1850 \
1851 sa = sa & 0x07; \
1852 temp = 0; \
1853 \
1854 for (i = 0; i < 8; i++) { \
1855 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1856 rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \
1857 temp |= (uint64_t)rt_t[i] << (8 * i); \
1858 } \
1859 \
1860 return temp; \
1861 }
1862
1863 SHIFT_OB_ENV(shll, lshift8);
1864 SHIFT_OB(shrl, rshift_u8);
1865
1866 SHIFT_OB(shra, rashift8);
1867 SHIFT_OB(shra_r, rnd8_rashift);
1868
1869 #undef SHIFT_OB
1870 #undef SHIFT_OB_ENV
1871
1872 #endif
1873
1874 #define SHIFT_PH(name, func) \
1875 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
1876 CPUMIPSState *env) \
1877 { \
1878 uint16_t rth, rtl; \
1879 \
1880 sa = sa & 0x0F; \
1881 \
1882 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1883 \
1884 rth = mipsdsp_##func(rth, sa, env); \
1885 rtl = mipsdsp_##func(rtl, sa, env); \
1886 \
1887 return MIPSDSP_RETURN32_16(rth, rtl); \
1888 }
1889
1890 SHIFT_PH(shll, lshift16);
1891 SHIFT_PH(shll_s, sat16_lshift);
1892
1893 #undef SHIFT_PH
1894
1895 #if defined(TARGET_MIPS64)
1896 #define SHIFT_QH(name, func) \
1897 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
1898 { \
1899 uint16_t rt3, rt2, rt1, rt0; \
1900 \
1901 sa = sa & 0x0F; \
1902 \
1903 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1904 \
1905 rt3 = mipsdsp_##func(rt3, sa); \
1906 rt2 = mipsdsp_##func(rt2, sa); \
1907 rt1 = mipsdsp_##func(rt1, sa); \
1908 rt0 = mipsdsp_##func(rt0, sa); \
1909 \
1910 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1911 }
1912
1913 #define SHIFT_QH_ENV(name, func) \
1914 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
1915 CPUMIPSState *env) \
1916 { \
1917 uint16_t rt3, rt2, rt1, rt0; \
1918 \
1919 sa = sa & 0x0F; \
1920 \
1921 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1922 \
1923 rt3 = mipsdsp_##func(rt3, sa, env); \
1924 rt2 = mipsdsp_##func(rt2, sa, env); \
1925 rt1 = mipsdsp_##func(rt1, sa, env); \
1926 rt0 = mipsdsp_##func(rt0, sa, env); \
1927 \
1928 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1929 }
1930
1931 SHIFT_QH_ENV(shll, lshift16);
1932 SHIFT_QH_ENV(shll_s, sat16_lshift);
1933
1934 SHIFT_QH(shrl, rshift_u16);
1935 SHIFT_QH(shra, rashift16);
1936 SHIFT_QH(shra_r, rnd16_rashift);
1937
1938 #undef SHIFT_QH
1939 #undef SHIFT_QH_ENV
1940
1941 #endif
1942
1943 #define SHIFT_W(name, func) \
1944 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
1945 { \
1946 uint32_t temp; \
1947 \
1948 sa = sa & 0x1F; \
1949 temp = mipsdsp_##func(rt, sa); \
1950 \
1951 return (target_long)(int32_t)temp; \
1952 }
1953
1954 #define SHIFT_W_ENV(name, func) \
1955 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
1956 CPUMIPSState *env) \
1957 { \
1958 uint32_t temp; \
1959 \
1960 sa = sa & 0x1F; \
1961 temp = mipsdsp_##func(rt, sa, env); \
1962 \
1963 return (target_long)(int32_t)temp; \
1964 }
1965
1966 SHIFT_W_ENV(shll_s, sat32_lshift);
1967 SHIFT_W(shra_r, rnd32_rashift);
1968
1969 #undef SHIFT_W
1970 #undef SHIFT_W_ENV
1971
1972 #if defined(TARGET_MIPS64)
1973 #define SHIFT_PW(name, func) \
1974 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
1975 { \
1976 uint32_t rt1, rt0; \
1977 \
1978 sa = sa & 0x1F; \
1979 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1980 \
1981 rt1 = mipsdsp_##func(rt1, sa); \
1982 rt0 = mipsdsp_##func(rt0, sa); \
1983 \
1984 return MIPSDSP_RETURN64_32(rt1, rt0); \
1985 }
1986
1987 #define SHIFT_PW_ENV(name, func) \
1988 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
1989 CPUMIPSState *env) \
1990 { \
1991 uint32_t rt1, rt0; \
1992 \
1993 sa = sa & 0x1F; \
1994 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1995 \
1996 rt1 = mipsdsp_##func(rt1, sa, env); \
1997 rt0 = mipsdsp_##func(rt0, sa, env); \
1998 \
1999 return MIPSDSP_RETURN64_32(rt1, rt0); \
2000 }
2001
2002 SHIFT_PW_ENV(shll, lshift32);
2003 SHIFT_PW_ENV(shll_s, sat32_lshift);
2004
2005 SHIFT_PW(shra, rashift32);
2006 SHIFT_PW(shra_r, rnd32_rashift);
2007
2008 #undef SHIFT_PW
2009 #undef SHIFT_PW_ENV
2010
2011 #endif
2012
2013 #define SHIFT_PH(name, func) \
2014 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
2015 { \
2016 uint16_t rth, rtl; \
2017 \
2018 sa = sa & 0x0F; \
2019 \
2020 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2021 \
2022 rth = mipsdsp_##func(rth, sa); \
2023 rtl = mipsdsp_##func(rtl, sa); \
2024 \
2025 return MIPSDSP_RETURN32_16(rth, rtl); \
2026 }
2027
2028 SHIFT_PH(shrl, rshift_u16);
2029 SHIFT_PH(shra, rashift16);
2030 SHIFT_PH(shra_r, rnd16_rashift);
2031
2032 #undef SHIFT_PH
2033
2034 /** DSP Multiply Sub-class insns **/
2035 /* Return value made up by two 16bits value.
2036 * FIXME give the macro a better name.
2037 */
2038 #define MUL_RETURN32_16_PH(name, func, \
2039 rsmov1, rsmov2, rsfilter, \
2040 rtmov1, rtmov2, rtfilter) \
2041 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2042 CPUMIPSState *env) \
2043 { \
2044 uint16_t rsB, rsA, rtB, rtA; \
2045 \
2046 rsB = (rs >> rsmov1) & rsfilter; \
2047 rsA = (rs >> rsmov2) & rsfilter; \
2048 rtB = (rt >> rtmov1) & rtfilter; \
2049 rtA = (rt >> rtmov2) & rtfilter; \
2050 \
2051 rsB = mipsdsp_##func(rsB, rtB, env); \
2052 rsA = mipsdsp_##func(rsA, rtA, env); \
2053 \
2054 return MIPSDSP_RETURN32_16(rsB, rsA); \
2055 }
2056
2057 MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \
2058 24, 16, MIPSDSP_Q0, \
2059 16, 0, MIPSDSP_LO);
2060 MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \
2061 8, 0, MIPSDSP_Q0, \
2062 16, 0, MIPSDSP_LO);
2063 MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \
2064 16, 0, MIPSDSP_LO, \
2065 16, 0, MIPSDSP_LO);
2066 MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \
2067 16, 0, MIPSDSP_LO, \
2068 16, 0, MIPSDSP_LO);
2069 MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \
2070 16, 0, MIPSDSP_LO, \
2071 16, 0, MIPSDSP_LO);
2072 MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \
2073 16, 0, MIPSDSP_LO, \
2074 16, 0, MIPSDSP_LO);
2075
2076 #undef MUL_RETURN32_16_PH
2077
2078 #define MUL_RETURN32_32_ph(name, func, movbits) \
2079 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2080 CPUMIPSState *env) \
2081 { \
2082 int16_t rsh, rth; \
2083 int32_t temp; \
2084 \
2085 rsh = (rs >> movbits) & MIPSDSP_LO; \
2086 rth = (rt >> movbits) & MIPSDSP_LO; \
2087 temp = mipsdsp_##func(rsh, rth, env); \
2088 \
2089 return (target_long)(int32_t)temp; \
2090 }
2091
2092 MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16);
2093 MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0);
2094
2095 #undef MUL_RETURN32_32_ph
2096
2097 #define MUL_VOID_PH(name, use_ac_env) \
2098 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2099 CPUMIPSState *env) \
2100 { \
2101 int16_t rsh, rsl, rth, rtl; \
2102 int32_t tempB, tempA; \
2103 int64_t acc, dotp; \
2104 \
2105 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2106 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2107 \
2108 if (use_ac_env == 1) { \
2109 tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2110 tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env); \
2111 } else { \
2112 tempB = mipsdsp_mul_u16_u16(rsh, rth); \
2113 tempA = mipsdsp_mul_u16_u16(rsl, rtl); \
2114 } \
2115 \
2116 dotp = (int64_t)tempB - (int64_t)tempA; \
2117 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2118 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2119 dotp = dotp + acc; \
2120 env->active_tc.HI[ac] = (target_long)(int32_t) \
2121 ((dotp & MIPSDSP_LHI) >> 32); \
2122 env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO); \
2123 }
2124
2125 MUL_VOID_PH(mulsaq_s_w_ph, 1);
2126 MUL_VOID_PH(mulsa_w_ph, 0);
2127
2128 #undef MUL_VOID_PH
2129
2130 #if defined(TARGET_MIPS64)
2131 #define MUL_RETURN64_16_QH(name, func, \
2132 rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \
2133 rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \
2134 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2135 CPUMIPSState *env) \
2136 { \
2137 uint16_t rs3, rs2, rs1, rs0; \
2138 uint16_t rt3, rt2, rt1, rt0; \
2139 uint16_t tempD, tempC, tempB, tempA; \
2140 \
2141 rs3 = (rs >> rsmov1) & rsfilter; \
2142 rs2 = (rs >> rsmov2) & rsfilter; \
2143 rs1 = (rs >> rsmov3) & rsfilter; \
2144 rs0 = (rs >> rsmov4) & rsfilter; \
2145 rt3 = (rt >> rtmov1) & rtfilter; \
2146 rt2 = (rt >> rtmov2) & rtfilter; \
2147 rt1 = (rt >> rtmov3) & rtfilter; \
2148 rt0 = (rt >> rtmov4) & rtfilter; \
2149 \
2150 tempD = mipsdsp_##func(rs3, rt3, env); \
2151 tempC = mipsdsp_##func(rs2, rt2, env); \
2152 tempB = mipsdsp_##func(rs1, rt1, env); \
2153 tempA = mipsdsp_##func(rs0, rt0, env); \
2154 \
2155 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
2156 }
2157
2158 MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \
2159 56, 48, 40, 32, MIPSDSP_Q0, \
2160 48, 32, 16, 0, MIPSDSP_LO);
2161 MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \
2162 24, 16, 8, 0, MIPSDSP_Q0, \
2163 48, 32, 16, 0, MIPSDSP_LO);
2164 MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \
2165 48, 32, 16, 0, MIPSDSP_LO, \
2166 48, 32, 16, 0, MIPSDSP_LO);
2167
2168 #undef MUL_RETURN64_16_QH
2169
2170 #define MUL_RETURN64_32_QH(name, \
2171 rsmov1, rsmov2, \
2172 rtmov1, rtmov2) \
2173 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2174 CPUMIPSState *env) \
2175 { \
2176 uint16_t rsB, rsA; \
2177 uint16_t rtB, rtA; \
2178 uint32_t tempB, tempA; \
2179 \
2180 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2181 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2182 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2183 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2184 \
2185 tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env); \
2186 tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env); \
2187 \
2188 return ((uint64_t)tempB << 32) | (uint64_t)tempA; \
2189 }
2190
2191 MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32);
2192 MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0);
2193
2194 #undef MUL_RETURN64_32_QH
2195
2196 void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac,
2197 CPUMIPSState *env)
2198 {
2199 int16_t rs3, rs2, rs1, rs0;
2200 int16_t rt3, rt2, rt1, rt0;
2201 int32_t tempD, tempC, tempB, tempA;
2202 int64_t acc[2];
2203 int64_t temp[2];
2204 int64_t temp_sum;
2205
2206 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
2207 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
2208
2209 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);
2210 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);
2211 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);
2212 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);
2213
2214 temp[0] = ((int32_t)tempD - (int32_t)tempC) +
2215 ((int32_t)tempB - (int32_t)tempA);
2216 temp[0] = (int64_t)(temp[0] << 30) >> 30;
2217 if (((temp[0] >> 33) & 0x01) == 0) {
2218 temp[1] = 0x00;
2219 } else {
2220 temp[1] = ~0ull;
2221 }
2222
2223 acc[0] = env->active_tc.LO[ac];
2224 acc[1] = env->active_tc.HI[ac];
2225
2226 temp_sum = acc[0] + temp[0];
2227 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2228 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2229 acc[1] += 1;
2230 }
2231 acc[0] = temp_sum;
2232 acc[1] += temp[1];
2233
2234 env->active_tc.HI[ac] = acc[1];
2235 env->active_tc.LO[ac] = acc[0];
2236 }
2237 #endif
2238
2239 #define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2240 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2241 CPUMIPSState *env) \
2242 { \
2243 uint8_t rs3, rs2; \
2244 uint8_t rt3, rt2; \
2245 uint16_t tempB, tempA; \
2246 uint64_t tempC, dotp; \
2247 \
2248 rs3 = (rs >> rsmov1) & MIPSDSP_Q0; \
2249 rs2 = (rs >> rsmov2) & MIPSDSP_Q0; \
2250 rt3 = (rt >> rtmov1) & MIPSDSP_Q0; \
2251 rt2 = (rt >> rtmov2) & MIPSDSP_Q0; \
2252 tempB = mipsdsp_##func(rs3, rt3); \
2253 tempA = mipsdsp_##func(rs2, rt2); \
2254 dotp = (int64_t)tempB + (int64_t)tempA; \
2255 if (is_add) { \
2256 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2257 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2258 + dotp; \
2259 } else { \
2260 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2261 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2262 - dotp; \
2263 } \
2264 \
2265 env->active_tc.HI[ac] = (target_long)(int32_t) \
2266 ((tempC & MIPSDSP_LHI) >> 32); \
2267 env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \
2268 }
2269
2270 DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16);
2271 DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0);
2272 DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16);
2273 DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0);
2274
2275 #undef DP_QB
2276
2277 #if defined(TARGET_MIPS64)
2278 #define DP_OB(name, add_sub, \
2279 rsmov1, rsmov2, rsmov3, rsmov4, \
2280 rtmov1, rtmov2, rtmov3, rtmov4) \
2281 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2282 CPUMIPSState *env) \
2283 { \
2284 uint8_t rsD, rsC, rsB, rsA; \
2285 uint8_t rtD, rtC, rtB, rtA; \
2286 uint16_t tempD, tempC, tempB, tempA; \
2287 uint64_t temp[2]; \
2288 uint64_t acc[2]; \
2289 uint64_t temp_sum; \
2290 \
2291 temp[0] = 0; \
2292 temp[1] = 0; \
2293 \
2294 rsD = (rs >> rsmov1) & MIPSDSP_Q0; \
2295 rsC = (rs >> rsmov2) & MIPSDSP_Q0; \
2296 rsB = (rs >> rsmov3) & MIPSDSP_Q0; \
2297 rsA = (rs >> rsmov4) & MIPSDSP_Q0; \
2298 rtD = (rt >> rtmov1) & MIPSDSP_Q0; \
2299 rtC = (rt >> rtmov2) & MIPSDSP_Q0; \
2300 rtB = (rt >> rtmov3) & MIPSDSP_Q0; \
2301 rtA = (rt >> rtmov4) & MIPSDSP_Q0; \
2302 \
2303 tempD = mipsdsp_mul_u8_u8(rsD, rtD); \
2304 tempC = mipsdsp_mul_u8_u8(rsC, rtC); \
2305 tempB = mipsdsp_mul_u8_u8(rsB, rtB); \
2306 tempA = mipsdsp_mul_u8_u8(rsA, rtA); \
2307 \
2308 temp[0] = (uint64_t)tempD + (uint64_t)tempC + \
2309 (uint64_t)tempB + (uint64_t)tempA; \
2310 \
2311 acc[0] = env->active_tc.LO[ac]; \
2312 acc[1] = env->active_tc.HI[ac]; \
2313 \
2314 if (add_sub) { \
2315 temp_sum = acc[0] + temp[0]; \
2316 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2317 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2318 acc[1] += 1; \
2319 } \
2320 temp[0] = temp_sum; \
2321 temp[1] = acc[1] + temp[1]; \
2322 } else { \
2323 temp_sum = acc[0] - temp[0]; \
2324 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2325 acc[1] -= 1; \
2326 } \
2327 temp[0] = temp_sum; \
2328 temp[1] = acc[1] - temp[1]; \
2329 } \
2330 \
2331 env->active_tc.HI[ac] = temp[1]; \
2332 env->active_tc.LO[ac] = temp[0]; \
2333 }
2334
2335 DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32);
2336 DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0);
2337 DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32);
2338 DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
2339
2340 #undef DP_OB
2341 #endif
2342
2343 #define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2344 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2345 CPUMIPSState *env) \
2346 { \
2347 int16_t rsB, rsA, rtB, rtA; \
2348 int32_t tempA, tempB; \
2349 int64_t acc; \
2350 \
2351 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2352 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2353 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2354 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2355 \
2356 tempB = (int32_t)rsB * (int32_t)rtB; \
2357 tempA = (int32_t)rsA * (int32_t)rtA; \
2358 \
2359 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2360 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2361 \
2362 if (is_add) { \
2363 acc = acc + ((int64_t)tempB + (int64_t)tempA); \
2364 } else { \
2365 acc = acc - ((int64_t)tempB + (int64_t)tempA); \
2366 } \
2367 \
2368 env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \
2369 env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO); \
2370 }
2371
2372 DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0);
2373 DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16);
2374 DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0);
2375 DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16);
2376 #undef DP_NOFUNC_PH
2377
2378 #define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2379 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2380 CPUMIPSState *env) \
2381 { \
2382 int16_t rsB, rsA, rtB, rtA; \
2383 int32_t tempB, tempA; \
2384 int64_t acc, dotp; \
2385 \
2386 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2387 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2388 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2389 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2390 \
2391 tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env); \
2392 tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env); \
2393 \
2394 dotp = (int64_t)tempB + (int64_t)tempA; \
2395 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2396 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2397 \
2398 if (is_add) { \
2399 acc = acc + dotp; \
2400 } else { \
2401 acc = acc - dotp; \
2402 } \
2403 \
2404 env->active_tc.HI[ac] = (target_long)(int32_t) \
2405 ((acc & MIPSDSP_LHI) >> 32); \
2406 env->active_tc.LO[ac] = (target_long)(int32_t) \
2407 (acc & MIPSDSP_LLO); \
2408 }
2409
2410 DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0);
2411 DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16);
2412 DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0);
2413 DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16);
2414
2415 #undef DP_HASFUNC_PH
2416
2417 #define DP_128OPERATION_PH(name, is_add) \
2418 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2419 CPUMIPSState *env) \
2420 { \
2421 int16_t rsh, rsl, rth, rtl; \
2422 int32_t tempB, tempA, tempC62_31, tempC63; \
2423 int64_t acc, dotp, tempC; \
2424 \
2425 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2426 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2427 \
2428 tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env); \
2429 tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env); \
2430 \
2431 dotp = (int64_t)tempB + (int64_t)tempA; \
2432 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2433 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2434 if (is_add) { \
2435 tempC = acc + dotp; \
2436 } else { \
2437 tempC = acc - dotp; \
2438 } \
2439 tempC63 = (tempC >> 63) & 0x01; \
2440 tempC62_31 = (tempC >> 31) & 0xFFFFFFFF; \
2441 \
2442 if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) { \
2443 tempC = 0x7FFFFFFF; \
2444 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2445 } \
2446 \
2447 if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) { \
2448 tempC = (int64_t)(int32_t)0x80000000; \
2449 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2450 } \
2451 \
2452 env->active_tc.HI[ac] = (target_long)(int32_t) \
2453 ((tempC & MIPSDSP_LHI) >> 32); \
2454 env->active_tc.LO[ac] = (target_long)(int32_t) \
2455 (tempC & MIPSDSP_LLO); \
2456 }
2457
2458 DP_128OPERATION_PH(dpaqx_sa_w_ph, 1);
2459 DP_128OPERATION_PH(dpsqx_sa_w_ph, 0);
2460
2461 #undef DP_128OPERATION_HP
2462
2463 #if defined(TARGET_MIPS64)
2464 #define DP_QH(name, is_add, use_ac_env) \
2465 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2466 CPUMIPSState *env) \
2467 { \
2468 int32_t rs3, rs2, rs1, rs0; \
2469 int32_t rt3, rt2, rt1, rt0; \
2470 int32_t tempD, tempC, tempB, tempA; \
2471 int64_t acc[2]; \
2472 int64_t temp[2]; \
2473 int64_t temp_sum; \
2474 \
2475 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
2476 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2477 \
2478 if (use_ac_env) { \
2479 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); \
2480 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); \
2481 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); \
2482 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); \
2483 } else { \
2484 tempD = mipsdsp_mul_u16_u16(rs3, rt3); \
2485 tempC = mipsdsp_mul_u16_u16(rs2, rt2); \
2486 tempB = mipsdsp_mul_u16_u16(rs1, rt1); \
2487 tempA = mipsdsp_mul_u16_u16(rs0, rt0); \
2488 } \
2489 \
2490 temp[0] = (int64_t)tempD + (int64_t)tempC + \
2491 (int64_t)tempB + (int64_t)tempA; \
2492 \
2493 if (temp[0] >= 0) { \
2494 temp[1] = 0; \
2495 } else { \
2496 temp[1] = ~0ull; \
2497 } \
2498 \
2499 acc[1] = env->active_tc.HI[ac]; \
2500 acc[0] = env->active_tc.LO[ac]; \
2501 \
2502 if (is_add) { \
2503 temp_sum = acc[0] + temp[0]; \
2504 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2505 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2506 acc[1] = acc[1] + 1; \
2507 } \
2508 temp[0] = temp_sum; \
2509 temp[1] = acc[1] + temp[1]; \
2510 } else { \
2511 temp_sum = acc[0] - temp[0]; \
2512 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2513 acc[1] = acc[1] - 1; \
2514 } \
2515 temp[0] = temp_sum; \
2516 temp[1] = acc[1] - temp[1]; \
2517 } \
2518 \
2519 env->active_tc.HI[ac] = temp[1]; \
2520 env->active_tc.LO[ac] = temp[0]; \
2521 }
2522
2523 DP_QH(dpa_w_qh, 1, 0);
2524 DP_QH(dpaq_s_w_qh, 1, 1);
2525 DP_QH(dps_w_qh, 0, 0);
2526 DP_QH(dpsq_s_w_qh, 0, 1);
2527
2528 #undef DP_QH
2529
2530 #endif
2531
2532 #define DP_L_W(name, is_add) \
2533 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2534 CPUMIPSState *env) \
2535 { \
2536 int32_t temp63; \
2537 int64_t dotp, acc; \
2538 uint64_t temp; \
2539 \
2540 dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env); \
2541 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2542 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2543 if (!is_add) { \
2544 dotp = -dotp; \
2545 } \
2546 \
2547 temp = acc + dotp; \
2548 if (MIPSDSP_OVERFLOW((uint64_t)acc, (uint64_t)dotp, temp, \
2549 (0x01ull << 63))) { \
2550 temp63 = (temp >> 63) & 0x01; \
2551 if (temp63 == 1) { \
2552 temp = (0x01ull << 63) - 1; \
2553 } else { \
2554 temp = 0x01ull << 63; \
2555 } \
2556 \
2557 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2558 } \
2559 \
2560 env->active_tc.HI[ac] = (target_long)(int32_t) \
2561 ((temp & MIPSDSP_LHI) >> 32); \
2562 env->active_tc.LO[ac] = (target_long)(int32_t) \
2563 (temp & MIPSDSP_LLO); \
2564 }
2565
2566 DP_L_W(dpaq_sa_l_w, 1);
2567 DP_L_W(dpsq_sa_l_w, 0);
2568
2569 #undef DP_L_W
2570
2571 #if defined(TARGET_MIPS64)
2572 #define DP_L_PW(name, func) \
2573 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2574 CPUMIPSState *env) \
2575 { \
2576 int32_t rs1, rs0; \
2577 int32_t rt1, rt0; \
2578 int64_t tempB[2], tempA[2]; \
2579 int64_t temp[2]; \
2580 int64_t acc[2]; \
2581 int64_t temp_sum; \
2582 \
2583 temp[0] = 0; \
2584 temp[1] = 0; \
2585 \
2586 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2587 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2588 \
2589 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); \
2590 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); \
2591 \
2592 if (tempB[0] >= 0) { \
2593 tempB[1] = 0x00; \
2594 } else { \
2595 tempB[1] = ~0ull; \
2596 } \
2597 \
2598 if (tempA[0] >= 0) { \
2599 tempA[1] = 0x00; \
2600 } else { \
2601 tempA[1] = ~0ull; \
2602 } \
2603 \
2604 temp_sum = tempB[0] + tempA[0]; \
2605 if (((uint64_t)temp_sum < (uint64_t)tempB[0]) && \
2606 ((uint64_t)temp_sum < (uint64_t)tempA[0])) { \
2607 temp[1] += 1; \
2608 } \
2609 temp[0] = temp_sum; \
2610 temp[1] += tempB[1] + tempA[1]; \
2611 \
2612 mipsdsp_##func(acc, ac, temp, env); \
2613 \
2614 env->active_tc.HI[ac] = acc[1]; \
2615 env->active_tc.LO[ac] = acc[0]; \
2616 }
2617
2618 DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63);
2619 DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63);
2620
2621 #undef DP_L_PW
2622
2623 void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac,
2624 CPUMIPSState *env)
2625 {
2626 int32_t rs1, rs0;
2627 int32_t rt1, rt0;
2628 int64_t tempB[2], tempA[2];
2629 int64_t temp[2];
2630 int64_t acc[2];
2631 int64_t temp_sum;
2632
2633 rs1 = (rs >> 32) & MIPSDSP_LLO;
2634 rs0 = rs & MIPSDSP_LLO;
2635 rt1 = (rt >> 32) & MIPSDSP_LLO;
2636 rt0 = rt & MIPSDSP_LLO;
2637
2638 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);
2639 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);
2640
2641 if (tempB[0] >= 0) {
2642 tempB[1] = 0x00;
2643 } else {
2644 tempB[1] = ~0ull;
2645 }
2646
2647 if (tempA[0] >= 0) {
2648 tempA[1] = 0x00;
2649 } else {
2650 tempA[1] = ~0ull;
2651 }
2652
2653 acc[0] = env->active_tc.LO[ac];
2654 acc[1] = env->active_tc.HI[ac];
2655
2656 temp_sum = tempB[0] - tempA[0];
2657 if ((uint64_t)temp_sum > (uint64_t)tempB[0]) {
2658 tempB[1] -= 1;
2659 }
2660 temp[0] = temp_sum;
2661 temp[1] = tempB[1] - tempA[1];
2662
2663 if ((temp[1] & 0x01) == 0) {
2664 temp[1] = 0x00;
2665 } else {
2666 temp[1] = ~0ull;
2667 }
2668
2669 temp_sum = acc[0] + temp[0];
2670 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2671 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2672 acc[1] += 1;
2673 }
2674 acc[0] = temp_sum;
2675 acc[1] += temp[1];
2676
2677 env->active_tc.HI[ac] = acc[1];
2678 env->active_tc.LO[ac] = acc[0];
2679 }
2680 #endif
2681
2682 #define MAQ_S_W(name, mov) \
2683 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2684 CPUMIPSState *env) \
2685 { \
2686 int16_t rsh, rth; \
2687 int32_t tempA; \
2688 int64_t tempL, acc; \
2689 \
2690 rsh = (rs >> mov) & MIPSDSP_LO; \
2691 rth = (rt >> mov) & MIPSDSP_LO; \
2692 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2693 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2694 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2695 tempL = (int64_t)tempA + acc; \
2696 env->active_tc.HI[ac] = (target_long)(int32_t) \
2697 ((tempL & MIPSDSP_LHI) >> 32); \
2698 env->active_tc.LO[ac] = (target_long)(int32_t) \
2699 (tempL & MIPSDSP_LLO); \
2700 }
2701
2702 MAQ_S_W(maq_s_w_phl, 16);
2703 MAQ_S_W(maq_s_w_phr, 0);
2704
2705 #undef MAQ_S_W
2706
2707 #define MAQ_SA_W(name, mov) \
2708 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2709 CPUMIPSState *env) \
2710 { \
2711 int16_t rsh, rth; \
2712 int32_t tempA; \
2713 \
2714 rsh = (rs >> mov) & MIPSDSP_LO; \
2715 rth = (rt >> mov) & MIPSDSP_LO; \
2716 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2717 tempA = mipsdsp_sat32_acc_q31(ac, tempA, env); \
2718 \
2719 env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA & \
2720 MIPSDSP_LHI) >> 32); \
2721 env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA & \
2722 MIPSDSP_LLO); \
2723 }
2724
2725 MAQ_SA_W(maq_sa_w_phl, 16);
2726 MAQ_SA_W(maq_sa_w_phr, 0);
2727
2728 #undef MAQ_SA_W
2729
2730 #define MULQ_W(name, addvar) \
2731 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2732 CPUMIPSState *env) \
2733 { \
2734 uint32_t rs_t, rt_t; \
2735 int32_t tempI; \
2736 int64_t tempL; \
2737 \
2738 rs_t = rs & MIPSDSP_LLO; \
2739 rt_t = rt & MIPSDSP_LLO; \
2740 \
2741 if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) { \
2742 tempL = 0x7FFFFFFF00000000ull; \
2743 set_DSPControl_overflow_flag(1, 21, env); \
2744 } else { \
2745 tempL = ((int64_t)rs_t * (int64_t)rt_t) << 1; \
2746 tempL += addvar; \
2747 } \
2748 tempI = (tempL & MIPSDSP_LHI) >> 32; \
2749 \
2750 return (target_long)(int32_t)tempI; \
2751 }
2752
2753 MULQ_W(mulq_s_w, 0);
2754 MULQ_W(mulq_rs_w, 0x80000000ull);
2755
2756 #undef MULQ_W
2757
2758 #if defined(TARGET_MIPS64)
2759
2760 #define MAQ_S_W_QH(name, mov) \
2761 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2762 CPUMIPSState *env) \
2763 { \
2764 int16_t rs_t, rt_t; \
2765 int32_t temp_mul; \
2766 int64_t temp[2]; \
2767 int64_t acc[2]; \
2768 int64_t temp_sum; \
2769 \
2770 temp[0] = 0; \
2771 temp[1] = 0; \
2772 \
2773 rs_t = (rs >> mov) & MIPSDSP_LO; \
2774 rt_t = (rt >> mov) & MIPSDSP_LO; \
2775 temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2776 \
2777 temp[0] = (int64_t)temp_mul; \
2778 if (temp[0] >= 0) { \
2779 temp[1] = 0x00; \
2780 } else { \
2781 temp[1] = ~0ull; \
2782 } \
2783 \
2784 acc[0] = env->active_tc.LO[ac]; \
2785 acc[1] = env->active_tc.HI[ac]; \
2786 \
2787 temp_sum = acc[0] + temp[0]; \
2788 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2789 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2790 acc[1] += 1; \
2791 } \
2792 acc[0] = temp_sum; \
2793 acc[1] += temp[1]; \
2794 \
2795 env->active_tc.HI[ac] = acc[1]; \
2796 env->active_tc.LO[ac] = acc[0]; \
2797 }
2798
2799 MAQ_S_W_QH(maq_s_w_qhll, 48);
2800 MAQ_S_W_QH(maq_s_w_qhlr, 32);
2801 MAQ_S_W_QH(maq_s_w_qhrl, 16);
2802 MAQ_S_W_QH(maq_s_w_qhrr, 0);
2803
2804 #undef MAQ_S_W_QH
2805
2806 #define MAQ_SA_W(name, mov) \
2807 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2808 CPUMIPSState *env) \
2809 { \
2810 int16_t rs_t, rt_t; \
2811 int32_t temp; \
2812 int64_t acc[2]; \
2813 \
2814 rs_t = (rs >> mov) & MIPSDSP_LO; \
2815 rt_t = (rt >> mov) & MIPSDSP_LO; \
2816 temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2817 temp = mipsdsp_sat32_acc_q31(ac, temp, env); \
2818 \
2819 acc[0] = (int64_t)(int32_t)temp; \
2820 if (acc[0] >= 0) { \
2821 acc[1] = 0x00; \
2822 } else { \
2823 acc[1] = ~0ull; \
2824 } \
2825 \
2826 env->active_tc.HI[ac] = acc[1]; \
2827 env->active_tc.LO[ac] = acc[0]; \
2828 }
2829
2830 MAQ_SA_W(maq_sa_w_qhll, 48);
2831 MAQ_SA_W(maq_sa_w_qhlr, 32);
2832 MAQ_SA_W(maq_sa_w_qhrl, 16);
2833 MAQ_SA_W(maq_sa_w_qhrr, 0);
2834
2835 #undef MAQ_SA_W
2836
2837 #define MAQ_S_L_PW(name, mov) \
2838 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2839 CPUMIPSState *env) \
2840 { \
2841 int32_t rs_t, rt_t; \
2842 int64_t temp[2]; \
2843 int64_t acc[2]; \
2844 int64_t temp_sum; \
2845 \
2846 temp[0] = 0; \
2847 temp[1] = 0; \
2848 \
2849 rs_t = (rs >> mov) & MIPSDSP_LLO; \
2850 rt_t = (rt >> mov) & MIPSDSP_LLO; \
2851 \
2852 temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env); \
2853 if (temp[0] >= 0) { \
2854 temp[1] = 0x00; \
2855 } else { \
2856 temp[1] = ~0ull; \
2857 } \
2858 \
2859 acc[0] = env->active_tc.LO[ac]; \
2860 acc[1] = env->active_tc.HI[ac]; \
2861 \
2862 temp_sum = acc[0] + temp[0]; \
2863 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2864 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2865 acc[1] += 1; \
2866 } \
2867 acc[0] = temp_sum; \
2868 acc[1] += temp[1]; \
2869 \
2870 env->active_tc.HI[ac] = acc[1]; \
2871 env->active_tc.LO[ac] = acc[0]; \
2872 }
2873
2874 MAQ_S_L_PW(maq_s_l_pwl, 32);
2875 MAQ_S_L_PW(maq_s_l_pwr, 0);
2876
2877 #undef MAQ_S_L_PW
2878
2879 #define DM_OPERATE(name, func, is_add, sigext) \
2880 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2881 CPUMIPSState *env) \
2882 { \
2883 int32_t rs1, rs0; \
2884 int32_t rt1, rt0; \
2885 int64_t tempBL[2], tempAL[2]; \
2886 int64_t acc[2]; \
2887 int64_t temp[2]; \
2888 int64_t temp_sum; \
2889 \
2890 temp[0] = 0x00; \
2891 temp[1] = 0x00; \
2892 \
2893 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2894 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2895 \
2896 if (sigext) { \
2897 tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1); \
2898 tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0); \
2899 \
2900 if (tempBL[0] >= 0) { \
2901 tempBL[1] = 0x0; \
2902 } else { \
2903 tempBL[1] = ~0ull; \
2904 } \
2905 \
2906 if (tempAL[0] >= 0) { \
2907 tempAL[1] = 0x0; \
2908 } else { \
2909 tempAL[1] = ~0ull; \
2910 } \
2911 } else { \
2912 tempBL[0] = mipsdsp_##func(rs1, rt1); \
2913 tempAL[0] = mipsdsp_##func(rs0, rt0); \
2914 tempBL[1] = 0; \
2915 tempAL[1] = 0; \
2916 } \
2917 \
2918 acc[1] = env->active_tc.HI[ac]; \
2919 acc[0] = env->active_tc.LO[ac]; \
2920 \
2921 temp_sum = tempBL[0] + tempAL[0]; \
2922 if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) && \
2923 ((uint64_t)temp_sum < (uint64_t)tempAL[0])) { \
2924 temp[1] += 1; \
2925 } \
2926 temp[0] = temp_sum; \
2927 temp[1] += tempBL[1] + tempAL[1]; \
2928 \
2929 if (is_add) { \
2930 temp_sum = acc[0] + temp[0]; \
2931 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2932 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2933 acc[1] += 1; \
2934 } \
2935 temp[0] = temp_sum; \
2936 temp[1] = acc[1] + temp[1]; \
2937 } else { \
2938 temp_sum = acc[0] - temp[0]; \
2939 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2940 acc[1] -= 1; \
2941 } \
2942 temp[0] = temp_sum; \
2943 temp[1] = acc[1] - temp[1]; \
2944 } \
2945 \
2946 env->active_tc.HI[ac] = temp[1]; \
2947 env->active_tc.LO[ac] = temp[0]; \
2948 }
2949
2950 DM_OPERATE(dmadd, mul_i32_i32, 1, 1);
2951 DM_OPERATE(dmaddu, mul_u32_u32, 1, 0);
2952 DM_OPERATE(dmsub, mul_i32_i32, 0, 1);
2953 DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
2954 #undef DM_OPERATE
2955 #endif
2956
2957 /** DSP Bit/Manipulation Sub-class insns **/
2958 target_ulong helper_bitrev(target_ulong rt)
2959 {
2960 int32_t temp;
2961 uint32_t rd;
2962 int i;
2963
2964 temp = rt & MIPSDSP_LO;
2965 rd = 0;
2966 for (i = 0; i < 16; i++) {
2967 rd = (rd << 1) | (temp & 1);
2968 temp = temp >> 1;
2969 }
2970
2971 return (target_ulong)rd;
2972 }
2973
2974 #define BIT_INSV(name, posfilter, sizefilter, ret_type) \
2975 target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
2976 target_ulong rt) \
2977 { \
2978 uint32_t pos, size, msb, lsb; \
2979 target_ulong filter; \
2980 target_ulong temp, temprs, temprt; \
2981 target_ulong dspc; \
2982 \
2983 dspc = env->active_tc.DSPControl; \
2984 \
2985 pos = dspc & posfilter; \
2986 size = (dspc >> 7) & sizefilter; \
2987 \
2988 msb = pos + size - 1; \
2989 lsb = pos; \
2990 \
2991 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
2992 return rt; \
2993 } \
2994 \
2995 filter = ((int32_t)0x01 << size) - 1; \
2996 filter = filter << pos; \
2997 temprs = (rs << pos) & filter; \
2998 temprt = rt & ~filter; \
2999 temp = temprs | temprt; \
3000 \
3001 return (target_long)(ret_type)temp; \
3002 }
3003
3004 BIT_INSV(insv, 0x1F, 0x1F, int32_t);
3005 #ifdef TARGET_MIPS64
3006 BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
3007 #endif
3008
3009 #undef BIT_INSV
3010
3011
3012 /** DSP Compare-Pick Sub-class insns **/
3013 #define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
3014 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
3015 { \
3016 uint32_t rs_t, rt_t; \
3017 uint8_t cc; \
3018 uint32_t temp = 0; \
3019 int i; \
3020 \
3021 for (i = 0; i < split_num; i++) { \
3022 rs_t = (rs >> (bit_size * i)) & filter; \
3023 rt_t = (rt >> (bit_size * i)) & filter; \
3024 cc = mipsdsp_##func(rs_t, rt_t); \
3025 temp |= cc << i; \
3026 } \
3027 \
3028 return (target_ulong)temp; \
3029 }
3030
3031 CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3032 CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3033 CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3034
3035 #ifdef TARGET_MIPS64
3036 CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3037 CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3038 CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3039 #endif
3040
3041 #undef CMP_HAS_RET
3042
3043
3044 #define CMP_NO_RET(name, func, split_num, filter, bit_size) \
3045 void helper_##name(target_ulong rs, target_ulong rt, \
3046 CPUMIPSState *env) \
3047 { \
3048 int##bit_size##_t rs_t, rt_t; \
3049 int##bit_size##_t flag = 0; \
3050 int##bit_size##_t cc; \
3051 int i; \
3052 \
3053 for (i = 0; i < split_num; i++) { \
3054 rs_t = (rs >> (bit_size * i)) & filter; \
3055 rt_t = (rt >> (bit_size * i)) & filter; \
3056 \
3057 cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \
3058 flag |= cc << i; \
3059 } \
3060 \
3061 set_DSPControl_24(flag, split_num, env); \
3062 }
3063
3064 CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3065 CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3066 CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3067
3068 CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
3069 CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
3070 CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
3071
3072 #ifdef TARGET_MIPS64
3073 CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3074 CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3075 CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3076
3077 CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
3078 CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
3079 CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
3080
3081 CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
3082 CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
3083 CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
3084 #endif
3085 #undef CMP_NO_RET
3086
3087 #if defined(TARGET_MIPS64)
3088
3089 #define CMPGDU_OB(name) \
3090 target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
3091 CPUMIPSState *env) \
3092 { \
3093 int i; \
3094 uint8_t rs_t, rt_t; \
3095 uint32_t cond; \
3096 \
3097 cond = 0; \
3098 \
3099 for (i = 0; i < 8; i++) { \
3100 rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \
3101 rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \
3102 \
3103 if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \
3104 cond |= 0x01 << i; \
3105 } \
3106 } \
3107 \
3108 set_DSPControl_24(cond, 8, env); \
3109 \
3110 return (uint64_t)cond; \
3111 }
3112
3113 CMPGDU_OB(eq)
3114 CMPGDU_OB(lt)
3115 CMPGDU_OB(le)
3116 #undef CMPGDU_OB
3117 #endif
3118
3119 #define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
3120 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3121 CPUMIPSState *env) \
3122 { \
3123 uint32_t rs_t, rt_t; \
3124 uint32_t cc; \
3125 target_ulong dsp; \
3126 int i; \
3127 target_ulong result = 0; \
3128 \
3129 dsp = env->active_tc.DSPControl; \
3130 for (i = 0; i < split_num; i++) { \
3131 rs_t = (rs >> (bit_size * i)) & filter; \
3132 rt_t = (rt >> (bit_size * i)) & filter; \
3133 cc = (dsp >> (24 + i)) & 0x01; \
3134 cc = cc == 1 ? rs_t : rt_t; \
3135 \
3136 result |= (target_ulong)cc << (bit_size * i); \
3137 } \
3138 \
3139 if (ret32bit) { \
3140 result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
3141 } \
3142 \
3143 return result; \
3144 }
3145
3146 PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
3147 PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
3148
3149 #ifdef TARGET_MIPS64
3150 PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
3151 PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
3152 PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
3153 #endif
3154 #undef PICK_INSN
3155
3156 #define APPEND_INSN(name, ret_32) \
3157 target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \
3158 { \
3159 target_ulong temp; \
3160 \
3161 if (ret_32) { \
3162 temp = ((rt & MIPSDSP_LLO) << sa) | \
3163 ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \
3164 temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \
3165 } else { \
3166 temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \
3167 } \
3168 \
3169 return temp; \
3170 }
3171
3172 APPEND_INSN(append, 1);
3173 #ifdef TARGET_MIPS64
3174 APPEND_INSN(dappend, 0);
3175 #endif
3176 #undef APPEND_INSN
3177
3178 #define PREPEND_INSN(name, or_val, ret_32) \
3179 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3180 uint32_t sa) \
3181 { \
3182 sa |= or_val; \
3183 \
3184 if (1) { \
3185 return (target_long)(int32_t)(uint32_t) \
3186 (((rs & MIPSDSP_LLO) << (32 - sa)) | \
3187 ((rt & MIPSDSP_LLO) >> sa)); \
3188 } else { \
3189 return (rs << (64 - sa)) | (rt >> sa); \
3190 } \
3191 }
3192
3193 PREPEND_INSN(prepend, 0, 1);
3194 #ifdef TARGET_MIPS64
3195 PREPEND_INSN(prependw, 0, 0);
3196 PREPEND_INSN(prependd, 0x20, 0);
3197 #endif
3198 #undef PREPEND_INSN
3199
3200 #define BALIGN_INSN(name, filter, ret32) \
3201 target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \
3202 { \
3203 bp = bp & 0x03; \
3204 \
3205 if ((bp & 1) == 0) { \
3206 return rt; \
3207 } else { \
3208 if (ret32) { \
3209 return (target_long)(int32_t)((rt << (8 * bp)) | \
3210 (rs >> (8 * (4 - bp)))); \
3211 } else { \
3212 return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \
3213 } \
3214 } \
3215 }
3216
3217 BALIGN_INSN(balign, 0x03, 1);
3218 #if defined(TARGET_MIPS64)
3219 BALIGN_INSN(dbalign, 0x07, 0);
3220 #endif
3221 #undef BALIGN_INSN
3222
3223 target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
3224 {
3225 uint32_t rsl, rth;
3226
3227 rsl = rs & MIPSDSP_LO;
3228 rth = (rt & MIPSDSP_HI) >> 16;
3229
3230 return (target_long)(int32_t)((rsl << 16) | rth);
3231 }
3232
3233 #if defined(TARGET_MIPS64)
3234 target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
3235 {
3236 uint32_t rs0, rt1;
3237
3238 rs0 = rs & MIPSDSP_LLO;
3239 rt1 = (rt >> 32) & MIPSDSP_LLO;
3240
3241 return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
3242 }
3243 #endif
3244
3245 /** DSP Accumulator and DSPControl Access Sub-class insns **/
3246 target_ulong helper_extr_w(target_ulong ac, target_ulong shift,
3247 CPUMIPSState *env)
3248 {
3249 int32_t tempI;
3250 int64_t tempDL[2];
3251
3252 shift = shift & 0x1F;
3253
3254 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3255 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3256 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3257 set_DSPControl_overflow_flag(1, 23, env);
3258 }
3259
3260 tempI = (tempDL[0] >> 1) & MIPSDSP_LLO;
3261
3262 tempDL[0] += 1;
3263 if (tempDL[0] == 0) {
3264 tempDL[1] += 1;
3265 }
3266
3267 if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) &&
3268 (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) {
3269 set_DSPControl_overflow_flag(1, 23, env);
3270 }
3271
3272 return (target_long)tempI;
3273 }
3274
3275 target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift,
3276 CPUMIPSState *env)
3277 {
3278 int64_t tempDL[2];
3279
3280 shift = shift & 0x1F;
3281
3282 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3283 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3284 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3285 set_DSPControl_overflow_flag(1, 23, env);
3286 }
3287
3288 tempDL[0] += 1;
3289 if (tempDL[0] == 0) {
3290 tempDL[1] += 1;
3291 }
3292
3293 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3294 (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3295 set_DSPControl_overflow_flag(1, 23, env);
3296 }
3297
3298 return (target_long)(int32_t)(tempDL[0] >> 1);
3299 }
3300
3301 target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift,
3302 CPUMIPSState *env)
3303 {
3304 int32_t tempI, temp64;
3305 int64_t tempDL[2];
3306
3307 shift = shift & 0x1F;
3308
3309 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3310 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3311 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3312 set_DSPControl_overflow_flag(1, 23, env);
3313 }
3314 tempDL[0] += 1;
3315 if (tempDL[0] == 0) {
3316 tempDL[1] += 1;
3317 }
3318 tempI = tempDL[0] >> 1;
3319
3320 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3321 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3322 temp64 = tempDL[1];
3323 if (temp64 == 0) {
3324 tempI = 0x7FFFFFFF;
3325 } else {
3326 tempI = 0x80000000;
3327 }
3328 set_DSPControl_overflow_flag(1, 23, env);
3329 }
3330
3331 return (target_long)tempI;
3332 }
3333
3334 #if defined(TARGET_MIPS64)
3335 target_ulong helper_dextr_w(target_ulong ac, target_ulong shift,
3336 CPUMIPSState *env)
3337 {
3338 uint64_t temp[3];
3339
3340 shift = shift & 0x3F;
3341
3342 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3343
3344 return (int64_t)(int32_t)(temp[0] >> 1);
3345 }
3346
3347 target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift,
3348 CPUMIPSState *env)
3349 {
3350 uint64_t temp[3];
3351 uint32_t temp128;
3352
3353 shift = shift & 0x3F;
3354 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3355
3356 temp[0] += 1;
3357 if (temp[0] == 0) {
3358 temp[1] += 1;
3359 if (temp[1] == 0) {
3360 temp[2] += 1;
3361 }
3362 }
3363
3364 temp128 = temp[2] & 0x01;
3365
3366 if ((temp128 != 0 || temp[1] != 0) &&
3367 (temp128 != 1 || temp[1] != ~0ull)) {
3368 set_DSPControl_overflow_flag(1, 23, env);
3369 }
3370
3371 return (int64_t)(int32_t)(temp[0] >> 1);
3372 }
3373
3374 target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift,
3375 CPUMIPSState *env)
3376 {
3377 uint64_t temp[3];
3378 uint32_t temp128;
3379
3380 shift = shift & 0x3F;
3381 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3382
3383 temp[0] += 1;
3384 if (temp[0] == 0) {
3385 temp[1] += 1;
3386 if (temp[1] == 0) {
3387 temp[2] += 1;
3388 }
3389 }
3390
3391 temp128 = temp[2] & 0x01;
3392
3393 if ((temp128 != 0 || temp[1] != 0) &&
3394 (temp128 != 1 || temp[1] != ~0ull)) {
3395 if (temp128 == 0) {
3396 temp[0] = 0x0FFFFFFFF;
3397 } else {
3398 temp[0] = 0x0100000000ULL;
3399 }
3400 set_DSPControl_overflow_flag(1, 23, env);
3401 }
3402
3403 return (int64_t)(int32_t)(temp[0] >> 1);
3404 }
3405
3406 target_ulong helper_dextr_l(target_ulong ac, target_ulong shift,
3407 CPUMIPSState *env)
3408 {
3409 uint64_t temp[3];
3410 target_ulong result;
3411
3412 shift = shift & 0x3F;
3413
3414 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3415 result = (temp[1] << 63) | (temp[0] >> 1);
3416
3417 return result;
3418 }
3419
3420 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift,
3421 CPUMIPSState *env)
3422 {
3423 uint64_t temp[3];
3424 uint32_t temp128;
3425 target_ulong result;
3426
3427 shift = shift & 0x3F;
3428 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3429
3430 temp[0] += 1;
3431 if (temp[0] == 0) {
3432 temp[1] += 1;
3433 if (temp[1] == 0) {
3434 temp[2] += 1;
3435 }
3436 }
3437
3438 temp128 = temp[2] & 0x01;
3439
3440 if ((temp128 != 0 || temp[1] != 0) &&
3441 (temp128 != 1 || temp[1] != ~0ull)) {
3442 set_DSPControl_overflow_flag(1, 23, env);
3443 }
3444
3445 result = (temp[1] << 63) | (temp[0] >> 1);
3446
3447 return result;
3448 }
3449
3450 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift,
3451 CPUMIPSState *env)
3452 {
3453 uint64_t temp[3];
3454 uint32_t temp128;
3455 target_ulong result;
3456
3457 shift = shift & 0x3F;
3458 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3459
3460 temp[0] += 1;
3461 if (temp[0] == 0) {
3462 temp[1] += 1;
3463 if (temp[1] == 0) {
3464 temp[2] += 1;
3465 }
3466 }
3467
3468 temp128 = temp[2] & 0x01;
3469
3470 if ((temp128 != 0 || temp[1] != 0) &&
3471 (temp128 != 1 || temp[1] != ~0ull)) {
3472 if (temp128 == 0) {
3473 temp[1] &= ~0x00ull - 1;
3474 temp[0] |= ~0x00ull - 1;
3475 } else {
3476 temp[1] |= 0x01;
3477 temp[0] &= 0x01;
3478 }
3479 set_DSPControl_overflow_flag(1, 23, env);
3480 }
3481 result = (temp[1] << 63) | (temp[0] >> 1);
3482
3483 return result;
3484 }
3485 #endif
3486
3487 target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift,
3488 CPUMIPSState *env)
3489 {
3490 int64_t temp, acc;
3491
3492 shift = shift & 0x1F;
3493
3494 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
3495 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
3496
3497 temp = acc >> shift;
3498
3499 if (temp > (int64_t)0x7FFF) {
3500 temp = 0x00007FFF;
3501 set_DSPControl_overflow_flag(1, 23, env);
3502 } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) {
3503 temp = 0xFFFF8000;
3504 set_DSPControl_overflow_flag(1, 23, env);
3505 }
3506
3507 return (target_long)(int32_t)(temp & 0xFFFFFFFF);
3508 }
3509
3510
3511 #if defined(TARGET_MIPS64)
3512 target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift,
3513 CPUMIPSState *env)
3514 {
3515 int64_t temp[2];
3516 uint32_t temp127;
3517
3518 shift = shift & 0x1F;
3519
3520 mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env);
3521
3522 temp127 = (temp[1] >> 63) & 0x01;
3523
3524 if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) {
3525 temp[0] &= 0xFFFF0000;
3526 temp[0] |= 0x00007FFF;
3527 set_DSPControl_overflow_flag(1, 23, env);
3528 } else if ((temp127 == 1) &&
3529 (temp[1] < 0xFFFFFFFFFFFFFFFFll
3530 || temp[0] < 0xFFFFFFFFFFFF1000ll)) {
3531 temp[0] &= 0xFFFF0000;
3532 temp[0] |= 0x00008000;
3533 set_DSPControl_overflow_flag(1, 23, env);
3534 }
3535
3536 return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO);
3537 }
3538
3539 #endif
3540
3541 target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3542 {
3543 int32_t start_pos;
3544 int sub;
3545 uint32_t temp;
3546 uint64_t acc;
3547
3548 size = size & 0x1F;
3549
3550 temp = 0;
3551 start_pos = get_DSPControl_pos(env);
3552 sub = start_pos - (size + 1);
3553 if (sub >= -1) {
3554 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3555 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3556 temp = (acc >> (start_pos - size)) &
3557 (((uint32_t)0x01 << (size + 1)) - 1);
3558 set_DSPControl_efi(0, env);
3559 } else {
3560 set_DSPControl_efi(1, env);
3561 }
3562
3563 return (target_ulong)temp;
3564 }
3565
3566 target_ulong helper_extpdp(target_ulong ac, target_ulong size,
3567 CPUMIPSState *env)
3568 {
3569 int32_t start_pos;
3570 int sub;
3571 uint32_t temp;
3572 uint64_t acc;
3573
3574 size = size & 0x1F;
3575 temp = 0;
3576 start_pos = get_DSPControl_pos(env);
3577 sub = start_pos - (size + 1);
3578 if (sub >= -1) {
3579 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3580 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3581 temp = (acc >> (start_pos - size)) &
3582 (((uint32_t)0x01 << (size + 1)) - 1);
3583
3584 set_DSPControl_pos(start_pos - (size + 1), env);
3585 set_DSPControl_efi(0, env);
3586 } else {
3587 set_DSPControl_efi(1, env);
3588 }
3589
3590 return (target_ulong)temp;
3591 }
3592
3593
3594 #if defined(TARGET_MIPS64)
3595 target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3596 {
3597 int start_pos;
3598 int len;
3599 int sub;
3600 uint64_t tempB, tempA;
3601 uint64_t temp;
3602
3603 temp = 0;
3604
3605 size = size & 0x3F;
3606 start_pos = get_DSPControl_pos(env);
3607 len = start_pos - size;
3608 tempB = env->active_tc.HI[ac];
3609 tempA = env->active_tc.LO[ac];
3610
3611 sub = start_pos - (size + 1);
3612
3613 if (sub >= -1) {
3614 temp = (tempB << (64 - len)) | (tempA >> len);
3615 temp = temp & ((0x01 << (size + 1)) - 1);
3616 set_DSPControl_efi(0, env);
3617 } else {
3618 set_DSPControl_efi(1, env);
3619 }
3620
3621 return temp;
3622 }
3623
3624 target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
3625 CPUMIPSState *env)
3626 {
3627 int start_pos;
3628 int len;
3629 int sub;
3630 uint64_t tempB, tempA;
3631 uint64_t temp;
3632
3633 temp = 0;
3634 size = size & 0x3F;
3635 start_pos = get_DSPControl_pos(env);
3636 len = start_pos - size;
3637 tempB = env->active_tc.HI[ac];
3638 tempA = env->active_tc.LO[ac];
3639
3640 sub = start_pos - (size + 1);
3641
3642 if (sub >= -1) {
3643 temp = (tempB << (64 - len)) | (tempA >> len);
3644 temp = temp & ((0x01 << (size + 1)) - 1);
3645 set_DSPControl_pos(sub, env);
3646 set_DSPControl_efi(0, env);
3647 } else {
3648 set_DSPControl_efi(1, env);
3649 }
3650
3651 return temp;
3652 }
3653
3654 #endif
3655
3656 void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3657 {
3658 int8_t rs5_0;
3659 uint64_t temp, acc;
3660
3661 rs5_0 = rs & 0x3F;
3662 rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
3663
3664 if (unlikely(rs5_0 == 0)) {
3665 return;
3666 }
3667
3668 acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
3669 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3670
3671 if (rs5_0 > 0) {
3672 temp = acc >> rs5_0;
3673 } else {
3674 temp = acc << -rs5_0;
3675 }
3676
3677 env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
3678 env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO);
3679 }
3680
3681 #if defined(TARGET_MIPS64)
3682 void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env)
3683 {
3684 int8_t shift_t;
3685 uint64_t tempB, tempA;
3686
3687 shift_t = (int8_t)(shift << 1) >> 1;
3688
3689 tempB = env->active_tc.HI[ac];
3690 tempA = env->active_tc.LO[ac];
3691
3692 if (shift_t != 0) {
3693 if (shift_t >= 0) {
3694 tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t);
3695 tempB = tempB >> shift_t;
3696 } else {
3697 shift_t = -shift_t;
3698 tempB = (tempB << shift_t) | (tempA >> (64 - shift_t));
3699 tempA = tempA << shift_t;
3700 }
3701 }
3702
3703 env->active_tc.HI[ac] = tempB;
3704 env->active_tc.LO[ac] = tempA;
3705 }
3706
3707 #endif
3708 void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3709 {
3710 int32_t tempA, tempB, pos;
3711
3712 tempA = rs;
3713 tempB = env->active_tc.LO[ac];
3714 env->active_tc.HI[ac] = (target_long)tempB;
3715 env->active_tc.LO[ac] = (target_long)tempA;
3716 pos = get_DSPControl_pos(env);
3717
3718 if (pos > 32) {
3719 return;
3720 } else {
3721 set_DSPControl_pos(pos + 32, env);
3722 }
3723 }
3724
3725 #if defined(TARGET_MIPS64)
3726 void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env)
3727 {
3728 uint8_t ac_t;
3729 uint8_t pos;
3730 uint64_t tempB, tempA;
3731
3732 ac_t = ac & 0x3;
3733
3734 tempA = rs;
3735 tempB = env->active_tc.LO[ac_t];
3736
3737 env->active_tc.HI[ac_t] = tempB;
3738 env->active_tc.LO[ac_t] = tempA;
3739
3740 pos = get_DSPControl_pos(env);
3741
3742 if (pos <= 64) {
3743 pos = pos + 64;
3744 set_DSPControl_pos(pos, env);
3745 }
3746 }
3747 #endif
3748
3749 void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
3750 {
3751 uint8_t mask[6];
3752 uint8_t i;
3753 uint32_t newbits, overwrite;
3754 target_ulong dsp;
3755
3756 newbits = 0x00;
3757 overwrite = 0xFFFFFFFF;
3758 dsp = env->active_tc.DSPControl;
3759
3760 for (i = 0; i < 6; i++) {
3761 mask[i] = (mask_num >> i) & 0x01;
3762 }
3763
3764 if (mask[0] == 1) {
3765 #if defined(TARGET_MIPS64)
3766 overwrite &= 0xFFFFFF80;
3767 newbits &= 0xFFFFFF80;
3768 newbits |= 0x0000007F & rs;
3769 #else
3770 overwrite &= 0xFFFFFFC0;
3771 newbits &= 0xFFFFFFC0;
3772 newbits |= 0x0000003F & rs;
3773 #endif
3774 }
3775
3776 if (mask[1] == 1) {
3777 overwrite &= 0xFFFFE07F;
3778 newbits &= 0xFFFFE07F;
3779 newbits |= 0x00001F80 & rs;
3780 }
3781
3782 if (mask[2] == 1) {
3783 overwrite &= 0xFFFFDFFF;
3784 newbits &= 0xFFFFDFFF;
3785 newbits |= 0x00002000 & rs;
3786 }
3787
3788 if (mask[3] == 1) {
3789 overwrite &= 0xFF00FFFF;
3790 newbits &= 0xFF00FFFF;
3791 newbits |= 0x00FF0000 & rs;
3792 }
3793
3794 if (mask[4] == 1) {
3795 overwrite &= 0x00FFFFFF;
3796 newbits &= 0x00FFFFFF;
3797 #if defined(TARGET_MIPS64)
3798 newbits |= 0xFF000000 & rs;
3799 #else
3800 newbits |= 0x0F000000 & rs;
3801 #endif
3802 }
3803
3804 if (mask[5] == 1) {
3805 overwrite &= 0xFFFFBFFF;
3806 newbits &= 0xFFFFBFFF;
3807 newbits |= 0x00004000 & rs;
3808 }
3809
3810 dsp = dsp & overwrite;
3811 dsp = dsp | newbits;
3812 env->active_tc.DSPControl = dsp;
3813 }
3814
3815 target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env)
3816 {
3817 uint8_t mask[6];
3818 uint32_t ruler, i;
3819 target_ulong temp;
3820 target_ulong dsp;
3821
3822 ruler = 0x01;
3823 for (i = 0; i < 6; i++) {
3824 mask[i] = (masknum & ruler) >> i ;
3825 ruler = ruler << 1;
3826 }
3827
3828 temp = 0x00;
3829 dsp = env->active_tc.DSPControl;
3830
3831 if (mask[0] == 1) {
3832 #if defined(TARGET_MIPS64)
3833 temp |= dsp & 0x7F;
3834 #else
3835 temp |= dsp & 0x3F;
3836 #endif
3837 }
3838
3839 if (mask[1] == 1) {
3840 temp |= dsp & 0x1F80;
3841 }
3842
3843 if (mask[2] == 1) {
3844 temp |= dsp & 0x2000;
3845 }
3846
3847 if (mask[3] == 1) {
3848 temp |= dsp & 0x00FF0000;
3849 }
3850
3851 if (mask[4] == 1) {
3852 #if defined(TARGET_MIPS64)
3853 temp |= dsp & 0xFF000000;
3854 #else
3855 temp |= dsp & 0x0F000000;
3856 #endif
3857 }
3858
3859 if (mask[5] == 1) {
3860 temp |= dsp & 0x4000;
3861 }
3862
3863 return temp;
3864 }
3865
3866
3867 #undef MIPSDSP_LHI
3868 #undef MIPSDSP_LLO
3869 #undef MIPSDSP_HI
3870 #undef MIPSDSP_LO
3871 #undef MIPSDSP_Q3
3872 #undef MIPSDSP_Q2
3873 #undef MIPSDSP_Q1
3874 #undef MIPSDSP_Q0
3875
3876 #undef MIPSDSP_SPLIT32_8
3877 #undef MIPSDSP_SPLIT32_16
3878
3879 #undef MIPSDSP_RETURN32_8
3880 #undef MIPSDSP_RETURN32_16
3881
3882 #ifdef TARGET_MIPS64
3883 #undef MIPSDSP_SPLIT64_16
3884 #undef MIPSDSP_SPLIT64_32
3885 #undef MIPSDSP_RETURN64_16
3886 #undef MIPSDSP_RETURN64_32
3887 #endif
Qemu copy for testing