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target-mips: use DSP unions for unary DSP operators
[qemu.git] / target-mips / dsp_helper.c
1 /*
2 * MIPS ASE DSP Instruction emulation helpers for QEMU.
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 * Dongxue Zhang <elta.era@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 /* As the byte ordering doesn't matter, i.e. all columns are treated
24 identically, these unions can be used directly. */
25 typedef union {
26 uint8_t ub[4];
27 int8_t sb[4];
28 uint16_t uh[2];
29 int16_t sh[2];
30 uint32_t uw[1];
31 int32_t sw[1];
32 } DSP32Value;
33
34 typedef union {
35 uint8_t ub[8];
36 int8_t sb[8];
37 uint16_t uh[4];
38 int16_t sh[4];
39 uint32_t uw[2];
40 int32_t sw[2];
41 uint64_t ul[1];
42 int64_t sl[1];
43 } DSP64Value;
44
45 /*** MIPS DSP internal functions begin ***/
46 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
47 #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
48
49 static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
50 CPUMIPSState *env)
51 {
52 env->active_tc.DSPControl |= (target_ulong)flag << position;
53 }
54
55 static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
56 {
57 env->active_tc.DSPControl |= (target_ulong)flag << 13;
58 }
59
60 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
61 {
62 return (env->active_tc.DSPControl >> 13) & 0x01;
63 }
64
65 static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
66 {
67 uint32_t filter;
68
69 filter = ((0x01 << len) - 1) << 24;
70 filter = ~filter;
71
72 env->active_tc.DSPControl &= filter;
73 env->active_tc.DSPControl |= (target_ulong)flag << 24;
74 }
75
76 static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
77 {
78 uint32_t filter;
79
80 filter = (0x01 << len) - 1;
81
82 return (env->active_tc.DSPControl >> 24) & filter;
83 }
84
85 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
86 {
87 target_ulong dspc;
88
89 dspc = env->active_tc.DSPControl;
90 #ifndef TARGET_MIPS64
91 dspc = dspc & 0xFFFFFFC0;
92 dspc |= pos;
93 #else
94 dspc = dspc & 0xFFFFFF80;
95 dspc |= pos;
96 #endif
97 env->active_tc.DSPControl = dspc;
98 }
99
100 static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
101 {
102 target_ulong dspc;
103 uint32_t pos;
104
105 dspc = env->active_tc.DSPControl;
106
107 #ifndef TARGET_MIPS64
108 pos = dspc & 0x3F;
109 #else
110 pos = dspc & 0x7F;
111 #endif
112
113 return pos;
114 }
115
116 static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
117 {
118 env->active_tc.DSPControl &= 0xFFFFBFFF;
119 env->active_tc.DSPControl |= (target_ulong)flag << 14;
120 }
121
122 #define DO_MIPS_SAT_ABS(size) \
123 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
124 CPUMIPSState *env) \
125 { \
126 if (a == INT##size##_MIN) { \
127 set_DSPControl_overflow_flag(1, 20, env); \
128 return INT##size##_MAX; \
129 } else { \
130 return MIPSDSP_ABS(a); \
131 } \
132 }
133 DO_MIPS_SAT_ABS(8)
134 DO_MIPS_SAT_ABS(16)
135 DO_MIPS_SAT_ABS(32)
136 #undef DO_MIPS_SAT_ABS
137
138 /* get sum value */
139 static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
140 {
141 int16_t tempI;
142
143 tempI = a + b;
144
145 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x8000)) {
146 set_DSPControl_overflow_flag(1, 20, env);
147 }
148
149 return tempI;
150 }
151
152 static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
153 CPUMIPSState *env)
154 {
155 int16_t tempS;
156
157 tempS = a + b;
158
159 if (MIPSDSP_OVERFLOW(a, b, tempS, 0x8000)) {
160 if (a > 0) {
161 tempS = 0x7FFF;
162 } else {
163 tempS = 0x8000;
164 }
165 set_DSPControl_overflow_flag(1, 20, env);
166 }
167
168 return tempS;
169 }
170
171 static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
172 CPUMIPSState *env)
173 {
174 int32_t tempI;
175
176 tempI = a + b;
177
178 if (MIPSDSP_OVERFLOW(a, b, tempI, 0x80000000)) {
179 if (a > 0) {
180 tempI = 0x7FFFFFFF;
181 } else {
182 tempI = 0x80000000;
183 }
184 set_DSPControl_overflow_flag(1, 20, env);
185 }
186
187 return tempI;
188 }
189
190 static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
191 {
192 uint16_t temp;
193
194 temp = (uint16_t)a + (uint16_t)b;
195
196 if (temp & 0x0100) {
197 set_DSPControl_overflow_flag(1, 20, env);
198 }
199
200 return temp & 0xFF;
201 }
202
203 static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
204 CPUMIPSState *env)
205 {
206 uint32_t temp;
207
208 temp = (uint32_t)a + (uint32_t)b;
209
210 if (temp & 0x00010000) {
211 set_DSPControl_overflow_flag(1, 20, env);
212 }
213
214 return temp & 0xFFFF;
215 }
216
217 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
218 CPUMIPSState *env)
219 {
220 uint8_t result;
221 uint16_t temp;
222
223 temp = (uint16_t)a + (uint16_t)b;
224 result = temp & 0xFF;
225
226 if (0x0100 & temp) {
227 result = 0xFF;
228 set_DSPControl_overflow_flag(1, 20, env);
229 }
230
231 return result;
232 }
233
234 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
235 CPUMIPSState *env)
236 {
237 uint16_t result;
238 uint32_t temp;
239
240 temp = (uint32_t)a + (uint32_t)b;
241 result = temp & 0xFFFF;
242
243 if (0x00010000 & temp) {
244 result = 0xFFFF;
245 set_DSPControl_overflow_flag(1, 20, env);
246 }
247
248 return result;
249 }
250
251 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
252 CPUMIPSState *env)
253 {
254 int64_t temp;
255 int32_t temp32, temp31, result;
256 int64_t temp_sum;
257
258 #ifndef TARGET_MIPS64
259 temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
260 (uint64_t)env->active_tc.LO[acc];
261 #else
262 temp = (uint64_t)env->active_tc.LO[acc];
263 #endif
264
265 temp_sum = (int64_t)a + temp;
266
267 temp32 = (temp_sum >> 32) & 0x01;
268 temp31 = (temp_sum >> 31) & 0x01;
269 result = temp_sum & 0xFFFFFFFF;
270
271 /* FIXME
272 This sat function may wrong, because user manual wrote:
273 temp127..0 ← temp + ( (signA) || a31..0
274 if ( temp32 ≠ temp31 ) then
275 if ( temp32 = 0 ) then
276 temp31..0 ← 0x80000000
277 else
278 temp31..0 ← 0x7FFFFFFF
279 endif
280 DSPControlouflag:16+acc ← 1
281 endif
282 */
283 if (temp32 != temp31) {
284 if (temp32 == 0) {
285 result = 0x7FFFFFFF;
286 } else {
287 result = 0x80000000;
288 }
289 set_DSPControl_overflow_flag(1, 16 + acc, env);
290 }
291
292 return result;
293 }
294
295 /* a[0] is LO, a[1] is HI. */
296 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
297 int32_t ac,
298 int64_t *a,
299 CPUMIPSState *env)
300 {
301 bool temp64;
302
303 ret[0] = env->active_tc.LO[ac] + a[0];
304 ret[1] = env->active_tc.HI[ac] + a[1];
305
306 if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
307 ((uint64_t)ret[0] < (uint64_t)a[0])) {
308 ret[1] += 1;
309 }
310 temp64 = ret[1] & 1;
311 if (temp64 != ((ret[0] >> 63) & 0x01)) {
312 if (temp64) {
313 ret[0] = (0x01ull << 63);
314 ret[1] = ~0ull;
315 } else {
316 ret[0] = (0x01ull << 63) - 1;
317 ret[1] = 0x00;
318 }
319 set_DSPControl_overflow_flag(1, 16 + ac, env);
320 }
321 }
322
323 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
324 int32_t ac,
325 int64_t *a,
326 CPUMIPSState *env)
327 {
328 bool temp64;
329
330 ret[0] = env->active_tc.LO[ac] - a[0];
331 ret[1] = env->active_tc.HI[ac] - a[1];
332
333 if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
334 ret[1] -= 1;
335 }
336 temp64 = ret[1] & 1;
337 if (temp64 != ((ret[0] >> 63) & 0x01)) {
338 if (temp64) {
339 ret[0] = (0x01ull << 63);
340 ret[1] = ~0ull;
341 } else {
342 ret[0] = (0x01ull << 63) - 1;
343 ret[1] = 0x00;
344 }
345 set_DSPControl_overflow_flag(1, 16 + ac, env);
346 }
347 }
348
349 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
350 CPUMIPSState *env)
351 {
352 int32_t temp;
353
354 temp = (int32_t)a * (int32_t)b;
355
356 if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
357 set_DSPControl_overflow_flag(1, 21, env);
358 }
359 temp &= 0x0000FFFF;
360
361 return temp;
362 }
363
364 static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
365 {
366 return a * b;
367 }
368
369 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
370 {
371 return a * b;
372 }
373
374 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
375 CPUMIPSState *env)
376 {
377 int32_t temp;
378
379 temp = (int32_t)a * (int32_t)b;
380
381 if (temp > (int)0x7FFF) {
382 temp = 0x00007FFF;
383 set_DSPControl_overflow_flag(1, 21, env);
384 } else if (temp < (int)0xffff8000) {
385 temp = 0xFFFF8000;
386 set_DSPControl_overflow_flag(1, 21, env);
387 }
388 temp &= 0x0000FFFF;
389
390 return temp;
391 }
392
393 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
394 CPUMIPSState *env)
395 {
396 int32_t temp;
397
398 if ((a == 0x8000) && (b == 0x8000)) {
399 temp = 0x7FFFFFFF;
400 set_DSPControl_overflow_flag(1, 21, env);
401 } else {
402 temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
403 }
404
405 return temp;
406 }
407
408 /* right shift */
409 static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
410 {
411 return a >> mov;
412 }
413
414 static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
415 {
416 return a >> mov;
417 }
418
419 static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
420 {
421 return a >> mov;
422 }
423
424 static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
425 {
426 return a >> mov;
427 }
428
429 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
430 {
431 return a >> mov;
432 }
433
434 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
435 {
436 int32_t temp;
437
438 temp = (int32_t)a + (int32_t)b;
439
440 return (temp >> 1) & 0xFFFF;
441 }
442
443 /* round right shift */
444 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
445 {
446 int32_t temp;
447
448 temp = (int32_t)a + (int32_t)b;
449 temp += 1;
450
451 return (temp >> 1) & 0xFFFF;
452 }
453
454 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
455 {
456 int64_t temp;
457
458 temp = (int64_t)a + (int64_t)b;
459
460 return (temp >> 1) & 0xFFFFFFFF;
461 }
462
463 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
464 {
465 int64_t temp;
466
467 temp = (int64_t)a + (int64_t)b;
468 temp += 1;
469
470 return (temp >> 1) & 0xFFFFFFFF;
471 }
472
473 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
474 {
475 uint16_t temp;
476
477 temp = (uint16_t)a + (uint16_t)b;
478
479 return (temp >> 1) & 0x00FF;
480 }
481
482 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
483 {
484 uint16_t temp;
485
486 temp = (uint16_t)a + (uint16_t)b + 1;
487
488 return (temp >> 1) & 0x00FF;
489 }
490
491 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
492 {
493 uint16_t temp;
494
495 temp = (uint16_t)a - (uint16_t)b;
496
497 return (temp >> 1) & 0x00FF;
498 }
499
500 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
501 {
502 uint16_t temp;
503
504 temp = (uint16_t)a - (uint16_t)b + 1;
505
506 return (temp >> 1) & 0x00FF;
507 }
508
509 /* 128 bits long. p[0] is LO, p[1] is HI. */
510 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
511 int32_t ac,
512 int32_t shift,
513 CPUMIPSState *env)
514 {
515 int64_t acc;
516
517 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
518 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
519 if (shift == 0) {
520 p[0] = acc << 1;
521 p[1] = (acc >> 63) & 0x01;
522 } else {
523 p[0] = acc >> (shift - 1);
524 p[1] = 0;
525 }
526 }
527
528 /* 128 bits long. p[0] is LO, p[1] is HI */
529 static inline void mipsdsp_rashift_acc(uint64_t *p,
530 uint32_t ac,
531 uint32_t shift,
532 CPUMIPSState *env)
533 {
534 uint64_t tempB, tempA;
535
536 tempB = env->active_tc.HI[ac];
537 tempA = env->active_tc.LO[ac];
538 shift = shift & 0x1F;
539
540 if (shift == 0) {
541 p[1] = tempB;
542 p[0] = tempA;
543 } else {
544 p[0] = (tempB << (64 - shift)) | (tempA >> shift);
545 p[1] = (int64_t)tempB >> shift;
546 }
547 }
548
549 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
550 static inline void mipsdsp_rndrashift_acc(uint64_t *p,
551 uint32_t ac,
552 uint32_t shift,
553 CPUMIPSState *env)
554 {
555 int64_t tempB, tempA;
556
557 tempB = env->active_tc.HI[ac];
558 tempA = env->active_tc.LO[ac];
559 shift = shift & 0x3F;
560
561 if (shift == 0) {
562 p[2] = tempB >> 63;
563 p[1] = (tempB << 1) | (tempA >> 63);
564 p[0] = tempA << 1;
565 } else {
566 p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
567 p[1] = (int64_t)tempB >> (shift - 1);
568 if (tempB >= 0) {
569 p[2] = 0x0;
570 } else {
571 p[2] = ~0ull;
572 }
573 }
574 }
575
576 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
577 CPUMIPSState *env)
578 {
579 int32_t temp;
580
581 if ((a == 0x8000) && (b == 0x8000)) {
582 temp = 0x7FFFFFFF;
583 set_DSPControl_overflow_flag(1, 16 + ac, env);
584 } else {
585 temp = ((uint32_t)a * (uint32_t)b) << 1;
586 }
587
588 return temp;
589 }
590
591 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
592 CPUMIPSState *env)
593 {
594 uint64_t temp;
595
596 if ((a == 0x80000000) && (b == 0x80000000)) {
597 temp = (0x01ull << 63) - 1;
598 set_DSPControl_overflow_flag(1, 16 + ac, env);
599 } else {
600 temp = ((uint64_t)a * (uint64_t)b) << 1;
601 }
602
603 return temp;
604 }
605
606 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
607 {
608 return (uint16_t)a * (uint16_t)b;
609 }
610
611 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
612 CPUMIPSState *env)
613 {
614 uint32_t tempI;
615
616 tempI = (uint32_t)a * (uint32_t)b;
617 if (tempI > 0x0000FFFF) {
618 tempI = 0x0000FFFF;
619 set_DSPControl_overflow_flag(1, 21, env);
620 }
621
622 return tempI & 0x0000FFFF;
623 }
624
625 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
626 {
627 return (uint64_t)a * (uint64_t)b;
628 }
629
630 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
631 CPUMIPSState *env)
632 {
633 uint32_t temp;
634
635 if ((a == 0x8000) && (b == 0x8000)) {
636 temp = 0x7FFF0000;
637 set_DSPControl_overflow_flag(1, 21, env);
638 } else {
639 temp = (a * b) << 1;
640 temp = temp + 0x00008000;
641 }
642
643 return (temp & 0xFFFF0000) >> 16;
644 }
645
646 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
647 CPUMIPSState *env)
648 {
649 int32_t temp;
650
651 if ((a == 0x8000) && (b == 0x8000)) {
652 temp = 0x7FFF0000;
653 set_DSPControl_overflow_flag(1, 21, env);
654 } else {
655 temp = ((uint32_t)a * (uint32_t)b);
656 temp = temp << 1;
657 }
658
659 return (temp >> 16) & 0x0000FFFF;
660 }
661
662 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
663 CPUMIPSState *env)
664 {
665 int64_t temp;
666
667 temp = (int32_t)a + 0x00008000;
668
669 if (a > (int)0x7fff8000) {
670 temp = 0x7FFFFFFF;
671 set_DSPControl_overflow_flag(1, 22, env);
672 }
673
674 return (temp >> 16) & 0xFFFF;
675 }
676
677 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
678 CPUMIPSState *env)
679 {
680 uint16_t mag;
681 uint32_t sign;
682
683 sign = (a >> 15) & 0x01;
684 mag = a & 0x7FFF;
685
686 if (sign == 0) {
687 if (mag > 0x7F80) {
688 set_DSPControl_overflow_flag(1, 22, env);
689 return 0xFF;
690 } else {
691 return (mag >> 7) & 0xFFFF;
692 }
693 } else {
694 set_DSPControl_overflow_flag(1, 22, env);
695 return 0x00;
696 }
697 }
698
699 static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
700 {
701 uint8_t sign;
702 uint8_t discard;
703
704 if (s == 0) {
705 return a;
706 } else {
707 sign = (a >> 7) & 0x01;
708 if (sign != 0) {
709 discard = (((0x01 << (8 - s)) - 1) << s) |
710 ((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
711 } else {
712 discard = a >> (6 - (s - 1));
713 }
714
715 if (discard != 0x00) {
716 set_DSPControl_overflow_flag(1, 22, env);
717 }
718 return a << s;
719 }
720 }
721
722 static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
723 CPUMIPSState *env)
724 {
725 uint8_t sign;
726 uint16_t discard;
727
728 if (s == 0) {
729 return a;
730 } else {
731 sign = (a >> 15) & 0x01;
732 if (sign != 0) {
733 discard = (((0x01 << (16 - s)) - 1) << s) |
734 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
735 } else {
736 discard = a >> (14 - (s - 1));
737 }
738
739 if ((discard != 0x0000) && (discard != 0xFFFF)) {
740 set_DSPControl_overflow_flag(1, 22, env);
741 }
742 return a << s;
743 }
744 }
745
746
747 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
748 CPUMIPSState *env)
749 {
750 uint32_t discard;
751
752 if (s == 0) {
753 return a;
754 } else {
755 discard = (int32_t)a >> (31 - (s - 1));
756
757 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
758 set_DSPControl_overflow_flag(1, 22, env);
759 }
760 return a << s;
761 }
762 }
763
764 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
765 CPUMIPSState *env)
766 {
767 uint8_t sign;
768 uint16_t discard;
769
770 if (s == 0) {
771 return a;
772 } else {
773 sign = (a >> 15) & 0x01;
774 if (sign != 0) {
775 discard = (((0x01 << (16 - s)) - 1) << s) |
776 ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
777 } else {
778 discard = a >> (14 - (s - 1));
779 }
780
781 if ((discard != 0x0000) && (discard != 0xFFFF)) {
782 set_DSPControl_overflow_flag(1, 22, env);
783 return (sign == 0) ? 0x7FFF : 0x8000;
784 } else {
785 return a << s;
786 }
787 }
788 }
789
790 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
791 CPUMIPSState *env)
792 {
793 uint8_t sign;
794 uint32_t discard;
795
796 if (s == 0) {
797 return a;
798 } else {
799 sign = (a >> 31) & 0x01;
800 if (sign != 0) {
801 discard = (((0x01 << (32 - s)) - 1) << s) |
802 ((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
803 } else {
804 discard = a >> (30 - (s - 1));
805 }
806
807 if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
808 set_DSPControl_overflow_flag(1, 22, env);
809 return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
810 } else {
811 return a << s;
812 }
813 }
814 }
815
816 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
817 {
818 uint32_t temp;
819
820 if (s == 0) {
821 temp = (uint32_t)a << 1;
822 } else {
823 temp = (int32_t)(int8_t)a >> (s - 1);
824 }
825
826 return (temp + 1) >> 1;
827 }
828
829 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
830 {
831 uint32_t temp;
832
833 if (s == 0) {
834 temp = (uint32_t)a << 1;
835 } else {
836 temp = (int32_t)(int16_t)a >> (s - 1);
837 }
838
839 return (temp + 1) >> 1;
840 }
841
842 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
843 {
844 int64_t temp;
845
846 if (s == 0) {
847 temp = (uint64_t)a << 1;
848 } else {
849 temp = (int64_t)(int32_t)a >> (s - 1);
850 }
851 temp += 1;
852
853 return (temp >> 1) & 0xFFFFFFFFull;
854 }
855
856 static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
857 {
858 int16_t temp;
859
860 temp = a - b;
861 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
862 set_DSPControl_overflow_flag(1, 20, env);
863 }
864
865 return temp;
866 }
867
868 static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
869 CPUMIPSState *env)
870 {
871 int16_t temp;
872
873 temp = a - b;
874 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) {
875 if (a > 0) {
876 temp = 0x7FFF;
877 } else {
878 temp = 0x8000;
879 }
880 set_DSPControl_overflow_flag(1, 20, env);
881 }
882
883 return temp;
884 }
885
886 static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
887 CPUMIPSState *env)
888 {
889 int32_t temp;
890
891 temp = a - b;
892 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
893 if (a > 0) {
894 temp = 0x7FFFFFFF;
895 } else {
896 temp = 0x80000000;
897 }
898 set_DSPControl_overflow_flag(1, 20, env);
899 }
900
901 return temp & 0xFFFFFFFFull;
902 }
903
904 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
905 {
906 int32_t temp;
907
908 temp = (int32_t)a - (int32_t)b;
909
910 return (temp >> 1) & 0x0000FFFF;
911 }
912
913 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
914 {
915 int32_t temp;
916
917 temp = (int32_t)a - (int32_t)b;
918 temp += 1;
919
920 return (temp >> 1) & 0x0000FFFF;
921 }
922
923 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
924 {
925 int64_t temp;
926
927 temp = (int64_t)a - (int64_t)b;
928
929 return (temp >> 1) & 0xFFFFFFFFull;
930 }
931
932 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
933 {
934 int64_t temp;
935
936 temp = (int64_t)a - (int64_t)b;
937 temp += 1;
938
939 return (temp >> 1) & 0xFFFFFFFFull;
940 }
941
942 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
943 CPUMIPSState *env)
944 {
945 uint8_t temp16;
946 uint32_t temp;
947
948 temp = (uint32_t)a - (uint32_t)b;
949 temp16 = (temp >> 16) & 0x01;
950 if (temp16 == 1) {
951 set_DSPControl_overflow_flag(1, 20, env);
952 }
953 return temp & 0x0000FFFF;
954 }
955
956 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
957 CPUMIPSState *env)
958 {
959 uint8_t temp16;
960 uint32_t temp;
961
962 temp = (uint32_t)a - (uint32_t)b;
963 temp16 = (temp >> 16) & 0x01;
964
965 if (temp16 == 1) {
966 temp = 0x0000;
967 set_DSPControl_overflow_flag(1, 20, env);
968 }
969
970 return temp & 0x0000FFFF;
971 }
972
973 static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
974 {
975 uint8_t temp8;
976 uint16_t temp;
977
978 temp = (uint16_t)a - (uint16_t)b;
979 temp8 = (temp >> 8) & 0x01;
980 if (temp8 == 1) {
981 set_DSPControl_overflow_flag(1, 20, env);
982 }
983
984 return temp & 0x00FF;
985 }
986
987 static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
988 {
989 uint8_t temp8;
990 uint16_t temp;
991
992 temp = (uint16_t)a - (uint16_t)b;
993 temp8 = (temp >> 8) & 0x01;
994 if (temp8 == 1) {
995 temp = 0x00;
996 set_DSPControl_overflow_flag(1, 20, env);
997 }
998
999 return temp & 0x00FF;
1000 }
1001
1002 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
1003 {
1004 int32_t temp;
1005
1006 temp = a - b;
1007 if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) {
1008 set_DSPControl_overflow_flag(1, 20, env);
1009 }
1010
1011 return temp;
1012 }
1013
1014 static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
1015 {
1016 int32_t temp;
1017
1018 temp = a + b;
1019
1020 if (MIPSDSP_OVERFLOW(a, b, temp, 0x80000000)) {
1021 set_DSPControl_overflow_flag(1, 20, env);
1022 }
1023
1024 return temp;
1025 }
1026
1027 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
1028 {
1029 return a == b;
1030 }
1031
1032 static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
1033 {
1034 return a <= b;
1035 }
1036
1037 static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
1038 {
1039 return a < b;
1040 }
1041
1042 static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
1043 {
1044 return a == b;
1045 }
1046
1047 static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
1048 {
1049 return a <= b;
1050 }
1051
1052 static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
1053 {
1054 return a < b;
1055 }
1056 /*** MIPS DSP internal functions end ***/
1057
1058 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1059 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1060 #define MIPSDSP_HI 0xFFFF0000
1061 #define MIPSDSP_LO 0x0000FFFF
1062 #define MIPSDSP_Q3 0xFF000000
1063 #define MIPSDSP_Q2 0x00FF0000
1064 #define MIPSDSP_Q1 0x0000FF00
1065 #define MIPSDSP_Q0 0x000000FF
1066
1067 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
1068 do { \
1069 a = (num >> 24) & MIPSDSP_Q0; \
1070 b = (num >> 16) & MIPSDSP_Q0; \
1071 c = (num >> 8) & MIPSDSP_Q0; \
1072 d = num & MIPSDSP_Q0; \
1073 } while (0)
1074
1075 #define MIPSDSP_SPLIT32_16(num, a, b) \
1076 do { \
1077 a = (num >> 16) & MIPSDSP_LO; \
1078 b = num & MIPSDSP_LO; \
1079 } while (0)
1080
1081 #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
1082 (((uint32_t)a << 24) | \
1083 (((uint32_t)b << 16) | \
1084 (((uint32_t)c << 8) | \
1085 ((uint32_t)d & 0xFF)))))
1086 #define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
1087 (((uint32_t)a << 16) | \
1088 ((uint32_t)b & 0xFFFF)))
1089
1090 #ifdef TARGET_MIPS64
1091 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
1092 do { \
1093 a = (num >> 48) & MIPSDSP_LO; \
1094 b = (num >> 32) & MIPSDSP_LO; \
1095 c = (num >> 16) & MIPSDSP_LO; \
1096 d = num & MIPSDSP_LO; \
1097 } while (0)
1098
1099 #define MIPSDSP_SPLIT64_32(num, a, b) \
1100 do { \
1101 a = (num >> 32) & MIPSDSP_LLO; \
1102 b = num & MIPSDSP_LLO; \
1103 } while (0)
1104
1105 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1106 ((uint64_t)b << 32) | \
1107 ((uint64_t)c << 16) | \
1108 (uint64_t)d)
1109 #define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
1110 #endif
1111
1112 /** DSP Arithmetic Sub-class insns **/
1113 #define MIPSDSP32_UNOP_ENV(name, func, element) \
1114 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
1115 { \
1116 DSP32Value dt; \
1117 unsigned int i, n; \
1118 \
1119 n = sizeof(DSP32Value) / sizeof(dt.element[0]); \
1120 dt.sw[0] = rt; \
1121 \
1122 for (i = 0; i < n; i++) { \
1123 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1124 } \
1125 \
1126 return (target_long)dt.sw[0]; \
1127 }
1128 MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh)
1129 MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb)
1130 MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw)
1131 #undef MIPSDSP32_UNOP_ENV
1132
1133 #if defined(TARGET_MIPS64)
1134 #define MIPSDSP64_UNOP_ENV(name, func, element) \
1135 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env) \
1136 { \
1137 DSP64Value dt; \
1138 unsigned int i, n; \
1139 \
1140 n = sizeof(DSP64Value) / sizeof(dt.element[0]); \
1141 dt.sl[0] = rt; \
1142 \
1143 for (i = 0; i < n; i++) { \
1144 dt.element[i] = mipsdsp_##func(dt.element[i], env); \
1145 } \
1146 \
1147 return dt.sl[0]; \
1148 }
1149 MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb)
1150 MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh)
1151 MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw)
1152 #undef MIPSDSP64_UNOP_ENV
1153 #endif
1154
1155 #define MIPSDSP32_BINOP(name, func, element) \
1156 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1157 { \
1158 DSP32Value ds, dt; \
1159 unsigned int i, n; \
1160 \
1161 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1162 ds.sw[0] = rs; \
1163 dt.sw[0] = rt; \
1164 \
1165 for (i = 0; i < n; i++) { \
1166 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1167 } \
1168 \
1169 return (target_long)ds.sw[0]; \
1170 }
1171 MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh);
1172 MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh);
1173 MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw);
1174 MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw);
1175 MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub);
1176 MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub);
1177 MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh);
1178 MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh);
1179 MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw);
1180 MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw);
1181 #undef MIPSDSP32_BINOP
1182
1183 #define MIPSDSP32_BINOP_ENV(name, func, element) \
1184 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1185 CPUMIPSState *env) \
1186 { \
1187 DSP32Value ds, dt; \
1188 unsigned int i, n; \
1189 \
1190 n = sizeof(DSP32Value) / sizeof(ds.element[0]); \
1191 ds.sw[0] = rs; \
1192 dt.sw[0] = rt; \
1193 \
1194 for (i = 0 ; i < n ; i++) { \
1195 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1196 } \
1197 \
1198 return (target_long)ds.sw[0]; \
1199 }
1200 MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh)
1201 MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh)
1202 MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw);
1203 MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh)
1204 MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub);
1205 MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh)
1206 MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub);
1207 MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh);
1208 MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh);
1209 MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw);
1210 MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh);
1211 MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub);
1212 MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh);
1213 MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub);
1214 #undef MIPSDSP32_BINOP_ENV
1215
1216 #ifdef TARGET_MIPS64
1217 #define MIPSDSP64_BINOP(name, func, element) \
1218 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
1219 { \
1220 DSP64Value ds, dt; \
1221 unsigned int i, n; \
1222 \
1223 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1224 ds.sl[0] = rs; \
1225 dt.sl[0] = rt; \
1226 \
1227 for (i = 0 ; i < n ; i++) { \
1228 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]); \
1229 } \
1230 \
1231 return ds.sl[0]; \
1232 }
1233 MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub);
1234 MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub);
1235 MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub);
1236 MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub);
1237 #undef MIPSDSP64_BINOP
1238
1239 #define MIPSDSP64_BINOP_ENV(name, func, element) \
1240 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1241 CPUMIPSState *env) \
1242 { \
1243 DSP64Value ds, dt; \
1244 unsigned int i, n; \
1245 \
1246 n = sizeof(DSP64Value) / sizeof(ds.element[0]); \
1247 ds.sl[0] = rs; \
1248 dt.sl[0] = rt; \
1249 \
1250 for (i = 0 ; i < n ; i++) { \
1251 ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1252 } \
1253 \
1254 return ds.sl[0]; \
1255 }
1256 MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw);
1257 MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh);
1258 MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw);
1259 MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh);
1260 MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh);
1261 MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh);
1262 MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh);
1263 MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh);
1264 MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw);
1265 MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh);
1266 MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw);
1267 MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh);
1268 MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh);
1269 MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh);
1270 MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh);
1271 MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh);
1272 #undef MIPSDSP64_BINOP_ENV
1273
1274 #endif
1275
1276 #define SUBUH_QB(name, var) \
1277 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1278 { \
1279 uint8_t rs3, rs2, rs1, rs0; \
1280 uint8_t rt3, rt2, rt1, rt0; \
1281 uint8_t tempD, tempC, tempB, tempA; \
1282 \
1283 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1284 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1285 \
1286 tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
1287 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1288 tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
1289 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1290 \
1291 return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
1292 ((uint32_t)tempB << 8) | ((uint32_t)tempA); \
1293 }
1294
1295 SUBUH_QB(subuh, 0);
1296 SUBUH_QB(subuh_r, 1);
1297
1298 #undef SUBUH_QB
1299
1300 target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1301 {
1302 uint64_t temp, tempRs, tempRt;
1303 int32_t flag;
1304
1305 tempRs = (uint64_t)rs & MIPSDSP_LLO;
1306 tempRt = (uint64_t)rt & MIPSDSP_LLO;
1307
1308 temp = tempRs + tempRt;
1309 flag = (temp & 0x0100000000ull) >> 32;
1310 set_DSPControl_carryflag(flag, env);
1311
1312 return (target_long)(int32_t)(temp & MIPSDSP_LLO);
1313 }
1314
1315 target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1316 {
1317 uint32_t rd;
1318 int32_t temp32, temp31;
1319 int64_t tempL;
1320
1321 tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt +
1322 get_DSPControl_carryflag(env);
1323 temp31 = (tempL >> 31) & 0x01;
1324 temp32 = (tempL >> 32) & 0x01;
1325
1326 if (temp31 != temp32) {
1327 set_DSPControl_overflow_flag(1, 20, env);
1328 }
1329
1330 rd = tempL & MIPSDSP_LLO;
1331
1332 return (target_long)(int32_t)rd;
1333 }
1334
1335 target_ulong helper_modsub(target_ulong rs, target_ulong rt)
1336 {
1337 int32_t decr;
1338 uint16_t lastindex;
1339 target_ulong rd;
1340
1341 decr = rt & MIPSDSP_Q0;
1342 lastindex = (rt >> 8) & MIPSDSP_LO;
1343
1344 if ((rs & MIPSDSP_LLO) == 0x00000000) {
1345 rd = (target_ulong)lastindex;
1346 } else {
1347 rd = rs - decr;
1348 }
1349
1350 return rd;
1351 }
1352
1353 target_ulong helper_raddu_w_qb(target_ulong rs)
1354 {
1355 uint8_t rs3, rs2, rs1, rs0;
1356 uint16_t temp;
1357
1358 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
1359
1360 temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
1361
1362 return (target_ulong)temp;
1363 }
1364
1365 #if defined(TARGET_MIPS64)
1366 target_ulong helper_raddu_l_ob(target_ulong rs)
1367 {
1368 int i;
1369 uint16_t rs_t[8];
1370 uint64_t temp;
1371
1372 temp = 0;
1373
1374 for (i = 0; i < 8; i++) {
1375 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
1376 temp += (uint64_t)rs_t[i];
1377 }
1378
1379 return temp;
1380 }
1381 #endif
1382
1383 #define PRECR_QB_PH(name, a, b)\
1384 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1385 { \
1386 uint8_t tempD, tempC, tempB, tempA; \
1387 \
1388 tempD = (rs >> a) & MIPSDSP_Q0; \
1389 tempC = (rs >> b) & MIPSDSP_Q0; \
1390 tempB = (rt >> a) & MIPSDSP_Q0; \
1391 tempA = (rt >> b) & MIPSDSP_Q0; \
1392 \
1393 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1394 }
1395
1396 PRECR_QB_PH(precr, 16, 0);
1397 PRECR_QB_PH(precrq, 24, 8);
1398
1399 #undef PRECR_QB_OH
1400
1401 target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
1402 target_ulong rt)
1403 {
1404 uint16_t tempB, tempA;
1405
1406 tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
1407 tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
1408
1409 return MIPSDSP_RETURN32_16(tempB, tempA);
1410 }
1411
1412 target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
1413 target_ulong rs, target_ulong rt)
1414 {
1415 uint64_t tempB, tempA;
1416
1417 /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1418 if (sa == 0) {
1419 tempB = (rt & MIPSDSP_LO) << 1;
1420 tempA = (rs & MIPSDSP_LO) << 1;
1421 } else {
1422 tempB = ((int32_t)rt >> (sa - 1)) + 1;
1423 tempA = ((int32_t)rs >> (sa - 1)) + 1;
1424 }
1425 rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
1426
1427 return (target_long)(int32_t)rt;
1428 }
1429
1430 target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
1431 {
1432 uint16_t tempB, tempA;
1433
1434 tempB = (rs & MIPSDSP_HI) >> 16;
1435 tempA = (rt & MIPSDSP_HI) >> 16;
1436
1437 return MIPSDSP_RETURN32_16(tempB, tempA);
1438 }
1439
1440 target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
1441 CPUMIPSState *env)
1442 {
1443 uint16_t tempB, tempA;
1444
1445 tempB = mipsdsp_trunc16_sat16_round(rs, env);
1446 tempA = mipsdsp_trunc16_sat16_round(rt, env);
1447
1448 return MIPSDSP_RETURN32_16(tempB, tempA);
1449 }
1450
1451 #if defined(TARGET_MIPS64)
1452 target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
1453 {
1454 uint8_t rs6, rs4, rs2, rs0;
1455 uint8_t rt6, rt4, rt2, rt0;
1456 uint64_t temp;
1457
1458 rs6 = (rs >> 48) & MIPSDSP_Q0;
1459 rs4 = (rs >> 32) & MIPSDSP_Q0;
1460 rs2 = (rs >> 16) & MIPSDSP_Q0;
1461 rs0 = rs & MIPSDSP_Q0;
1462 rt6 = (rt >> 48) & MIPSDSP_Q0;
1463 rt4 = (rt >> 32) & MIPSDSP_Q0;
1464 rt2 = (rt >> 16) & MIPSDSP_Q0;
1465 rt0 = rt & MIPSDSP_Q0;
1466
1467 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1468 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1469 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1470 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1471
1472 return temp;
1473 }
1474
1475 #define PRECR_QH_PW(name, var) \
1476 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1477 uint32_t sa) \
1478 { \
1479 uint16_t rs3, rs2, rs1, rs0; \
1480 uint16_t rt3, rt2, rt1, rt0; \
1481 uint16_t tempD, tempC, tempB, tempA; \
1482 \
1483 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1484 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1485 \
1486 /* When sa = 0, we use rt2, rt0, rs2, rs0; \
1487 * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
1488 if (sa == 0) { \
1489 tempD = rt2 << var; \
1490 tempC = rt0 << var; \
1491 tempB = rs2 << var; \
1492 tempA = rs0 << var; \
1493 } else { \
1494 tempD = (((int16_t)rt3 >> sa) + var) >> var; \
1495 tempC = (((int16_t)rt1 >> sa) + var) >> var; \
1496 tempB = (((int16_t)rs3 >> sa) + var) >> var; \
1497 tempA = (((int16_t)rs1 >> sa) + var) >> var; \
1498 } \
1499 \
1500 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1501 }
1502
1503 PRECR_QH_PW(sra, 0);
1504 PRECR_QH_PW(sra_r, 1);
1505
1506 #undef PRECR_QH_PW
1507
1508 target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
1509 {
1510 uint8_t rs6, rs4, rs2, rs0;
1511 uint8_t rt6, rt4, rt2, rt0;
1512 uint64_t temp;
1513
1514 rs6 = (rs >> 56) & MIPSDSP_Q0;
1515 rs4 = (rs >> 40) & MIPSDSP_Q0;
1516 rs2 = (rs >> 24) & MIPSDSP_Q0;
1517 rs0 = (rs >> 8) & MIPSDSP_Q0;
1518 rt6 = (rt >> 56) & MIPSDSP_Q0;
1519 rt4 = (rt >> 40) & MIPSDSP_Q0;
1520 rt2 = (rt >> 24) & MIPSDSP_Q0;
1521 rt0 = (rt >> 8) & MIPSDSP_Q0;
1522
1523 temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1524 ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1525 ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1526 ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1527
1528 return temp;
1529 }
1530
1531 target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
1532 {
1533 uint16_t tempD, tempC, tempB, tempA;
1534
1535 tempD = (rs >> 48) & MIPSDSP_LO;
1536 tempC = (rs >> 16) & MIPSDSP_LO;
1537 tempB = (rt >> 48) & MIPSDSP_LO;
1538 tempA = (rt >> 16) & MIPSDSP_LO;
1539
1540 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1541 }
1542
1543 target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
1544 CPUMIPSState *env)
1545 {
1546 uint32_t rs2, rs0;
1547 uint32_t rt2, rt0;
1548 uint16_t tempD, tempC, tempB, tempA;
1549
1550 rs2 = (rs >> 32) & MIPSDSP_LLO;
1551 rs0 = rs & MIPSDSP_LLO;
1552 rt2 = (rt >> 32) & MIPSDSP_LLO;
1553 rt0 = rt & MIPSDSP_LLO;
1554
1555 tempD = mipsdsp_trunc16_sat16_round(rs2, env);
1556 tempC = mipsdsp_trunc16_sat16_round(rs0, env);
1557 tempB = mipsdsp_trunc16_sat16_round(rt2, env);
1558 tempA = mipsdsp_trunc16_sat16_round(rt0, env);
1559
1560 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1561 }
1562
1563 target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
1564 {
1565 uint32_t tempB, tempA;
1566
1567 tempB = (rs >> 32) & MIPSDSP_LLO;
1568 tempA = (rt >> 32) & MIPSDSP_LLO;
1569
1570 return MIPSDSP_RETURN64_32(tempB, tempA);
1571 }
1572 #endif
1573
1574 target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
1575 CPUMIPSState *env)
1576 {
1577 uint8_t tempD, tempC, tempB, tempA;
1578 uint16_t rsh, rsl, rth, rtl;
1579
1580 rsh = (rs & MIPSDSP_HI) >> 16;
1581 rsl = rs & MIPSDSP_LO;
1582 rth = (rt & MIPSDSP_HI) >> 16;
1583 rtl = rt & MIPSDSP_LO;
1584
1585 tempD = mipsdsp_sat8_reduce_precision(rsh, env);
1586 tempC = mipsdsp_sat8_reduce_precision(rsl, env);
1587 tempB = mipsdsp_sat8_reduce_precision(rth, env);
1588 tempA = mipsdsp_sat8_reduce_precision(rtl, env);
1589
1590 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1591 }
1592
1593 #if defined(TARGET_MIPS64)
1594 target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
1595 CPUMIPSState *env)
1596 {
1597 int i;
1598 uint16_t rs3, rs2, rs1, rs0;
1599 uint16_t rt3, rt2, rt1, rt0;
1600 uint8_t temp[8];
1601 uint64_t result;
1602
1603 result = 0;
1604
1605 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
1606 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
1607
1608 temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
1609 temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
1610 temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
1611 temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
1612 temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
1613 temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
1614 temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
1615 temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
1616
1617 for (i = 0; i < 8; i++) {
1618 result |= (uint64_t)temp[i] << (8 * i);
1619 }
1620
1621 return result;
1622 }
1623
1624 #define PRECEQ_PW(name, a, b) \
1625 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1626 { \
1627 uint16_t tempB, tempA; \
1628 uint32_t tempBI, tempAI; \
1629 \
1630 tempB = (rt >> a) & MIPSDSP_LO; \
1631 tempA = (rt >> b) & MIPSDSP_LO; \
1632 \
1633 tempBI = (uint32_t)tempB << 16; \
1634 tempAI = (uint32_t)tempA << 16; \
1635 \
1636 return MIPSDSP_RETURN64_32(tempBI, tempAI); \
1637 }
1638
1639 PRECEQ_PW(qhl, 48, 32);
1640 PRECEQ_PW(qhr, 16, 0);
1641 PRECEQ_PW(qhla, 48, 16);
1642 PRECEQ_PW(qhra, 32, 0);
1643
1644 #undef PRECEQ_PW
1645
1646 #endif
1647
1648 #define PRECEQU_PH(name, a, b) \
1649 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1650 { \
1651 uint16_t tempB, tempA; \
1652 \
1653 tempB = (rt >> a) & MIPSDSP_Q0; \
1654 tempA = (rt >> b) & MIPSDSP_Q0; \
1655 \
1656 tempB = tempB << 7; \
1657 tempA = tempA << 7; \
1658 \
1659 return MIPSDSP_RETURN32_16(tempB, tempA); \
1660 }
1661
1662 PRECEQU_PH(qbl, 24, 16);
1663 PRECEQU_PH(qbr, 8, 0);
1664 PRECEQU_PH(qbla, 24, 8);
1665 PRECEQU_PH(qbra, 16, 0);
1666
1667 #undef PRECEQU_PH
1668
1669 #if defined(TARGET_MIPS64)
1670 #define PRECEQU_QH(name, a, b, c, d) \
1671 target_ulong helper_precequ_qh_##name(target_ulong rt) \
1672 { \
1673 uint16_t tempD, tempC, tempB, tempA; \
1674 \
1675 tempD = (rt >> a) & MIPSDSP_Q0; \
1676 tempC = (rt >> b) & MIPSDSP_Q0; \
1677 tempB = (rt >> c) & MIPSDSP_Q0; \
1678 tempA = (rt >> d) & MIPSDSP_Q0; \
1679 \
1680 tempD = tempD << 7; \
1681 tempC = tempC << 7; \
1682 tempB = tempB << 7; \
1683 tempA = tempA << 7; \
1684 \
1685 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1686 }
1687
1688 PRECEQU_QH(obl, 56, 48, 40, 32);
1689 PRECEQU_QH(obr, 24, 16, 8, 0);
1690 PRECEQU_QH(obla, 56, 40, 24, 8);
1691 PRECEQU_QH(obra, 48, 32, 16, 0);
1692
1693 #undef PRECEQU_QH
1694
1695 #endif
1696
1697 #define PRECEU_PH(name, a, b) \
1698 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1699 { \
1700 uint16_t tempB, tempA; \
1701 \
1702 tempB = (rt >> a) & MIPSDSP_Q0; \
1703 tempA = (rt >> b) & MIPSDSP_Q0; \
1704 \
1705 return MIPSDSP_RETURN32_16(tempB, tempA); \
1706 }
1707
1708 PRECEU_PH(qbl, 24, 16);
1709 PRECEU_PH(qbr, 8, 0);
1710 PRECEU_PH(qbla, 24, 8);
1711 PRECEU_PH(qbra, 16, 0);
1712
1713 #undef PRECEU_PH
1714
1715 #if defined(TARGET_MIPS64)
1716 #define PRECEU_QH(name, a, b, c, d) \
1717 target_ulong helper_preceu_qh_##name(target_ulong rt) \
1718 { \
1719 uint16_t tempD, tempC, tempB, tempA; \
1720 \
1721 tempD = (rt >> a) & MIPSDSP_Q0; \
1722 tempC = (rt >> b) & MIPSDSP_Q0; \
1723 tempB = (rt >> c) & MIPSDSP_Q0; \
1724 tempA = (rt >> d) & MIPSDSP_Q0; \
1725 \
1726 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1727 }
1728
1729 PRECEU_QH(obl, 56, 48, 40, 32);
1730 PRECEU_QH(obr, 24, 16, 8, 0);
1731 PRECEU_QH(obla, 56, 40, 24, 8);
1732 PRECEU_QH(obra, 48, 32, 16, 0);
1733
1734 #undef PRECEU_QH
1735
1736 #endif
1737
1738 /** DSP GPR-Based Shift Sub-class insns **/
1739 #define SHIFT_QB(name, func) \
1740 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1741 { \
1742 uint8_t rt3, rt2, rt1, rt0; \
1743 \
1744 sa = sa & 0x07; \
1745 \
1746 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1747 \
1748 rt3 = mipsdsp_##func(rt3, sa); \
1749 rt2 = mipsdsp_##func(rt2, sa); \
1750 rt1 = mipsdsp_##func(rt1, sa); \
1751 rt0 = mipsdsp_##func(rt0, sa); \
1752 \
1753 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1754 }
1755
1756 #define SHIFT_QB_ENV(name, func) \
1757 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1758 CPUMIPSState *env) \
1759 { \
1760 uint8_t rt3, rt2, rt1, rt0; \
1761 \
1762 sa = sa & 0x07; \
1763 \
1764 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1765 \
1766 rt3 = mipsdsp_##func(rt3, sa, env); \
1767 rt2 = mipsdsp_##func(rt2, sa, env); \
1768 rt1 = mipsdsp_##func(rt1, sa, env); \
1769 rt0 = mipsdsp_##func(rt0, sa, env); \
1770 \
1771 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1772 }
1773
1774 SHIFT_QB_ENV(shll, lshift8);
1775 SHIFT_QB(shrl, rshift_u8);
1776
1777 SHIFT_QB(shra, rashift8);
1778 SHIFT_QB(shra_r, rnd8_rashift);
1779
1780 #undef SHIFT_QB
1781 #undef SHIFT_QB_ENV
1782
1783 #if defined(TARGET_MIPS64)
1784 #define SHIFT_OB(name, func) \
1785 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1786 { \
1787 int i; \
1788 uint8_t rt_t[8]; \
1789 uint64_t temp; \
1790 \
1791 sa = sa & 0x07; \
1792 temp = 0; \
1793 \
1794 for (i = 0; i < 8; i++) { \
1795 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1796 rt_t[i] = mipsdsp_##func(rt_t[i], sa); \
1797 temp |= (uint64_t)rt_t[i] << (8 * i); \
1798 } \
1799 \
1800 return temp; \
1801 }
1802
1803 #define SHIFT_OB_ENV(name, func) \
1804 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
1805 CPUMIPSState *env) \
1806 { \
1807 int i; \
1808 uint8_t rt_t[8]; \
1809 uint64_t temp; \
1810 \
1811 sa = sa & 0x07; \
1812 temp = 0; \
1813 \
1814 for (i = 0; i < 8; i++) { \
1815 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1816 rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \
1817 temp |= (uint64_t)rt_t[i] << (8 * i); \
1818 } \
1819 \
1820 return temp; \
1821 }
1822
1823 SHIFT_OB_ENV(shll, lshift8);
1824 SHIFT_OB(shrl, rshift_u8);
1825
1826 SHIFT_OB(shra, rashift8);
1827 SHIFT_OB(shra_r, rnd8_rashift);
1828
1829 #undef SHIFT_OB
1830 #undef SHIFT_OB_ENV
1831
1832 #endif
1833
1834 #define SHIFT_PH(name, func) \
1835 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
1836 CPUMIPSState *env) \
1837 { \
1838 uint16_t rth, rtl; \
1839 \
1840 sa = sa & 0x0F; \
1841 \
1842 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1843 \
1844 rth = mipsdsp_##func(rth, sa, env); \
1845 rtl = mipsdsp_##func(rtl, sa, env); \
1846 \
1847 return MIPSDSP_RETURN32_16(rth, rtl); \
1848 }
1849
1850 SHIFT_PH(shll, lshift16);
1851 SHIFT_PH(shll_s, sat16_lshift);
1852
1853 #undef SHIFT_PH
1854
1855 #if defined(TARGET_MIPS64)
1856 #define SHIFT_QH(name, func) \
1857 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
1858 { \
1859 uint16_t rt3, rt2, rt1, rt0; \
1860 \
1861 sa = sa & 0x0F; \
1862 \
1863 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1864 \
1865 rt3 = mipsdsp_##func(rt3, sa); \
1866 rt2 = mipsdsp_##func(rt2, sa); \
1867 rt1 = mipsdsp_##func(rt1, sa); \
1868 rt0 = mipsdsp_##func(rt0, sa); \
1869 \
1870 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1871 }
1872
1873 #define SHIFT_QH_ENV(name, func) \
1874 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
1875 CPUMIPSState *env) \
1876 { \
1877 uint16_t rt3, rt2, rt1, rt0; \
1878 \
1879 sa = sa & 0x0F; \
1880 \
1881 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1882 \
1883 rt3 = mipsdsp_##func(rt3, sa, env); \
1884 rt2 = mipsdsp_##func(rt2, sa, env); \
1885 rt1 = mipsdsp_##func(rt1, sa, env); \
1886 rt0 = mipsdsp_##func(rt0, sa, env); \
1887 \
1888 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
1889 }
1890
1891 SHIFT_QH_ENV(shll, lshift16);
1892 SHIFT_QH_ENV(shll_s, sat16_lshift);
1893
1894 SHIFT_QH(shrl, rshift_u16);
1895 SHIFT_QH(shra, rashift16);
1896 SHIFT_QH(shra_r, rnd16_rashift);
1897
1898 #undef SHIFT_QH
1899 #undef SHIFT_QH_ENV
1900
1901 #endif
1902
1903 #define SHIFT_W(name, func) \
1904 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
1905 { \
1906 uint32_t temp; \
1907 \
1908 sa = sa & 0x1F; \
1909 temp = mipsdsp_##func(rt, sa); \
1910 \
1911 return (target_long)(int32_t)temp; \
1912 }
1913
1914 #define SHIFT_W_ENV(name, func) \
1915 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
1916 CPUMIPSState *env) \
1917 { \
1918 uint32_t temp; \
1919 \
1920 sa = sa & 0x1F; \
1921 temp = mipsdsp_##func(rt, sa, env); \
1922 \
1923 return (target_long)(int32_t)temp; \
1924 }
1925
1926 SHIFT_W_ENV(shll_s, sat32_lshift);
1927 SHIFT_W(shra_r, rnd32_rashift);
1928
1929 #undef SHIFT_W
1930 #undef SHIFT_W_ENV
1931
1932 #if defined(TARGET_MIPS64)
1933 #define SHIFT_PW(name, func) \
1934 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
1935 { \
1936 uint32_t rt1, rt0; \
1937 \
1938 sa = sa & 0x1F; \
1939 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1940 \
1941 rt1 = mipsdsp_##func(rt1, sa); \
1942 rt0 = mipsdsp_##func(rt0, sa); \
1943 \
1944 return MIPSDSP_RETURN64_32(rt1, rt0); \
1945 }
1946
1947 #define SHIFT_PW_ENV(name, func) \
1948 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
1949 CPUMIPSState *env) \
1950 { \
1951 uint32_t rt1, rt0; \
1952 \
1953 sa = sa & 0x1F; \
1954 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1955 \
1956 rt1 = mipsdsp_##func(rt1, sa, env); \
1957 rt0 = mipsdsp_##func(rt0, sa, env); \
1958 \
1959 return MIPSDSP_RETURN64_32(rt1, rt0); \
1960 }
1961
1962 SHIFT_PW_ENV(shll, lshift32);
1963 SHIFT_PW_ENV(shll_s, sat32_lshift);
1964
1965 SHIFT_PW(shra, rashift32);
1966 SHIFT_PW(shra_r, rnd32_rashift);
1967
1968 #undef SHIFT_PW
1969 #undef SHIFT_PW_ENV
1970
1971 #endif
1972
1973 #define SHIFT_PH(name, func) \
1974 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
1975 { \
1976 uint16_t rth, rtl; \
1977 \
1978 sa = sa & 0x0F; \
1979 \
1980 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1981 \
1982 rth = mipsdsp_##func(rth, sa); \
1983 rtl = mipsdsp_##func(rtl, sa); \
1984 \
1985 return MIPSDSP_RETURN32_16(rth, rtl); \
1986 }
1987
1988 SHIFT_PH(shrl, rshift_u16);
1989 SHIFT_PH(shra, rashift16);
1990 SHIFT_PH(shra_r, rnd16_rashift);
1991
1992 #undef SHIFT_PH
1993
1994 /** DSP Multiply Sub-class insns **/
1995 /* Return value made up by two 16bits value.
1996 * FIXME give the macro a better name.
1997 */
1998 #define MUL_RETURN32_16_PH(name, func, \
1999 rsmov1, rsmov2, rsfilter, \
2000 rtmov1, rtmov2, rtfilter) \
2001 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2002 CPUMIPSState *env) \
2003 { \
2004 uint16_t rsB, rsA, rtB, rtA; \
2005 \
2006 rsB = (rs >> rsmov1) & rsfilter; \
2007 rsA = (rs >> rsmov2) & rsfilter; \
2008 rtB = (rt >> rtmov1) & rtfilter; \
2009 rtA = (rt >> rtmov2) & rtfilter; \
2010 \
2011 rsB = mipsdsp_##func(rsB, rtB, env); \
2012 rsA = mipsdsp_##func(rsA, rtA, env); \
2013 \
2014 return MIPSDSP_RETURN32_16(rsB, rsA); \
2015 }
2016
2017 MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \
2018 24, 16, MIPSDSP_Q0, \
2019 16, 0, MIPSDSP_LO);
2020 MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \
2021 8, 0, MIPSDSP_Q0, \
2022 16, 0, MIPSDSP_LO);
2023 MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \
2024 16, 0, MIPSDSP_LO, \
2025 16, 0, MIPSDSP_LO);
2026 MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \
2027 16, 0, MIPSDSP_LO, \
2028 16, 0, MIPSDSP_LO);
2029 MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \
2030 16, 0, MIPSDSP_LO, \
2031 16, 0, MIPSDSP_LO);
2032 MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \
2033 16, 0, MIPSDSP_LO, \
2034 16, 0, MIPSDSP_LO);
2035
2036 #undef MUL_RETURN32_16_PH
2037
2038 #define MUL_RETURN32_32_ph(name, func, movbits) \
2039 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2040 CPUMIPSState *env) \
2041 { \
2042 int16_t rsh, rth; \
2043 int32_t temp; \
2044 \
2045 rsh = (rs >> movbits) & MIPSDSP_LO; \
2046 rth = (rt >> movbits) & MIPSDSP_LO; \
2047 temp = mipsdsp_##func(rsh, rth, env); \
2048 \
2049 return (target_long)(int32_t)temp; \
2050 }
2051
2052 MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16);
2053 MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0);
2054
2055 #undef MUL_RETURN32_32_ph
2056
2057 #define MUL_VOID_PH(name, use_ac_env) \
2058 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2059 CPUMIPSState *env) \
2060 { \
2061 int16_t rsh, rsl, rth, rtl; \
2062 int32_t tempB, tempA; \
2063 int64_t acc, dotp; \
2064 \
2065 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2066 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2067 \
2068 if (use_ac_env == 1) { \
2069 tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2070 tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env); \
2071 } else { \
2072 tempB = mipsdsp_mul_u16_u16(rsh, rth); \
2073 tempA = mipsdsp_mul_u16_u16(rsl, rtl); \
2074 } \
2075 \
2076 dotp = (int64_t)tempB - (int64_t)tempA; \
2077 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2078 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2079 dotp = dotp + acc; \
2080 env->active_tc.HI[ac] = (target_long)(int32_t) \
2081 ((dotp & MIPSDSP_LHI) >> 32); \
2082 env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO); \
2083 }
2084
2085 MUL_VOID_PH(mulsaq_s_w_ph, 1);
2086 MUL_VOID_PH(mulsa_w_ph, 0);
2087
2088 #undef MUL_VOID_PH
2089
2090 #if defined(TARGET_MIPS64)
2091 #define MUL_RETURN64_16_QH(name, func, \
2092 rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \
2093 rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \
2094 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2095 CPUMIPSState *env) \
2096 { \
2097 uint16_t rs3, rs2, rs1, rs0; \
2098 uint16_t rt3, rt2, rt1, rt0; \
2099 uint16_t tempD, tempC, tempB, tempA; \
2100 \
2101 rs3 = (rs >> rsmov1) & rsfilter; \
2102 rs2 = (rs >> rsmov2) & rsfilter; \
2103 rs1 = (rs >> rsmov3) & rsfilter; \
2104 rs0 = (rs >> rsmov4) & rsfilter; \
2105 rt3 = (rt >> rtmov1) & rtfilter; \
2106 rt2 = (rt >> rtmov2) & rtfilter; \
2107 rt1 = (rt >> rtmov3) & rtfilter; \
2108 rt0 = (rt >> rtmov4) & rtfilter; \
2109 \
2110 tempD = mipsdsp_##func(rs3, rt3, env); \
2111 tempC = mipsdsp_##func(rs2, rt2, env); \
2112 tempB = mipsdsp_##func(rs1, rt1, env); \
2113 tempA = mipsdsp_##func(rs0, rt0, env); \
2114 \
2115 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
2116 }
2117
2118 MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \
2119 56, 48, 40, 32, MIPSDSP_Q0, \
2120 48, 32, 16, 0, MIPSDSP_LO);
2121 MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \
2122 24, 16, 8, 0, MIPSDSP_Q0, \
2123 48, 32, 16, 0, MIPSDSP_LO);
2124 MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \
2125 48, 32, 16, 0, MIPSDSP_LO, \
2126 48, 32, 16, 0, MIPSDSP_LO);
2127
2128 #undef MUL_RETURN64_16_QH
2129
2130 #define MUL_RETURN64_32_QH(name, \
2131 rsmov1, rsmov2, \
2132 rtmov1, rtmov2) \
2133 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2134 CPUMIPSState *env) \
2135 { \
2136 uint16_t rsB, rsA; \
2137 uint16_t rtB, rtA; \
2138 uint32_t tempB, tempA; \
2139 \
2140 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2141 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2142 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2143 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2144 \
2145 tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env); \
2146 tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env); \
2147 \
2148 return ((uint64_t)tempB << 32) | (uint64_t)tempA; \
2149 }
2150
2151 MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32);
2152 MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0);
2153
2154 #undef MUL_RETURN64_32_QH
2155
2156 void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac,
2157 CPUMIPSState *env)
2158 {
2159 int16_t rs3, rs2, rs1, rs0;
2160 int16_t rt3, rt2, rt1, rt0;
2161 int32_t tempD, tempC, tempB, tempA;
2162 int64_t acc[2];
2163 int64_t temp[2];
2164 int64_t temp_sum;
2165
2166 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
2167 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
2168
2169 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);
2170 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);
2171 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);
2172 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);
2173
2174 temp[0] = ((int32_t)tempD - (int32_t)tempC) +
2175 ((int32_t)tempB - (int32_t)tempA);
2176 temp[0] = (int64_t)(temp[0] << 30) >> 30;
2177 if (((temp[0] >> 33) & 0x01) == 0) {
2178 temp[1] = 0x00;
2179 } else {
2180 temp[1] = ~0ull;
2181 }
2182
2183 acc[0] = env->active_tc.LO[ac];
2184 acc[1] = env->active_tc.HI[ac];
2185
2186 temp_sum = acc[0] + temp[0];
2187 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2188 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2189 acc[1] += 1;
2190 }
2191 acc[0] = temp_sum;
2192 acc[1] += temp[1];
2193
2194 env->active_tc.HI[ac] = acc[1];
2195 env->active_tc.LO[ac] = acc[0];
2196 }
2197 #endif
2198
2199 #define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2200 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2201 CPUMIPSState *env) \
2202 { \
2203 uint8_t rs3, rs2; \
2204 uint8_t rt3, rt2; \
2205 uint16_t tempB, tempA; \
2206 uint64_t tempC, dotp; \
2207 \
2208 rs3 = (rs >> rsmov1) & MIPSDSP_Q0; \
2209 rs2 = (rs >> rsmov2) & MIPSDSP_Q0; \
2210 rt3 = (rt >> rtmov1) & MIPSDSP_Q0; \
2211 rt2 = (rt >> rtmov2) & MIPSDSP_Q0; \
2212 tempB = mipsdsp_##func(rs3, rt3); \
2213 tempA = mipsdsp_##func(rs2, rt2); \
2214 dotp = (int64_t)tempB + (int64_t)tempA; \
2215 if (is_add) { \
2216 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2217 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2218 + dotp; \
2219 } else { \
2220 tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \
2221 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \
2222 - dotp; \
2223 } \
2224 \
2225 env->active_tc.HI[ac] = (target_long)(int32_t) \
2226 ((tempC & MIPSDSP_LHI) >> 32); \
2227 env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \
2228 }
2229
2230 DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16);
2231 DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0);
2232 DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16);
2233 DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0);
2234
2235 #undef DP_QB
2236
2237 #if defined(TARGET_MIPS64)
2238 #define DP_OB(name, add_sub, \
2239 rsmov1, rsmov2, rsmov3, rsmov4, \
2240 rtmov1, rtmov2, rtmov3, rtmov4) \
2241 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2242 CPUMIPSState *env) \
2243 { \
2244 uint8_t rsD, rsC, rsB, rsA; \
2245 uint8_t rtD, rtC, rtB, rtA; \
2246 uint16_t tempD, tempC, tempB, tempA; \
2247 uint64_t temp[2]; \
2248 uint64_t acc[2]; \
2249 uint64_t temp_sum; \
2250 \
2251 temp[0] = 0; \
2252 temp[1] = 0; \
2253 \
2254 rsD = (rs >> rsmov1) & MIPSDSP_Q0; \
2255 rsC = (rs >> rsmov2) & MIPSDSP_Q0; \
2256 rsB = (rs >> rsmov3) & MIPSDSP_Q0; \
2257 rsA = (rs >> rsmov4) & MIPSDSP_Q0; \
2258 rtD = (rt >> rtmov1) & MIPSDSP_Q0; \
2259 rtC = (rt >> rtmov2) & MIPSDSP_Q0; \
2260 rtB = (rt >> rtmov3) & MIPSDSP_Q0; \
2261 rtA = (rt >> rtmov4) & MIPSDSP_Q0; \
2262 \
2263 tempD = mipsdsp_mul_u8_u8(rsD, rtD); \
2264 tempC = mipsdsp_mul_u8_u8(rsC, rtC); \
2265 tempB = mipsdsp_mul_u8_u8(rsB, rtB); \
2266 tempA = mipsdsp_mul_u8_u8(rsA, rtA); \
2267 \
2268 temp[0] = (uint64_t)tempD + (uint64_t)tempC + \
2269 (uint64_t)tempB + (uint64_t)tempA; \
2270 \
2271 acc[0] = env->active_tc.LO[ac]; \
2272 acc[1] = env->active_tc.HI[ac]; \
2273 \
2274 if (add_sub) { \
2275 temp_sum = acc[0] + temp[0]; \
2276 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2277 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2278 acc[1] += 1; \
2279 } \
2280 temp[0] = temp_sum; \
2281 temp[1] = acc[1] + temp[1]; \
2282 } else { \
2283 temp_sum = acc[0] - temp[0]; \
2284 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2285 acc[1] -= 1; \
2286 } \
2287 temp[0] = temp_sum; \
2288 temp[1] = acc[1] - temp[1]; \
2289 } \
2290 \
2291 env->active_tc.HI[ac] = temp[1]; \
2292 env->active_tc.LO[ac] = temp[0]; \
2293 }
2294
2295 DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32);
2296 DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0);
2297 DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32);
2298 DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
2299
2300 #undef DP_OB
2301 #endif
2302
2303 #define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2304 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2305 CPUMIPSState *env) \
2306 { \
2307 int16_t rsB, rsA, rtB, rtA; \
2308 int32_t tempA, tempB; \
2309 int64_t acc; \
2310 \
2311 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2312 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2313 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2314 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2315 \
2316 tempB = (int32_t)rsB * (int32_t)rtB; \
2317 tempA = (int32_t)rsA * (int32_t)rtA; \
2318 \
2319 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2320 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2321 \
2322 if (is_add) { \
2323 acc = acc + ((int64_t)tempB + (int64_t)tempA); \
2324 } else { \
2325 acc = acc - ((int64_t)tempB + (int64_t)tempA); \
2326 } \
2327 \
2328 env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \
2329 env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO); \
2330 }
2331
2332 DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0);
2333 DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16);
2334 DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0);
2335 DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16);
2336 #undef DP_NOFUNC_PH
2337
2338 #define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2339 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2340 CPUMIPSState *env) \
2341 { \
2342 int16_t rsB, rsA, rtB, rtA; \
2343 int32_t tempB, tempA; \
2344 int64_t acc, dotp; \
2345 \
2346 rsB = (rs >> rsmov1) & MIPSDSP_LO; \
2347 rsA = (rs >> rsmov2) & MIPSDSP_LO; \
2348 rtB = (rt >> rtmov1) & MIPSDSP_LO; \
2349 rtA = (rt >> rtmov2) & MIPSDSP_LO; \
2350 \
2351 tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env); \
2352 tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env); \
2353 \
2354 dotp = (int64_t)tempB + (int64_t)tempA; \
2355 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2356 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2357 \
2358 if (is_add) { \
2359 acc = acc + dotp; \
2360 } else { \
2361 acc = acc - dotp; \
2362 } \
2363 \
2364 env->active_tc.HI[ac] = (target_long)(int32_t) \
2365 ((acc & MIPSDSP_LHI) >> 32); \
2366 env->active_tc.LO[ac] = (target_long)(int32_t) \
2367 (acc & MIPSDSP_LLO); \
2368 }
2369
2370 DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0);
2371 DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16);
2372 DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0);
2373 DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16);
2374
2375 #undef DP_HASFUNC_PH
2376
2377 #define DP_128OPERATION_PH(name, is_add) \
2378 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2379 CPUMIPSState *env) \
2380 { \
2381 int16_t rsh, rsl, rth, rtl; \
2382 int32_t tempB, tempA, tempC62_31, tempC63; \
2383 int64_t acc, dotp, tempC; \
2384 \
2385 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
2386 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2387 \
2388 tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env); \
2389 tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env); \
2390 \
2391 dotp = (int64_t)tempB + (int64_t)tempA; \
2392 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2393 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2394 if (is_add) { \
2395 tempC = acc + dotp; \
2396 } else { \
2397 tempC = acc - dotp; \
2398 } \
2399 tempC63 = (tempC >> 63) & 0x01; \
2400 tempC62_31 = (tempC >> 31) & 0xFFFFFFFF; \
2401 \
2402 if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) { \
2403 tempC = 0x7FFFFFFF; \
2404 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2405 } \
2406 \
2407 if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) { \
2408 tempC = (int64_t)(int32_t)0x80000000; \
2409 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2410 } \
2411 \
2412 env->active_tc.HI[ac] = (target_long)(int32_t) \
2413 ((tempC & MIPSDSP_LHI) >> 32); \
2414 env->active_tc.LO[ac] = (target_long)(int32_t) \
2415 (tempC & MIPSDSP_LLO); \
2416 }
2417
2418 DP_128OPERATION_PH(dpaqx_sa_w_ph, 1);
2419 DP_128OPERATION_PH(dpsqx_sa_w_ph, 0);
2420
2421 #undef DP_128OPERATION_HP
2422
2423 #if defined(TARGET_MIPS64)
2424 #define DP_QH(name, is_add, use_ac_env) \
2425 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2426 CPUMIPSState *env) \
2427 { \
2428 int32_t rs3, rs2, rs1, rs0; \
2429 int32_t rt3, rt2, rt1, rt0; \
2430 int32_t tempD, tempC, tempB, tempA; \
2431 int64_t acc[2]; \
2432 int64_t temp[2]; \
2433 int64_t temp_sum; \
2434 \
2435 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
2436 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2437 \
2438 if (use_ac_env) { \
2439 tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); \
2440 tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); \
2441 tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); \
2442 tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); \
2443 } else { \
2444 tempD = mipsdsp_mul_u16_u16(rs3, rt3); \
2445 tempC = mipsdsp_mul_u16_u16(rs2, rt2); \
2446 tempB = mipsdsp_mul_u16_u16(rs1, rt1); \
2447 tempA = mipsdsp_mul_u16_u16(rs0, rt0); \
2448 } \
2449 \
2450 temp[0] = (int64_t)tempD + (int64_t)tempC + \
2451 (int64_t)tempB + (int64_t)tempA; \
2452 \
2453 if (temp[0] >= 0) { \
2454 temp[1] = 0; \
2455 } else { \
2456 temp[1] = ~0ull; \
2457 } \
2458 \
2459 acc[1] = env->active_tc.HI[ac]; \
2460 acc[0] = env->active_tc.LO[ac]; \
2461 \
2462 if (is_add) { \
2463 temp_sum = acc[0] + temp[0]; \
2464 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2465 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2466 acc[1] = acc[1] + 1; \
2467 } \
2468 temp[0] = temp_sum; \
2469 temp[1] = acc[1] + temp[1]; \
2470 } else { \
2471 temp_sum = acc[0] - temp[0]; \
2472 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2473 acc[1] = acc[1] - 1; \
2474 } \
2475 temp[0] = temp_sum; \
2476 temp[1] = acc[1] - temp[1]; \
2477 } \
2478 \
2479 env->active_tc.HI[ac] = temp[1]; \
2480 env->active_tc.LO[ac] = temp[0]; \
2481 }
2482
2483 DP_QH(dpa_w_qh, 1, 0);
2484 DP_QH(dpaq_s_w_qh, 1, 1);
2485 DP_QH(dps_w_qh, 0, 0);
2486 DP_QH(dpsq_s_w_qh, 0, 1);
2487
2488 #undef DP_QH
2489
2490 #endif
2491
2492 #define DP_L_W(name, is_add) \
2493 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2494 CPUMIPSState *env) \
2495 { \
2496 int32_t temp63; \
2497 int64_t dotp, acc; \
2498 uint64_t temp; \
2499 \
2500 dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env); \
2501 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2502 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2503 if (!is_add) { \
2504 dotp = -dotp; \
2505 } \
2506 \
2507 temp = acc + dotp; \
2508 if (MIPSDSP_OVERFLOW((uint64_t)acc, (uint64_t)dotp, temp, \
2509 (0x01ull << 63))) { \
2510 temp63 = (temp >> 63) & 0x01; \
2511 if (temp63 == 1) { \
2512 temp = (0x01ull << 63) - 1; \
2513 } else { \
2514 temp = 0x01ull << 63; \
2515 } \
2516 \
2517 set_DSPControl_overflow_flag(1, 16 + ac, env); \
2518 } \
2519 \
2520 env->active_tc.HI[ac] = (target_long)(int32_t) \
2521 ((temp & MIPSDSP_LHI) >> 32); \
2522 env->active_tc.LO[ac] = (target_long)(int32_t) \
2523 (temp & MIPSDSP_LLO); \
2524 }
2525
2526 DP_L_W(dpaq_sa_l_w, 1);
2527 DP_L_W(dpsq_sa_l_w, 0);
2528
2529 #undef DP_L_W
2530
2531 #if defined(TARGET_MIPS64)
2532 #define DP_L_PW(name, func) \
2533 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2534 CPUMIPSState *env) \
2535 { \
2536 int32_t rs1, rs0; \
2537 int32_t rt1, rt0; \
2538 int64_t tempB[2], tempA[2]; \
2539 int64_t temp[2]; \
2540 int64_t acc[2]; \
2541 int64_t temp_sum; \
2542 \
2543 temp[0] = 0; \
2544 temp[1] = 0; \
2545 \
2546 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2547 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2548 \
2549 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); \
2550 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); \
2551 \
2552 if (tempB[0] >= 0) { \
2553 tempB[1] = 0x00; \
2554 } else { \
2555 tempB[1] = ~0ull; \
2556 } \
2557 \
2558 if (tempA[0] >= 0) { \
2559 tempA[1] = 0x00; \
2560 } else { \
2561 tempA[1] = ~0ull; \
2562 } \
2563 \
2564 temp_sum = tempB[0] + tempA[0]; \
2565 if (((uint64_t)temp_sum < (uint64_t)tempB[0]) && \
2566 ((uint64_t)temp_sum < (uint64_t)tempA[0])) { \
2567 temp[1] += 1; \
2568 } \
2569 temp[0] = temp_sum; \
2570 temp[1] += tempB[1] + tempA[1]; \
2571 \
2572 mipsdsp_##func(acc, ac, temp, env); \
2573 \
2574 env->active_tc.HI[ac] = acc[1]; \
2575 env->active_tc.LO[ac] = acc[0]; \
2576 }
2577
2578 DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63);
2579 DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63);
2580
2581 #undef DP_L_PW
2582
2583 void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac,
2584 CPUMIPSState *env)
2585 {
2586 int32_t rs1, rs0;
2587 int32_t rt1, rt0;
2588 int64_t tempB[2], tempA[2];
2589 int64_t temp[2];
2590 int64_t acc[2];
2591 int64_t temp_sum;
2592
2593 rs1 = (rs >> 32) & MIPSDSP_LLO;
2594 rs0 = rs & MIPSDSP_LLO;
2595 rt1 = (rt >> 32) & MIPSDSP_LLO;
2596 rt0 = rt & MIPSDSP_LLO;
2597
2598 tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);
2599 tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);
2600
2601 if (tempB[0] >= 0) {
2602 tempB[1] = 0x00;
2603 } else {
2604 tempB[1] = ~0ull;
2605 }
2606
2607 if (tempA[0] >= 0) {
2608 tempA[1] = 0x00;
2609 } else {
2610 tempA[1] = ~0ull;
2611 }
2612
2613 acc[0] = env->active_tc.LO[ac];
2614 acc[1] = env->active_tc.HI[ac];
2615
2616 temp_sum = tempB[0] - tempA[0];
2617 if ((uint64_t)temp_sum > (uint64_t)tempB[0]) {
2618 tempB[1] -= 1;
2619 }
2620 temp[0] = temp_sum;
2621 temp[1] = tempB[1] - tempA[1];
2622
2623 if ((temp[1] & 0x01) == 0) {
2624 temp[1] = 0x00;
2625 } else {
2626 temp[1] = ~0ull;
2627 }
2628
2629 temp_sum = acc[0] + temp[0];
2630 if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2631 ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2632 acc[1] += 1;
2633 }
2634 acc[0] = temp_sum;
2635 acc[1] += temp[1];
2636
2637 env->active_tc.HI[ac] = acc[1];
2638 env->active_tc.LO[ac] = acc[0];
2639 }
2640 #endif
2641
2642 #define MAQ_S_W(name, mov) \
2643 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2644 CPUMIPSState *env) \
2645 { \
2646 int16_t rsh, rth; \
2647 int32_t tempA; \
2648 int64_t tempL, acc; \
2649 \
2650 rsh = (rs >> mov) & MIPSDSP_LO; \
2651 rth = (rt >> mov) & MIPSDSP_LO; \
2652 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2653 acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \
2654 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2655 tempL = (int64_t)tempA + acc; \
2656 env->active_tc.HI[ac] = (target_long)(int32_t) \
2657 ((tempL & MIPSDSP_LHI) >> 32); \
2658 env->active_tc.LO[ac] = (target_long)(int32_t) \
2659 (tempL & MIPSDSP_LLO); \
2660 }
2661
2662 MAQ_S_W(maq_s_w_phl, 16);
2663 MAQ_S_W(maq_s_w_phr, 0);
2664
2665 #undef MAQ_S_W
2666
2667 #define MAQ_SA_W(name, mov) \
2668 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2669 CPUMIPSState *env) \
2670 { \
2671 int16_t rsh, rth; \
2672 int32_t tempA; \
2673 \
2674 rsh = (rs >> mov) & MIPSDSP_LO; \
2675 rth = (rt >> mov) & MIPSDSP_LO; \
2676 tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \
2677 tempA = mipsdsp_sat32_acc_q31(ac, tempA, env); \
2678 \
2679 env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA & \
2680 MIPSDSP_LHI) >> 32); \
2681 env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA & \
2682 MIPSDSP_LLO); \
2683 }
2684
2685 MAQ_SA_W(maq_sa_w_phl, 16);
2686 MAQ_SA_W(maq_sa_w_phr, 0);
2687
2688 #undef MAQ_SA_W
2689
2690 #define MULQ_W(name, addvar) \
2691 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2692 CPUMIPSState *env) \
2693 { \
2694 uint32_t rs_t, rt_t; \
2695 int32_t tempI; \
2696 int64_t tempL; \
2697 \
2698 rs_t = rs & MIPSDSP_LLO; \
2699 rt_t = rt & MIPSDSP_LLO; \
2700 \
2701 if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) { \
2702 tempL = 0x7FFFFFFF00000000ull; \
2703 set_DSPControl_overflow_flag(1, 21, env); \
2704 } else { \
2705 tempL = ((int64_t)rs_t * (int64_t)rt_t) << 1; \
2706 tempL += addvar; \
2707 } \
2708 tempI = (tempL & MIPSDSP_LHI) >> 32; \
2709 \
2710 return (target_long)(int32_t)tempI; \
2711 }
2712
2713 MULQ_W(mulq_s_w, 0);
2714 MULQ_W(mulq_rs_w, 0x80000000ull);
2715
2716 #undef MULQ_W
2717
2718 #if defined(TARGET_MIPS64)
2719
2720 #define MAQ_S_W_QH(name, mov) \
2721 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2722 CPUMIPSState *env) \
2723 { \
2724 int16_t rs_t, rt_t; \
2725 int32_t temp_mul; \
2726 int64_t temp[2]; \
2727 int64_t acc[2]; \
2728 int64_t temp_sum; \
2729 \
2730 temp[0] = 0; \
2731 temp[1] = 0; \
2732 \
2733 rs_t = (rs >> mov) & MIPSDSP_LO; \
2734 rt_t = (rt >> mov) & MIPSDSP_LO; \
2735 temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2736 \
2737 temp[0] = (int64_t)temp_mul; \
2738 if (temp[0] >= 0) { \
2739 temp[1] = 0x00; \
2740 } else { \
2741 temp[1] = ~0ull; \
2742 } \
2743 \
2744 acc[0] = env->active_tc.LO[ac]; \
2745 acc[1] = env->active_tc.HI[ac]; \
2746 \
2747 temp_sum = acc[0] + temp[0]; \
2748 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2749 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2750 acc[1] += 1; \
2751 } \
2752 acc[0] = temp_sum; \
2753 acc[1] += temp[1]; \
2754 \
2755 env->active_tc.HI[ac] = acc[1]; \
2756 env->active_tc.LO[ac] = acc[0]; \
2757 }
2758
2759 MAQ_S_W_QH(maq_s_w_qhll, 48);
2760 MAQ_S_W_QH(maq_s_w_qhlr, 32);
2761 MAQ_S_W_QH(maq_s_w_qhrl, 16);
2762 MAQ_S_W_QH(maq_s_w_qhrr, 0);
2763
2764 #undef MAQ_S_W_QH
2765
2766 #define MAQ_SA_W(name, mov) \
2767 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2768 CPUMIPSState *env) \
2769 { \
2770 int16_t rs_t, rt_t; \
2771 int32_t temp; \
2772 int64_t acc[2]; \
2773 \
2774 rs_t = (rs >> mov) & MIPSDSP_LO; \
2775 rt_t = (rt >> mov) & MIPSDSP_LO; \
2776 temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \
2777 temp = mipsdsp_sat32_acc_q31(ac, temp, env); \
2778 \
2779 acc[0] = (int64_t)(int32_t)temp; \
2780 if (acc[0] >= 0) { \
2781 acc[1] = 0x00; \
2782 } else { \
2783 acc[1] = ~0ull; \
2784 } \
2785 \
2786 env->active_tc.HI[ac] = acc[1]; \
2787 env->active_tc.LO[ac] = acc[0]; \
2788 }
2789
2790 MAQ_SA_W(maq_sa_w_qhll, 48);
2791 MAQ_SA_W(maq_sa_w_qhlr, 32);
2792 MAQ_SA_W(maq_sa_w_qhrl, 16);
2793 MAQ_SA_W(maq_sa_w_qhrr, 0);
2794
2795 #undef MAQ_SA_W
2796
2797 #define MAQ_S_L_PW(name, mov) \
2798 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2799 CPUMIPSState *env) \
2800 { \
2801 int32_t rs_t, rt_t; \
2802 int64_t temp[2]; \
2803 int64_t acc[2]; \
2804 int64_t temp_sum; \
2805 \
2806 temp[0] = 0; \
2807 temp[1] = 0; \
2808 \
2809 rs_t = (rs >> mov) & MIPSDSP_LLO; \
2810 rt_t = (rt >> mov) & MIPSDSP_LLO; \
2811 \
2812 temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env); \
2813 if (temp[0] >= 0) { \
2814 temp[1] = 0x00; \
2815 } else { \
2816 temp[1] = ~0ull; \
2817 } \
2818 \
2819 acc[0] = env->active_tc.LO[ac]; \
2820 acc[1] = env->active_tc.HI[ac]; \
2821 \
2822 temp_sum = acc[0] + temp[0]; \
2823 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2824 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2825 acc[1] += 1; \
2826 } \
2827 acc[0] = temp_sum; \
2828 acc[1] += temp[1]; \
2829 \
2830 env->active_tc.HI[ac] = acc[1]; \
2831 env->active_tc.LO[ac] = acc[0]; \
2832 }
2833
2834 MAQ_S_L_PW(maq_s_l_pwl, 32);
2835 MAQ_S_L_PW(maq_s_l_pwr, 0);
2836
2837 #undef MAQ_S_L_PW
2838
2839 #define DM_OPERATE(name, func, is_add, sigext) \
2840 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2841 CPUMIPSState *env) \
2842 { \
2843 int32_t rs1, rs0; \
2844 int32_t rt1, rt0; \
2845 int64_t tempBL[2], tempAL[2]; \
2846 int64_t acc[2]; \
2847 int64_t temp[2]; \
2848 int64_t temp_sum; \
2849 \
2850 temp[0] = 0x00; \
2851 temp[1] = 0x00; \
2852 \
2853 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
2854 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2855 \
2856 if (sigext) { \
2857 tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1); \
2858 tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0); \
2859 \
2860 if (tempBL[0] >= 0) { \
2861 tempBL[1] = 0x0; \
2862 } else { \
2863 tempBL[1] = ~0ull; \
2864 } \
2865 \
2866 if (tempAL[0] >= 0) { \
2867 tempAL[1] = 0x0; \
2868 } else { \
2869 tempAL[1] = ~0ull; \
2870 } \
2871 } else { \
2872 tempBL[0] = mipsdsp_##func(rs1, rt1); \
2873 tempAL[0] = mipsdsp_##func(rs0, rt0); \
2874 tempBL[1] = 0; \
2875 tempAL[1] = 0; \
2876 } \
2877 \
2878 acc[1] = env->active_tc.HI[ac]; \
2879 acc[0] = env->active_tc.LO[ac]; \
2880 \
2881 temp_sum = tempBL[0] + tempAL[0]; \
2882 if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) && \
2883 ((uint64_t)temp_sum < (uint64_t)tempAL[0])) { \
2884 temp[1] += 1; \
2885 } \
2886 temp[0] = temp_sum; \
2887 temp[1] += tempBL[1] + tempAL[1]; \
2888 \
2889 if (is_add) { \
2890 temp_sum = acc[0] + temp[0]; \
2891 if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \
2892 ((uint64_t)temp_sum < (uint64_t)temp[0])) { \
2893 acc[1] += 1; \
2894 } \
2895 temp[0] = temp_sum; \
2896 temp[1] = acc[1] + temp[1]; \
2897 } else { \
2898 temp_sum = acc[0] - temp[0]; \
2899 if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \
2900 acc[1] -= 1; \
2901 } \
2902 temp[0] = temp_sum; \
2903 temp[1] = acc[1] - temp[1]; \
2904 } \
2905 \
2906 env->active_tc.HI[ac] = temp[1]; \
2907 env->active_tc.LO[ac] = temp[0]; \
2908 }
2909
2910 DM_OPERATE(dmadd, mul_i32_i32, 1, 1);
2911 DM_OPERATE(dmaddu, mul_u32_u32, 1, 0);
2912 DM_OPERATE(dmsub, mul_i32_i32, 0, 1);
2913 DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
2914 #undef DM_OPERATE
2915 #endif
2916
2917 /** DSP Bit/Manipulation Sub-class insns **/
2918 target_ulong helper_bitrev(target_ulong rt)
2919 {
2920 int32_t temp;
2921 uint32_t rd;
2922 int i;
2923
2924 temp = rt & MIPSDSP_LO;
2925 rd = 0;
2926 for (i = 0; i < 16; i++) {
2927 rd = (rd << 1) | (temp & 1);
2928 temp = temp >> 1;
2929 }
2930
2931 return (target_ulong)rd;
2932 }
2933
2934 #define BIT_INSV(name, posfilter, sizefilter, ret_type) \
2935 target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
2936 target_ulong rt) \
2937 { \
2938 uint32_t pos, size, msb, lsb; \
2939 target_ulong filter; \
2940 target_ulong temp, temprs, temprt; \
2941 target_ulong dspc; \
2942 \
2943 dspc = env->active_tc.DSPControl; \
2944 \
2945 pos = dspc & posfilter; \
2946 size = (dspc >> 7) & sizefilter; \
2947 \
2948 msb = pos + size - 1; \
2949 lsb = pos; \
2950 \
2951 if (lsb > msb || (msb > TARGET_LONG_BITS)) { \
2952 return rt; \
2953 } \
2954 \
2955 filter = ((int32_t)0x01 << size) - 1; \
2956 filter = filter << pos; \
2957 temprs = (rs << pos) & filter; \
2958 temprt = rt & ~filter; \
2959 temp = temprs | temprt; \
2960 \
2961 return (target_long)(ret_type)temp; \
2962 }
2963
2964 BIT_INSV(insv, 0x1F, 0x1F, int32_t);
2965 #ifdef TARGET_MIPS64
2966 BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
2967 #endif
2968
2969 #undef BIT_INSV
2970
2971
2972 /** DSP Compare-Pick Sub-class insns **/
2973 #define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
2974 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
2975 { \
2976 uint32_t rs_t, rt_t; \
2977 uint8_t cc; \
2978 uint32_t temp = 0; \
2979 int i; \
2980 \
2981 for (i = 0; i < split_num; i++) { \
2982 rs_t = (rs >> (bit_size * i)) & filter; \
2983 rt_t = (rt >> (bit_size * i)) & filter; \
2984 cc = mipsdsp_##func(rs_t, rt_t); \
2985 temp |= cc << i; \
2986 } \
2987 \
2988 return (target_ulong)temp; \
2989 }
2990
2991 CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
2992 CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
2993 CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
2994
2995 #ifdef TARGET_MIPS64
2996 CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
2997 CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
2998 CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
2999 #endif
3000
3001 #undef CMP_HAS_RET
3002
3003
3004 #define CMP_NO_RET(name, func, split_num, filter, bit_size) \
3005 void helper_##name(target_ulong rs, target_ulong rt, \
3006 CPUMIPSState *env) \
3007 { \
3008 int##bit_size##_t rs_t, rt_t; \
3009 int##bit_size##_t flag = 0; \
3010 int##bit_size##_t cc; \
3011 int i; \
3012 \
3013 for (i = 0; i < split_num; i++) { \
3014 rs_t = (rs >> (bit_size * i)) & filter; \
3015 rt_t = (rt >> (bit_size * i)) & filter; \
3016 \
3017 cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \
3018 flag |= cc << i; \
3019 } \
3020 \
3021 set_DSPControl_24(flag, split_num, env); \
3022 }
3023
3024 CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3025 CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3026 CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3027
3028 CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
3029 CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
3030 CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
3031
3032 #ifdef TARGET_MIPS64
3033 CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3034 CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3035 CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3036
3037 CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
3038 CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
3039 CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
3040
3041 CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
3042 CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
3043 CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
3044 #endif
3045 #undef CMP_NO_RET
3046
3047 #if defined(TARGET_MIPS64)
3048
3049 #define CMPGDU_OB(name) \
3050 target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
3051 CPUMIPSState *env) \
3052 { \
3053 int i; \
3054 uint8_t rs_t, rt_t; \
3055 uint32_t cond; \
3056 \
3057 cond = 0; \
3058 \
3059 for (i = 0; i < 8; i++) { \
3060 rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \
3061 rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \
3062 \
3063 if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \
3064 cond |= 0x01 << i; \
3065 } \
3066 } \
3067 \
3068 set_DSPControl_24(cond, 8, env); \
3069 \
3070 return (uint64_t)cond; \
3071 }
3072
3073 CMPGDU_OB(eq)
3074 CMPGDU_OB(lt)
3075 CMPGDU_OB(le)
3076 #undef CMPGDU_OB
3077 #endif
3078
3079 #define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
3080 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3081 CPUMIPSState *env) \
3082 { \
3083 uint32_t rs_t, rt_t; \
3084 uint32_t cc; \
3085 target_ulong dsp; \
3086 int i; \
3087 target_ulong result = 0; \
3088 \
3089 dsp = env->active_tc.DSPControl; \
3090 for (i = 0; i < split_num; i++) { \
3091 rs_t = (rs >> (bit_size * i)) & filter; \
3092 rt_t = (rt >> (bit_size * i)) & filter; \
3093 cc = (dsp >> (24 + i)) & 0x01; \
3094 cc = cc == 1 ? rs_t : rt_t; \
3095 \
3096 result |= (target_ulong)cc << (bit_size * i); \
3097 } \
3098 \
3099 if (ret32bit) { \
3100 result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
3101 } \
3102 \
3103 return result; \
3104 }
3105
3106 PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
3107 PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
3108
3109 #ifdef TARGET_MIPS64
3110 PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
3111 PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
3112 PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
3113 #endif
3114 #undef PICK_INSN
3115
3116 #define APPEND_INSN(name, ret_32) \
3117 target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \
3118 { \
3119 target_ulong temp; \
3120 \
3121 if (ret_32) { \
3122 temp = ((rt & MIPSDSP_LLO) << sa) | \
3123 ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \
3124 temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \
3125 } else { \
3126 temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \
3127 } \
3128 \
3129 return temp; \
3130 }
3131
3132 APPEND_INSN(append, 1);
3133 #ifdef TARGET_MIPS64
3134 APPEND_INSN(dappend, 0);
3135 #endif
3136 #undef APPEND_INSN
3137
3138 #define PREPEND_INSN(name, or_val, ret_32) \
3139 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
3140 uint32_t sa) \
3141 { \
3142 sa |= or_val; \
3143 \
3144 if (1) { \
3145 return (target_long)(int32_t)(uint32_t) \
3146 (((rs & MIPSDSP_LLO) << (32 - sa)) | \
3147 ((rt & MIPSDSP_LLO) >> sa)); \
3148 } else { \
3149 return (rs << (64 - sa)) | (rt >> sa); \
3150 } \
3151 }
3152
3153 PREPEND_INSN(prepend, 0, 1);
3154 #ifdef TARGET_MIPS64
3155 PREPEND_INSN(prependw, 0, 0);
3156 PREPEND_INSN(prependd, 0x20, 0);
3157 #endif
3158 #undef PREPEND_INSN
3159
3160 #define BALIGN_INSN(name, filter, ret32) \
3161 target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \
3162 { \
3163 bp = bp & 0x03; \
3164 \
3165 if ((bp & 1) == 0) { \
3166 return rt; \
3167 } else { \
3168 if (ret32) { \
3169 return (target_long)(int32_t)((rt << (8 * bp)) | \
3170 (rs >> (8 * (4 - bp)))); \
3171 } else { \
3172 return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \
3173 } \
3174 } \
3175 }
3176
3177 BALIGN_INSN(balign, 0x03, 1);
3178 #if defined(TARGET_MIPS64)
3179 BALIGN_INSN(dbalign, 0x07, 0);
3180 #endif
3181 #undef BALIGN_INSN
3182
3183 target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
3184 {
3185 uint32_t rsl, rth;
3186
3187 rsl = rs & MIPSDSP_LO;
3188 rth = (rt & MIPSDSP_HI) >> 16;
3189
3190 return (target_long)(int32_t)((rsl << 16) | rth);
3191 }
3192
3193 #if defined(TARGET_MIPS64)
3194 target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
3195 {
3196 uint32_t rs0, rt1;
3197
3198 rs0 = rs & MIPSDSP_LLO;
3199 rt1 = (rt >> 32) & MIPSDSP_LLO;
3200
3201 return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
3202 }
3203 #endif
3204
3205 /** DSP Accumulator and DSPControl Access Sub-class insns **/
3206 target_ulong helper_extr_w(target_ulong ac, target_ulong shift,
3207 CPUMIPSState *env)
3208 {
3209 int32_t tempI;
3210 int64_t tempDL[2];
3211
3212 shift = shift & 0x1F;
3213
3214 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3215 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3216 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3217 set_DSPControl_overflow_flag(1, 23, env);
3218 }
3219
3220 tempI = (tempDL[0] >> 1) & MIPSDSP_LLO;
3221
3222 tempDL[0] += 1;
3223 if (tempDL[0] == 0) {
3224 tempDL[1] += 1;
3225 }
3226
3227 if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) &&
3228 (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) {
3229 set_DSPControl_overflow_flag(1, 23, env);
3230 }
3231
3232 return (target_long)tempI;
3233 }
3234
3235 target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift,
3236 CPUMIPSState *env)
3237 {
3238 int64_t tempDL[2];
3239
3240 shift = shift & 0x1F;
3241
3242 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3243 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3244 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3245 set_DSPControl_overflow_flag(1, 23, env);
3246 }
3247
3248 tempDL[0] += 1;
3249 if (tempDL[0] == 0) {
3250 tempDL[1] += 1;
3251 }
3252
3253 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3254 (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3255 set_DSPControl_overflow_flag(1, 23, env);
3256 }
3257
3258 return (target_long)(int32_t)(tempDL[0] >> 1);
3259 }
3260
3261 target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift,
3262 CPUMIPSState *env)
3263 {
3264 int32_t tempI, temp64;
3265 int64_t tempDL[2];
3266
3267 shift = shift & 0x1F;
3268
3269 mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3270 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3271 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3272 set_DSPControl_overflow_flag(1, 23, env);
3273 }
3274 tempDL[0] += 1;
3275 if (tempDL[0] == 0) {
3276 tempDL[1] += 1;
3277 }
3278 tempI = tempDL[0] >> 1;
3279
3280 if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3281 (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3282 temp64 = tempDL[1];
3283 if (temp64 == 0) {
3284 tempI = 0x7FFFFFFF;
3285 } else {
3286 tempI = 0x80000000;
3287 }
3288 set_DSPControl_overflow_flag(1, 23, env);
3289 }
3290
3291 return (target_long)tempI;
3292 }
3293
3294 #if defined(TARGET_MIPS64)
3295 target_ulong helper_dextr_w(target_ulong ac, target_ulong shift,
3296 CPUMIPSState *env)
3297 {
3298 uint64_t temp[3];
3299
3300 shift = shift & 0x3F;
3301
3302 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3303
3304 return (int64_t)(int32_t)(temp[0] >> 1);
3305 }
3306
3307 target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift,
3308 CPUMIPSState *env)
3309 {
3310 uint64_t temp[3];
3311 uint32_t temp128;
3312
3313 shift = shift & 0x3F;
3314 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3315
3316 temp[0] += 1;
3317 if (temp[0] == 0) {
3318 temp[1] += 1;
3319 if (temp[1] == 0) {
3320 temp[2] += 1;
3321 }
3322 }
3323
3324 temp128 = temp[2] & 0x01;
3325
3326 if ((temp128 != 0 || temp[1] != 0) &&
3327 (temp128 != 1 || temp[1] != ~0ull)) {
3328 set_DSPControl_overflow_flag(1, 23, env);
3329 }
3330
3331 return (int64_t)(int32_t)(temp[0] >> 1);
3332 }
3333
3334 target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift,
3335 CPUMIPSState *env)
3336 {
3337 uint64_t temp[3];
3338 uint32_t temp128;
3339
3340 shift = shift & 0x3F;
3341 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3342
3343 temp[0] += 1;
3344 if (temp[0] == 0) {
3345 temp[1] += 1;
3346 if (temp[1] == 0) {
3347 temp[2] += 1;
3348 }
3349 }
3350
3351 temp128 = temp[2] & 0x01;
3352
3353 if ((temp128 != 0 || temp[1] != 0) &&
3354 (temp128 != 1 || temp[1] != ~0ull)) {
3355 if (temp128 == 0) {
3356 temp[0] = 0x0FFFFFFFF;
3357 } else {
3358 temp[0] = 0x0100000000ULL;
3359 }
3360 set_DSPControl_overflow_flag(1, 23, env);
3361 }
3362
3363 return (int64_t)(int32_t)(temp[0] >> 1);
3364 }
3365
3366 target_ulong helper_dextr_l(target_ulong ac, target_ulong shift,
3367 CPUMIPSState *env)
3368 {
3369 uint64_t temp[3];
3370 target_ulong result;
3371
3372 shift = shift & 0x3F;
3373
3374 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3375 result = (temp[1] << 63) | (temp[0] >> 1);
3376
3377 return result;
3378 }
3379
3380 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift,
3381 CPUMIPSState *env)
3382 {
3383 uint64_t temp[3];
3384 uint32_t temp128;
3385 target_ulong result;
3386
3387 shift = shift & 0x3F;
3388 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3389
3390 temp[0] += 1;
3391 if (temp[0] == 0) {
3392 temp[1] += 1;
3393 if (temp[1] == 0) {
3394 temp[2] += 1;
3395 }
3396 }
3397
3398 temp128 = temp[2] & 0x01;
3399
3400 if ((temp128 != 0 || temp[1] != 0) &&
3401 (temp128 != 1 || temp[1] != ~0ull)) {
3402 set_DSPControl_overflow_flag(1, 23, env);
3403 }
3404
3405 result = (temp[1] << 63) | (temp[0] >> 1);
3406
3407 return result;
3408 }
3409
3410 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift,
3411 CPUMIPSState *env)
3412 {
3413 uint64_t temp[3];
3414 uint32_t temp128;
3415 target_ulong result;
3416
3417 shift = shift & 0x3F;
3418 mipsdsp_rndrashift_acc(temp, ac, shift, env);
3419
3420 temp[0] += 1;
3421 if (temp[0] == 0) {
3422 temp[1] += 1;
3423 if (temp[1] == 0) {
3424 temp[2] += 1;
3425 }
3426 }
3427
3428 temp128 = temp[2] & 0x01;
3429
3430 if ((temp128 != 0 || temp[1] != 0) &&
3431 (temp128 != 1 || temp[1] != ~0ull)) {
3432 if (temp128 == 0) {
3433 temp[1] &= ~0x00ull - 1;
3434 temp[0] |= ~0x00ull - 1;
3435 } else {
3436 temp[1] |= 0x01;
3437 temp[0] &= 0x01;
3438 }
3439 set_DSPControl_overflow_flag(1, 23, env);
3440 }
3441 result = (temp[1] << 63) | (temp[0] >> 1);
3442
3443 return result;
3444 }
3445 #endif
3446
3447 target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift,
3448 CPUMIPSState *env)
3449 {
3450 int64_t temp, acc;
3451
3452 shift = shift & 0x1F;
3453
3454 acc = ((int64_t)env->active_tc.HI[ac] << 32) |
3455 ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
3456
3457 temp = acc >> shift;
3458
3459 if (temp > (int64_t)0x7FFF) {
3460 temp = 0x00007FFF;
3461 set_DSPControl_overflow_flag(1, 23, env);
3462 } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) {
3463 temp = 0xFFFF8000;
3464 set_DSPControl_overflow_flag(1, 23, env);
3465 }
3466
3467 return (target_long)(int32_t)(temp & 0xFFFFFFFF);
3468 }
3469
3470
3471 #if defined(TARGET_MIPS64)
3472 target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift,
3473 CPUMIPSState *env)
3474 {
3475 int64_t temp[2];
3476 uint32_t temp127;
3477
3478 shift = shift & 0x1F;
3479
3480 mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env);
3481
3482 temp127 = (temp[1] >> 63) & 0x01;
3483
3484 if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) {
3485 temp[0] &= 0xFFFF0000;
3486 temp[0] |= 0x00007FFF;
3487 set_DSPControl_overflow_flag(1, 23, env);
3488 } else if ((temp127 == 1) &&
3489 (temp[1] < 0xFFFFFFFFFFFFFFFFll
3490 || temp[0] < 0xFFFFFFFFFFFF1000ll)) {
3491 temp[0] &= 0xFFFF0000;
3492 temp[0] |= 0x00008000;
3493 set_DSPControl_overflow_flag(1, 23, env);
3494 }
3495
3496 return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO);
3497 }
3498
3499 #endif
3500
3501 target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3502 {
3503 int32_t start_pos;
3504 int sub;
3505 uint32_t temp;
3506 uint64_t acc;
3507
3508 size = size & 0x1F;
3509
3510 temp = 0;
3511 start_pos = get_DSPControl_pos(env);
3512 sub = start_pos - (size + 1);
3513 if (sub >= -1) {
3514 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3515 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3516 temp = (acc >> (start_pos - size)) &
3517 (((uint32_t)0x01 << (size + 1)) - 1);
3518 set_DSPControl_efi(0, env);
3519 } else {
3520 set_DSPControl_efi(1, env);
3521 }
3522
3523 return (target_ulong)temp;
3524 }
3525
3526 target_ulong helper_extpdp(target_ulong ac, target_ulong size,
3527 CPUMIPSState *env)
3528 {
3529 int32_t start_pos;
3530 int sub;
3531 uint32_t temp;
3532 uint64_t acc;
3533
3534 size = size & 0x1F;
3535 temp = 0;
3536 start_pos = get_DSPControl_pos(env);
3537 sub = start_pos - (size + 1);
3538 if (sub >= -1) {
3539 acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3540 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3541 temp = (acc >> (start_pos - size)) &
3542 (((uint32_t)0x01 << (size + 1)) - 1);
3543
3544 set_DSPControl_pos(start_pos - (size + 1), env);
3545 set_DSPControl_efi(0, env);
3546 } else {
3547 set_DSPControl_efi(1, env);
3548 }
3549
3550 return (target_ulong)temp;
3551 }
3552
3553
3554 #if defined(TARGET_MIPS64)
3555 target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3556 {
3557 int start_pos;
3558 int len;
3559 int sub;
3560 uint64_t tempB, tempA;
3561 uint64_t temp;
3562
3563 temp = 0;
3564
3565 size = size & 0x3F;
3566 start_pos = get_DSPControl_pos(env);
3567 len = start_pos - size;
3568 tempB = env->active_tc.HI[ac];
3569 tempA = env->active_tc.LO[ac];
3570
3571 sub = start_pos - (size + 1);
3572
3573 if (sub >= -1) {
3574 temp = (tempB << (64 - len)) | (tempA >> len);
3575 temp = temp & ((0x01 << (size + 1)) - 1);
3576 set_DSPControl_efi(0, env);
3577 } else {
3578 set_DSPControl_efi(1, env);
3579 }
3580
3581 return temp;
3582 }
3583
3584 target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
3585 CPUMIPSState *env)
3586 {
3587 int start_pos;
3588 int len;
3589 int sub;
3590 uint64_t tempB, tempA;
3591 uint64_t temp;
3592
3593 temp = 0;
3594 size = size & 0x3F;
3595 start_pos = get_DSPControl_pos(env);
3596 len = start_pos - size;
3597 tempB = env->active_tc.HI[ac];
3598 tempA = env->active_tc.LO[ac];
3599
3600 sub = start_pos - (size + 1);
3601
3602 if (sub >= -1) {
3603 temp = (tempB << (64 - len)) | (tempA >> len);
3604 temp = temp & ((0x01 << (size + 1)) - 1);
3605 set_DSPControl_pos(sub, env);
3606 set_DSPControl_efi(0, env);
3607 } else {
3608 set_DSPControl_efi(1, env);
3609 }
3610
3611 return temp;
3612 }
3613
3614 #endif
3615
3616 void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3617 {
3618 int8_t rs5_0;
3619 uint64_t temp, acc;
3620
3621 rs5_0 = rs & 0x3F;
3622 rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
3623
3624 if (unlikely(rs5_0 == 0)) {
3625 return;
3626 }
3627
3628 acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
3629 ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3630
3631 if (rs5_0 > 0) {
3632 temp = acc >> rs5_0;
3633 } else {
3634 temp = acc << -rs5_0;
3635 }
3636
3637 env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
3638 env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO);
3639 }
3640
3641 #if defined(TARGET_MIPS64)
3642 void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env)
3643 {
3644 int8_t shift_t;
3645 uint64_t tempB, tempA;
3646
3647 shift_t = (int8_t)(shift << 1) >> 1;
3648
3649 tempB = env->active_tc.HI[ac];
3650 tempA = env->active_tc.LO[ac];
3651
3652 if (shift_t != 0) {
3653 if (shift_t >= 0) {
3654 tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t);
3655 tempB = tempB >> shift_t;
3656 } else {
3657 shift_t = -shift_t;
3658 tempB = (tempB << shift_t) | (tempA >> (64 - shift_t));
3659 tempA = tempA << shift_t;
3660 }
3661 }
3662
3663 env->active_tc.HI[ac] = tempB;
3664 env->active_tc.LO[ac] = tempA;
3665 }
3666
3667 #endif
3668 void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3669 {
3670 int32_t tempA, tempB, pos;
3671
3672 tempA = rs;
3673 tempB = env->active_tc.LO[ac];
3674 env->active_tc.HI[ac] = (target_long)tempB;
3675 env->active_tc.LO[ac] = (target_long)tempA;
3676 pos = get_DSPControl_pos(env);
3677
3678 if (pos > 32) {
3679 return;
3680 } else {
3681 set_DSPControl_pos(pos + 32, env);
3682 }
3683 }
3684
3685 #if defined(TARGET_MIPS64)
3686 void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env)
3687 {
3688 uint8_t ac_t;
3689 uint8_t pos;
3690 uint64_t tempB, tempA;
3691
3692 ac_t = ac & 0x3;
3693
3694 tempA = rs;
3695 tempB = env->active_tc.LO[ac_t];
3696
3697 env->active_tc.HI[ac_t] = tempB;
3698 env->active_tc.LO[ac_t] = tempA;
3699
3700 pos = get_DSPControl_pos(env);
3701
3702 if (pos <= 64) {
3703 pos = pos + 64;
3704 set_DSPControl_pos(pos, env);
3705 }
3706 }
3707 #endif
3708
3709 void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
3710 {
3711 uint8_t mask[6];
3712 uint8_t i;
3713 uint32_t newbits, overwrite;
3714 target_ulong dsp;
3715
3716 newbits = 0x00;
3717 overwrite = 0xFFFFFFFF;
3718 dsp = env->active_tc.DSPControl;
3719
3720 for (i = 0; i < 6; i++) {
3721 mask[i] = (mask_num >> i) & 0x01;
3722 }
3723
3724 if (mask[0] == 1) {
3725 #if defined(TARGET_MIPS64)
3726 overwrite &= 0xFFFFFF80;
3727 newbits &= 0xFFFFFF80;
3728 newbits |= 0x0000007F & rs;
3729 #else
3730 overwrite &= 0xFFFFFFC0;
3731 newbits &= 0xFFFFFFC0;
3732 newbits |= 0x0000003F & rs;
3733 #endif
3734 }
3735
3736 if (mask[1] == 1) {
3737 overwrite &= 0xFFFFE07F;
3738 newbits &= 0xFFFFE07F;
3739 newbits |= 0x00001F80 & rs;
3740 }
3741
3742 if (mask[2] == 1) {
3743 overwrite &= 0xFFFFDFFF;
3744 newbits &= 0xFFFFDFFF;
3745 newbits |= 0x00002000 & rs;
3746 }
3747
3748 if (mask[3] == 1) {
3749 overwrite &= 0xFF00FFFF;
3750 newbits &= 0xFF00FFFF;
3751 newbits |= 0x00FF0000 & rs;
3752 }
3753
3754 if (mask[4] == 1) {
3755 overwrite &= 0x00FFFFFF;
3756 newbits &= 0x00FFFFFF;
3757 #if defined(TARGET_MIPS64)
3758 newbits |= 0xFF000000 & rs;
3759 #else
3760 newbits |= 0x0F000000 & rs;
3761 #endif
3762 }
3763
3764 if (mask[5] == 1) {
3765 overwrite &= 0xFFFFBFFF;
3766 newbits &= 0xFFFFBFFF;
3767 newbits |= 0x00004000 & rs;
3768 }
3769
3770 dsp = dsp & overwrite;
3771 dsp = dsp | newbits;
3772 env->active_tc.DSPControl = dsp;
3773 }
3774
3775 target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env)
3776 {
3777 uint8_t mask[6];
3778 uint32_t ruler, i;
3779 target_ulong temp;
3780 target_ulong dsp;
3781
3782 ruler = 0x01;
3783 for (i = 0; i < 6; i++) {
3784 mask[i] = (masknum & ruler) >> i ;
3785 ruler = ruler << 1;
3786 }
3787
3788 temp = 0x00;
3789 dsp = env->active_tc.DSPControl;
3790
3791 if (mask[0] == 1) {
3792 #if defined(TARGET_MIPS64)
3793 temp |= dsp & 0x7F;
3794 #else
3795 temp |= dsp & 0x3F;
3796 #endif
3797 }
3798
3799 if (mask[1] == 1) {
3800 temp |= dsp & 0x1F80;
3801 }
3802
3803 if (mask[2] == 1) {
3804 temp |= dsp & 0x2000;
3805 }
3806
3807 if (mask[3] == 1) {
3808 temp |= dsp & 0x00FF0000;
3809 }
3810
3811 if (mask[4] == 1) {
3812 #if defined(TARGET_MIPS64)
3813 temp |= dsp & 0xFF000000;
3814 #else
3815 temp |= dsp & 0x0F000000;
3816 #endif
3817 }
3818
3819 if (mask[5] == 1) {
3820 temp |= dsp & 0x4000;
3821 }
3822
3823 return temp;
3824 }
3825
3826
3827 #undef MIPSDSP_LHI
3828 #undef MIPSDSP_LLO
3829 #undef MIPSDSP_HI
3830 #undef MIPSDSP_LO
3831 #undef MIPSDSP_Q3
3832 #undef MIPSDSP_Q2
3833 #undef MIPSDSP_Q1
3834 #undef MIPSDSP_Q0
3835
3836 #undef MIPSDSP_SPLIT32_8
3837 #undef MIPSDSP_SPLIT32_16
3838
3839 #undef MIPSDSP_RETURN32_8
3840 #undef MIPSDSP_RETURN32_16
3841
3842 #ifdef TARGET_MIPS64
3843 #undef MIPSDSP_SPLIT64_16
3844 #undef MIPSDSP_SPLIT64_32
3845 #undef MIPSDSP_RETURN64_16
3846 #undef MIPSDSP_RETURN64_32
3847 #endif
Qemu copy for testing