]>
git.proxmox.com Git - qemu.git/blob - target-mips/dsp_helper.c
2 * MIPS ASE DSP Instruction emulation helpers for QEMU.
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 * Dongxue Zhang <elat.era@gmail.com>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 /*** MIPS DSP internal functions begin ***/
24 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
25 #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
27 static inline void set_DSPControl_overflow_flag(uint32_t flag
, int position
,
30 env
->active_tc
.DSPControl
|= (target_ulong
)flag
<< position
;
33 static inline void set_DSPControl_carryflag(uint32_t flag
, CPUMIPSState
*env
)
35 env
->active_tc
.DSPControl
|= (target_ulong
)flag
<< 13;
38 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState
*env
)
40 return (env
->active_tc
.DSPControl
>> 13) & 0x01;
43 static inline void set_DSPControl_24(uint32_t flag
, int len
, CPUMIPSState
*env
)
47 filter
= ((0x01 << len
) - 1) << 24;
50 env
->active_tc
.DSPControl
&= filter
;
51 env
->active_tc
.DSPControl
|= (target_ulong
)flag
<< 24;
54 static inline uint32_t get_DSPControl_24(int len
, CPUMIPSState
*env
)
58 filter
= (0x01 << len
) - 1;
60 return (env
->active_tc
.DSPControl
>> 24) & filter
;
63 static inline void set_DSPControl_pos(uint32_t pos
, CPUMIPSState
*env
)
67 dspc
= env
->active_tc
.DSPControl
;
69 dspc
= dspc
& 0xFFFFFFC0;
72 dspc
= dspc
& 0xFFFFFF80;
75 env
->active_tc
.DSPControl
= dspc
;
78 static inline uint32_t get_DSPControl_pos(CPUMIPSState
*env
)
83 dspc
= env
->active_tc
.DSPControl
;
94 static inline void set_DSPControl_efi(uint32_t flag
, CPUMIPSState
*env
)
96 env
->active_tc
.DSPControl
&= 0xFFFFBFFF;
97 env
->active_tc
.DSPControl
|= (target_ulong
)flag
<< 14;
100 #define DO_MIPS_SAT_ABS(size) \
101 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \
104 if (a == INT##size##_MIN) { \
105 set_DSPControl_overflow_flag(1, 20, env); \
106 return INT##size##_MAX; \
108 return MIPSDSP_ABS(a); \
114 #undef DO_MIPS_SAT_ABS
117 static inline int16_t mipsdsp_add_i16(int16_t a
, int16_t b
, CPUMIPSState
*env
)
123 if (MIPSDSP_OVERFLOW(a
, b
, tempI
, 0x8000)) {
124 set_DSPControl_overflow_flag(1, 20, env
);
130 static inline int16_t mipsdsp_sat_add_i16(int16_t a
, int16_t b
,
137 if (MIPSDSP_OVERFLOW(a
, b
, tempS
, 0x8000)) {
143 set_DSPControl_overflow_flag(1, 20, env
);
149 static inline int32_t mipsdsp_sat_add_i32(int32_t a
, int32_t b
,
156 if (MIPSDSP_OVERFLOW(a
, b
, tempI
, 0x80000000)) {
162 set_DSPControl_overflow_flag(1, 20, env
);
168 static inline uint8_t mipsdsp_add_u8(uint8_t a
, uint8_t b
, CPUMIPSState
*env
)
172 temp
= (uint16_t)a
+ (uint16_t)b
;
175 set_DSPControl_overflow_flag(1, 20, env
);
181 static inline uint16_t mipsdsp_add_u16(uint16_t a
, uint16_t b
,
186 temp
= (uint32_t)a
+ (uint32_t)b
;
188 if (temp
& 0x00010000) {
189 set_DSPControl_overflow_flag(1, 20, env
);
192 return temp
& 0xFFFF;
195 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a
, uint8_t b
,
201 temp
= (uint16_t)a
+ (uint16_t)b
;
202 result
= temp
& 0xFF;
206 set_DSPControl_overflow_flag(1, 20, env
);
212 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a
, uint16_t b
,
218 temp
= (uint32_t)a
+ (uint32_t)b
;
219 result
= temp
& 0xFFFF;
221 if (0x00010000 & temp
) {
223 set_DSPControl_overflow_flag(1, 20, env
);
229 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc
, int32_t a
,
233 int32_t temp32
, temp31
, result
;
236 #ifndef TARGET_MIPS64
237 temp
= ((uint64_t)env
->active_tc
.HI
[acc
] << 32) |
238 (uint64_t)env
->active_tc
.LO
[acc
];
240 temp
= (uint64_t)env
->active_tc
.LO
[acc
];
243 temp_sum
= (int64_t)a
+ temp
;
245 temp32
= (temp_sum
>> 32) & 0x01;
246 temp31
= (temp_sum
>> 31) & 0x01;
247 result
= temp_sum
& 0xFFFFFFFF;
250 This sat function may wrong, because user manual wrote:
251 temp127..0 ← temp + ( (signA) || a31..0
252 if ( temp32 ≠ temp31 ) then
253 if ( temp32 = 0 ) then
254 temp31..0 ← 0x80000000
256 temp31..0 ← 0x7FFFFFFF
258 DSPControlouflag:16+acc ← 1
261 if (temp32
!= temp31
) {
267 set_DSPControl_overflow_flag(1, 16 + acc
, env
);
273 /* a[0] is LO, a[1] is HI. */
274 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret
,
281 ret
[0] = env
->active_tc
.LO
[ac
] + a
[0];
282 ret
[1] = env
->active_tc
.HI
[ac
] + a
[1];
284 if (((uint64_t)ret
[0] < (uint64_t)env
->active_tc
.LO
[ac
]) &&
285 ((uint64_t)ret
[0] < (uint64_t)a
[0])) {
289 if (temp64
!= ((ret
[0] >> 63) & 0x01)) {
291 ret
[0] = (0x01ull
<< 63);
294 ret
[0] = (0x01ull
<< 63) - 1;
297 set_DSPControl_overflow_flag(1, 16 + ac
, env
);
301 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret
,
308 ret
[0] = env
->active_tc
.LO
[ac
] - a
[0];
309 ret
[1] = env
->active_tc
.HI
[ac
] - a
[1];
311 if ((uint64_t)ret
[0] > (uint64_t)env
->active_tc
.LO
[ac
]) {
315 if (temp64
!= ((ret
[0] >> 63) & 0x01)) {
317 ret
[0] = (0x01ull
<< 63);
320 ret
[0] = (0x01ull
<< 63) - 1;
323 set_DSPControl_overflow_flag(1, 16 + ac
, env
);
327 static inline int32_t mipsdsp_mul_i16_i16(int16_t a
, int16_t b
,
332 temp
= (int32_t)a
* (int32_t)b
;
334 if ((temp
> (int)0x7FFF) || (temp
< (int)0xFFFF8000)) {
335 set_DSPControl_overflow_flag(1, 21, env
);
342 static inline int32_t mipsdsp_mul_u16_u16(int32_t a
, int32_t b
)
347 static inline int32_t mipsdsp_mul_i32_i32(int32_t a
, int32_t b
)
352 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a
, int16_t b
,
357 temp
= (int32_t)a
* (int32_t)b
;
359 if (temp
> (int)0x7FFF) {
361 set_DSPControl_overflow_flag(1, 21, env
);
362 } else if (temp
< (int)0xffff8000) {
364 set_DSPControl_overflow_flag(1, 21, env
);
371 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a
, uint16_t b
,
376 if ((a
== 0x8000) && (b
== 0x8000)) {
378 set_DSPControl_overflow_flag(1, 21, env
);
380 temp
= ((int32_t)(int16_t)a
* (int32_t)(int16_t)b
) << 1;
387 static inline uint8_t mipsdsp_rshift_u8(uint8_t a
, target_ulong mov
)
392 static inline uint16_t mipsdsp_rshift_u16(uint16_t a
, target_ulong mov
)
397 static inline int8_t mipsdsp_rashift8(int8_t a
, target_ulong mov
)
402 static inline int16_t mipsdsp_rashift16(int16_t a
, target_ulong mov
)
407 static inline int32_t mipsdsp_rashift32(int32_t a
, target_ulong mov
)
412 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a
, int16_t b
)
416 temp
= (int32_t)a
+ (int32_t)b
;
418 return (temp
>> 1) & 0xFFFF;
421 /* round right shift */
422 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a
, int16_t b
)
426 temp
= (int32_t)a
+ (int32_t)b
;
429 return (temp
>> 1) & 0xFFFF;
432 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a
, int32_t b
)
436 temp
= (int64_t)a
+ (int64_t)b
;
438 return (temp
>> 1) & 0xFFFFFFFF;
441 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a
, int32_t b
)
445 temp
= (int64_t)a
+ (int64_t)b
;
448 return (temp
>> 1) & 0xFFFFFFFF;
451 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a
, uint8_t b
)
455 temp
= (uint16_t)a
+ (uint16_t)b
;
457 return (temp
>> 1) & 0x00FF;
460 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a
, uint8_t b
)
464 temp
= (uint16_t)a
+ (uint16_t)b
+ 1;
466 return (temp
>> 1) & 0x00FF;
469 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a
, uint8_t b
)
473 temp
= (uint16_t)a
- (uint16_t)b
;
475 return (temp
>> 1) & 0x00FF;
478 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a
, uint8_t b
)
482 temp
= (uint16_t)a
- (uint16_t)b
+ 1;
484 return (temp
>> 1) & 0x00FF;
487 static inline int64_t mipsdsp_rashift_short_acc(int32_t ac
,
491 int32_t sign
, temp31
;
494 sign
= (env
->active_tc
.HI
[ac
] >> 31) & 0x01;
495 acc
= ((int64_t)env
->active_tc
.HI
[ac
] << 32) |
496 ((int64_t)env
->active_tc
.LO
[ac
] & 0xFFFFFFFF);
501 temp
= (((int64_t)0x01 << (32 - shift
+ 1)) - 1) & (acc
>> shift
);
503 temp
= ((((int64_t)0x01 << (shift
+ 1)) - 1) << (32 - shift
)) |
508 temp31
= (temp
>> 31) & 0x01;
509 if (sign
!= temp31
) {
510 set_DSPControl_overflow_flag(1, 23, env
);
516 /* 128 bits long. p[0] is LO, p[1] is HI. */
517 static inline void mipsdsp_rndrashift_short_acc(int64_t *p
,
524 acc
= ((int64_t)env
->active_tc
.HI
[ac
] << 32) |
525 ((int64_t)env
->active_tc
.LO
[ac
] & 0xFFFFFFFF);
528 p
[1] = (acc
>> 63) & 0x01;
530 p
[0] = acc
>> (shift
- 1);
535 /* 128 bits long. p[0] is LO, p[1] is HI */
536 static inline void mipsdsp_rashift_acc(uint64_t *p
,
541 uint64_t tempB
, tempA
;
543 tempB
= env
->active_tc
.HI
[ac
];
544 tempA
= env
->active_tc
.LO
[ac
];
545 shift
= shift
& 0x1F;
551 p
[0] = (tempB
<< (64 - shift
)) | (tempA
>> shift
);
552 p
[1] = (int64_t)tempB
>> shift
;
556 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
557 static inline void mipsdsp_rndrashift_acc(uint64_t *p
,
562 int64_t tempB
, tempA
;
564 tempB
= env
->active_tc
.HI
[ac
];
565 tempA
= env
->active_tc
.LO
[ac
];
566 shift
= shift
& 0x3F;
570 p
[1] = (tempB
<< 1) | (tempA
>> 63);
573 p
[0] = (tempB
<< (65 - shift
)) | (tempA
>> (shift
- 1));
574 p
[1] = (int64_t)tempB
>> (shift
- 1);
583 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac
, uint16_t a
, uint16_t b
,
588 if ((a
== 0x8000) && (b
== 0x8000)) {
590 set_DSPControl_overflow_flag(1, 16 + ac
, env
);
592 temp
= ((uint32_t)a
* (uint32_t)b
) << 1;
598 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac
, uint32_t a
, uint32_t b
,
603 if ((a
== 0x80000000) && (b
== 0x80000000)) {
604 temp
= (0x01ull
<< 63) - 1;
605 set_DSPControl_overflow_flag(1, 16 + ac
, env
);
607 temp
= ((uint64_t)a
* (uint64_t)b
) << 1;
613 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a
, uint8_t b
)
615 return (uint16_t)a
* (uint16_t)b
;
618 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a
, uint16_t b
,
623 tempI
= (uint32_t)a
* (uint32_t)b
;
624 if (tempI
> 0x0000FFFF) {
626 set_DSPControl_overflow_flag(1, 21, env
);
629 return tempI
& 0x0000FFFF;
632 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a
, uint32_t b
)
634 return (uint64_t)a
* (uint64_t)b
;
637 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a
, uint16_t b
,
642 if ((a
== 0x8000) && (b
== 0x8000)) {
644 set_DSPControl_overflow_flag(1, 21, env
);
647 temp
= temp
+ 0x00008000;
650 return (temp
& 0xFFFF0000) >> 16;
653 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a
, uint16_t b
,
658 if ((a
== 0x8000) && (b
== 0x8000)) {
660 set_DSPControl_overflow_flag(1, 21, env
);
662 temp
= ((uint32_t)a
* (uint32_t)b
);
666 return (temp
>> 16) & 0x0000FFFF;
669 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a
,
674 temp
= (int32_t)a
+ 0x00008000;
676 if (a
> (int)0x7fff8000) {
678 set_DSPControl_overflow_flag(1, 22, env
);
681 return (temp
>> 16) & 0xFFFF;
684 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a
,
690 sign
= (a
>> 15) & 0x01;
695 set_DSPControl_overflow_flag(1, 22, env
);
698 return (mag
>> 7) & 0xFFFF;
701 set_DSPControl_overflow_flag(1, 22, env
);
706 static inline uint8_t mipsdsp_lshift8(uint8_t a
, uint8_t s
, CPUMIPSState
*env
)
714 sign
= (a
>> 7) & 0x01;
716 discard
= (((0x01 << (8 - s
)) - 1) << s
) |
717 ((a
>> (6 - (s
- 1))) & ((0x01 << s
) - 1));
719 discard
= a
>> (6 - (s
- 1));
722 if (discard
!= 0x00) {
723 set_DSPControl_overflow_flag(1, 22, env
);
729 static inline uint16_t mipsdsp_lshift16(uint16_t a
, uint8_t s
,
738 sign
= (a
>> 15) & 0x01;
740 discard
= (((0x01 << (16 - s
)) - 1) << s
) |
741 ((a
>> (14 - (s
- 1))) & ((0x01 << s
) - 1));
743 discard
= a
>> (14 - (s
- 1));
746 if ((discard
!= 0x0000) && (discard
!= 0xFFFF)) {
747 set_DSPControl_overflow_flag(1, 22, env
);
754 static inline uint32_t mipsdsp_lshift32(uint32_t a
, uint8_t s
,
762 discard
= (int32_t)a
>> (31 - (s
- 1));
764 if ((discard
!= 0x00000000) && (discard
!= 0xFFFFFFFF)) {
765 set_DSPControl_overflow_flag(1, 22, env
);
771 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a
, uint8_t s
,
780 sign
= (a
>> 15) & 0x01;
782 discard
= (((0x01 << (16 - s
)) - 1) << s
) |
783 ((a
>> (14 - (s
- 1))) & ((0x01 << s
) - 1));
785 discard
= a
>> (14 - (s
- 1));
788 if ((discard
!= 0x0000) && (discard
!= 0xFFFF)) {
789 set_DSPControl_overflow_flag(1, 22, env
);
790 return (sign
== 0) ? 0x7FFF : 0x8000;
797 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a
, uint8_t s
,
806 sign
= (a
>> 31) & 0x01;
808 discard
= (((0x01 << (32 - s
)) - 1) << s
) |
809 ((a
>> (30 - (s
- 1))) & ((0x01 << s
) - 1));
811 discard
= a
>> (30 - (s
- 1));
814 if ((discard
!= 0x00000000) && (discard
!= 0xFFFFFFFF)) {
815 set_DSPControl_overflow_flag(1, 22, env
);
816 return (sign
== 0) ? 0x7FFFFFFF : 0x80000000;
823 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a
, uint8_t s
)
828 temp
= (uint32_t)a
<< 1;
830 temp
= (int32_t)(int8_t)a
>> (s
- 1);
833 return (temp
+ 1) >> 1;
836 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a
, uint8_t s
)
841 temp
= (uint32_t)a
<< 1;
843 temp
= (int32_t)(int16_t)a
>> (s
- 1);
846 return (temp
+ 1) >> 1;
849 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a
, uint8_t s
)
854 temp
= (uint64_t)a
<< 1;
856 temp
= (int64_t)(int32_t)a
>> (s
- 1);
860 return (temp
>> 1) & 0xFFFFFFFFull
;
863 static inline uint16_t mipsdsp_sub_i16(int16_t a
, int16_t b
, CPUMIPSState
*env
)
868 if (MIPSDSP_OVERFLOW(a
, -b
, temp
, 0x8000)) {
869 set_DSPControl_overflow_flag(1, 20, env
);
875 static inline uint16_t mipsdsp_sat16_sub(int16_t a
, int16_t b
,
881 if (MIPSDSP_OVERFLOW(a
, -b
, temp
, 0x8000)) {
887 set_DSPControl_overflow_flag(1, 20, env
);
893 static inline uint32_t mipsdsp_sat32_sub(int32_t a
, int32_t b
,
899 if (MIPSDSP_OVERFLOW(a
, -b
, temp
, 0x80000000)) {
905 set_DSPControl_overflow_flag(1, 20, env
);
908 return temp
& 0xFFFFFFFFull
;
911 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a
, int16_t b
)
915 temp
= (int32_t)a
- (int32_t)b
;
917 return (temp
>> 1) & 0x0000FFFF;
920 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a
, int16_t b
)
924 temp
= (int32_t)a
- (int32_t)b
;
927 return (temp
>> 1) & 0x0000FFFF;
930 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a
, int32_t b
)
934 temp
= (int64_t)a
- (int64_t)b
;
936 return (temp
>> 1) & 0xFFFFFFFFull
;
939 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a
, int32_t b
)
943 temp
= (int64_t)a
- (int64_t)b
;
946 return (temp
>> 1) & 0xFFFFFFFFull
;
949 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a
, uint16_t b
,
955 temp
= (uint32_t)a
- (uint32_t)b
;
956 temp16
= (temp
>> 16) & 0x01;
958 set_DSPControl_overflow_flag(1, 20, env
);
960 return temp
& 0x0000FFFF;
963 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a
, uint16_t b
,
969 temp
= (uint32_t)a
- (uint32_t)b
;
970 temp16
= (temp
>> 16) & 0x01;
974 set_DSPControl_overflow_flag(1, 20, env
);
977 return temp
& 0x0000FFFF;
980 static inline uint8_t mipsdsp_sub_u8(uint8_t a
, uint8_t b
, CPUMIPSState
*env
)
985 temp
= (uint16_t)a
- (uint16_t)b
;
986 temp8
= (temp
>> 8) & 0x01;
988 set_DSPControl_overflow_flag(1, 20, env
);
991 return temp
& 0x00FF;
994 static inline uint8_t mipsdsp_satu8_sub(uint8_t a
, uint8_t b
, CPUMIPSState
*env
)
999 temp
= (uint16_t)a
- (uint16_t)b
;
1000 temp8
= (temp
>> 8) & 0x01;
1003 set_DSPControl_overflow_flag(1, 20, env
);
1006 return temp
& 0x00FF;
1009 static inline uint32_t mipsdsp_sub32(int32_t a
, int32_t b
, CPUMIPSState
*env
)
1014 if (MIPSDSP_OVERFLOW(a
, -b
, temp
, 0x80000000)) {
1015 set_DSPControl_overflow_flag(1, 20, env
);
1021 static inline int32_t mipsdsp_add_i32(int32_t a
, int32_t b
, CPUMIPSState
*env
)
1027 if (MIPSDSP_OVERFLOW(a
, b
, temp
, 0x80000000)) {
1028 set_DSPControl_overflow_flag(1, 20, env
);
1034 static inline int32_t mipsdsp_cmp_eq(int32_t a
, int32_t b
)
1039 static inline int32_t mipsdsp_cmp_le(int32_t a
, int32_t b
)
1044 static inline int32_t mipsdsp_cmp_lt(int32_t a
, int32_t b
)
1049 static inline int32_t mipsdsp_cmpu_eq(uint32_t a
, uint32_t b
)
1054 static inline int32_t mipsdsp_cmpu_le(uint32_t a
, uint32_t b
)
1059 static inline int32_t mipsdsp_cmpu_lt(uint32_t a
, uint32_t b
)
1063 /*** MIPS DSP internal functions end ***/
1065 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1066 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1067 #define MIPSDSP_HI 0xFFFF0000
1068 #define MIPSDSP_LO 0x0000FFFF
1069 #define MIPSDSP_Q3 0xFF000000
1070 #define MIPSDSP_Q2 0x00FF0000
1071 #define MIPSDSP_Q1 0x0000FF00
1072 #define MIPSDSP_Q0 0x000000FF
1074 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
1076 a = (num >> 24) & MIPSDSP_Q0; \
1077 b = (num >> 16) & MIPSDSP_Q0; \
1078 c = (num >> 8) & MIPSDSP_Q0; \
1079 d = num & MIPSDSP_Q0; \
1082 #define MIPSDSP_SPLIT32_16(num, a, b) \
1084 a = (num >> 16) & MIPSDSP_LO; \
1085 b = num & MIPSDSP_LO; \
1088 #define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a)
1089 #define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
1090 (((uint32_t)a << 24) | \
1091 (((uint32_t)b << 16) | \
1092 (((uint32_t)c << 8) | \
1093 ((uint32_t)d & 0xFF)))))
1094 #define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
1095 (((uint32_t)a << 16) | \
1096 ((uint32_t)b & 0xFFFF)))
1098 #ifdef TARGET_MIPS64
1099 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
1101 a = (num >> 48) & MIPSDSP_LO; \
1102 b = (num >> 32) & MIPSDSP_LO; \
1103 c = (num >> 16) & MIPSDSP_LO; \
1104 d = num & MIPSDSP_LO; \
1107 #define MIPSDSP_SPLIT64_32(num, a, b) \
1109 a = (num >> 32) & MIPSDSP_LLO; \
1110 b = num & MIPSDSP_LLO; \
1113 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1114 ((uint64_t)b << 32) | \
1115 ((uint64_t)c << 16) | \
1117 #define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
1120 /** DSP Arithmetic Sub-class insns **/
1121 #define ARITH_PH(name, func) \
1122 target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \
1124 uint16_t rsh, rsl, rth, rtl, temph, templ; \
1126 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
1127 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1129 temph = mipsdsp_##func(rsh, rth); \
1130 templ = mipsdsp_##func(rsl, rtl); \
1132 return MIPSDSP_RETURN32_16(temph, templ); \
1135 #define ARITH_PH_ENV(name, func) \
1136 target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \
1137 CPUMIPSState *env) \
1139 uint16_t rsh, rsl, rth, rtl, temph, templ; \
1141 MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
1142 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
1144 temph = mipsdsp_##func(rsh, rth, env); \
1145 templ = mipsdsp_##func(rsl, rtl, env); \
1147 return MIPSDSP_RETURN32_16(temph, templ); \
1151 ARITH_PH_ENV(addq
, add_i16
);
1152 ARITH_PH_ENV(addq_s
, sat_add_i16
);
1153 ARITH_PH_ENV(addu
, add_u16
);
1154 ARITH_PH_ENV(addu_s
, sat_add_u16
);
1156 ARITH_PH(addqh
, rshift1_add_q16
);
1157 ARITH_PH(addqh_r
, rrshift1_add_q16
);
1159 ARITH_PH_ENV(subq
, sub_i16
);
1160 ARITH_PH_ENV(subq_s
, sat16_sub
);
1161 ARITH_PH_ENV(subu
, sub_u16_u16
);
1162 ARITH_PH_ENV(subu_s
, satu16_sub_u16_u16
);
1164 ARITH_PH(subqh
, rshift1_sub_q16
);
1165 ARITH_PH(subqh_r
, rrshift1_sub_q16
);
1170 #ifdef TARGET_MIPS64
1171 #define ARITH_QH_ENV(name, func) \
1172 target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \
1173 CPUMIPSState *env) \
1175 uint16_t rs3, rs2, rs1, rs0; \
1176 uint16_t rt3, rt2, rt1, rt0; \
1177 uint16_t tempD, tempC, tempB, tempA; \
1179 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1180 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1182 tempD = mipsdsp_##func(rs3, rt3, env); \
1183 tempC = mipsdsp_##func(rs2, rt2, env); \
1184 tempB = mipsdsp_##func(rs1, rt1, env); \
1185 tempA = mipsdsp_##func(rs0, rt0, env); \
1187 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1190 ARITH_QH_ENV(addq
, add_i16
);
1191 ARITH_QH_ENV(addq_s
, sat_add_i16
);
1192 ARITH_QH_ENV(addu
, add_u16
);
1193 ARITH_QH_ENV(addu_s
, sat_add_u16
);
1195 ARITH_QH_ENV(subq
, sub_i16
);
1196 ARITH_QH_ENV(subq_s
, sat16_sub
);
1197 ARITH_QH_ENV(subu
, sub_u16_u16
);
1198 ARITH_QH_ENV(subu_s
, satu16_sub_u16_u16
);
1204 #define ARITH_W(name, func) \
1205 target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \
1208 rd = mipsdsp_##func(rs, rt); \
1209 return MIPSDSP_RETURN32(rd); \
1212 #define ARITH_W_ENV(name, func) \
1213 target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \
1214 CPUMIPSState *env) \
1217 rd = mipsdsp_##func(rs, rt, env); \
1218 return MIPSDSP_RETURN32(rd); \
1221 ARITH_W_ENV(addq_s
, sat_add_i32
);
1223 ARITH_W(addqh
, rshift1_add_q32
);
1224 ARITH_W(addqh_r
, rrshift1_add_q32
);
1226 ARITH_W_ENV(subq_s
, sat32_sub
);
1228 ARITH_W(subqh
, rshift1_sub_q32
);
1229 ARITH_W(subqh_r
, rrshift1_sub_q32
);
1234 target_ulong
helper_absq_s_w(target_ulong rt
, CPUMIPSState
*env
)
1238 rd
= mipsdsp_sat_abs32(rt
, env
);
1240 return (target_ulong
)rd
;
1244 #if defined(TARGET_MIPS64)
1246 #define ARITH_PW_ENV(name, func) \
1247 target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \
1248 CPUMIPSState *env) \
1250 uint32_t rs1, rs0; \
1251 uint32_t rt1, rt0; \
1252 uint32_t tempB, tempA; \
1254 MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
1255 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
1257 tempB = mipsdsp_##func(rs1, rt1, env); \
1258 tempA = mipsdsp_##func(rs0, rt0, env); \
1260 return MIPSDSP_RETURN64_32(tempB, tempA); \
1263 ARITH_PW_ENV(addq
, add_i32
);
1264 ARITH_PW_ENV(addq_s
, sat_add_i32
);
1265 ARITH_PW_ENV(subq
, sub32
);
1266 ARITH_PW_ENV(subq_s
, sat32_sub
);
1272 #define ARITH_QB(name, func) \
1273 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1275 uint8_t rs0, rs1, rs2, rs3; \
1276 uint8_t rt0, rt1, rt2, rt3; \
1277 uint8_t temp0, temp1, temp2, temp3; \
1279 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1280 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1282 temp0 = mipsdsp_##func(rs0, rt0); \
1283 temp1 = mipsdsp_##func(rs1, rt1); \
1284 temp2 = mipsdsp_##func(rs2, rt2); \
1285 temp3 = mipsdsp_##func(rs3, rt3); \
1287 return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
1290 #define ARITH_QB_ENV(name, func) \
1291 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \
1292 CPUMIPSState *env) \
1294 uint8_t rs0, rs1, rs2, rs3; \
1295 uint8_t rt0, rt1, rt2, rt3; \
1296 uint8_t temp0, temp1, temp2, temp3; \
1298 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1299 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1301 temp0 = mipsdsp_##func(rs0, rt0, env); \
1302 temp1 = mipsdsp_##func(rs1, rt1, env); \
1303 temp2 = mipsdsp_##func(rs2, rt2, env); \
1304 temp3 = mipsdsp_##func(rs3, rt3, env); \
1306 return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
1309 ARITH_QB(adduh
, rshift1_add_u8
);
1310 ARITH_QB(adduh_r
, rrshift1_add_u8
);
1312 ARITH_QB_ENV(addu
, add_u8
);
1313 ARITH_QB_ENV(addu_s
, sat_add_u8
);
1318 #if defined(TARGET_MIPS64)
1319 #define ARITH_OB(name, func) \
1320 target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \
1323 uint8_t rs_t[8], rt_t[8]; \
1329 for (i = 0; i < 8; i++) { \
1330 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
1331 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1332 temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \
1333 result |= (uint64_t)temp[i] << (8 * i); \
1339 #define ARITH_OB_ENV(name, func) \
1340 target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \
1341 CPUMIPSState *env) \
1344 uint8_t rs_t[8], rt_t[8]; \
1350 for (i = 0; i < 8; i++) { \
1351 rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
1352 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1353 temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \
1354 result |= (uint64_t)temp[i] << (8 * i); \
1360 ARITH_OB_ENV(addu
, add_u8
);
1361 ARITH_OB_ENV(addu_s
, sat_add_u8
);
1363 ARITH_OB(adduh
, rshift1_add_u8
);
1364 ARITH_OB(adduh_r
, rrshift1_add_u8
);
1366 ARITH_OB_ENV(subu
, sub_u8
);
1367 ARITH_OB_ENV(subu_s
, satu8_sub
);
1369 ARITH_OB(subuh
, rshift1_sub_u8
);
1370 ARITH_OB(subuh_r
, rrshift1_sub_u8
);
1377 #define SUBU_QB(name, func) \
1378 target_ulong helper_##name##_qb(target_ulong rs, \
1380 CPUMIPSState *env) \
1382 uint8_t rs3, rs2, rs1, rs0; \
1383 uint8_t rt3, rt2, rt1, rt0; \
1384 uint8_t tempD, tempC, tempB, tempA; \
1386 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1387 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1389 tempD = mipsdsp_##func(rs3, rt3, env); \
1390 tempC = mipsdsp_##func(rs2, rt2, env); \
1391 tempB = mipsdsp_##func(rs1, rt1, env); \
1392 tempA = mipsdsp_##func(rs0, rt0, env); \
1394 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1397 SUBU_QB(subu
, sub_u8
);
1398 SUBU_QB(subu_s
, satu8_sub
);
1402 #define SUBUH_QB(name, var) \
1403 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1405 uint8_t rs3, rs2, rs1, rs0; \
1406 uint8_t rt3, rt2, rt1, rt0; \
1407 uint8_t tempD, tempC, tempB, tempA; \
1409 MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
1410 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1412 tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
1413 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1414 tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
1415 tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
1417 return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \
1418 ((uint32_t)tempB << 8) | ((uint32_t)tempA); \
1422 SUBUH_QB(subuh_r
, 1);
1426 target_ulong
helper_addsc(target_ulong rs
, target_ulong rt
, CPUMIPSState
*env
)
1428 uint64_t temp
, tempRs
, tempRt
;
1431 tempRs
= (uint64_t)rs
& MIPSDSP_LLO
;
1432 tempRt
= (uint64_t)rt
& MIPSDSP_LLO
;
1434 temp
= tempRs
+ tempRt
;
1435 flag
= (temp
& 0x0100000000ull
) >> 32;
1436 set_DSPControl_carryflag(flag
, env
);
1438 return (target_long
)(int32_t)(temp
& MIPSDSP_LLO
);
1441 target_ulong
helper_addwc(target_ulong rs
, target_ulong rt
, CPUMIPSState
*env
)
1444 int32_t temp32
, temp31
;
1447 tempL
= (int64_t)(int32_t)rs
+ (int64_t)(int32_t)rt
+
1448 get_DSPControl_carryflag(env
);
1449 temp31
= (tempL
>> 31) & 0x01;
1450 temp32
= (tempL
>> 32) & 0x01;
1452 if (temp31
!= temp32
) {
1453 set_DSPControl_overflow_flag(1, 20, env
);
1456 rd
= tempL
& MIPSDSP_LLO
;
1458 return (target_long
)(int32_t)rd
;
1461 target_ulong
helper_modsub(target_ulong rs
, target_ulong rt
)
1467 decr
= rt
& MIPSDSP_Q0
;
1468 lastindex
= (rt
>> 8) & MIPSDSP_LO
;
1470 if ((rs
& MIPSDSP_LLO
) == 0x00000000) {
1471 rd
= (target_ulong
)lastindex
;
1479 target_ulong
helper_raddu_w_qb(target_ulong rs
)
1481 uint8_t rs3
, rs2
, rs1
, rs0
;
1484 MIPSDSP_SPLIT32_8(rs
, rs3
, rs2
, rs1
, rs0
);
1486 temp
= (uint16_t)rs3
+ (uint16_t)rs2
+ (uint16_t)rs1
+ (uint16_t)rs0
;
1488 return (target_ulong
)temp
;
1491 #if defined(TARGET_MIPS64)
1492 target_ulong
helper_raddu_l_ob(target_ulong rs
)
1500 for (i
= 0; i
< 8; i
++) {
1501 rs_t
[i
] = (rs
>> (8 * i
)) & MIPSDSP_Q0
;
1502 temp
+= (uint64_t)rs_t
[i
];
1509 target_ulong
helper_absq_s_qb(target_ulong rt
, CPUMIPSState
*env
)
1511 uint8_t tempD
, tempC
, tempB
, tempA
;
1513 MIPSDSP_SPLIT32_8(rt
, tempD
, tempC
, tempB
, tempA
);
1515 tempD
= mipsdsp_sat_abs8(tempD
, env
);
1516 tempC
= mipsdsp_sat_abs8(tempC
, env
);
1517 tempB
= mipsdsp_sat_abs8(tempB
, env
);
1518 tempA
= mipsdsp_sat_abs8(tempA
, env
);
1520 return MIPSDSP_RETURN32_8(tempD
, tempC
, tempB
, tempA
);
1523 target_ulong
helper_absq_s_ph(target_ulong rt
, CPUMIPSState
*env
)
1525 uint16_t tempB
, tempA
;
1527 MIPSDSP_SPLIT32_16(rt
, tempB
, tempA
);
1529 tempB
= mipsdsp_sat_abs16 (tempB
, env
);
1530 tempA
= mipsdsp_sat_abs16 (tempA
, env
);
1532 return MIPSDSP_RETURN32_16(tempB
, tempA
);
1535 #if defined(TARGET_MIPS64)
1536 target_ulong
helper_absq_s_ob(target_ulong rt
, CPUMIPSState
*env
)
1542 for (i
= 0; i
< 8; i
++) {
1543 temp
[i
] = (rt
>> (8 * i
)) & MIPSDSP_Q0
;
1544 temp
[i
] = mipsdsp_sat_abs8(temp
[i
], env
);
1547 for (i
= 0; i
< 8; i
++) {
1548 result
= (uint64_t)(uint8_t)temp
[i
] << (8 * i
);
1554 target_ulong
helper_absq_s_qh(target_ulong rt
, CPUMIPSState
*env
)
1556 int16_t tempD
, tempC
, tempB
, tempA
;
1558 MIPSDSP_SPLIT64_16(rt
, tempD
, tempC
, tempB
, tempA
);
1560 tempD
= mipsdsp_sat_abs16(tempD
, env
);
1561 tempC
= mipsdsp_sat_abs16(tempC
, env
);
1562 tempB
= mipsdsp_sat_abs16(tempB
, env
);
1563 tempA
= mipsdsp_sat_abs16(tempA
, env
);
1565 return MIPSDSP_RETURN64_16(tempD
, tempC
, tempB
, tempA
);
1568 target_ulong
helper_absq_s_pw(target_ulong rt
, CPUMIPSState
*env
)
1570 int32_t tempB
, tempA
;
1572 MIPSDSP_SPLIT64_32(rt
, tempB
, tempA
);
1574 tempB
= mipsdsp_sat_abs32(tempB
, env
);
1575 tempA
= mipsdsp_sat_abs32(tempA
, env
);
1577 return MIPSDSP_RETURN64_32(tempB
, tempA
);
1581 #define PRECR_QB_PH(name, a, b)\
1582 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1584 uint8_t tempD, tempC, tempB, tempA; \
1586 tempD = (rs >> a) & MIPSDSP_Q0; \
1587 tempC = (rs >> b) & MIPSDSP_Q0; \
1588 tempB = (rt >> a) & MIPSDSP_Q0; \
1589 tempA = (rt >> b) & MIPSDSP_Q0; \
1591 return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
1594 PRECR_QB_PH(precr
, 16, 0);
1595 PRECR_QB_PH(precrq
, 24, 8);
1599 target_ulong
helper_precr_sra_ph_w(uint32_t sa
, target_ulong rs
,
1602 uint16_t tempB
, tempA
;
1604 tempB
= ((int32_t)rt
>> sa
) & MIPSDSP_LO
;
1605 tempA
= ((int32_t)rs
>> sa
) & MIPSDSP_LO
;
1607 return MIPSDSP_RETURN32_16(tempB
, tempA
);
1610 target_ulong
helper_precr_sra_r_ph_w(uint32_t sa
,
1611 target_ulong rs
, target_ulong rt
)
1613 uint64_t tempB
, tempA
;
1615 /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1617 tempB
= (rt
& MIPSDSP_LO
) << 1;
1618 tempA
= (rs
& MIPSDSP_LO
) << 1;
1620 tempB
= ((int32_t)rt
>> (sa
- 1)) + 1;
1621 tempA
= ((int32_t)rs
>> (sa
- 1)) + 1;
1623 rt
= (((tempB
>> 1) & MIPSDSP_LO
) << 16) | ((tempA
>> 1) & MIPSDSP_LO
);
1625 return (target_long
)(int32_t)rt
;
1628 target_ulong
helper_precrq_ph_w(target_ulong rs
, target_ulong rt
)
1630 uint16_t tempB
, tempA
;
1632 tempB
= (rs
& MIPSDSP_HI
) >> 16;
1633 tempA
= (rt
& MIPSDSP_HI
) >> 16;
1635 return MIPSDSP_RETURN32_16(tempB
, tempA
);
1638 target_ulong
helper_precrq_rs_ph_w(target_ulong rs
, target_ulong rt
,
1641 uint16_t tempB
, tempA
;
1643 tempB
= mipsdsp_trunc16_sat16_round(rs
, env
);
1644 tempA
= mipsdsp_trunc16_sat16_round(rt
, env
);
1646 return MIPSDSP_RETURN32_16(tempB
, tempA
);
1649 #if defined(TARGET_MIPS64)
1650 target_ulong
helper_precr_ob_qh(target_ulong rs
, target_ulong rt
)
1652 uint8_t rs6
, rs4
, rs2
, rs0
;
1653 uint8_t rt6
, rt4
, rt2
, rt0
;
1656 rs6
= (rs
>> 48) & MIPSDSP_Q0
;
1657 rs4
= (rs
>> 32) & MIPSDSP_Q0
;
1658 rs2
= (rs
>> 16) & MIPSDSP_Q0
;
1659 rs0
= rs
& MIPSDSP_Q0
;
1660 rt6
= (rt
>> 48) & MIPSDSP_Q0
;
1661 rt4
= (rt
>> 32) & MIPSDSP_Q0
;
1662 rt2
= (rt
>> 16) & MIPSDSP_Q0
;
1663 rt0
= rt
& MIPSDSP_Q0
;
1665 temp
= ((uint64_t)rs6
<< 56) | ((uint64_t)rs4
<< 48) |
1666 ((uint64_t)rs2
<< 40) | ((uint64_t)rs0
<< 32) |
1667 ((uint64_t)rt6
<< 24) | ((uint64_t)rt4
<< 16) |
1668 ((uint64_t)rt2
<< 8) | (uint64_t)rt0
;
1673 #define PRECR_QH_PW(name, var) \
1674 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1677 uint16_t rs3, rs2, rs1, rs0; \
1678 uint16_t rt3, rt2, rt1, rt0; \
1679 uint16_t tempD, tempC, tempB, tempA; \
1681 MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
1682 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1684 /* When sa = 0, we use rt2, rt0, rs2, rs0; \
1685 * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
1687 tempD = rt2 << var; \
1688 tempC = rt0 << var; \
1689 tempB = rs2 << var; \
1690 tempA = rs0 << var; \
1692 tempD = (((int16_t)rt3 >> sa) + var) >> var; \
1693 tempC = (((int16_t)rt1 >> sa) + var) >> var; \
1694 tempB = (((int16_t)rs3 >> sa) + var) >> var; \
1695 tempA = (((int16_t)rs1 >> sa) + var) >> var; \
1698 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1701 PRECR_QH_PW(sra
, 0);
1702 PRECR_QH_PW(sra_r
, 1);
1706 target_ulong
helper_precrq_ob_qh(target_ulong rs
, target_ulong rt
)
1708 uint8_t rs6
, rs4
, rs2
, rs0
;
1709 uint8_t rt6
, rt4
, rt2
, rt0
;
1712 rs6
= (rs
>> 56) & MIPSDSP_Q0
;
1713 rs4
= (rs
>> 40) & MIPSDSP_Q0
;
1714 rs2
= (rs
>> 24) & MIPSDSP_Q0
;
1715 rs0
= (rs
>> 8) & MIPSDSP_Q0
;
1716 rt6
= (rt
>> 56) & MIPSDSP_Q0
;
1717 rt4
= (rt
>> 40) & MIPSDSP_Q0
;
1718 rt2
= (rt
>> 24) & MIPSDSP_Q0
;
1719 rt0
= (rt
>> 8) & MIPSDSP_Q0
;
1721 temp
= ((uint64_t)rs6
<< 56) | ((uint64_t)rs4
<< 48) |
1722 ((uint64_t)rs2
<< 40) | ((uint64_t)rs0
<< 32) |
1723 ((uint64_t)rt6
<< 24) | ((uint64_t)rt4
<< 16) |
1724 ((uint64_t)rt2
<< 8) | (uint64_t)rt0
;
1729 target_ulong
helper_precrq_qh_pw(target_ulong rs
, target_ulong rt
)
1731 uint16_t tempD
, tempC
, tempB
, tempA
;
1733 tempD
= (rs
>> 48) & MIPSDSP_LO
;
1734 tempC
= (rs
>> 16) & MIPSDSP_LO
;
1735 tempB
= (rt
>> 48) & MIPSDSP_LO
;
1736 tempA
= (rt
>> 16) & MIPSDSP_LO
;
1738 return MIPSDSP_RETURN64_16(tempD
, tempC
, tempB
, tempA
);
1741 target_ulong
helper_precrq_rs_qh_pw(target_ulong rs
, target_ulong rt
,
1746 uint16_t tempD
, tempC
, tempB
, tempA
;
1748 rs2
= (rs
>> 32) & MIPSDSP_LLO
;
1749 rs0
= rs
& MIPSDSP_LLO
;
1750 rt2
= (rt
>> 32) & MIPSDSP_LLO
;
1751 rt0
= rt
& MIPSDSP_LLO
;
1753 tempD
= mipsdsp_trunc16_sat16_round(rs2
, env
);
1754 tempC
= mipsdsp_trunc16_sat16_round(rs0
, env
);
1755 tempB
= mipsdsp_trunc16_sat16_round(rt2
, env
);
1756 tempA
= mipsdsp_trunc16_sat16_round(rt0
, env
);
1758 return MIPSDSP_RETURN64_16(tempD
, tempC
, tempB
, tempA
);
1761 target_ulong
helper_precrq_pw_l(target_ulong rs
, target_ulong rt
)
1763 uint32_t tempB
, tempA
;
1765 tempB
= (rs
>> 32) & MIPSDSP_LLO
;
1766 tempA
= (rt
>> 32) & MIPSDSP_LLO
;
1768 return MIPSDSP_RETURN64_32(tempB
, tempA
);
1772 target_ulong
helper_precrqu_s_qb_ph(target_ulong rs
, target_ulong rt
,
1775 uint8_t tempD
, tempC
, tempB
, tempA
;
1776 uint16_t rsh
, rsl
, rth
, rtl
;
1778 rsh
= (rs
& MIPSDSP_HI
) >> 16;
1779 rsl
= rs
& MIPSDSP_LO
;
1780 rth
= (rt
& MIPSDSP_HI
) >> 16;
1781 rtl
= rt
& MIPSDSP_LO
;
1783 tempD
= mipsdsp_sat8_reduce_precision(rsh
, env
);
1784 tempC
= mipsdsp_sat8_reduce_precision(rsl
, env
);
1785 tempB
= mipsdsp_sat8_reduce_precision(rth
, env
);
1786 tempA
= mipsdsp_sat8_reduce_precision(rtl
, env
);
1788 return MIPSDSP_RETURN32_8(tempD
, tempC
, tempB
, tempA
);
1791 #if defined(TARGET_MIPS64)
1792 target_ulong
helper_precrqu_s_ob_qh(target_ulong rs
, target_ulong rt
,
1796 uint16_t rs3
, rs2
, rs1
, rs0
;
1797 uint16_t rt3
, rt2
, rt1
, rt0
;
1803 MIPSDSP_SPLIT64_16(rs
, rs3
, rs2
, rs1
, rs0
);
1804 MIPSDSP_SPLIT64_16(rt
, rt3
, rt2
, rt1
, rt0
);
1806 temp
[7] = mipsdsp_sat8_reduce_precision(rs3
, env
);
1807 temp
[6] = mipsdsp_sat8_reduce_precision(rs2
, env
);
1808 temp
[5] = mipsdsp_sat8_reduce_precision(rs1
, env
);
1809 temp
[4] = mipsdsp_sat8_reduce_precision(rs0
, env
);
1810 temp
[3] = mipsdsp_sat8_reduce_precision(rt3
, env
);
1811 temp
[2] = mipsdsp_sat8_reduce_precision(rt2
, env
);
1812 temp
[1] = mipsdsp_sat8_reduce_precision(rt1
, env
);
1813 temp
[0] = mipsdsp_sat8_reduce_precision(rt0
, env
);
1815 for (i
= 0; i
< 8; i
++) {
1816 result
|= (uint64_t)temp
[i
] << (8 * i
);
1822 #define PRECEQ_PW(name, a, b) \
1823 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1825 uint16_t tempB, tempA; \
1826 uint32_t tempBI, tempAI; \
1828 tempB = (rt >> a) & MIPSDSP_LO; \
1829 tempA = (rt >> b) & MIPSDSP_LO; \
1831 tempBI = (uint32_t)tempB << 16; \
1832 tempAI = (uint32_t)tempA << 16; \
1834 return MIPSDSP_RETURN64_32(tempBI, tempAI); \
1837 PRECEQ_PW(qhl
, 48, 32);
1838 PRECEQ_PW(qhr
, 16, 0);
1839 PRECEQ_PW(qhla
, 48, 16);
1840 PRECEQ_PW(qhra
, 32, 0);
1846 #define PRECEQU_PH(name, a, b) \
1847 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1849 uint16_t tempB, tempA; \
1851 tempB = (rt >> a) & MIPSDSP_Q0; \
1852 tempA = (rt >> b) & MIPSDSP_Q0; \
1854 tempB = tempB << 7; \
1855 tempA = tempA << 7; \
1857 return MIPSDSP_RETURN32_16(tempB, tempA); \
1860 PRECEQU_PH(qbl
, 24, 16);
1861 PRECEQU_PH(qbr
, 8, 0);
1862 PRECEQU_PH(qbla
, 24, 8);
1863 PRECEQU_PH(qbra
, 16, 0);
1867 #if defined(TARGET_MIPS64)
1868 #define PRECEQU_QH(name, a, b, c, d) \
1869 target_ulong helper_precequ_qh_##name(target_ulong rt) \
1871 uint16_t tempD, tempC, tempB, tempA; \
1873 tempD = (rt >> a) & MIPSDSP_Q0; \
1874 tempC = (rt >> b) & MIPSDSP_Q0; \
1875 tempB = (rt >> c) & MIPSDSP_Q0; \
1876 tempA = (rt >> d) & MIPSDSP_Q0; \
1878 tempD = tempD << 7; \
1879 tempC = tempC << 7; \
1880 tempB = tempB << 7; \
1881 tempA = tempA << 7; \
1883 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1886 PRECEQU_QH(obl
, 56, 48, 40, 32);
1887 PRECEQU_QH(obr
, 24, 16, 8, 0);
1888 PRECEQU_QH(obla
, 56, 40, 24, 8);
1889 PRECEQU_QH(obra
, 48, 32, 16, 0);
1895 #define PRECEU_PH(name, a, b) \
1896 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1898 uint16_t tempB, tempA; \
1900 tempB = (rt >> a) & MIPSDSP_Q0; \
1901 tempA = (rt >> b) & MIPSDSP_Q0; \
1903 return MIPSDSP_RETURN32_16(tempB, tempA); \
1906 PRECEU_PH(qbl
, 24, 16);
1907 PRECEU_PH(qbr
, 8, 0);
1908 PRECEU_PH(qbla
, 24, 8);
1909 PRECEU_PH(qbra
, 16, 0);
1913 #if defined(TARGET_MIPS64)
1914 #define PRECEU_QH(name, a, b, c, d) \
1915 target_ulong helper_preceu_qh_##name(target_ulong rt) \
1917 uint16_t tempD, tempC, tempB, tempA; \
1919 tempD = (rt >> a) & MIPSDSP_Q0; \
1920 tempC = (rt >> b) & MIPSDSP_Q0; \
1921 tempB = (rt >> c) & MIPSDSP_Q0; \
1922 tempA = (rt >> d) & MIPSDSP_Q0; \
1924 return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
1927 PRECEU_QH(obl
, 56, 48, 40, 32);
1928 PRECEU_QH(obr
, 24, 16, 8, 0);
1929 PRECEU_QH(obla
, 56, 40, 24, 8);
1930 PRECEU_QH(obra
, 48, 32, 16, 0);
1936 /** DSP GPR-Based Shift Sub-class insns **/
1937 #define SHIFT_QB(name, func) \
1938 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1940 uint8_t rt3, rt2, rt1, rt0; \
1944 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1946 rt3 = mipsdsp_##func(rt3, sa); \
1947 rt2 = mipsdsp_##func(rt2, sa); \
1948 rt1 = mipsdsp_##func(rt1, sa); \
1949 rt0 = mipsdsp_##func(rt0, sa); \
1951 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1954 #define SHIFT_QB_ENV(name, func) \
1955 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1956 CPUMIPSState *env) \
1958 uint8_t rt3, rt2, rt1, rt0; \
1962 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1964 rt3 = mipsdsp_##func(rt3, sa, env); \
1965 rt2 = mipsdsp_##func(rt2, sa, env); \
1966 rt1 = mipsdsp_##func(rt1, sa, env); \
1967 rt0 = mipsdsp_##func(rt0, sa, env); \
1969 return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \
1972 SHIFT_QB_ENV(shll
, lshift8
);
1973 SHIFT_QB(shrl
, rshift_u8
);
1975 SHIFT_QB(shra
, rashift8
);
1976 SHIFT_QB(shra_r
, rnd8_rashift
);
1981 #if defined(TARGET_MIPS64)
1982 #define SHIFT_OB(name, func) \
1983 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1992 for (i = 0; i < 8; i++) { \
1993 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
1994 rt_t[i] = mipsdsp_##func(rt_t[i], sa); \
1995 temp |= (uint64_t)rt_t[i] << (8 * i); \
2001 #define SHIFT_OB_ENV(name, func) \
2002 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
2003 CPUMIPSState *env) \
2012 for (i = 0; i < 8; i++) { \
2013 rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
2014 rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \
2015 temp |= (uint64_t)rt_t[i] << (8 * i); \
2021 SHIFT_OB_ENV(shll
, lshift8
);
2022 SHIFT_OB(shrl
, rshift_u8
);
2024 SHIFT_OB(shra
, rashift8
);
2025 SHIFT_OB(shra_r
, rnd8_rashift
);
2032 #define SHIFT_PH(name, func) \
2033 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
2034 CPUMIPSState *env) \
2036 uint16_t rth, rtl; \
2040 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2042 rth = mipsdsp_##func(rth, sa, env); \
2043 rtl = mipsdsp_##func(rtl, sa, env); \
2045 return MIPSDSP_RETURN32_16(rth, rtl); \
2048 SHIFT_PH(shll
, lshift16
);
2049 SHIFT_PH(shll_s
, sat16_lshift
);
2053 #if defined(TARGET_MIPS64)
2054 #define SHIFT_QH(name, func) \
2055 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
2057 uint16_t rt3, rt2, rt1, rt0; \
2061 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2063 rt3 = mipsdsp_##func(rt3, sa); \
2064 rt2 = mipsdsp_##func(rt2, sa); \
2065 rt1 = mipsdsp_##func(rt1, sa); \
2066 rt0 = mipsdsp_##func(rt0, sa); \
2068 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
2071 #define SHIFT_QH_ENV(name, func) \
2072 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
2073 CPUMIPSState *env) \
2075 uint16_t rt3, rt2, rt1, rt0; \
2079 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
2081 rt3 = mipsdsp_##func(rt3, sa, env); \
2082 rt2 = mipsdsp_##func(rt2, sa, env); \
2083 rt1 = mipsdsp_##func(rt1, sa, env); \
2084 rt0 = mipsdsp_##func(rt0, sa, env); \
2086 return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \
2089 SHIFT_QH_ENV(shll
, lshift16
);
2090 SHIFT_QH_ENV(shll_s
, sat16_lshift
);
2092 SHIFT_QH(shrl
, rshift_u16
);
2093 SHIFT_QH(shra
, rashift16
);
2094 SHIFT_QH(shra_r
, rnd16_rashift
);
2101 #define SHIFT_W(name, func) \
2102 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
2107 temp = mipsdsp_##func(rt, sa); \
2109 return (target_long)(int32_t)temp; \
2112 #define SHIFT_W_ENV(name, func) \
2113 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
2114 CPUMIPSState *env) \
2119 temp = mipsdsp_##func(rt, sa, env); \
2121 return (target_long)(int32_t)temp; \
2124 SHIFT_W_ENV(shll_s
, sat32_lshift
);
2125 SHIFT_W(shra_r
, rnd32_rashift
);
2130 #if defined(TARGET_MIPS64)
2131 #define SHIFT_PW(name, func) \
2132 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
2134 uint32_t rt1, rt0; \
2137 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2139 rt1 = mipsdsp_##func(rt1, sa); \
2140 rt0 = mipsdsp_##func(rt0, sa); \
2142 return MIPSDSP_RETURN64_32(rt1, rt0); \
2145 #define SHIFT_PW_ENV(name, func) \
2146 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
2147 CPUMIPSState *env) \
2149 uint32_t rt1, rt0; \
2152 MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
2154 rt1 = mipsdsp_##func(rt1, sa, env); \
2155 rt0 = mipsdsp_##func(rt0, sa, env); \
2157 return MIPSDSP_RETURN64_32(rt1, rt0); \
2160 SHIFT_PW_ENV(shll
, lshift32
);
2161 SHIFT_PW_ENV(shll_s
, sat32_lshift
);
2163 SHIFT_PW(shra
, rashift32
);
2164 SHIFT_PW(shra_r
, rnd32_rashift
);
2171 #define SHIFT_PH(name, func) \
2172 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
2174 uint16_t rth, rtl; \
2178 MIPSDSP_SPLIT32_16(rt, rth, rtl); \
2180 rth = mipsdsp_##func(rth, sa); \
2181 rtl = mipsdsp_##func(rtl, sa); \
2183 return MIPSDSP_RETURN32_16(rth, rtl); \
2186 SHIFT_PH(shrl
, rshift_u16
);
2187 SHIFT_PH(shra
, rashift16
);
2188 SHIFT_PH(shra_r
, rnd16_rashift
);
2201 #undef MIPSDSP_SPLIT32_8
2202 #undef MIPSDSP_SPLIT32_16
2204 #undef MIPSDSP_RETURN32
2205 #undef MIPSDSP_RETURN32_8
2206 #undef MIPSDSP_RETURN32_16
2208 #ifdef TARGET_MIPS64
2209 #undef MIPSDSP_SPLIT64_16
2210 #undef MIPSDSP_SPLIT64_32
2211 #undef MIPSDSP_RETURN64_16
2212 #undef MIPSDSP_RETURN64_32