target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9
  10 register struct CPUMIPSState *env asm(AREG0);
  11
  12 #if defined (USE_64BITS_REGS)
  13 typedef int64_t host_int_t;
  14 typedef uint64_t host_uint_t;
  15 #else
  16 typedef int32_t host_int_t;
  17 typedef uint32_t host_uint_t;
  18 #endif
  19
  20 #if TARGET_LONG_BITS > HOST_LONG_BITS
  21 #define T0 (env->t0)
  22 #define T1 (env->t1)
  23 #define T2 (env->t2)
  24 #else
  25 register host_uint_t T0 asm(AREG1);
  26 register host_uint_t T1 asm(AREG2);
  27 register host_uint_t T2 asm(AREG3);
  28 #endif
  29
  30 #if defined (USE_HOST_FLOAT_REGS)
  31 #error "implement me."
  32 #else
  33 #define FDT0 (env->ft0.fd)
  34 #define FDT1 (env->ft1.fd)
  35 #define FDT2 (env->ft2.fd)
  36 #define FST0 (env->ft0.fs[FP_ENDIAN_IDX])
  37 #define FST1 (env->ft1.fs[FP_ENDIAN_IDX])
  38 #define FST2 (env->ft2.fs[FP_ENDIAN_IDX])
  39 #define DT0 (env->ft0.d)
  40 #define DT1 (env->ft1.d)
  41 #define DT2 (env->ft2.d)
  42 #define WT0 (env->ft0.w[FP_ENDIAN_IDX])
  43 #define WT1 (env->ft1.w[FP_ENDIAN_IDX])
  44 #define WT2 (env->ft2.w[FP_ENDIAN_IDX])
  45 #endif
  46
  47 #if defined (DEBUG_OP)
  48 # define RETURN() __asm__ __volatile__("nop" : : : "memory");
  49 #else
  50 # define RETURN() __asm__ __volatile__("" : : : "memory");
  51 #endif
  52
  53 #include "cpu.h"
  54 #include "exec-all.h"
  55
  56 #if !defined(CONFIG_USER_ONLY)
  57 #include "softmmu_exec.h"
  58 #endif /* !defined(CONFIG_USER_ONLY) */
  59
  60 static inline void env_to_regs(void)
  61 {
  62 }
  63
  64 static inline void regs_to_env(void)
  65 {
  66 }
  67
  68 #ifdef MIPS_HAS_MIPS64
  69 #if TARGET_LONG_BITS > HOST_LONG_BITS
  70 void do_dsll (void);
  71 void do_dsll32 (void);
  72 void do_dsra (void);
  73 void do_dsra32 (void);
  74 void do_dsrl (void);
  75 void do_dsrl32 (void);
  76 void do_drotr (void);
  77 void do_drotr32 (void);
  78 void do_dsllv (void);
  79 void do_dsrav (void);
  80 void do_dsrlv (void);
  81 void do_drotrv (void);
  82 #endif
  83 #endif
  84
  85 #if TARGET_LONG_BITS > HOST_LONG_BITS
  86 void do_mult (void);
  87 void do_multu (void);
  88 void do_madd (void);
  89 void do_maddu (void);
  90 void do_msub (void);
  91 void do_msubu (void);
  92 void do_ddiv (void);
  93 void do_ddivu (void);
  94 #endif
  95 #ifdef MIPS_HAS_MIPS64
  96 void do_dmult (void);
  97 void do_dmultu (void);
  98 #endif
  99 void do_mfc0_random(void);
 100 void do_mfc0_count(void);
 101 void do_mtc0_entryhi(uint32_t in);
 102 void do_mtc0_status_debug(uint32_t old, uint32_t val);
 103 void do_mtc0_status_irqraise_debug(void);
 104 void do_tlbwi (void);
 105 void do_tlbwr (void);
 106 void do_tlbp (void);
 107 void do_tlbr (void);
 108 #ifdef MIPS_USES_FPU
 109 void dump_fpu(CPUState *env);
 110 void fpu_dump_state(CPUState *env, FILE *f,
 111                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
 112                     int flags);
 113 #endif
 114 void dump_sc (void);
 115 void do_lwl_raw (uint32_t);
 116 void do_lwr_raw (uint32_t);
 117 uint32_t do_swl_raw (uint32_t);
 118 uint32_t do_swr_raw (uint32_t);
 119 #ifdef MIPS_HAS_MIPS64
 120 void do_ldl_raw (uint64_t);
 121 void do_ldr_raw (uint64_t);
 122 uint64_t do_sdl_raw (uint64_t);
 123 uint64_t do_sdr_raw (uint64_t);
 124 #endif
 125 #if !defined(CONFIG_USER_ONLY)
 126 void do_lwl_user (uint32_t);
 127 void do_lwl_kernel (uint32_t);
 128 void do_lwr_user (uint32_t);
 129 void do_lwr_kernel (uint32_t);
 130 uint32_t do_swl_user (uint32_t);
 131 uint32_t do_swl_kernel (uint32_t);
 132 uint32_t do_swr_user (uint32_t);
 133 uint32_t do_swr_kernel (uint32_t);
 134 #ifdef MIPS_HAS_MIPS64
 135 void do_ldl_user (uint64_t);
 136 void do_ldl_kernel (uint64_t);
 137 void do_ldr_user (uint64_t);
 138 void do_ldr_kernel (uint64_t);
 139 uint64_t do_sdl_user (uint64_t);
 140 uint64_t do_sdl_kernel (uint64_t);
 141 uint64_t do_sdr_user (uint64_t);
 142 uint64_t do_sdr_kernel (uint64_t);
 143 #endif
 144 #endif
 145 void do_pmon (int function);
 146
 147 void dump_sc (void);
 148
 149 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 150                                int is_user, int is_softmmu);
 151 void do_interrupt (CPUState *env);
 152 void invalidate_tlb (CPUState *env, int idx, int use_extra);
 153
 154 void cpu_loop_exit(void);
 155 void do_raise_exception_err (uint32_t exception, int error_code);
 156 void do_raise_exception (uint32_t exception);
 157 void do_raise_exception_direct (uint32_t exception);
 158
 159 void cpu_dump_state(CPUState *env, FILE *f,
 160                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
 161                     int flags);
 162 void cpu_mips_irqctrl_init (void);
 163 uint32_t cpu_mips_get_random (CPUState *env);
 164 uint32_t cpu_mips_get_count (CPUState *env);
 165 void cpu_mips_store_count (CPUState *env, uint32_t value);
 166 void cpu_mips_store_compare (CPUState *env, uint32_t value);
 167 void cpu_mips_update_irq(CPUState *env);
 168 void cpu_mips_clock_init (CPUState *env);
 169 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
 170
 171 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */