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git.proxmox.com Git - qemu.git/blob - target-mips/exec.h
1 #if !defined(__QEMU_MIPS_EXEC_H__)
2 #define __QEMU_MIPS_EXEC_H__
8 #include "dyngen-exec.h"
11 register struct CPUMIPSState
*env
asm(AREG0
);
13 #if TARGET_LONG_BITS > HOST_LONG_BITS
17 register target_ulong T0
asm(AREG1
);
18 register target_ulong T1
asm(AREG2
);
21 #if defined (USE_HOST_FLOAT_REGS)
22 #error "implement me."
24 #define FDT0 (env->fpu->ft0.fd)
25 #define FDT1 (env->fpu->ft1.fd)
26 #define FDT2 (env->fpu->ft2.fd)
27 #define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX])
28 #define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX])
29 #define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX])
30 #define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX])
31 #define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX])
32 #define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX])
33 #define DT0 (env->fpu->ft0.d)
34 #define DT1 (env->fpu->ft1.d)
35 #define DT2 (env->fpu->ft2.d)
36 #define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX])
37 #define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX])
38 #define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX])
39 #define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX])
40 #define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX])
41 #define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX])
47 #if !defined(CONFIG_USER_ONLY)
48 #include "softmmu_exec.h"
49 #endif /* !defined(CONFIG_USER_ONLY) */
51 #if TARGET_LONG_BITS > HOST_LONG_BITS
61 void do_macchi (void);
63 void do_macchiu (void);
65 void do_msachi (void);
67 void do_msachiu (void);
69 void do_mulhiu (void);
70 void do_mulshi (void);
71 void do_mulshiu (void);
74 void do_mtc0_status_debug(uint32_t old
, uint32_t val
);
75 void do_mtc0_status_irqraise_debug(void);
76 void dump_fpu(CPUState
*env
);
77 void fpu_dump_state(CPUState
*env
, FILE *f
,
78 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
81 void do_pmon (int function
);
83 int cpu_mips_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
84 int mmu_idx
, int is_softmmu
);
85 void do_interrupt (CPUState
*env
);
86 void r4k_invalidate_tlb (CPUState
*env
, int idx
, int use_extra
);
88 void cpu_loop_exit(void);
89 void do_raise_exception_err (uint32_t exception
, int error_code
);
90 void do_raise_exception (uint32_t exception
);
92 void cpu_dump_state(CPUState
*env
, FILE *f
,
93 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
95 void cpu_mips_irqctrl_init (void);
96 uint32_t cpu_mips_get_random (CPUState
*env
);
97 uint32_t cpu_mips_get_count (CPUState
*env
);
98 void cpu_mips_store_count (CPUState
*env
, uint32_t value
);
99 void cpu_mips_store_compare (CPUState
*env
, uint32_t value
);
100 void cpu_mips_start_count(CPUState
*env
);
101 void cpu_mips_stop_count(CPUState
*env
);
102 void cpu_mips_update_irq (CPUState
*env
);
103 void cpu_mips_clock_init (CPUState
*env
);
104 void cpu_mips_tlb_flush (CPUState
*env
, int flush_global
);
106 #define FOP_PROTO(op) \
107 void do_float_ ## op ## _s(void); \
108 void do_float_ ## op ## _d(void);
121 #define FOP_PROTO(op) \
122 void do_float_ ## op ## _s(void); \
123 void do_float_ ## op ## _d(void); \
124 void do_float_ ## op ## _ps(void);
135 void do_float_cvtd_s(void);
136 void do_float_cvtd_w(void);
137 void do_float_cvtd_l(void);
138 void do_float_cvtl_d(void);
139 void do_float_cvtl_s(void);
140 void do_float_cvtps_pw(void);
141 void do_float_cvtpw_ps(void);
142 void do_float_cvts_d(void);
143 void do_float_cvts_w(void);
144 void do_float_cvts_l(void);
145 void do_float_cvts_pl(void);
146 void do_float_cvts_pu(void);
147 void do_float_cvtw_s(void);
148 void do_float_cvtw_d(void);
150 void do_float_addr_ps(void);
151 void do_float_mulr_ps(void);
153 #define FOP_PROTO(op) \
154 void do_cmp_d_ ## op(long cc); \
155 void do_cmpabs_d_ ## op(long cc); \
156 void do_cmp_s_ ## op(long cc); \
157 void do_cmpabs_s_ ## op(long cc); \
158 void do_cmp_ps_ ## op(long cc); \
159 void do_cmpabs_ps_ ## op(long cc);
179 static always_inline
void env_to_regs(void)
183 static always_inline
void regs_to_env(void)
187 static always_inline
int cpu_halted(CPUState
*env
)
191 if (env
->interrupt_request
&
192 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
199 static always_inline
void compute_hflags(CPUState
*env
)
201 env
->hflags
&= ~(MIPS_HFLAG_COP1X
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
|
202 MIPS_HFLAG_F64
| MIPS_HFLAG_FPU
| MIPS_HFLAG_KSU
);
203 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
204 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
205 !(env
->hflags
& MIPS_HFLAG_DM
)) {
206 env
->hflags
|= (env
->CP0_Status
>> CP0St_KSU
) & MIPS_HFLAG_KSU
;
208 #if defined(TARGET_MIPS64)
209 if (((env
->hflags
& MIPS_HFLAG_KSU
) != MIPS_HFLAG_UM
) ||
210 (env
->CP0_Status
& (1 << CP0St_PX
)) ||
211 (env
->CP0_Status
& (1 << CP0St_UX
)))
212 env
->hflags
|= MIPS_HFLAG_64
;
214 if ((env
->CP0_Status
& (1 << CP0St_CU0
)) ||
215 !(env
->hflags
& MIPS_HFLAG_KSU
))
216 env
->hflags
|= MIPS_HFLAG_CP0
;
217 if (env
->CP0_Status
& (1 << CP0St_CU1
))
218 env
->hflags
|= MIPS_HFLAG_FPU
;
219 if (env
->CP0_Status
& (1 << CP0St_FR
))
220 env
->hflags
|= MIPS_HFLAG_F64
;
221 if (env
->insn_flags
& ISA_MIPS32R2
) {
222 if (env
->fpu
->fcr0
& (1 << FCR0_F64
))
223 env
->hflags
|= MIPS_HFLAG_COP1X
;
224 } else if (env
->insn_flags
& ISA_MIPS32
) {
225 if (env
->hflags
& MIPS_HFLAG_64
)
226 env
->hflags
|= MIPS_HFLAG_COP1X
;
227 } else if (env
->insn_flags
& ISA_MIPS4
) {
228 /* All supported MIPS IV CPUs use the XX (CU3) to enable
229 and disable the MIPS IV extensions to the MIPS III ISA.
230 Some other MIPS IV CPUs ignore the bit, so the check here
231 would be too restrictive for them. */
232 if (env
->CP0_Status
& (1 << CP0St_CU3
))
233 env
->hflags
|= MIPS_HFLAG_COP1X
;
237 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */