2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 /* no MMU emulation */
38 int no_mmu_map_address (CPUState
*env
, target_phys_addr_t
*physical
, int *prot
,
39 target_ulong address
, int rw
, int access_type
)
42 *prot
= PAGE_READ
| PAGE_WRITE
;
46 /* fixed mapping MMU emulation */
47 int fixed_mmu_map_address (CPUState
*env
, target_phys_addr_t
*physical
, int *prot
,
48 target_ulong address
, int rw
, int access_type
)
50 if (address
<= (int32_t)0x7FFFFFFFUL
) {
51 if (!(env
->CP0_Status
& (1 << CP0St_ERL
)))
52 *physical
= address
+ 0x40000000UL
;
55 } else if (address
<= (int32_t)0xBFFFFFFFUL
)
56 *physical
= address
& 0x1FFFFFFF;
60 *prot
= PAGE_READ
| PAGE_WRITE
;
64 /* MIPS32/MIPS64 R4000-style MMU emulation */
65 int r4k_map_address (CPUState
*env
, target_phys_addr_t
*physical
, int *prot
,
66 target_ulong address
, int rw
, int access_type
)
68 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
71 for (i
= 0; i
< env
->tlb
->tlb_in_use
; i
++) {
72 r4k_tlb_t
*tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
73 /* 1k pages are not supported. */
74 target_ulong mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
75 target_ulong tag
= address
& ~mask
;
76 target_ulong VPN
= tlb
->VPN
& ~mask
;
77 #if defined(TARGET_MIPS64)
81 /* Check ASID, virtual page number & size */
82 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
84 int n
= !!(address
& mask
& ~(mask
>> 1));
85 /* Check access rights */
86 if (!(n
? tlb
->V1
: tlb
->V0
))
87 return TLBRET_INVALID
;
88 if (rw
== 0 || (n
? tlb
->D1
: tlb
->D0
)) {
89 *physical
= tlb
->PFN
[n
] | (address
& (mask
>> 1));
91 if (n
? tlb
->D1
: tlb
->D0
)
98 return TLBRET_NOMATCH
;
101 #if !defined(CONFIG_USER_ONLY)
102 static int get_physical_address (CPUState
*env
, target_phys_addr_t
*physical
,
103 int *prot
, target_ulong address
,
104 int rw
, int access_type
)
106 /* User mode can only access useg/xuseg */
107 int user_mode
= (env
->hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_UM
;
108 int supervisor_mode
= (env
->hflags
& MIPS_HFLAG_MODE
) == MIPS_HFLAG_SM
;
109 int kernel_mode
= !user_mode
&& !supervisor_mode
;
110 #if defined(TARGET_MIPS64)
111 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
112 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
113 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
115 int ret
= TLBRET_MATCH
;
118 qemu_log("user mode %d h %08x\n", user_mode
, env
->hflags
);
121 if (address
<= (int32_t)0x7FFFFFFFUL
) {
123 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
124 *physical
= address
& 0xFFFFFFFF;
125 *prot
= PAGE_READ
| PAGE_WRITE
;
127 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
129 #if defined(TARGET_MIPS64)
130 } else if (address
< 0x4000000000000000ULL
) {
132 if (UX
&& address
<= (0x3FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
133 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
135 ret
= TLBRET_BADADDR
;
137 } else if (address
< 0x8000000000000000ULL
) {
139 if ((supervisor_mode
|| kernel_mode
) &&
140 SX
&& address
<= (0x7FFFFFFFFFFFFFFFULL
& env
->SEGMask
)) {
141 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
143 ret
= TLBRET_BADADDR
;
145 } else if (address
< 0xC000000000000000ULL
) {
147 if (kernel_mode
&& KX
&&
148 (address
& 0x07FFFFFFFFFFFFFFULL
) <= env
->PAMask
) {
149 *physical
= address
& env
->PAMask
;
150 *prot
= PAGE_READ
| PAGE_WRITE
;
152 ret
= TLBRET_BADADDR
;
154 } else if (address
< 0xFFFFFFFF80000000ULL
) {
156 if (kernel_mode
&& KX
&&
157 address
<= (0xFFFFFFFF7FFFFFFFULL
& env
->SEGMask
)) {
158 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
160 ret
= TLBRET_BADADDR
;
163 } else if (address
< (int32_t)0xA0000000UL
) {
166 *physical
= address
- (int32_t)0x80000000UL
;
167 *prot
= PAGE_READ
| PAGE_WRITE
;
169 ret
= TLBRET_BADADDR
;
171 } else if (address
< (int32_t)0xC0000000UL
) {
174 *physical
= address
- (int32_t)0xA0000000UL
;
175 *prot
= PAGE_READ
| PAGE_WRITE
;
177 ret
= TLBRET_BADADDR
;
179 } else if (address
< (int32_t)0xE0000000UL
) {
181 if (supervisor_mode
|| kernel_mode
) {
182 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
184 ret
= TLBRET_BADADDR
;
188 /* XXX: debug segment is not emulated */
190 ret
= env
->tlb
->map_address(env
, physical
, prot
, address
, rw
, access_type
);
192 ret
= TLBRET_BADADDR
;
196 qemu_log(TARGET_FMT_lx
" %d %d => " TARGET_FMT_lx
" %d (%d)\n",
197 address
, rw
, access_type
, *physical
, *prot
, ret
);
204 static void raise_mmu_exception(CPUState
*env
, target_ulong address
,
205 int rw
, int tlb_error
)
207 int exception
= 0, error_code
= 0;
212 /* Reference to kernel address from user mode or supervisor mode */
213 /* Reference to supervisor address from user mode */
215 exception
= EXCP_AdES
;
217 exception
= EXCP_AdEL
;
220 /* No TLB match for a mapped address */
222 exception
= EXCP_TLBS
;
224 exception
= EXCP_TLBL
;
228 /* TLB match with no valid bit */
230 exception
= EXCP_TLBS
;
232 exception
= EXCP_TLBL
;
235 /* TLB match but 'D' bit is cleared */
236 exception
= EXCP_LTLBL
;
240 /* Raise exception */
241 env
->CP0_BadVAddr
= address
;
242 env
->CP0_Context
= (env
->CP0_Context
& ~0x007fffff) |
243 ((address
>> 9) & 0x007ffff0);
245 (env
->CP0_EntryHi
& 0xFF) | (address
& (TARGET_PAGE_MASK
<< 1));
246 #if defined(TARGET_MIPS64)
247 env
->CP0_EntryHi
&= env
->SEGMask
;
248 env
->CP0_XContext
= (env
->CP0_XContext
& ((~0ULL) << (env
->SEGBITS
- 7))) |
249 ((address
& 0xC00000000000ULL
) >> (55 - env
->SEGBITS
)) |
250 ((address
& ((1ULL << env
->SEGBITS
) - 1) & 0xFFFFFFFFFFFFE000ULL
) >> 9);
252 env
->exception_index
= exception
;
253 env
->error_code
= error_code
;
256 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
)
258 #if defined(CONFIG_USER_ONLY)
261 target_phys_addr_t phys_addr
;
264 if (get_physical_address(env
, &phys_addr
, &prot
, addr
, 0, ACCESS_INT
) != 0)
270 int cpu_mips_handle_mmu_fault (CPUState
*env
, target_ulong address
, int rw
,
271 int mmu_idx
, int is_softmmu
)
273 #if !defined(CONFIG_USER_ONLY)
274 target_phys_addr_t physical
;
281 log_cpu_state(env
, 0);
283 qemu_log("%s pc " TARGET_FMT_lx
" ad " TARGET_FMT_lx
" rw %d mmu_idx %d smmu %d\n",
284 __func__
, env
->active_tc
.PC
, address
, rw
, mmu_idx
, is_softmmu
);
289 /* XXX: put correct access by using cpu_restore_state()
291 access_type
= ACCESS_INT
;
292 #if defined(CONFIG_USER_ONLY)
293 ret
= TLBRET_NOMATCH
;
295 ret
= get_physical_address(env
, &physical
, &prot
,
296 address
, rw
, access_type
);
297 qemu_log("%s address=" TARGET_FMT_lx
" ret %d physical " TARGET_FMT_plx
" prot %d\n",
298 __func__
, address
, ret
, physical
, prot
);
299 if (ret
== TLBRET_MATCH
) {
300 ret
= tlb_set_page(env
, address
& TARGET_PAGE_MASK
,
301 physical
& TARGET_PAGE_MASK
, prot
,
302 mmu_idx
, is_softmmu
);
306 raise_mmu_exception(env
, address
, rw
, ret
);
313 static const char * const excp_names
[EXCP_LAST
+ 1] = {
314 [EXCP_RESET
] = "reset",
315 [EXCP_SRESET
] = "soft reset",
316 [EXCP_DSS
] = "debug single step",
317 [EXCP_DINT
] = "debug interrupt",
318 [EXCP_NMI
] = "non-maskable interrupt",
319 [EXCP_MCHECK
] = "machine check",
320 [EXCP_EXT_INTERRUPT
] = "interrupt",
321 [EXCP_DFWATCH
] = "deferred watchpoint",
322 [EXCP_DIB
] = "debug instruction breakpoint",
323 [EXCP_IWATCH
] = "instruction fetch watchpoint",
324 [EXCP_AdEL
] = "address error load",
325 [EXCP_AdES
] = "address error store",
326 [EXCP_TLBF
] = "TLB refill",
327 [EXCP_IBE
] = "instruction bus error",
328 [EXCP_DBp
] = "debug breakpoint",
329 [EXCP_SYSCALL
] = "syscall",
330 [EXCP_BREAK
] = "break",
331 [EXCP_CpU
] = "coprocessor unusable",
332 [EXCP_RI
] = "reserved instruction",
333 [EXCP_OVERFLOW
] = "arithmetic overflow",
334 [EXCP_TRAP
] = "trap",
335 [EXCP_FPE
] = "floating point",
336 [EXCP_DDBS
] = "debug data break store",
337 [EXCP_DWATCH
] = "data watchpoint",
338 [EXCP_LTLBL
] = "TLB modify",
339 [EXCP_TLBL
] = "TLB load",
340 [EXCP_TLBS
] = "TLB store",
341 [EXCP_DBE
] = "data bus error",
342 [EXCP_DDBL
] = "debug data break load",
343 [EXCP_THREAD
] = "thread",
344 [EXCP_MDMX
] = "MDMX",
345 [EXCP_C2E
] = "precise coprocessor 2",
346 [EXCP_CACHE
] = "cache error",
349 void do_interrupt (CPUState
*env
)
351 #if !defined(CONFIG_USER_ONLY)
356 if (qemu_log_enabled() && env
->exception_index
!= EXCP_EXT_INTERRUPT
) {
357 if (env
->exception_index
< 0 || env
->exception_index
> EXCP_LAST
)
360 name
= excp_names
[env
->exception_index
];
362 qemu_log("%s enter: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" %s exception\n",
363 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, name
);
365 if (env
->exception_index
== EXCP_EXT_INTERRUPT
&&
366 (env
->hflags
& MIPS_HFLAG_DM
))
367 env
->exception_index
= EXCP_DINT
;
369 switch (env
->exception_index
) {
371 env
->CP0_Debug
|= 1 << CP0DB_DSS
;
372 /* Debug single step cannot be raised inside a delay slot and
373 resume will always occur on the next instruction
374 (but we assume the pc has always been updated during
375 code translation). */
376 env
->CP0_DEPC
= env
->active_tc
.PC
;
377 goto enter_debug_mode
;
379 env
->CP0_Debug
|= 1 << CP0DB_DINT
;
382 env
->CP0_Debug
|= 1 << CP0DB_DIB
;
385 env
->CP0_Debug
|= 1 << CP0DB_DBp
;
388 env
->CP0_Debug
|= 1 << CP0DB_DDBS
;
391 env
->CP0_Debug
|= 1 << CP0DB_DDBL
;
393 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
394 /* If the exception was raised from a delay slot,
395 come back to the jump. */
396 env
->CP0_DEPC
= env
->active_tc
.PC
- 4;
397 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
399 env
->CP0_DEPC
= env
->active_tc
.PC
;
402 env
->hflags
|= MIPS_HFLAG_DM
| MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
403 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
404 /* EJTAG probe trap enable is not implemented... */
405 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
406 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
407 env
->active_tc
.PC
= (int32_t)0xBFC00480;
413 env
->CP0_Status
|= (1 << CP0St_SR
);
414 memset(env
->CP0_WatchLo
, 0, sizeof(*env
->CP0_WatchLo
));
417 env
->CP0_Status
|= (1 << CP0St_NMI
);
419 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
420 /* If the exception was raised from a delay slot,
421 come back to the jump. */
422 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
423 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
425 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
427 env
->CP0_Status
|= (1 << CP0St_ERL
) | (1 << CP0St_BEV
);
428 env
->hflags
|= MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
429 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
430 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)))
431 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
432 env
->active_tc
.PC
= (int32_t)0xBFC00000;
434 case EXCP_EXT_INTERRUPT
:
436 if (env
->CP0_Cause
& (1 << CP0Ca_IV
))
444 if (env
->error_code
== 1 && !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
445 #if defined(TARGET_MIPS64)
446 int R
= env
->CP0_BadVAddr
>> 62;
447 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
448 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
449 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
451 if ((R
== 0 && UX
) || (R
== 1 && SX
) || (R
== 3 && KX
))
460 if (env
->error_code
== 1 && !(env
->CP0_Status
& (1 << CP0St_EXL
))) {
461 #if defined(TARGET_MIPS64)
462 int R
= env
->CP0_BadVAddr
>> 62;
463 int UX
= (env
->CP0_Status
& (1 << CP0St_UX
)) != 0;
464 int SX
= (env
->CP0_Status
& (1 << CP0St_SX
)) != 0;
465 int KX
= (env
->CP0_Status
& (1 << CP0St_KX
)) != 0;
467 if ((R
== 0 && UX
) || (R
== 1 && SX
) || (R
== 3 && KX
))
497 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x3 << CP0Ca_CE
)) |
498 (env
->error_code
<< CP0Ca_CE
);
517 /* XXX: TODO: manage defered watch exceptions */
527 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
533 if (!(env
->CP0_Status
& (1 << CP0St_EXL
))) {
534 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
535 /* If the exception was raised from a delay slot,
536 come back to the jump. */
537 env
->CP0_EPC
= env
->active_tc
.PC
- 4;
538 env
->CP0_Cause
|= (1 << CP0Ca_BD
);
540 env
->CP0_EPC
= env
->active_tc
.PC
;
541 env
->CP0_Cause
&= ~(1 << CP0Ca_BD
);
543 env
->CP0_Status
|= (1 << CP0St_EXL
);
544 env
->hflags
|= MIPS_HFLAG_64
| MIPS_HFLAG_CP0
;
545 env
->hflags
&= ~(MIPS_HFLAG_KSU
);
547 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
548 if (env
->CP0_Status
& (1 << CP0St_BEV
)) {
549 env
->active_tc
.PC
= (int32_t)0xBFC00200;
551 env
->active_tc
.PC
= (int32_t)(env
->CP0_EBase
& ~0x3ff);
553 env
->active_tc
.PC
+= offset
;
554 env
->CP0_Cause
= (env
->CP0_Cause
& ~(0x1f << CP0Ca_EC
)) | (cause
<< CP0Ca_EC
);
557 qemu_log("Invalid MIPS exception %d. Exiting\n", env
->exception_index
);
558 printf("Invalid MIPS exception %d. Exiting\n", env
->exception_index
);
561 if (qemu_log_enabled() && env
->exception_index
!= EXCP_EXT_INTERRUPT
) {
562 qemu_log("%s: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
" cause %d\n"
563 " S %08x C %08x A " TARGET_FMT_lx
" D " TARGET_FMT_lx
"\n",
564 __func__
, env
->active_tc
.PC
, env
->CP0_EPC
, cause
,
565 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_BadVAddr
,
569 env
->exception_index
= EXCP_NONE
;
572 void r4k_invalidate_tlb (CPUState
*env
, int idx
, int use_extra
)
577 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
580 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
581 /* The qemu TLB is flushed when the ASID changes, so no need to
582 flush these entries again. */
583 if (tlb
->G
== 0 && tlb
->ASID
!= ASID
) {
587 if (use_extra
&& env
->tlb
->tlb_in_use
< MIPS_TLB_MAX
) {
588 /* For tlbwr, we can shadow the discarded entry into
589 a new (fake) TLB entry, as long as the guest can not
590 tell that it's there. */
591 env
->tlb
->mmu
.r4k
.tlb
[env
->tlb
->tlb_in_use
] = *tlb
;
592 env
->tlb
->tlb_in_use
++;
596 /* 1k pages are not supported. */
597 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
599 addr
= tlb
->VPN
& ~mask
;
600 #if defined(TARGET_MIPS64)
601 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
602 addr
|= 0x3FFFFF0000000000ULL
;
605 end
= addr
| (mask
>> 1);
607 tlb_flush_page (env
, addr
);
608 addr
+= TARGET_PAGE_SIZE
;
612 addr
= (tlb
->VPN
& ~mask
) | ((mask
>> 1) + 1);
613 #if defined(TARGET_MIPS64)
614 if (addr
>= (0xFFFFFFFF80000000ULL
& env
->SEGMask
)) {
615 addr
|= 0x3FFFFF0000000000ULL
;
619 while (addr
- 1 < end
) {
620 tlb_flush_page (env
, addr
);
621 addr
+= TARGET_PAGE_SIZE
;