target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <stdarg.h>
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <string.h>
  24 #include <inttypes.h>
  25 #include <signal.h>
  26 #include <assert.h>
  27
  28 #include "cpu.h"
  29 #include "exec-all.h"
  30
  31 enum {
  32     TLBRET_DIRTY = -4,
  33     TLBRET_INVALID = -3,
  34     TLBRET_NOMATCH = -2,
  35     TLBRET_BADADDR = -1,
  36     TLBRET_MATCH = 0
  37 };
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUState *env, target_ulong *physical,
 104                                 int *prot, target_ulong address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 110     int kernel_mode = !user_mode && !supervisor_mode;
 111 #if defined(TARGET_MIPS64)
 112     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 113     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 114     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 115 #endif
 116     int ret = TLBRET_MATCH;
 117
 118 #if 0
 119     if (logfile) {
 120         fprintf(logfile, "user mode %d h %08x\n",
 121                 user_mode, env->hflags);
 122     }
 123 #endif
 124
 125     if (address <= (int32_t)0x7FFFFFFFUL) {
 126         /* useg */
 127         if (env->CP0_Status & (1 << CP0St_ERL)) {
 128             *physical = address & 0xFFFFFFFF;
 129             *prot = PAGE_READ | PAGE_WRITE;
 130         } else {
 131             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 132         }
 133 #if defined(TARGET_MIPS64)
 134     } else if (address < 0x4000000000000000ULL) {
 135         /* xuseg */
 136         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 137             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 138         } else {
 139             ret = TLBRET_BADADDR;
 140         }
 141     } else if (address < 0x8000000000000000ULL) {
 142         /* xsseg */
 143         if ((supervisor_mode || kernel_mode) &&
 144             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 145             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 146         } else {
 147             ret = TLBRET_BADADDR;
 148         }
 149     } else if (address < 0xC000000000000000ULL) {
 150         /* xkphys */
 151         /* XXX: Assumes PABITS = 36 (correct for MIPS64R1) */
 152         if (kernel_mode && KX &&
 153             (address & 0x07FFFFFFFFFFFFFFULL) <= 0x0000000FFFFFFFFFULL) {
 154             *physical = address & 0x0000000FFFFFFFFFULL;
 155             *prot = PAGE_READ | PAGE_WRITE;
 156         } else {
 157             ret = TLBRET_BADADDR;
 158         }
 159     } else if (address < 0xFFFFFFFF80000000ULL) {
 160         /* xkseg */
 161         if (kernel_mode && KX &&
 162             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 163             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 164         } else {
 165             ret = TLBRET_BADADDR;
 166         }
 167 #endif
 168     } else if (address < (int32_t)0xA0000000UL) {
 169         /* kseg0 */
 170         if (kernel_mode) {
 171             *physical = address - (int32_t)0x80000000UL;
 172             *prot = PAGE_READ | PAGE_WRITE;
 173         } else {
 174             ret = TLBRET_BADADDR;
 175         }
 176     } else if (address < (int32_t)0xC0000000UL) {
 177         /* kseg1 */
 178         if (kernel_mode) {
 179             *physical = address - (int32_t)0xA0000000UL;
 180             *prot = PAGE_READ | PAGE_WRITE;
 181         } else {
 182             ret = TLBRET_BADADDR;
 183         }
 184     } else if (address < (int32_t)0xE0000000UL) {
 185         /* sseg (kseg2) */
 186         if (supervisor_mode || kernel_mode) {
 187             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 188         } else {
 189             ret = TLBRET_BADADDR;
 190         }
 191     } else {
 192         /* kseg3 */
 193         /* XXX: debug segment is not emulated */
 194         if (kernel_mode) {
 195             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 196         } else {
 197             ret = TLBRET_BADADDR;
 198         }
 199     }
 200 #if 0
 201     if (logfile) {
 202         fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 203                 address, rw, access_type, *physical, *prot, ret);
 204     }
 205 #endif
 206
 207     return ret;
 208 }
 209
 210 #if defined(CONFIG_USER_ONLY)
 211 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 212 {
 213     return addr;
 214 }
 215 #else
 216 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 217 {
 218     target_ulong phys_addr;
 219     int prot;
 220
 221     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 222         return -1;
 223     return phys_addr;
 224 }
 225
 226 void cpu_mips_init_mmu (CPUState *env)
 227 {
 228 }
 229 #endif /* !defined(CONFIG_USER_ONLY) */
 230
 231 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 232                                int mmu_idx, int is_softmmu)
 233 {
 234     target_ulong physical;
 235     int prot;
 236     int exception = 0, error_code = 0;
 237     int access_type;
 238     int ret = 0;
 239
 240     if (logfile) {
 241 #if 0
 242         cpu_dump_state(env, logfile, fprintf, 0);
 243 #endif
 244         fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
 245                 __func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu);
 246     }
 247
 248     rw &= 1;
 249
 250     /* data access */
 251     /* XXX: put correct access by using cpu_restore_state()
 252        correctly */
 253     access_type = ACCESS_INT;
 254     if (env->user_mode_only) {
 255         /* user mode only emulation */
 256         ret = TLBRET_NOMATCH;
 257         goto do_fault;
 258     }
 259     ret = get_physical_address(env, &physical, &prot,
 260                                address, rw, access_type);
 261     if (logfile) {
 262         fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",
 263                 __func__, address, ret, physical, prot);
 264     }
 265     if (ret == TLBRET_MATCH) {
 266        ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
 267                           physical & TARGET_PAGE_MASK, prot,
 268                           mmu_idx, is_softmmu);
 269     } else if (ret < 0) {
 270     do_fault:
 271         switch (ret) {
 272         default:
 273         case TLBRET_BADADDR:
 274             /* Reference to kernel address from user mode or supervisor mode */
 275             /* Reference to supervisor address from user mode */
 276             if (rw)
 277                 exception = EXCP_AdES;
 278             else
 279                 exception = EXCP_AdEL;
 280             break;
 281         case TLBRET_NOMATCH:
 282             /* No TLB match for a mapped address */
 283             if (rw)
 284                 exception = EXCP_TLBS;
 285             else
 286                 exception = EXCP_TLBL;
 287             error_code = 1;
 288             break;
 289         case TLBRET_INVALID:
 290             /* TLB match with no valid bit */
 291             if (rw)
 292                 exception = EXCP_TLBS;
 293             else
 294                 exception = EXCP_TLBL;
 295             break;
 296         case TLBRET_DIRTY:
 297             /* TLB match but 'D' bit is cleared */
 298             exception = EXCP_LTLBL;
 299             break;
 300
 301         }
 302         /* Raise exception */
 303         env->CP0_BadVAddr = address;
 304         env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 305                            ((address >> 9) &   0x007ffff0);
 306         env->CP0_EntryHi =
 307             (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 308 #if defined(TARGET_MIPS64)
 309         env->CP0_EntryHi &= env->SEGMask;
 310         env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 311                             ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |
 312                             ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 313 #endif
 314         env->exception_index = exception;
 315         env->error_code = error_code;
 316         ret = 1;
 317     }
 318
 319     return ret;
 320 }
 321
 322 #if defined(CONFIG_USER_ONLY)
 323 void do_interrupt (CPUState *env)
 324 {
 325     env->exception_index = EXCP_NONE;
 326 }
 327 #else
 328 void do_interrupt (CPUState *env)
 329 {
 330     target_ulong offset;
 331     int cause = -1;
 332
 333     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 334         fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n",
 335                 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index);
 336     }
 337     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 338         (env->hflags & MIPS_HFLAG_DM))
 339         env->exception_index = EXCP_DINT;
 340     offset = 0x180;
 341     switch (env->exception_index) {
 342     case EXCP_DSS:
 343         env->CP0_Debug |= 1 << CP0DB_DSS;
 344         /* Debug single step cannot be raised inside a delay slot and
 345          * resume will always occur on the next instruction
 346          * (but we assume the pc has always been updated during
 347          *  code translation).
 348          */
 349         env->CP0_DEPC = env->PC[env->current_tc];
 350         goto enter_debug_mode;
 351     case EXCP_DINT:
 352         env->CP0_Debug |= 1 << CP0DB_DINT;
 353         goto set_DEPC;
 354     case EXCP_DIB:
 355         env->CP0_Debug |= 1 << CP0DB_DIB;
 356         goto set_DEPC;
 357     case EXCP_DBp:
 358         env->CP0_Debug |= 1 << CP0DB_DBp;
 359         goto set_DEPC;
 360     case EXCP_DDBS:
 361         env->CP0_Debug |= 1 << CP0DB_DDBS;
 362         goto set_DEPC;
 363     case EXCP_DDBL:
 364         env->CP0_Debug |= 1 << CP0DB_DDBL;
 365     set_DEPC:
 366         if (env->hflags & MIPS_HFLAG_BMASK) {
 367             /* If the exception was raised from a delay slot,
 368                come back to the jump.  */
 369             env->CP0_DEPC = env->PC[env->current_tc] - 4;
 370             env->hflags &= ~MIPS_HFLAG_BMASK;
 371         } else {
 372             env->CP0_DEPC = env->PC[env->current_tc];
 373         }
 374     enter_debug_mode:
 375         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 376         env->hflags &= ~(MIPS_HFLAG_KSU);
 377         /* EJTAG probe trap enable is not implemented... */
 378         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 379             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 380         env->PC[env->current_tc] = (int32_t)0xBFC00480;
 381         break;
 382     case EXCP_RESET:
 383         cpu_reset(env);
 384         break;
 385     case EXCP_SRESET:
 386         env->CP0_Status |= (1 << CP0St_SR);
 387         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 388         goto set_error_EPC;
 389     case EXCP_NMI:
 390         env->CP0_Status |= (1 << CP0St_NMI);
 391     set_error_EPC:
 392         if (env->hflags & MIPS_HFLAG_BMASK) {
 393             /* If the exception was raised from a delay slot,
 394                come back to the jump.  */
 395             env->CP0_ErrorEPC = env->PC[env->current_tc] - 4;
 396             env->hflags &= ~MIPS_HFLAG_BMASK;
 397         } else {
 398             env->CP0_ErrorEPC = env->PC[env->current_tc];
 399         }
 400         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 401         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 402         env->hflags &= ~(MIPS_HFLAG_KSU);
 403         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 404             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 405         env->PC[env->current_tc] = (int32_t)0xBFC00000;
 406         break;
 407     case EXCP_MCHECK:
 408         cause = 24;
 409         goto set_EPC;
 410     case EXCP_EXT_INTERRUPT:
 411         cause = 0;
 412         if (env->CP0_Cause & (1 << CP0Ca_IV))
 413             offset = 0x200;
 414         goto set_EPC;
 415     case EXCP_DWATCH:
 416         cause = 23;
 417         /* XXX: TODO: manage defered watch exceptions */
 418         goto set_EPC;
 419     case EXCP_AdEL:
 420         cause = 4;
 421         goto set_EPC;
 422     case EXCP_AdES:
 423         cause = 5;
 424         goto set_EPC;
 425     case EXCP_TLBL:
 426         cause = 2;
 427         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 428 #if defined(TARGET_MIPS64)
 429             int R = env->CP0_BadVAddr >> 62;
 430             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 431             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 432             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 433
 434             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 435                 offset = 0x080;
 436             else
 437 #endif
 438                 offset = 0x000;
 439         }
 440         goto set_EPC;
 441     case EXCP_IBE:
 442         cause = 6;
 443         goto set_EPC;
 444     case EXCP_DBE:
 445         cause = 7;
 446         goto set_EPC;
 447     case EXCP_SYSCALL:
 448         cause = 8;
 449         goto set_EPC;
 450     case EXCP_BREAK:
 451         cause = 9;
 452         goto set_EPC;
 453     case EXCP_RI:
 454         cause = 10;
 455         goto set_EPC;
 456     case EXCP_CpU:
 457         cause = 11;
 458         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 459                          (env->error_code << CP0Ca_CE);
 460         goto set_EPC;
 461     case EXCP_OVERFLOW:
 462         cause = 12;
 463         goto set_EPC;
 464     case EXCP_TRAP:
 465         cause = 13;
 466         goto set_EPC;
 467     case EXCP_FPE:
 468         cause = 15;
 469         goto set_EPC;
 470     case EXCP_LTLBL:
 471         cause = 1;
 472         goto set_EPC;
 473     case EXCP_TLBS:
 474         cause = 3;
 475         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 476 #if defined(TARGET_MIPS64)
 477             int R = env->CP0_BadVAddr >> 62;
 478             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 479             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 480             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 481
 482             if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
 483                 offset = 0x080;
 484             else
 485 #endif
 486                 offset = 0x000;
 487         }
 488         goto set_EPC;
 489     case EXCP_THREAD:
 490         cause = 25;
 491     set_EPC:
 492         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 493             if (env->hflags & MIPS_HFLAG_BMASK) {
 494                 /* If the exception was raised from a delay slot,
 495                    come back to the jump.  */
 496                 env->CP0_EPC = env->PC[env->current_tc] - 4;
 497                 env->CP0_Cause |= (1 << CP0Ca_BD);
 498             } else {
 499                 env->CP0_EPC = env->PC[env->current_tc];
 500                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 501             }
 502             env->CP0_Status |= (1 << CP0St_EXL);
 503             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 504             env->hflags &= ~(MIPS_HFLAG_KSU);
 505         }
 506         env->hflags &= ~MIPS_HFLAG_BMASK;
 507         if (env->CP0_Status & (1 << CP0St_BEV)) {
 508             env->PC[env->current_tc] = (int32_t)0xBFC00200;
 509         } else {
 510             env->PC[env->current_tc] = (int32_t)(env->CP0_EBase & ~0x3ff);
 511         }
 512         env->PC[env->current_tc] += offset;
 513         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 514         break;
 515     default:
 516         if (logfile) {
 517             fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
 518                     env->exception_index);
 519         }
 520         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 521         exit(1);
 522     }
 523     if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
 524         fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d excp %d\n"
 525                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 526                 __func__, env->PC[env->current_tc], env->CP0_EPC, cause, env->exception_index,
 527                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 528                 env->CP0_DEPC);
 529     }
 530     env->exception_index = EXCP_NONE;
 531 }
 532 #endif /* !defined(CONFIG_USER_ONLY) */
 533
 534 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 535 {
 536     r4k_tlb_t *tlb;
 537     target_ulong addr;
 538     target_ulong end;
 539     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 540     target_ulong mask;
 541
 542     tlb = &env->tlb->mmu.r4k.tlb[idx];
 543     /* The qemu TLB is flushed when the ASID changes, so no need to
 544        flush these entries again.  */
 545     if (tlb->G == 0 && tlb->ASID != ASID) {
 546         return;
 547     }
 548
 549     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 550         /* For tlbwr, we can shadow the discarded entry into
 551            a new (fake) TLB entry, as long as the guest can not
 552            tell that it's there.  */
 553         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 554         env->tlb->tlb_in_use++;
 555         return;
 556     }
 557
 558     /* 1k pages are not supported. */
 559     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 560     if (tlb->V0) {
 561         addr = tlb->VPN & ~mask;
 562 #if defined(TARGET_MIPS64)
 563         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 564             addr |= 0x3FFFFF0000000000ULL;
 565         }
 566 #endif
 567         end = addr | (mask >> 1);
 568         while (addr < end) {
 569             tlb_flush_page (env, addr);
 570             addr += TARGET_PAGE_SIZE;
 571         }
 572     }
 573     if (tlb->V1) {
 574         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 575 #if defined(TARGET_MIPS64)
 576         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 577             addr |= 0x3FFFFF0000000000ULL;
 578         }
 579 #endif
 580         end = addr | mask;
 581         while (addr < end) {
 582             tlb_flush_page (env, addr);
 583             addr += TARGET_PAGE_SIZE;
 584         }
 585     }
 586 }