2 * MIPS emulation micro-operations for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #define CALL_FROM_TB0(func) func();
29 #define CALL_FROM_TB1(func, arg0) func(arg0);
31 #ifndef CALL_FROM_TB1_CONST16
32 #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0);
35 #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1);
37 #ifndef CALL_FROM_TB2_CONST16
38 #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
39 CALL_FROM_TB2(func, arg0, arg1);
42 #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2);
45 #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
46 func(arg0, arg1, arg2, arg3);
50 #include "op_template.c"
53 #include "op_template.c"
56 #include "op_template.c"
59 #include "op_template.c"
62 #include "op_template.c"
65 #include "op_template.c"
68 #include "op_template.c"
71 #include "op_template.c"
74 #include "op_template.c"
77 #include "op_template.c"
80 #include "op_template.c"
83 #include "op_template.c"
86 #include "op_template.c"
89 #include "op_template.c"
92 #include "op_template.c"
95 #include "op_template.c"
98 #include "op_template.c"
101 #include "op_template.c"
104 #include "op_template.c"
107 #include "op_template.c"
110 #include "op_template.c"
113 #include "op_template.c"
116 #include "op_template.c"
119 #include "op_template.c"
122 #include "op_template.c"
125 #include "op_template.c"
128 #include "op_template.c"
131 #include "op_template.c"
134 #include "op_template.c"
137 #include "op_template.c"
140 #include "op_template.c"
144 #include "op_template.c"
149 #include "fop_template.c"
153 #include "fop_template.c"
157 #include "fop_template.c"
161 #include "fop_template.c"
165 #include "fop_template.c"
169 #include "fop_template.c"
173 #include "fop_template.c"
177 #include "fop_template.c"
181 #include "fop_template.c"
185 #include "fop_template.c"
189 #include "fop_template.c"
193 #include "fop_template.c"
197 #include "fop_template.c"
201 #include "fop_template.c"
205 #include "fop_template.c"
209 #include "fop_template.c"
213 #include "fop_template.c"
217 #include "fop_template.c"
221 #include "fop_template.c"
225 #include "fop_template.c"
229 #include "fop_template.c"
233 #include "fop_template.c"
237 #include "fop_template.c"
241 #include "fop_template.c"
245 #include "fop_template.c"
249 #include "fop_template.c"
253 #include "fop_template.c"
257 #include "fop_template.c"
261 #include "fop_template.c"
265 #include "fop_template.c"
269 #include "fop_template.c"
273 #include "fop_template.c"
277 #include "fop_template.c"
280 void op_dup_T0 (void)
286 void op_load_HI (void)
292 void op_store_HI (void)
298 void op_load_LO (void)
304 void op_store_LO (void)
311 #define MEMSUFFIX _raw
314 #if !defined(CONFIG_USER_ONLY)
315 #define MEMSUFFIX _user
319 #define MEMSUFFIX _kernel
327 T0
= (int32_t)((int32_t)T0
+ (int32_t)T1
);
336 T0
= (int32_t)T0
+ (int32_t)T1
;
337 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 31) {
338 /* operands of same sign, result different sign */
339 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_OVERFLOW
);
347 T0
= (int32_t)((int32_t)T0
- (int32_t)T1
);
356 T0
= (int32_t)T0
- (int32_t)T1
;
357 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 31) {
358 /* operands of different sign, first operand and result different sign */
359 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_OVERFLOW
);
367 T0
= (int32_t)((int32_t)T0
* (int32_t)T1
);
374 env
->LO
= (int32_t)((int32_t)T0
/ (int32_t)T1
);
375 env
->HI
= (int32_t)((int32_t)T0
% (int32_t)T1
);
383 env
->LO
= (int32_t)((uint32_t)T0
/ (uint32_t)T1
);
384 env
->HI
= (int32_t)((uint32_t)T0
% (uint32_t)T1
);
403 if (((tmp
^ T1
^ (-1)) & (T0
^ T1
)) >> 63) {
404 /* operands of same sign, result different sign */
405 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_OVERFLOW
);
421 T0
= (int64_t)T0
- (int64_t)T1
;
422 if (((tmp
^ T1
) & (tmp
^ T0
)) >> 63) {
423 /* operands of different sign, first operand and result different sign */
424 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_OVERFLOW
);
431 T0
= (int64_t)T0
* (int64_t)T1
;
435 #if TARGET_LONG_BITS > HOST_LONG_BITS
436 /* Those might call libgcc functions. */
452 env
->LO
= (int64_t)T0
/ (int64_t)T1
;
453 env
->HI
= (int64_t)T0
% (int64_t)T1
;
467 #endif /* TARGET_MIPS64 */
496 T0
= (int32_t)((uint32_t)T0
<< (uint32_t)T1
);
502 T0
= (int32_t)((int32_t)T0
>> (uint32_t)T1
);
508 T0
= (int32_t)((uint32_t)T0
>> (uint32_t)T1
);
517 tmp
= (int32_t)((uint32_t)T0
<< (0x20 - (uint32_t)T1
));
518 T0
= (int32_t)((uint32_t)T0
>> (uint32_t)T1
) | tmp
;
526 T0
= (int32_t)((uint32_t)T1
<< ((uint32_t)T0
& 0x1F));
532 T0
= (int32_t)((int32_t)T1
>> (T0
& 0x1F));
538 T0
= (int32_t)((uint32_t)T1
>> (T0
& 0x1F));
548 tmp
= (int32_t)((uint32_t)T1
<< (0x20 - T0
));
549 T0
= (int32_t)((uint32_t)T1
>> T0
) | tmp
;
559 if (T0
== ~((target_ulong
)0)) {
562 for (n
= 0; n
< 32; n
++) {
563 if (!(T0
& (1 << 31)))
579 for (n
= 0; n
< 32; n
++) {
591 #if TARGET_LONG_BITS > HOST_LONG_BITS
592 /* Those might call libgcc functions. */
595 CALL_FROM_TB0(do_dsll
);
599 void op_dsll32 (void)
601 CALL_FROM_TB0(do_dsll32
);
607 CALL_FROM_TB0(do_dsra
);
611 void op_dsra32 (void)
613 CALL_FROM_TB0(do_dsra32
);
619 CALL_FROM_TB0(do_dsrl
);
623 void op_dsrl32 (void)
625 CALL_FROM_TB0(do_dsrl32
);
631 CALL_FROM_TB0(do_drotr
);
635 void op_drotr32 (void)
637 CALL_FROM_TB0(do_drotr32
);
643 CALL_FROM_TB0(do_dsllv
);
649 CALL_FROM_TB0(do_dsrav
);
655 CALL_FROM_TB0(do_dsrlv
);
659 void op_drotrv (void)
661 CALL_FROM_TB0(do_drotrv
);
665 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
673 void op_dsll32 (void)
675 T0
= T0
<< (T1
+ 32);
681 T0
= (int64_t)T0
>> T1
;
685 void op_dsra32 (void)
687 T0
= (int64_t)T0
>> (T1
+ 32);
697 void op_dsrl32 (void)
699 T0
= T0
>> (T1
+ 32);
708 tmp
= T0
<< (0x40 - T1
);
709 T0
= (T0
>> T1
) | tmp
;
715 void op_drotr32 (void)
720 tmp
= T0
<< (0x40 - (32 + T1
));
721 T0
= (T0
>> (32 + T1
)) | tmp
;
729 T0
= T1
<< (T0
& 0x3F);
735 T0
= (int64_t)T1
>> (T0
& 0x3F);
741 T0
= T1
>> (T0
& 0x3F);
745 void op_drotrv (void)
751 tmp
= T1
<< (0x40 - T0
);
752 T0
= (T1
>> T0
) | tmp
;
757 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
763 if (T0
== ~((target_ulong
)0)) {
766 for (n
= 0; n
< 64; n
++) {
767 if (!(T0
& (1ULL << 63)))
783 for (n
= 0; n
< 64; n
++) {
784 if (T0
& (1ULL << 63))
794 /* 64 bits arithmetic */
795 #if TARGET_LONG_BITS > HOST_LONG_BITS
798 CALL_FROM_TB0(do_mult
);
804 CALL_FROM_TB0(do_multu
);
810 CALL_FROM_TB0(do_madd
);
816 CALL_FROM_TB0(do_maddu
);
822 CALL_FROM_TB0(do_msub
);
828 CALL_FROM_TB0(do_msubu
);
832 #else /* TARGET_LONG_BITS > HOST_LONG_BITS */
834 static inline uint64_t get_HILO (void)
836 return ((uint64_t)env
->HI
<< 32) | ((uint64_t)(uint32_t)env
->LO
);
839 static inline void set_HILO (uint64_t HILO
)
841 env
->LO
= (int32_t)(HILO
& 0xFFFFFFFF);
842 env
->HI
= (int32_t)(HILO
>> 32);
847 set_HILO((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
853 set_HILO((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
861 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
862 set_HILO((int64_t)get_HILO() + tmp
);
870 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
871 set_HILO(get_HILO() + tmp
);
879 tmp
= ((int64_t)(int32_t)T0
* (int64_t)(int32_t)T1
);
880 set_HILO((int64_t)get_HILO() - tmp
);
888 tmp
= ((uint64_t)(uint32_t)T0
* (uint64_t)(uint32_t)T1
);
889 set_HILO(get_HILO() - tmp
);
892 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
897 CALL_FROM_TB0(do_dmult
);
901 void op_dmultu (void)
903 CALL_FROM_TB0(do_dmultu
);
908 /* Conditional moves */
912 env
->gpr
[PARAM1
] = T0
;
919 env
->gpr
[PARAM1
] = T0
;
925 if (!(env
->fcr31
& PARAM1
))
926 env
->gpr
[PARAM2
] = env
->gpr
[PARAM3
];
932 if (env
->fcr31
& PARAM1
)
933 env
->gpr
[PARAM2
] = env
->gpr
[PARAM3
];
938 #define OP_COND(name, cond) \
939 void glue(op_, name) (void) \
949 OP_COND(eq
, T0
== T1
);
950 OP_COND(ne
, T0
!= T1
);
951 OP_COND(ge
, (int32_t)T0
>= (int32_t)T1
);
952 OP_COND(geu
, T0
>= T1
);
953 OP_COND(lt
, (int32_t)T0
< (int32_t)T1
);
954 OP_COND(ltu
, T0
< T1
);
955 OP_COND(gez
, (int32_t)T0
>= 0);
956 OP_COND(gtz
, (int32_t)T0
> 0);
957 OP_COND(lez
, (int32_t)T0
<= 0);
958 OP_COND(ltz
, (int32_t)T0
< 0);
961 //#undef USE_DIRECT_JUMP
963 void OPPROTO
op_goto_tb0(void)
965 GOTO_TB(op_goto_tb0
, PARAM1
, 0);
969 void OPPROTO
op_goto_tb1(void)
971 GOTO_TB(op_goto_tb1
, PARAM1
, 1);
975 /* Branch to register */
976 void op_save_breg_target (void)
982 void op_restore_breg_target (void)
994 void op_save_btarget (void)
996 env
->btarget
= PARAM1
;
1000 /* Conditional branch */
1001 void op_set_bcond (void)
1007 void op_save_bcond (void)
1013 void op_restore_bcond (void)
1019 void op_jnz_T2 (void)
1022 GOTO_LABEL_PARAM(1);
1027 void op_mfc0_index (void)
1029 T0
= env
->CP0_Index
;
1033 void op_mfc0_random (void)
1035 CALL_FROM_TB0(do_mfc0_random
);
1039 void op_mfc0_entrylo0 (void)
1041 T0
= (int32_t)env
->CP0_EntryLo0
;
1045 void op_mfc0_entrylo1 (void)
1047 T0
= (int32_t)env
->CP0_EntryLo1
;
1051 void op_mfc0_context (void)
1053 T0
= (int32_t)env
->CP0_Context
;
1057 void op_mfc0_pagemask (void)
1059 T0
= env
->CP0_PageMask
;
1063 void op_mfc0_pagegrain (void)
1065 T0
= env
->CP0_PageGrain
;
1069 void op_mfc0_wired (void)
1071 T0
= env
->CP0_Wired
;
1075 void op_mfc0_hwrena (void)
1077 T0
= env
->CP0_HWREna
;
1081 void op_mfc0_badvaddr (void)
1083 T0
= (int32_t)env
->CP0_BadVAddr
;
1087 void op_mfc0_count (void)
1089 CALL_FROM_TB0(do_mfc0_count
);
1093 void op_mfc0_entryhi (void)
1095 T0
= (int32_t)env
->CP0_EntryHi
;
1099 void op_mfc0_compare (void)
1101 T0
= env
->CP0_Compare
;
1105 void op_mfc0_status (void)
1107 T0
= env
->CP0_Status
;
1111 void op_mfc0_intctl (void)
1113 T0
= env
->CP0_IntCtl
;
1117 void op_mfc0_srsctl (void)
1119 T0
= env
->CP0_SRSCtl
;
1123 void op_mfc0_srsmap (void)
1125 T0
= env
->CP0_SRSMap
;
1129 void op_mfc0_cause (void)
1131 T0
= env
->CP0_Cause
;
1135 void op_mfc0_epc (void)
1137 T0
= (int32_t)env
->CP0_EPC
;
1141 void op_mfc0_prid (void)
1147 void op_mfc0_ebase (void)
1149 T0
= env
->CP0_EBase
;
1153 void op_mfc0_config0 (void)
1155 T0
= env
->CP0_Config0
;
1159 void op_mfc0_config1 (void)
1161 T0
= env
->CP0_Config1
;
1165 void op_mfc0_config2 (void)
1167 T0
= env
->CP0_Config2
;
1171 void op_mfc0_config3 (void)
1173 T0
= env
->CP0_Config3
;
1177 void op_mfc0_config6 (void)
1179 T0
= env
->CP0_Config6
;
1183 void op_mfc0_config7 (void)
1185 T0
= env
->CP0_Config7
;
1189 void op_mfc0_lladdr (void)
1191 T0
= (int32_t)env
->CP0_LLAddr
>> 4;
1195 void op_mfc0_watchlo0 (void)
1197 T0
= (int32_t)env
->CP0_WatchLo
;
1201 void op_mfc0_watchhi0 (void)
1203 T0
= env
->CP0_WatchHi
;
1207 void op_mfc0_xcontext (void)
1209 T0
= (int32_t)env
->CP0_XContext
;
1213 void op_mfc0_framemask (void)
1215 T0
= env
->CP0_Framemask
;
1219 void op_mfc0_debug (void)
1221 T0
= env
->CP0_Debug
;
1222 if (env
->hflags
& MIPS_HFLAG_DM
)
1223 T0
|= 1 << CP0DB_DM
;
1227 void op_mfc0_depc (void)
1229 T0
= (int32_t)env
->CP0_DEPC
;
1233 void op_mfc0_performance0 (void)
1235 T0
= env
->CP0_Performance0
;
1239 void op_mfc0_taglo (void)
1241 T0
= env
->CP0_TagLo
;
1245 void op_mfc0_datalo (void)
1247 T0
= env
->CP0_DataLo
;
1251 void op_mfc0_taghi (void)
1253 T0
= env
->CP0_TagHi
;
1257 void op_mfc0_datahi (void)
1259 T0
= env
->CP0_DataHi
;
1263 void op_mfc0_errorepc (void)
1265 T0
= (int32_t)env
->CP0_ErrorEPC
;
1269 void op_mfc0_desave (void)
1271 T0
= env
->CP0_DESAVE
;
1275 void op_mtc0_index (void)
1277 env
->CP0_Index
= (env
->CP0_Index
& 0x80000000) | (T0
& (MIPS_TLB_NB
- 1));
1281 void op_mtc0_entrylo0 (void)
1283 /* Large physaddr not implemented */
1284 /* 1k pages not implemented */
1285 env
->CP0_EntryLo0
= (int32_t)T0
& 0x3FFFFFFF;
1289 void op_mtc0_entrylo1 (void)
1291 /* Large physaddr not implemented */
1292 /* 1k pages not implemented */
1293 env
->CP0_EntryLo1
= (int32_t)T0
& 0x3FFFFFFF;
1297 void op_mtc0_context (void)
1299 env
->CP0_Context
= (env
->CP0_Context
& ~0x007FFFFF) | (T0
& 0x007FFFF0);
1303 void op_mtc0_pagemask (void)
1305 /* 1k pages not implemented */
1306 env
->CP0_PageMask
= T0
& 0x1FFFE000;
1310 void op_mtc0_pagegrain (void)
1312 /* SmartMIPS not implemented */
1313 /* Large physaddr not implemented */
1314 /* 1k pages not implemented */
1315 env
->CP0_PageGrain
= 0;
1319 void op_mtc0_wired (void)
1321 env
->CP0_Wired
= T0
& (MIPS_TLB_NB
- 1);
1325 void op_mtc0_hwrena (void)
1327 env
->CP0_HWREna
= T0
& 0x0000000F;
1331 void op_mtc0_count (void)
1333 CALL_FROM_TB2(cpu_mips_store_count
, env
, T0
);
1337 void op_mtc0_entryhi (void)
1339 target_ulong old
, val
;
1341 /* 1k pages not implemented */
1342 /* Ignore MIPS64 TLB for now */
1343 val
= (target_ulong
)(int32_t)T0
& ~(target_ulong
)0x1F00;
1344 old
= env
->CP0_EntryHi
;
1345 env
->CP0_EntryHi
= val
;
1346 /* If the ASID changes, flush qemu's TLB. */
1347 if ((old
& 0xFF) != (val
& 0xFF))
1348 CALL_FROM_TB2(cpu_mips_tlb_flush
, env
, 1);
1352 void op_mtc0_compare (void)
1354 CALL_FROM_TB2(cpu_mips_store_compare
, env
, T0
);
1358 void op_mtc0_status (void)
1362 /* No 64bit FPU, no reverse endianness, no MDMX/DSP, no 64bit ops,
1363 no 64bit addressing implemented. */
1364 val
= (int32_t)T0
& 0xF878FF17;
1365 old
= env
->CP0_Status
;
1366 env
->CP0_Status
= val
;
1367 if (loglevel
& CPU_LOG_TB_IN_ASM
)
1368 CALL_FROM_TB2(do_mtc0_status_debug
, old
, val
);
1369 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
1373 void op_mtc0_intctl (void)
1375 /* vectored interrupts not implemented */
1376 env
->CP0_IntCtl
= 0;
1380 void op_mtc0_srsctl (void)
1382 /* shadow registers not implemented */
1383 env
->CP0_SRSCtl
= 0;
1387 void op_mtc0_srsmap (void)
1389 /* shadow registers not implemented */
1390 env
->CP0_SRSMap
= 0;
1394 void op_mtc0_cause (void)
1396 uint32_t mask
= 0x00C00300;
1398 if ((env
->CP0_Config0
& (0x7 << CP0C0_AR
)) == (1 << CP0C0_AR
))
1399 mask
|= 1 << CP0Ca_DC
;
1401 env
->CP0_Cause
= (env
->CP0_Cause
& 0xFCC0FF7C) | (T0
& mask
);
1403 /* Handle the software interrupt as an hardware one, as they
1405 if (T0
& CP0Ca_IP_mask
) {
1406 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
1411 void op_mtc0_epc (void)
1413 env
->CP0_EPC
= (int32_t)T0
;
1417 void op_mtc0_ebase (void)
1419 /* vectored interrupts not implemented */
1420 /* Multi-CPU not implemented */
1421 env
->CP0_EBase
= 0x80000000 | (T0
& 0x3FFFF000);
1425 void op_mtc0_config0 (void)
1427 #if defined(MIPS_USES_R4K_TLB)
1428 /* Fixed mapping MMU not implemented */
1429 env
->CP0_Config0
= (env
->CP0_Config0
& 0x8017FF88) | (T0
& 0x00000001);
1431 env
->CP0_Config0
= (env
->CP0_Config0
& 0xFE17FF88) | (T0
& 0x00000001);
1436 void op_mtc0_config2 (void)
1438 /* tertiary/secondary caches not implemented */
1439 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1443 void op_mtc0_watchlo0 (void)
1445 env
->CP0_WatchLo
= (int32_t)T0
;
1449 void op_mtc0_watchhi0 (void)
1451 env
->CP0_WatchHi
= T0
& 0x40FF0FF8;
1455 void op_mtc0_xcontext (void)
1457 env
->CP0_XContext
= (int32_t)T0
; /* XXX */
1461 void op_mtc0_framemask (void)
1463 env
->CP0_Framemask
= T0
; /* XXX */
1467 void op_mtc0_debug (void)
1469 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (T0
& 0x13300120);
1470 if (T0
& (1 << CP0DB_DM
))
1471 env
->hflags
|= MIPS_HFLAG_DM
;
1473 env
->hflags
&= ~MIPS_HFLAG_DM
;
1477 void op_mtc0_depc (void)
1479 env
->CP0_DEPC
= (int32_t)T0
;
1483 void op_mtc0_performance0 (void)
1485 env
->CP0_Performance0
= T0
; /* XXX */
1489 void op_mtc0_taglo (void)
1491 env
->CP0_TagLo
= T0
& 0xFFFFFCF6;
1495 void op_mtc0_datalo (void)
1497 env
->CP0_DataLo
= T0
; /* XXX */
1501 void op_mtc0_taghi (void)
1503 env
->CP0_TagHi
= T0
; /* XXX */
1507 void op_mtc0_datahi (void)
1509 env
->CP0_DataHi
= T0
; /* XXX */
1513 void op_mtc0_errorepc (void)
1515 env
->CP0_ErrorEPC
= (int32_t)T0
;
1519 void op_mtc0_desave (void)
1521 env
->CP0_DESAVE
= T0
;
1525 void op_dmfc0_entrylo0 (void)
1527 T0
= env
->CP0_EntryLo0
;
1531 void op_dmfc0_entrylo1 (void)
1533 T0
= env
->CP0_EntryLo1
;
1537 void op_dmfc0_context (void)
1539 T0
= env
->CP0_Context
;
1543 void op_dmfc0_badvaddr (void)
1545 T0
= env
->CP0_BadVAddr
;
1549 void op_dmfc0_entryhi (void)
1551 T0
= env
->CP0_EntryHi
;
1555 void op_dmfc0_epc (void)
1561 void op_dmfc0_lladdr (void)
1563 T0
= env
->CP0_LLAddr
>> 4;
1567 void op_dmfc0_watchlo0 (void)
1569 T0
= env
->CP0_WatchLo
;
1573 void op_dmfc0_xcontext (void)
1575 T0
= env
->CP0_XContext
;
1579 void op_dmfc0_depc (void)
1585 void op_dmfc0_errorepc (void)
1587 T0
= env
->CP0_ErrorEPC
;
1591 void op_dmtc0_entrylo0 (void)
1593 /* Large physaddr not implemented */
1594 /* 1k pages not implemented */
1595 env
->CP0_EntryLo0
= T0
& 0x3FFFFFFF;
1599 void op_dmtc0_entrylo1 (void)
1601 /* Large physaddr not implemented */
1602 /* 1k pages not implemented */
1603 env
->CP0_EntryLo1
= T0
& 0x3FFFFFFF;
1607 void op_dmtc0_context (void)
1609 env
->CP0_Context
= (env
->CP0_Context
& ~0x007FFFFF) | (T0
& 0x007FFFF0);
1613 void op_dmtc0_epc (void)
1619 void op_dmtc0_watchlo0 (void)
1621 env
->CP0_WatchLo
= T0
;
1625 void op_dmtc0_xcontext (void)
1627 env
->CP0_XContext
= T0
; /* XXX */
1631 void op_dmtc0_depc (void)
1637 void op_dmtc0_errorepc (void)
1639 env
->CP0_ErrorEPC
= T0
;
1644 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
1646 # define DEBUG_FPU_STATE() do { } while(0)
1649 void op_cp0_enabled(void)
1651 if (!(env
->CP0_Status
& (1 << CP0St_CU0
)) &&
1652 (env
->hflags
& MIPS_HFLAG_UM
)) {
1653 CALL_FROM_TB2(do_raise_exception_direct_err
, EXCP_CpU
, 0);
1658 void op_cp1_enabled(void)
1660 if (!(env
->CP0_Status
& (1 << CP0St_CU1
))) {
1661 CALL_FROM_TB2(do_raise_exception_direct_err
, EXCP_CpU
, 1);
1673 /* fetch fcr31, masking unused bits */
1674 T0
= env
->fcr31
& 0x0183FFFF;
1680 /* convert MIPS rounding mode in FCR31 to IEEE library */
1681 unsigned int ieee_rm
[] = {
1682 float_round_nearest_even
,
1683 float_round_to_zero
,
1688 #define RESTORE_ROUNDING_MODE \
1689 set_float_rounding_mode(ieee_rm[env->fcr31 & 3], &env->fp_status)
1694 /* XXX should this throw an exception?
1695 * don't write to FCR0.
1700 /* store new fcr31, masking unused bits */
1701 env
->fcr31
= T0
& 0x0183FFFF;
1703 /* set rounding mode */
1704 RESTORE_ROUNDING_MODE
;
1706 #ifndef CONFIG_SOFTFLOAT
1707 /* no floating point exception for native float */
1708 SET_FP_ENABLE(env
->fcr31
, 0);
1730 Single precition routines have a "s" suffix, double precision a
1733 #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
1737 FDT2
= float32_to_float64(FST0
, &env
->fp_status
);
1743 FDT2
= int32_to_float64(WT0
, &env
->fp_status
);
1749 FST2
= float64_to_float32(FDT0
, &env
->fp_status
);
1755 FST2
= int32_to_float32(WT0
, &env
->fp_status
);
1761 WT2
= float32_to_int32(FST0
, &env
->fp_status
);
1767 WT2
= float64_to_int32(FDT0
, &env
->fp_status
);
1774 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
1775 WT2
= float64_round_to_int(FDT0
, &env
->fp_status
);
1776 RESTORE_ROUNDING_MODE
;
1783 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
1784 WT2
= float32_round_to_int(FST0
, &env
->fp_status
);
1785 RESTORE_ROUNDING_MODE
;
1792 WT2
= float64_to_int32_round_to_zero(FDT0
, &env
->fp_status
);
1798 WT2
= float32_to_int32_round_to_zero(FST0
, &env
->fp_status
);
1805 set_float_rounding_mode(float_round_up
, &env
->fp_status
);
1806 WT2
= float64_round_to_int(FDT0
, &env
->fp_status
);
1807 RESTORE_ROUNDING_MODE
;
1814 set_float_rounding_mode(float_round_up
, &env
->fp_status
);
1815 WT2
= float32_round_to_int(FST0
, &env
->fp_status
);
1816 RESTORE_ROUNDING_MODE
;
1823 set_float_rounding_mode(float_round_down
, &env
->fp_status
);
1824 WT2
= float64_round_to_int(FDT0
, &env
->fp_status
);
1825 RESTORE_ROUNDING_MODE
;
1832 set_float_rounding_mode(float_round_down
, &env
->fp_status
);
1833 WT2
= float32_round_to_int(FST0
, &env
->fp_status
);
1834 RESTORE_ROUNDING_MODE
;
1839 /* binary operations */
1840 #define FLOAT_BINOP(name) \
1843 FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status); \
1844 DEBUG_FPU_STATE(); \
1848 FST2 = float32_ ## name (FST0, FST1, &env->fp_status); \
1849 DEBUG_FPU_STATE(); \
1857 /* unary operations, modifying fp status */
1858 #define FLOAT_UNOP(name) \
1861 FDT2 = float64_ ## name(FDT0, &env->fp_status); \
1862 DEBUG_FPU_STATE(); \
1866 FST2 = float32_ ## name(FST0, &env->fp_status); \
1867 DEBUG_FPU_STATE(); \
1872 /* unary operations, not modifying fp status */
1873 #define FLOAT_UNOP(name) \
1876 FDT2 = float64_ ## name(FDT0); \
1877 DEBUG_FPU_STATE(); \
1881 FST2 = float32_ ## name(FST0); \
1882 DEBUG_FPU_STATE(); \
1901 #ifdef CONFIG_SOFTFLOAT
1902 #define clear_invalid() do { \
1903 int flags = get_float_exception_flags(&env->fp_status); \
1904 flags &= ~float_flag_invalid; \
1905 set_float_exception_flags(flags, &env->fp_status); \
1908 #define clear_invalid() do { } while(0)
1911 extern void dump_fpu_s(CPUState
*env
);
1913 #define FOP_COND(fmt, op, sig, cond) \
1914 void op_cmp_ ## fmt ## _ ## op (void) \
1917 SET_FP_COND(env->fcr31); \
1919 CLEAR_FP_COND(env->fcr31); \
1922 /*CALL_FROM_TB1(dump_fpu_s, env);*/ \
1923 DEBUG_FPU_STATE(); \
1927 int float64_is_unordered(float64 a
, float64 b STATUS_PARAM
)
1929 if (float64_is_nan(a
) || float64_is_nan(b
)) {
1930 float_raise(float_flag_invalid
, status
);
1938 FOP_COND(d
, f
, 0, 0)
1939 FOP_COND(d
, un
, 0, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
))
1940 FOP_COND(d
, eq
, 0, float64_eq(FDT0
, FDT1
, &env
->fp_status
))
1941 FOP_COND(d
, ueq
, 0, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_eq(FDT0
, FDT1
, &env
->fp_status
))
1942 FOP_COND(d
, olt
, 0, float64_lt(FDT0
, FDT1
, &env
->fp_status
))
1943 FOP_COND(d
, ult
, 0, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_lt(FDT0
, FDT1
, &env
->fp_status
))
1944 FOP_COND(d
, ole
, 0, float64_le(FDT0
, FDT1
, &env
->fp_status
))
1945 FOP_COND(d
, ule
, 0, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_le(FDT0
, FDT1
, &env
->fp_status
))
1946 /* NOTE: the comma operator will make "cond" to eval to false,
1947 * but float*_is_unordered() is still called
1949 FOP_COND(d
, sf
, 1, (float64_is_unordered(FDT0
, FDT1
, &env
->fp_status
), 0))
1950 FOP_COND(d
, ngle
,1, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
))
1951 FOP_COND(d
, seq
, 1, float64_eq(FDT0
, FDT1
, &env
->fp_status
))
1952 FOP_COND(d
, ngl
, 1, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_eq(FDT0
, FDT1
, &env
->fp_status
))
1953 FOP_COND(d
, lt
, 1, float64_lt(FDT0
, FDT1
, &env
->fp_status
))
1954 FOP_COND(d
, nge
, 1, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_lt(FDT0
, FDT1
, &env
->fp_status
))
1955 FOP_COND(d
, le
, 1, float64_le(FDT0
, FDT1
, &env
->fp_status
))
1956 FOP_COND(d
, ngt
, 1, float64_is_unordered(FDT1
, FDT0
, &env
->fp_status
) || float64_le(FDT0
, FDT1
, &env
->fp_status
))
1958 flag
float32_is_unordered(float32 a
, float32 b STATUS_PARAM
)
1960 extern flag
float32_is_nan( float32 a
);
1961 if (float32_is_nan(a
) || float32_is_nan(b
)) {
1962 float_raise(float_flag_invalid
, status
);
1970 /* NOTE: the comma operator will make "cond" to eval to false,
1971 * but float*_is_unordered() is still called
1973 FOP_COND(s
, f
, 0, 0)
1974 FOP_COND(s
, un
, 0, float32_is_unordered(FST1
, FST0
, &env
->fp_status
))
1975 FOP_COND(s
, eq
, 0, float32_eq(FST0
, FST1
, &env
->fp_status
))
1976 FOP_COND(s
, ueq
, 0, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fp_status
))
1977 FOP_COND(s
, olt
, 0, float32_lt(FST0
, FST1
, &env
->fp_status
))
1978 FOP_COND(s
, ult
, 0, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fp_status
))
1979 FOP_COND(s
, ole
, 0, float32_le(FST0
, FST1
, &env
->fp_status
))
1980 FOP_COND(s
, ule
, 0, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_le(FST0
, FST1
, &env
->fp_status
))
1981 /* NOTE: the comma operator will make "cond" to eval to false,
1982 * but float*_is_unordered() is still called
1984 FOP_COND(s
, sf
, 1, (float32_is_unordered(FST0
, FST1
, &env
->fp_status
), 0))
1985 FOP_COND(s
, ngle
,1, float32_is_unordered(FST1
, FST0
, &env
->fp_status
))
1986 FOP_COND(s
, seq
, 1, float32_eq(FST0
, FST1
, &env
->fp_status
))
1987 FOP_COND(s
, ngl
, 1, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_eq(FST0
, FST1
, &env
->fp_status
))
1988 FOP_COND(s
, lt
, 1, float32_lt(FST0
, FST1
, &env
->fp_status
))
1989 FOP_COND(s
, nge
, 1, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_lt(FST0
, FST1
, &env
->fp_status
))
1990 FOP_COND(s
, le
, 1, float32_le(FST0
, FST1
, &env
->fp_status
))
1991 FOP_COND(s
, ngt
, 1, float32_is_unordered(FST1
, FST0
, &env
->fp_status
) || float32_le(FST0
, FST1
, &env
->fp_status
))
1995 T0
= ! IS_FP_COND_SET(env
->fcr31
);
2002 T0
= IS_FP_COND_SET(env
->fcr31
);
2007 #if defined(MIPS_USES_R4K_TLB)
2008 void op_tlbwi (void)
2010 CALL_FROM_TB0(do_tlbwi
);
2014 void op_tlbwr (void)
2016 CALL_FROM_TB0(do_tlbwr
);
2022 CALL_FROM_TB0(do_tlbp
);
2028 CALL_FROM_TB0(do_tlbr
);
2034 #if defined (CONFIG_USER_ONLY)
2035 void op_tls_value (void)
2037 T0
= env
->tls_value
;
2043 CALL_FROM_TB1(do_pmon
, PARAM1
);
2049 T0
= env
->CP0_Status
;
2050 env
->CP0_Status
= T0
& ~(1 << CP0St_IE
);
2051 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2057 T0
= env
->CP0_Status
;
2058 env
->CP0_Status
= T0
| (1 << CP0St_IE
);
2059 CALL_FROM_TB1(cpu_mips_update_irq
, env
);
2066 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_TRAP
);
2071 void op_debug (void)
2073 CALL_FROM_TB1(do_raise_exception
, EXCP_DEBUG
);
2077 void op_set_lladdr (void)
2079 env
->CP0_LLAddr
= T2
;
2083 void debug_eret (void);
2086 CALL_FROM_TB0(debug_eret
);
2087 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2088 env
->PC
= env
->CP0_ErrorEPC
;
2089 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2091 env
->PC
= env
->CP0_EPC
;
2092 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2094 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
2095 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
2096 !(env
->hflags
& MIPS_HFLAG_DM
) &&
2097 (env
->CP0_Status
& (1 << CP0St_UM
)))
2098 env
->hflags
|= MIPS_HFLAG_UM
;
2099 env
->CP0_LLAddr
= 1;
2103 void op_deret (void)
2105 CALL_FROM_TB0(debug_eret
);
2106 env
->PC
= env
->CP0_DEPC
;
2107 env
->hflags
|= MIPS_HFLAG_DM
;
2108 if (!(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
2109 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
2110 !(env
->hflags
& MIPS_HFLAG_DM
) &&
2111 (env
->CP0_Status
& (1 << CP0St_UM
)))
2112 env
->hflags
|= MIPS_HFLAG_UM
;
2113 env
->CP0_LLAddr
= 1;
2117 void op_rdhwr_cpunum(void)
2119 if (env
->CP0_HWREna
& (1 << 0))
2120 T0
= env
->CP0_EBase
& 0x2ff;
2122 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_RI
);
2126 void op_rdhwr_synci_step(void)
2128 if (env
->CP0_HWREna
& (1 << 1))
2129 T0
= env
->SYNCI_Step
;
2131 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_RI
);
2135 void op_rdhwr_cc(void)
2137 if (env
->CP0_HWREna
& (1 << 2))
2138 T0
= env
->CP0_Count
;
2140 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_RI
);
2144 void op_rdhwr_ccres(void)
2146 if (env
->CP0_HWREna
& (1 << 3))
2149 CALL_FROM_TB1(do_raise_exception_direct
, EXCP_RI
);
2153 void op_save_state (void)
2155 env
->hflags
= PARAM1
;
2159 void op_save_pc (void)
2165 void op_raise_exception (void)
2167 CALL_FROM_TB1(do_raise_exception
, PARAM1
);
2171 void op_raise_exception_err (void)
2173 CALL_FROM_TB2(do_raise_exception_err
, PARAM1
, PARAM2
);
2177 void op_exit_tb (void)
2186 CALL_FROM_TB1(do_raise_exception
, EXCP_HLT
);
2190 /* Bitfield operations. */
2193 unsigned int pos
= PARAM1
;
2194 unsigned int size
= PARAM2
;
2196 T0
= ((uint32_t)T1
>> pos
) & ((1 << size
) - 1);
2202 unsigned int pos
= PARAM1
;
2203 unsigned int size
= PARAM2
;
2204 target_ulong mask
= ((1 << size
) - 1) << pos
;
2206 T0
= (T2
& ~mask
) | (((uint32_t)T1
<< pos
) & mask
);
2212 T0
= ((T1
<< 8) & ~0x00FF00FF) | ((T1
>> 8) & 0x00FF00FF);
2216 #ifdef TARGET_MIPS64
2219 unsigned int pos
= PARAM1
;
2220 unsigned int size
= PARAM2
;
2222 T0
= (T1
>> pos
) & ((1 << size
) - 1);
2228 unsigned int pos
= PARAM1
;
2229 unsigned int size
= PARAM2
;
2230 target_ulong mask
= ((1 << size
) - 1) << pos
;
2232 T0
= (T2
& ~mask
) | ((T1
<< pos
) & mask
);
2238 T0
= ((T1
<< 8) & ~0x00FF00FF00FF00FFULL
) | ((T1
>> 8) & 0x00FF00FF00FF00FFULL
);
2244 T0
= ((T1
<< 16) & ~0x0000FFFF0000FFFFULL
) | ((T1
>> 16) & 0x0000FFFF0000FFFFULL
);
2251 T0
= ((T1
& 0xFF) ^ 0x80) - 0x80;
2257 T0
= ((T1
& 0xFFFF) ^ 0x8000) - 0x8000;