target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "host-utils.h"
  22
  23 #include "helper.h"
  24
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "softmmu_exec.h"
  27 #endif /* !defined(CONFIG_USER_ONLY) */
  28
  29 #ifndef CONFIG_USER_ONLY
  30 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  31 #endif
  32
  33 /*****************************************************************************/
  34 /* Exceptions processing helpers */
  35
  36 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  37                                                         uint32_t exception,
  38                                                         int error_code,
  39                                                         uintptr_t pc)
  40 {
  41     TranslationBlock *tb;
  42 #if 1
  43     if (exception < 0x100)
  44         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  45 #endif
  46     env->exception_index = exception;
  47     env->error_code = error_code;
  48
  49     if (pc) {
  50         /* now we have a real cpu fault */
  51         tb = tb_find_pc(pc);
  52         if (tb) {
  53             /* the PC is inside the translated code. It means that we have
  54                a virtual CPU fault */
  55             cpu_restore_state(tb, env, pc);
  56         }
  57     }
  58
  59     cpu_loop_exit(env);
  60 }
  61
  62 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  63                                                     uint32_t exception,
  64                                                     uintptr_t pc)
  65 {
  66     do_raise_exception_err(env, exception, 0, pc);
  67 }
  68
  69 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  70                                 int error_code)
  71 {
  72     do_raise_exception_err(env, exception, error_code, 0);
  73 }
  74
  75 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  76 {
  77     do_raise_exception(env, exception, 0);
  78 }
  79
  80 #if defined(CONFIG_USER_ONLY)
  81 #define HELPER_LD(name, insn, type)                                     \
  82 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  83                              int mem_idx)                               \
  84 {                                                                       \
  85     return (type) insn##_raw(addr);                                     \
  86 }
  87 #else
  88 #define HELPER_LD(name, insn, type)                                     \
  89 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  90                              int mem_idx)                               \
  91 {                                                                       \
  92     switch (mem_idx)                                                    \
  93     {                                                                   \
  94     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  95     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  96     default:                                                            \
  97     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  98     }                                                                   \
  99 }
 100 #endif
 101 HELPER_LD(lbu, ldub, uint8_t)
 102 HELPER_LD(lw, ldl, int32_t)
 103 #ifdef TARGET_MIPS64
 104 HELPER_LD(ld, ldq, int64_t)
 105 #endif
 106 #undef HELPER_LD
 107
 108 #if defined(CONFIG_USER_ONLY)
 109 #define HELPER_ST(name, insn, type)                                     \
 110 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 111                              type val, int mem_idx)                     \
 112 {                                                                       \
 113     insn##_raw(addr, val);                                              \
 114 }
 115 #else
 116 #define HELPER_ST(name, insn, type)                                     \
 117 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 118                              type val, int mem_idx)                     \
 119 {                                                                       \
 120     switch (mem_idx)                                                    \
 121     {                                                                   \
 122     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 123     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 124     default:                                                            \
 125     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 126     }                                                                   \
 127 }
 128 #endif
 129 HELPER_ST(sb, stb, uint8_t)
 130 HELPER_ST(sw, stl, uint32_t)
 131 #ifdef TARGET_MIPS64
 132 HELPER_ST(sd, stq, uint64_t)
 133 #endif
 134 #undef HELPER_ST
 135
 136 target_ulong helper_clo (target_ulong arg1)
 137 {
 138     return clo32(arg1);
 139 }
 140
 141 target_ulong helper_clz (target_ulong arg1)
 142 {
 143     return clz32(arg1);
 144 }
 145
 146 #if defined(TARGET_MIPS64)
 147 target_ulong helper_dclo (target_ulong arg1)
 148 {
 149     return clo64(arg1);
 150 }
 151
 152 target_ulong helper_dclz (target_ulong arg1)
 153 {
 154     return clz64(arg1);
 155 }
 156 #endif /* TARGET_MIPS64 */
 157
 158 /* 64 bits arithmetic for 32 bits hosts */
 159 static inline uint64_t get_HILO(CPUMIPSState *env)
 160 {
 161     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 162 }
 163
 164 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 165 {
 166     target_ulong tmp;
 167     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 168     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 169     return tmp;
 170 }
 171
 172 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 173 {
 174     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 175     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 176     return tmp;
 177 }
 178
 179 /* Multiplication variants of the vr54xx. */
 180 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 181                          target_ulong arg2)
 182 {
 183     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 184                                  (int64_t)(int32_t)arg2));
 185 }
 186
 187 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 188                           target_ulong arg2)
 189 {
 190     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 191                        (uint64_t)(uint32_t)arg2);
 192 }
 193
 194 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 195                          target_ulong arg2)
 196 {
 197     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 198                        (int64_t)(int32_t)arg2);
 199 }
 200
 201 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 202                            target_ulong arg2)
 203 {
 204     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 205                        (int64_t)(int32_t)arg2);
 206 }
 207
 208 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 209                           target_ulong arg2)
 210 {
 211     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 212                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 213 }
 214
 215 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 216                             target_ulong arg2)
 217 {
 218     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 219                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 220 }
 221
 222 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 223                          target_ulong arg2)
 224 {
 225     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 226                        (int64_t)(int32_t)arg2);
 227 }
 228
 229 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 230                            target_ulong arg2)
 231 {
 232     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 233                        (int64_t)(int32_t)arg2);
 234 }
 235
 236 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 237                           target_ulong arg2)
 238 {
 239     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 240                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 241 }
 242
 243 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 244                             target_ulong arg2)
 245 {
 246     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 247                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 248 }
 249
 250 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 251                           target_ulong arg2)
 252 {
 253     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 254 }
 255
 256 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 257                            target_ulong arg2)
 258 {
 259     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 260                        (uint64_t)(uint32_t)arg2);
 261 }
 262
 263 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 264                            target_ulong arg2)
 265 {
 266     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 267                        (int64_t)(int32_t)arg2);
 268 }
 269
 270 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 271                             target_ulong arg2)
 272 {
 273     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 274                        (uint64_t)(uint32_t)arg2);
 275 }
 276
 277 #ifdef TARGET_MIPS64
 278 void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 279 {
 280     muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 281 }
 282
 283 void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
 284 {
 285     mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
 286 }
 287 #endif
 288
 289 #ifndef CONFIG_USER_ONLY
 290
 291 static inline hwaddr do_translate_address(CPUMIPSState *env,
 292                                                       target_ulong address,
 293                                                       int rw)
 294 {
 295     hwaddr lladdr;
 296
 297     lladdr = cpu_mips_translate_address(env, address, rw);
 298
 299     if (lladdr == -1LL) {
 300         cpu_loop_exit(env);
 301     } else {
 302         return lladdr;
 303     }
 304 }
 305
 306 #define HELPER_LD_ATOMIC(name, insn)                                          \
 307 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 308 {                                                                             \
 309     env->lladdr = do_translate_address(env, arg, 0);                          \
 310     env->llval = do_##insn(env, arg, mem_idx);                                \
 311     return env->llval;                                                        \
 312 }
 313 HELPER_LD_ATOMIC(ll, lw)
 314 #ifdef TARGET_MIPS64
 315 HELPER_LD_ATOMIC(lld, ld)
 316 #endif
 317 #undef HELPER_LD_ATOMIC
 318
 319 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 320 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 321                            target_ulong arg2, int mem_idx)                    \
 322 {                                                                             \
 323     target_long tmp;                                                          \
 324                                                                               \
 325     if (arg2 & almask) {                                                      \
 326         env->CP0_BadVAddr = arg2;                                             \
 327         helper_raise_exception(env, EXCP_AdES);                               \
 328     }                                                                         \
 329     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 330         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 331         if (tmp == env->llval) {                                              \
 332             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 333             return 1;                                                         \
 334         }                                                                     \
 335     }                                                                         \
 336     return 0;                                                                 \
 337 }
 338 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 339 #ifdef TARGET_MIPS64
 340 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 341 #endif
 342 #undef HELPER_ST_ATOMIC
 343 #endif
 344
 345 #ifdef TARGET_WORDS_BIGENDIAN
 346 #define GET_LMASK(v) ((v) & 3)
 347 #define GET_OFFSET(addr, offset) (addr + (offset))
 348 #else
 349 #define GET_LMASK(v) (((v) & 3) ^ 3)
 350 #define GET_OFFSET(addr, offset) (addr - (offset))
 351 #endif
 352
 353 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 354                 int mem_idx)
 355 {
 356     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 357
 358     if (GET_LMASK(arg2) <= 2)
 359         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 360
 361     if (GET_LMASK(arg2) <= 1)
 362         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 363
 364     if (GET_LMASK(arg2) == 0)
 365         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 366 }
 367
 368 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 369                 int mem_idx)
 370 {
 371     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 372
 373     if (GET_LMASK(arg2) >= 1)
 374         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 375
 376     if (GET_LMASK(arg2) >= 2)
 377         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 378
 379     if (GET_LMASK(arg2) == 3)
 380         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 381 }
 382
 383 #if defined(TARGET_MIPS64)
 384 /* "half" load and stores.  We must do the memory access inline,
 385    or fault handling won't work.  */
 386
 387 #ifdef TARGET_WORDS_BIGENDIAN
 388 #define GET_LMASK64(v) ((v) & 7)
 389 #else
 390 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 391 #endif
 392
 393 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 394                 int mem_idx)
 395 {
 396     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 397
 398     if (GET_LMASK64(arg2) <= 6)
 399         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 400
 401     if (GET_LMASK64(arg2) <= 5)
 402         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 403
 404     if (GET_LMASK64(arg2) <= 4)
 405         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 406
 407     if (GET_LMASK64(arg2) <= 3)
 408         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 409
 410     if (GET_LMASK64(arg2) <= 2)
 411         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 412
 413     if (GET_LMASK64(arg2) <= 1)
 414         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 415
 416     if (GET_LMASK64(arg2) <= 0)
 417         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 418 }
 419
 420 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 421                 int mem_idx)
 422 {
 423     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 424
 425     if (GET_LMASK64(arg2) >= 1)
 426         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 427
 428     if (GET_LMASK64(arg2) >= 2)
 429         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 430
 431     if (GET_LMASK64(arg2) >= 3)
 432         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 433
 434     if (GET_LMASK64(arg2) >= 4)
 435         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 436
 437     if (GET_LMASK64(arg2) >= 5)
 438         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 439
 440     if (GET_LMASK64(arg2) >= 6)
 441         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 442
 443     if (GET_LMASK64(arg2) == 7)
 444         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 445 }
 446 #endif /* TARGET_MIPS64 */
 447
 448 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 449
 450 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 451                 uint32_t mem_idx)
 452 {
 453     target_ulong base_reglist = reglist & 0xf;
 454     target_ulong do_r31 = reglist & 0x10;
 455
 456     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 457         target_ulong i;
 458
 459         for (i = 0; i < base_reglist; i++) {
 460             env->active_tc.gpr[multiple_regs[i]] =
 461                 (target_long)do_lw(env, addr, mem_idx);
 462             addr += 4;
 463         }
 464     }
 465
 466     if (do_r31) {
 467         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 468     }
 469 }
 470
 471 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 472                 uint32_t mem_idx)
 473 {
 474     target_ulong base_reglist = reglist & 0xf;
 475     target_ulong do_r31 = reglist & 0x10;
 476
 477     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 478         target_ulong i;
 479
 480         for (i = 0; i < base_reglist; i++) {
 481             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 482             addr += 4;
 483         }
 484     }
 485
 486     if (do_r31) {
 487         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 488     }
 489 }
 490
 491 #if defined(TARGET_MIPS64)
 492 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 493                 uint32_t mem_idx)
 494 {
 495     target_ulong base_reglist = reglist & 0xf;
 496     target_ulong do_r31 = reglist & 0x10;
 497
 498     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 499         target_ulong i;
 500
 501         for (i = 0; i < base_reglist; i++) {
 502             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 503             addr += 8;
 504         }
 505     }
 506
 507     if (do_r31) {
 508         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 509     }
 510 }
 511
 512 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 513                 uint32_t mem_idx)
 514 {
 515     target_ulong base_reglist = reglist & 0xf;
 516     target_ulong do_r31 = reglist & 0x10;
 517
 518     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 519         target_ulong i;
 520
 521         for (i = 0; i < base_reglist; i++) {
 522             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 523             addr += 8;
 524         }
 525     }
 526
 527     if (do_r31) {
 528         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 529     }
 530 }
 531 #endif
 532
 533 #ifndef CONFIG_USER_ONLY
 534 /* SMP helpers.  */
 535 static bool mips_vpe_is_wfi(MIPSCPU *c)
 536 {
 537     CPUMIPSState *env = &c->env;
 538
 539     /* If the VPE is halted but otherwise active, it means it's waiting for
 540        an interrupt.  */
 541     return env->halted && mips_vpe_active(env);
 542 }
 543
 544 static inline void mips_vpe_wake(CPUMIPSState *c)
 545 {
 546     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 547        because there might be other conditions that state that c should
 548        be sleeping.  */
 549     cpu_interrupt(c, CPU_INTERRUPT_WAKE);
 550 }
 551
 552 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 553 {
 554     CPUMIPSState *c = &cpu->env;
 555
 556     /* The VPE was shut off, really go to bed.
 557        Reset any old _WAKE requests.  */
 558     c->halted = 1;
 559     cpu_reset_interrupt(c, CPU_INTERRUPT_WAKE);
 560 }
 561
 562 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 563 {
 564     CPUMIPSState *c = &cpu->env;
 565
 566     /* FIXME: TC reschedule.  */
 567     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 568         mips_vpe_wake(c);
 569     }
 570 }
 571
 572 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 573 {
 574     CPUMIPSState *c = &cpu->env;
 575
 576     /* FIXME: TC reschedule.  */
 577     if (!mips_vpe_active(c)) {
 578         mips_vpe_sleep(cpu);
 579     }
 580 }
 581
 582 /* tc should point to an int with the value of the global TC index.
 583    This function will transform it into a local index within the
 584    returned CPUMIPSState.
 585
 586    FIXME: This code assumes that all VPEs have the same number of TCs,
 587           which depends on runtime setup. Can probably be fixed by
 588           walking the list of CPUMIPSStates.  */
 589 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 590 {
 591     CPUMIPSState *other;
 592     int vpe_idx, nr_threads = env->nr_threads;
 593     int tc_idx = *tc;
 594
 595     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 596         /* Not allowed to address other CPUs.  */
 597         *tc = env->current_tc;
 598         return env;
 599     }
 600
 601     vpe_idx = tc_idx / nr_threads;
 602     *tc = tc_idx % nr_threads;
 603     other = qemu_get_cpu(vpe_idx);
 604     return other ? other : env;
 605 }
 606
 607 /* The per VPE CP0_Status register shares some fields with the per TC
 608    CP0_TCStatus registers. These fields are wired to the same registers,
 609    so changes to either of them should be reflected on both registers.
 610
 611    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 612
 613    These helper call synchronizes the regs for a given cpu.  */
 614
 615 /* Called for updates to CP0_Status.  */
 616 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 617 {
 618     int32_t tcstatus, *tcst;
 619     uint32_t v = cpu->CP0_Status;
 620     uint32_t cu, mx, asid, ksu;
 621     uint32_t mask = ((1 << CP0TCSt_TCU3)
 622                        | (1 << CP0TCSt_TCU2)
 623                        | (1 << CP0TCSt_TCU1)
 624                        | (1 << CP0TCSt_TCU0)
 625                        | (1 << CP0TCSt_TMX)
 626                        | (3 << CP0TCSt_TKSU)
 627                        | (0xff << CP0TCSt_TASID));
 628
 629     cu = (v >> CP0St_CU0) & 0xf;
 630     mx = (v >> CP0St_MX) & 0x1;
 631     ksu = (v >> CP0St_KSU) & 0x3;
 632     asid = env->CP0_EntryHi & 0xff;
 633
 634     tcstatus = cu << CP0TCSt_TCU0;
 635     tcstatus |= mx << CP0TCSt_TMX;
 636     tcstatus |= ksu << CP0TCSt_TKSU;
 637     tcstatus |= asid;
 638
 639     if (tc == cpu->current_tc) {
 640         tcst = &cpu->active_tc.CP0_TCStatus;
 641     } else {
 642         tcst = &cpu->tcs[tc].CP0_TCStatus;
 643     }
 644
 645     *tcst &= ~mask;
 646     *tcst |= tcstatus;
 647     compute_hflags(cpu);
 648 }
 649
 650 /* Called for updates to CP0_TCStatus.  */
 651 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 652                              target_ulong v)
 653 {
 654     uint32_t status;
 655     uint32_t tcu, tmx, tasid, tksu;
 656     uint32_t mask = ((1 << CP0St_CU3)
 657                        | (1 << CP0St_CU2)
 658                        | (1 << CP0St_CU1)
 659                        | (1 << CP0St_CU0)
 660                        | (1 << CP0St_MX)
 661                        | (3 << CP0St_KSU));
 662
 663     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 664     tmx = (v >> CP0TCSt_TMX) & 0x1;
 665     tasid = v & 0xff;
 666     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 667
 668     status = tcu << CP0St_CU0;
 669     status |= tmx << CP0St_MX;
 670     status |= tksu << CP0St_KSU;
 671
 672     cpu->CP0_Status &= ~mask;
 673     cpu->CP0_Status |= status;
 674
 675     /* Sync the TASID with EntryHi.  */
 676     cpu->CP0_EntryHi &= ~0xff;
 677     cpu->CP0_EntryHi = tasid;
 678
 679     compute_hflags(cpu);
 680 }
 681
 682 /* Called for updates to CP0_EntryHi.  */
 683 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 684 {
 685     int32_t *tcst;
 686     uint32_t asid, v = cpu->CP0_EntryHi;
 687
 688     asid = v & 0xff;
 689
 690     if (tc == cpu->current_tc) {
 691         tcst = &cpu->active_tc.CP0_TCStatus;
 692     } else {
 693         tcst = &cpu->tcs[tc].CP0_TCStatus;
 694     }
 695
 696     *tcst &= ~0xff;
 697     *tcst |= asid;
 698 }
 699
 700 /* CP0 helpers */
 701 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 702 {
 703     return env->mvp->CP0_MVPControl;
 704 }
 705
 706 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 707 {
 708     return env->mvp->CP0_MVPConf0;
 709 }
 710
 711 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 712 {
 713     return env->mvp->CP0_MVPConf1;
 714 }
 715
 716 target_ulong helper_mfc0_random(CPUMIPSState *env)
 717 {
 718     return (int32_t)cpu_mips_get_random(env);
 719 }
 720
 721 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 722 {
 723     return env->active_tc.CP0_TCStatus;
 724 }
 725
 726 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 727 {
 728     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 729     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 730
 731     if (other_tc == other->current_tc)
 732         return other->active_tc.CP0_TCStatus;
 733     else
 734         return other->tcs[other_tc].CP0_TCStatus;
 735 }
 736
 737 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 738 {
 739     return env->active_tc.CP0_TCBind;
 740 }
 741
 742 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 743 {
 744     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 745     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 746
 747     if (other_tc == other->current_tc)
 748         return other->active_tc.CP0_TCBind;
 749     else
 750         return other->tcs[other_tc].CP0_TCBind;
 751 }
 752
 753 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 754 {
 755     return env->active_tc.PC;
 756 }
 757
 758 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 759 {
 760     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 761     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 762
 763     if (other_tc == other->current_tc)
 764         return other->active_tc.PC;
 765     else
 766         return other->tcs[other_tc].PC;
 767 }
 768
 769 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 770 {
 771     return env->active_tc.CP0_TCHalt;
 772 }
 773
 774 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 775 {
 776     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 777     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 778
 779     if (other_tc == other->current_tc)
 780         return other->active_tc.CP0_TCHalt;
 781     else
 782         return other->tcs[other_tc].CP0_TCHalt;
 783 }
 784
 785 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 786 {
 787     return env->active_tc.CP0_TCContext;
 788 }
 789
 790 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 791 {
 792     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 793     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 794
 795     if (other_tc == other->current_tc)
 796         return other->active_tc.CP0_TCContext;
 797     else
 798         return other->tcs[other_tc].CP0_TCContext;
 799 }
 800
 801 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 802 {
 803     return env->active_tc.CP0_TCSchedule;
 804 }
 805
 806 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 807 {
 808     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 809     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 810
 811     if (other_tc == other->current_tc)
 812         return other->active_tc.CP0_TCSchedule;
 813     else
 814         return other->tcs[other_tc].CP0_TCSchedule;
 815 }
 816
 817 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 818 {
 819     return env->active_tc.CP0_TCScheFBack;
 820 }
 821
 822 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 823 {
 824     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 825     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 826
 827     if (other_tc == other->current_tc)
 828         return other->active_tc.CP0_TCScheFBack;
 829     else
 830         return other->tcs[other_tc].CP0_TCScheFBack;
 831 }
 832
 833 target_ulong helper_mfc0_count(CPUMIPSState *env)
 834 {
 835     return (int32_t)cpu_mips_get_count(env);
 836 }
 837
 838 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 839 {
 840     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 841     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 842
 843     return other->CP0_EntryHi;
 844 }
 845
 846 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 847 {
 848     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 849     int32_t tccause;
 850     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 851
 852     if (other_tc == other->current_tc) {
 853         tccause = other->CP0_Cause;
 854     } else {
 855         tccause = other->CP0_Cause;
 856     }
 857
 858     return tccause;
 859 }
 860
 861 target_ulong helper_mftc0_status(CPUMIPSState *env)
 862 {
 863     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 864     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 865
 866     return other->CP0_Status;
 867 }
 868
 869 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 870 {
 871     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 872 }
 873
 874 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 875 {
 876     return (int32_t)env->CP0_WatchLo[sel];
 877 }
 878
 879 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 880 {
 881     return env->CP0_WatchHi[sel];
 882 }
 883
 884 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 885 {
 886     target_ulong t0 = env->CP0_Debug;
 887     if (env->hflags & MIPS_HFLAG_DM)
 888         t0 |= 1 << CP0DB_DM;
 889
 890     return t0;
 891 }
 892
 893 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 894 {
 895     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 896     int32_t tcstatus;
 897     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 898
 899     if (other_tc == other->current_tc)
 900         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 901     else
 902         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 903
 904     /* XXX: Might be wrong, check with EJTAG spec. */
 905     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 906             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 907 }
 908
 909 #if defined(TARGET_MIPS64)
 910 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 911 {
 912     return env->active_tc.PC;
 913 }
 914
 915 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 916 {
 917     return env->active_tc.CP0_TCHalt;
 918 }
 919
 920 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 921 {
 922     return env->active_tc.CP0_TCContext;
 923 }
 924
 925 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 926 {
 927     return env->active_tc.CP0_TCSchedule;
 928 }
 929
 930 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 931 {
 932     return env->active_tc.CP0_TCScheFBack;
 933 }
 934
 935 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 936 {
 937     return env->lladdr >> env->CP0_LLAddr_shift;
 938 }
 939
 940 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 941 {
 942     return env->CP0_WatchLo[sel];
 943 }
 944 #endif /* TARGET_MIPS64 */
 945
 946 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 947 {
 948     int num = 1;
 949     unsigned int tmp = env->tlb->nb_tlb;
 950
 951     do {
 952         tmp >>= 1;
 953         num <<= 1;
 954     } while (tmp);
 955     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 956 }
 957
 958 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 959 {
 960     uint32_t mask = 0;
 961     uint32_t newval;
 962
 963     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 964         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 965                 (1 << CP0MVPCo_EVP);
 966     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 967         mask |= (1 << CP0MVPCo_STLB);
 968     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 969
 970     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 971
 972     env->mvp->CP0_MVPControl = newval;
 973 }
 974
 975 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 976 {
 977     uint32_t mask;
 978     uint32_t newval;
 979
 980     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 981            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 982     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 983
 984     /* Yield scheduler intercept not implemented. */
 985     /* Gating storage scheduler intercept not implemented. */
 986
 987     // TODO: Enable/disable TCs.
 988
 989     env->CP0_VPEControl = newval;
 990 }
 991
 992 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 993 {
 994     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 995     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 996     uint32_t mask;
 997     uint32_t newval;
 998
 999     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1000            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1001     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1002
1003     /* TODO: Enable/disable TCs.  */
1004
1005     other->CP0_VPEControl = newval;
1006 }
1007
1008 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1009 {
1010     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1011     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1012     /* FIXME: Mask away return zero on read bits.  */
1013     return other->CP0_VPEControl;
1014 }
1015
1016 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1017 {
1018     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1019     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1020
1021     return other->CP0_VPEConf0;
1022 }
1023
1024 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1025 {
1026     uint32_t mask = 0;
1027     uint32_t newval;
1028
1029     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1030         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1031             mask |= (0xff << CP0VPEC0_XTC);
1032         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1033     }
1034     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1035
1036     // TODO: TC exclusive handling due to ERL/EXL.
1037
1038     env->CP0_VPEConf0 = newval;
1039 }
1040
1041 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1042 {
1043     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1044     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1045     uint32_t mask = 0;
1046     uint32_t newval;
1047
1048     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1049     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1050
1051     /* TODO: TC exclusive handling due to ERL/EXL.  */
1052     other->CP0_VPEConf0 = newval;
1053 }
1054
1055 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1056 {
1057     uint32_t mask = 0;
1058     uint32_t newval;
1059
1060     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1061         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1062                 (0xff << CP0VPEC1_NCP1);
1063     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1064
1065     /* UDI not implemented. */
1066     /* CP2 not implemented. */
1067
1068     // TODO: Handle FPU (CP1) binding.
1069
1070     env->CP0_VPEConf1 = newval;
1071 }
1072
1073 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1074 {
1075     /* Yield qualifier inputs not implemented. */
1076     env->CP0_YQMask = 0x00000000;
1077 }
1078
1079 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1080 {
1081     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1082 }
1083
1084 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1085 {
1086     /* Large physaddr (PABITS) not implemented */
1087     /* 1k pages not implemented */
1088     env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1089 }
1090
1091 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1092 {
1093     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1094     uint32_t newval;
1095
1096     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1097
1098     env->active_tc.CP0_TCStatus = newval;
1099     sync_c0_tcstatus(env, env->current_tc, newval);
1100 }
1101
1102 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1103 {
1104     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1105     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1106
1107     if (other_tc == other->current_tc)
1108         other->active_tc.CP0_TCStatus = arg1;
1109     else
1110         other->tcs[other_tc].CP0_TCStatus = arg1;
1111     sync_c0_tcstatus(other, other_tc, arg1);
1112 }
1113
1114 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1115 {
1116     uint32_t mask = (1 << CP0TCBd_TBE);
1117     uint32_t newval;
1118
1119     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1120         mask |= (1 << CP0TCBd_CurVPE);
1121     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1122     env->active_tc.CP0_TCBind = newval;
1123 }
1124
1125 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1126 {
1127     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1128     uint32_t mask = (1 << CP0TCBd_TBE);
1129     uint32_t newval;
1130     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1131
1132     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1133         mask |= (1 << CP0TCBd_CurVPE);
1134     if (other_tc == other->current_tc) {
1135         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1136         other->active_tc.CP0_TCBind = newval;
1137     } else {
1138         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1139         other->tcs[other_tc].CP0_TCBind = newval;
1140     }
1141 }
1142
1143 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1144 {
1145     env->active_tc.PC = arg1;
1146     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1147     env->lladdr = 0ULL;
1148     /* MIPS16 not implemented. */
1149 }
1150
1151 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1152 {
1153     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1154     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1155
1156     if (other_tc == other->current_tc) {
1157         other->active_tc.PC = arg1;
1158         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1159         other->lladdr = 0ULL;
1160         /* MIPS16 not implemented. */
1161     } else {
1162         other->tcs[other_tc].PC = arg1;
1163         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1164         other->lladdr = 0ULL;
1165         /* MIPS16 not implemented. */
1166     }
1167 }
1168
1169 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1170 {
1171     MIPSCPU *cpu = mips_env_get_cpu(env);
1172
1173     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1174
1175     // TODO: Halt TC / Restart (if allocated+active) TC.
1176     if (env->active_tc.CP0_TCHalt & 1) {
1177         mips_tc_sleep(cpu, env->current_tc);
1178     } else {
1179         mips_tc_wake(cpu, env->current_tc);
1180     }
1181 }
1182
1183 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1184 {
1185     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1186     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1187     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1188
1189     // TODO: Halt TC / Restart (if allocated+active) TC.
1190
1191     if (other_tc == other->current_tc)
1192         other->active_tc.CP0_TCHalt = arg1;
1193     else
1194         other->tcs[other_tc].CP0_TCHalt = arg1;
1195
1196     if (arg1 & 1) {
1197         mips_tc_sleep(other_cpu, other_tc);
1198     } else {
1199         mips_tc_wake(other_cpu, other_tc);
1200     }
1201 }
1202
1203 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1204 {
1205     env->active_tc.CP0_TCContext = arg1;
1206 }
1207
1208 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1209 {
1210     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1211     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1212
1213     if (other_tc == other->current_tc)
1214         other->active_tc.CP0_TCContext = arg1;
1215     else
1216         other->tcs[other_tc].CP0_TCContext = arg1;
1217 }
1218
1219 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1220 {
1221     env->active_tc.CP0_TCSchedule = arg1;
1222 }
1223
1224 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1225 {
1226     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1227     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1228
1229     if (other_tc == other->current_tc)
1230         other->active_tc.CP0_TCSchedule = arg1;
1231     else
1232         other->tcs[other_tc].CP0_TCSchedule = arg1;
1233 }
1234
1235 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1236 {
1237     env->active_tc.CP0_TCScheFBack = arg1;
1238 }
1239
1240 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1241 {
1242     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1243     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1244
1245     if (other_tc == other->current_tc)
1246         other->active_tc.CP0_TCScheFBack = arg1;
1247     else
1248         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1249 }
1250
1251 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1252 {
1253     /* Large physaddr (PABITS) not implemented */
1254     /* 1k pages not implemented */
1255     env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1256 }
1257
1258 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1259 {
1260     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1261 }
1262
1263 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1264 {
1265     /* 1k pages not implemented */
1266     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1267 }
1268
1269 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1270 {
1271     /* SmartMIPS not implemented */
1272     /* Large physaddr (PABITS) not implemented */
1273     /* 1k pages not implemented */
1274     env->CP0_PageGrain = 0;
1275 }
1276
1277 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1278 {
1279     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1280 }
1281
1282 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1283 {
1284     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1285 }
1286
1287 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1288 {
1289     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1290 }
1291
1292 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1293 {
1294     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1295 }
1296
1297 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1298 {
1299     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1300 }
1301
1302 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1303 {
1304     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1305 }
1306
1307 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1308 {
1309     env->CP0_HWREna = arg1 & 0x0000000F;
1310 }
1311
1312 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1313 {
1314     cpu_mips_store_count(env, arg1);
1315 }
1316
1317 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1318 {
1319     target_ulong old, val;
1320
1321     /* 1k pages not implemented */
1322     val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1323 #if defined(TARGET_MIPS64)
1324     val &= env->SEGMask;
1325 #endif
1326     old = env->CP0_EntryHi;
1327     env->CP0_EntryHi = val;
1328     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1329         sync_c0_entryhi(env, env->current_tc);
1330     }
1331     /* If the ASID changes, flush qemu's TLB.  */
1332     if ((old & 0xFF) != (val & 0xFF))
1333         cpu_mips_tlb_flush(env, 1);
1334 }
1335
1336 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1337 {
1338     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1339     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1340
1341     other->CP0_EntryHi = arg1;
1342     sync_c0_entryhi(other, other_tc);
1343 }
1344
1345 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1346 {
1347     cpu_mips_store_compare(env, arg1);
1348 }
1349
1350 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1351 {
1352     uint32_t val, old;
1353     uint32_t mask = env->CP0_Status_rw_bitmask;
1354
1355     val = arg1 & mask;
1356     old = env->CP0_Status;
1357     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1358     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1359         sync_c0_status(env, env, env->current_tc);
1360     } else {
1361         compute_hflags(env);
1362     }
1363
1364     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1365         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1366                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1367                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1368                 env->CP0_Cause);
1369         switch (env->hflags & MIPS_HFLAG_KSU) {
1370         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1371         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1372         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1373         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1374         }
1375     }
1376 }
1377
1378 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1379 {
1380     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1381     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1382
1383     other->CP0_Status = arg1 & ~0xf1000018;
1384     sync_c0_status(env, other, other_tc);
1385 }
1386
1387 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1388 {
1389     /* vectored interrupts not implemented, no performance counters. */
1390     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1391 }
1392
1393 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1394 {
1395     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1396     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1397 }
1398
1399 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1400 {
1401     uint32_t mask = 0x00C00300;
1402     uint32_t old = cpu->CP0_Cause;
1403     int i;
1404
1405     if (cpu->insn_flags & ISA_MIPS32R2) {
1406         mask |= 1 << CP0Ca_DC;
1407     }
1408
1409     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1410
1411     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1412         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1413             cpu_mips_stop_count(cpu);
1414         } else {
1415             cpu_mips_start_count(cpu);
1416         }
1417     }
1418
1419     /* Set/reset software interrupts */
1420     for (i = 0 ; i < 2 ; i++) {
1421         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1422             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1423         }
1424     }
1425 }
1426
1427 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1428 {
1429     mtc0_cause(env, arg1);
1430 }
1431
1432 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1433 {
1434     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1435     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1436
1437     mtc0_cause(other, arg1);
1438 }
1439
1440 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1441 {
1442     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1443     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1444
1445     return other->CP0_EPC;
1446 }
1447
1448 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1449 {
1450     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1451     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1452
1453     return other->CP0_EBase;
1454 }
1455
1456 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1457 {
1458     /* vectored interrupts not implemented */
1459     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1460 }
1461
1462 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1463 {
1464     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1465     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1466     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1467 }
1468
1469 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1470 {
1471     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1472     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1473
1474     switch (idx) {
1475     case 0: return other->CP0_Config0;
1476     case 1: return other->CP0_Config1;
1477     case 2: return other->CP0_Config2;
1478     case 3: return other->CP0_Config3;
1479     /* 4 and 5 are reserved.  */
1480     case 6: return other->CP0_Config6;
1481     case 7: return other->CP0_Config7;
1482     default:
1483         break;
1484     }
1485     return 0;
1486 }
1487
1488 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1489 {
1490     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1491 }
1492
1493 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1494 {
1495     /* tertiary/secondary caches not implemented */
1496     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1497 }
1498
1499 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1500 {
1501     target_long mask = env->CP0_LLAddr_rw_bitmask;
1502     arg1 = arg1 << env->CP0_LLAddr_shift;
1503     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1504 }
1505
1506 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1507 {
1508     /* Watch exceptions for instructions, data loads, data stores
1509        not implemented. */
1510     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1511 }
1512
1513 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1514 {
1515     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1516     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1517 }
1518
1519 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1520 {
1521     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1522     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1523 }
1524
1525 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1526 {
1527     env->CP0_Framemask = arg1; /* XXX */
1528 }
1529
1530 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1531 {
1532     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1533     if (arg1 & (1 << CP0DB_DM))
1534         env->hflags |= MIPS_HFLAG_DM;
1535     else
1536         env->hflags &= ~MIPS_HFLAG_DM;
1537 }
1538
1539 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1540 {
1541     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1542     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1543     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1544
1545     /* XXX: Might be wrong, check with EJTAG spec. */
1546     if (other_tc == other->current_tc)
1547         other->active_tc.CP0_Debug_tcstatus = val;
1548     else
1549         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1550     other->CP0_Debug = (other->CP0_Debug &
1551                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1552                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1553 }
1554
1555 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1556 {
1557     env->CP0_Performance0 = arg1 & 0x000007ff;
1558 }
1559
1560 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1561 {
1562     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1563 }
1564
1565 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1566 {
1567     env->CP0_DataLo = arg1; /* XXX */
1568 }
1569
1570 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1571 {
1572     env->CP0_TagHi = arg1; /* XXX */
1573 }
1574
1575 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1576 {
1577     env->CP0_DataHi = arg1; /* XXX */
1578 }
1579
1580 /* MIPS MT functions */
1581 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1582 {
1583     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1584     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1585
1586     if (other_tc == other->current_tc)
1587         return other->active_tc.gpr[sel];
1588     else
1589         return other->tcs[other_tc].gpr[sel];
1590 }
1591
1592 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1593 {
1594     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1595     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1596
1597     if (other_tc == other->current_tc)
1598         return other->active_tc.LO[sel];
1599     else
1600         return other->tcs[other_tc].LO[sel];
1601 }
1602
1603 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1604 {
1605     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1606     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1607
1608     if (other_tc == other->current_tc)
1609         return other->active_tc.HI[sel];
1610     else
1611         return other->tcs[other_tc].HI[sel];
1612 }
1613
1614 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1615 {
1616     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1617     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1618
1619     if (other_tc == other->current_tc)
1620         return other->active_tc.ACX[sel];
1621     else
1622         return other->tcs[other_tc].ACX[sel];
1623 }
1624
1625 target_ulong helper_mftdsp(CPUMIPSState *env)
1626 {
1627     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1628     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1629
1630     if (other_tc == other->current_tc)
1631         return other->active_tc.DSPControl;
1632     else
1633         return other->tcs[other_tc].DSPControl;
1634 }
1635
1636 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1637 {
1638     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1639     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1640
1641     if (other_tc == other->current_tc)
1642         other->active_tc.gpr[sel] = arg1;
1643     else
1644         other->tcs[other_tc].gpr[sel] = arg1;
1645 }
1646
1647 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1648 {
1649     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1650     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1651
1652     if (other_tc == other->current_tc)
1653         other->active_tc.LO[sel] = arg1;
1654     else
1655         other->tcs[other_tc].LO[sel] = arg1;
1656 }
1657
1658 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1659 {
1660     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1661     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1662
1663     if (other_tc == other->current_tc)
1664         other->active_tc.HI[sel] = arg1;
1665     else
1666         other->tcs[other_tc].HI[sel] = arg1;
1667 }
1668
1669 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1670 {
1671     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1672     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1673
1674     if (other_tc == other->current_tc)
1675         other->active_tc.ACX[sel] = arg1;
1676     else
1677         other->tcs[other_tc].ACX[sel] = arg1;
1678 }
1679
1680 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1681 {
1682     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1683     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1684
1685     if (other_tc == other->current_tc)
1686         other->active_tc.DSPControl = arg1;
1687     else
1688         other->tcs[other_tc].DSPControl = arg1;
1689 }
1690
1691 /* MIPS MT functions */
1692 target_ulong helper_dmt(void)
1693 {
1694     // TODO
1695      return 0;
1696 }
1697
1698 target_ulong helper_emt(void)
1699 {
1700     // TODO
1701     return 0;
1702 }
1703
1704 target_ulong helper_dvpe(CPUMIPSState *env)
1705 {
1706     CPUMIPSState *other_cpu_env = first_cpu;
1707     target_ulong prev = env->mvp->CP0_MVPControl;
1708
1709     do {
1710         /* Turn off all VPEs except the one executing the dvpe.  */
1711         if (other_cpu_env != env) {
1712             MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1713
1714             other_cpu_env->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1715             mips_vpe_sleep(other_cpu);
1716         }
1717         other_cpu_env = other_cpu_env->next_cpu;
1718     } while (other_cpu_env);
1719     return prev;
1720 }
1721
1722 target_ulong helper_evpe(CPUMIPSState *env)
1723 {
1724     CPUMIPSState *other_cpu_env = first_cpu;
1725     target_ulong prev = env->mvp->CP0_MVPControl;
1726
1727     do {
1728         MIPSCPU *other_cpu = mips_env_get_cpu(other_cpu_env);
1729
1730         if (other_cpu_env != env
1731             /* If the VPE is WFI, don't disturb its sleep.  */
1732             && !mips_vpe_is_wfi(other_cpu)) {
1733             /* Enable the VPE.  */
1734             other_cpu_env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1735             mips_vpe_wake(other_cpu_env); /* And wake it up.  */
1736         }
1737         other_cpu_env = other_cpu_env->next_cpu;
1738     } while (other_cpu_env);
1739     return prev;
1740 }
1741 #endif /* !CONFIG_USER_ONLY */
1742
1743 void helper_fork(target_ulong arg1, target_ulong arg2)
1744 {
1745     // arg1 = rt, arg2 = rs
1746     arg1 = 0;
1747     // TODO: store to TC register
1748 }
1749
1750 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1751 {
1752     target_long arg1 = arg;
1753
1754     if (arg1 < 0) {
1755         /* No scheduling policy implemented. */
1756         if (arg1 != -2) {
1757             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1758                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1759                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1760                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1761                 helper_raise_exception(env, EXCP_THREAD);
1762             }
1763         }
1764     } else if (arg1 == 0) {
1765         if (0 /* TODO: TC underflow */) {
1766             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1767             helper_raise_exception(env, EXCP_THREAD);
1768         } else {
1769             // TODO: Deallocate TC
1770         }
1771     } else if (arg1 > 0) {
1772         /* Yield qualifier inputs not implemented. */
1773         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1774         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1775         helper_raise_exception(env, EXCP_THREAD);
1776     }
1777     return env->CP0_YQMask;
1778 }
1779
1780 #ifndef CONFIG_USER_ONLY
1781 /* TLB management */
1782 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1783 {
1784     /* Flush qemu's TLB and discard all shadowed entries.  */
1785     tlb_flush (env, flush_global);
1786     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1787 }
1788
1789 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1790 {
1791     /* Discard entries from env->tlb[first] onwards.  */
1792     while (env->tlb->tlb_in_use > first) {
1793         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1794     }
1795 }
1796
1797 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1798 {
1799     r4k_tlb_t *tlb;
1800
1801     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1802     tlb = &env->tlb->mmu.r4k.tlb[idx];
1803     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1804 #if defined(TARGET_MIPS64)
1805     tlb->VPN &= env->SEGMask;
1806 #endif
1807     tlb->ASID = env->CP0_EntryHi & 0xFF;
1808     tlb->PageMask = env->CP0_PageMask;
1809     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1810     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1811     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1812     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1813     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1814     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1815     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1816     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1817     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1818 }
1819
1820 void r4k_helper_tlbwi(CPUMIPSState *env)
1821 {
1822     r4k_tlb_t *tlb;
1823     int idx;
1824     target_ulong VPN;
1825     uint8_t ASID;
1826     bool G, V0, D0, V1, D1;
1827
1828     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1829     tlb = &env->tlb->mmu.r4k.tlb[idx];
1830     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1831 #if defined(TARGET_MIPS64)
1832     VPN &= env->SEGMask;
1833 #endif
1834     ASID = env->CP0_EntryHi & 0xff;
1835     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1836     V0 = (env->CP0_EntryLo0 & 2) != 0;
1837     D0 = (env->CP0_EntryLo0 & 4) != 0;
1838     V1 = (env->CP0_EntryLo1 & 2) != 0;
1839     D1 = (env->CP0_EntryLo1 & 4) != 0;
1840
1841     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1842        permissions on the current entry. */
1843     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1844         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1845         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1846         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1847     }
1848
1849     r4k_invalidate_tlb(env, idx, 0);
1850     r4k_fill_tlb(env, idx);
1851 }
1852
1853 void r4k_helper_tlbwr(CPUMIPSState *env)
1854 {
1855     int r = cpu_mips_get_random(env);
1856
1857     r4k_invalidate_tlb(env, r, 1);
1858     r4k_fill_tlb(env, r);
1859 }
1860
1861 void r4k_helper_tlbp(CPUMIPSState *env)
1862 {
1863     r4k_tlb_t *tlb;
1864     target_ulong mask;
1865     target_ulong tag;
1866     target_ulong VPN;
1867     uint8_t ASID;
1868     int i;
1869
1870     ASID = env->CP0_EntryHi & 0xFF;
1871     for (i = 0; i < env->tlb->nb_tlb; i++) {
1872         tlb = &env->tlb->mmu.r4k.tlb[i];
1873         /* 1k pages are not supported. */
1874         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1875         tag = env->CP0_EntryHi & ~mask;
1876         VPN = tlb->VPN & ~mask;
1877 #if defined(TARGET_MIPS64)
1878         tag &= env->SEGMask;
1879 #endif
1880         /* Check ASID, virtual page number & size */
1881         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1882             /* TLB match */
1883             env->CP0_Index = i;
1884             break;
1885         }
1886     }
1887     if (i == env->tlb->nb_tlb) {
1888         /* No match.  Discard any shadow entries, if any of them match.  */
1889         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1890             tlb = &env->tlb->mmu.r4k.tlb[i];
1891             /* 1k pages are not supported. */
1892             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1893             tag = env->CP0_EntryHi & ~mask;
1894             VPN = tlb->VPN & ~mask;
1895 #if defined(TARGET_MIPS64)
1896             tag &= env->SEGMask;
1897 #endif
1898             /* Check ASID, virtual page number & size */
1899             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1900                 r4k_mips_tlb_flush_extra (env, i);
1901                 break;
1902             }
1903         }
1904
1905         env->CP0_Index |= 0x80000000;
1906     }
1907 }
1908
1909 void r4k_helper_tlbr(CPUMIPSState *env)
1910 {
1911     r4k_tlb_t *tlb;
1912     uint8_t ASID;
1913     int idx;
1914
1915     ASID = env->CP0_EntryHi & 0xFF;
1916     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1917     tlb = &env->tlb->mmu.r4k.tlb[idx];
1918
1919     /* If this will change the current ASID, flush qemu's TLB.  */
1920     if (ASID != tlb->ASID)
1921         cpu_mips_tlb_flush (env, 1);
1922
1923     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1924
1925     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1926     env->CP0_PageMask = tlb->PageMask;
1927     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1928                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1929     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1930                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1931 }
1932
1933 void helper_tlbwi(CPUMIPSState *env)
1934 {
1935     env->tlb->helper_tlbwi(env);
1936 }
1937
1938 void helper_tlbwr(CPUMIPSState *env)
1939 {
1940     env->tlb->helper_tlbwr(env);
1941 }
1942
1943 void helper_tlbp(CPUMIPSState *env)
1944 {
1945     env->tlb->helper_tlbp(env);
1946 }
1947
1948 void helper_tlbr(CPUMIPSState *env)
1949 {
1950     env->tlb->helper_tlbr(env);
1951 }
1952
1953 /* Specials */
1954 target_ulong helper_di(CPUMIPSState *env)
1955 {
1956     target_ulong t0 = env->CP0_Status;
1957
1958     env->CP0_Status = t0 & ~(1 << CP0St_IE);
1959     return t0;
1960 }
1961
1962 target_ulong helper_ei(CPUMIPSState *env)
1963 {
1964     target_ulong t0 = env->CP0_Status;
1965
1966     env->CP0_Status = t0 | (1 << CP0St_IE);
1967     return t0;
1968 }
1969
1970 static void debug_pre_eret(CPUMIPSState *env)
1971 {
1972     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1973         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1974                 env->active_tc.PC, env->CP0_EPC);
1975         if (env->CP0_Status & (1 << CP0St_ERL))
1976             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1977         if (env->hflags & MIPS_HFLAG_DM)
1978             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1979         qemu_log("\n");
1980     }
1981 }
1982
1983 static void debug_post_eret(CPUMIPSState *env)
1984 {
1985     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1986         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1987                 env->active_tc.PC, env->CP0_EPC);
1988         if (env->CP0_Status & (1 << CP0St_ERL))
1989             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1990         if (env->hflags & MIPS_HFLAG_DM)
1991             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1992         switch (env->hflags & MIPS_HFLAG_KSU) {
1993         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1994         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1995         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1996         default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1997         }
1998     }
1999 }
2000
2001 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2002 {
2003     env->active_tc.PC = error_pc & ~(target_ulong)1;
2004     if (error_pc & 1) {
2005         env->hflags |= MIPS_HFLAG_M16;
2006     } else {
2007         env->hflags &= ~(MIPS_HFLAG_M16);
2008     }
2009 }
2010
2011 void helper_eret(CPUMIPSState *env)
2012 {
2013     debug_pre_eret(env);
2014     if (env->CP0_Status & (1 << CP0St_ERL)) {
2015         set_pc(env, env->CP0_ErrorEPC);
2016         env->CP0_Status &= ~(1 << CP0St_ERL);
2017     } else {
2018         set_pc(env, env->CP0_EPC);
2019         env->CP0_Status &= ~(1 << CP0St_EXL);
2020     }
2021     compute_hflags(env);
2022     debug_post_eret(env);
2023     env->lladdr = 1;
2024 }
2025
2026 void helper_deret(CPUMIPSState *env)
2027 {
2028     debug_pre_eret(env);
2029     set_pc(env, env->CP0_DEPC);
2030
2031     env->hflags &= MIPS_HFLAG_DM;
2032     compute_hflags(env);
2033     debug_post_eret(env);
2034     env->lladdr = 1;
2035 }
2036 #endif /* !CONFIG_USER_ONLY */
2037
2038 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2039 {
2040     if ((env->hflags & MIPS_HFLAG_CP0) ||
2041         (env->CP0_HWREna & (1 << 0)))
2042         return env->CP0_EBase & 0x3ff;
2043     else
2044         helper_raise_exception(env, EXCP_RI);
2045
2046     return 0;
2047 }
2048
2049 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2050 {
2051     if ((env->hflags & MIPS_HFLAG_CP0) ||
2052         (env->CP0_HWREna & (1 << 1)))
2053         return env->SYNCI_Step;
2054     else
2055         helper_raise_exception(env, EXCP_RI);
2056
2057     return 0;
2058 }
2059
2060 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2061 {
2062     if ((env->hflags & MIPS_HFLAG_CP0) ||
2063         (env->CP0_HWREna & (1 << 2)))
2064         return env->CP0_Count;
2065     else
2066         helper_raise_exception(env, EXCP_RI);
2067
2068     return 0;
2069 }
2070
2071 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2072 {
2073     if ((env->hflags & MIPS_HFLAG_CP0) ||
2074         (env->CP0_HWREna & (1 << 3)))
2075         return env->CCRes;
2076     else
2077         helper_raise_exception(env, EXCP_RI);
2078
2079     return 0;
2080 }
2081
2082 void helper_pmon(CPUMIPSState *env, int function)
2083 {
2084     function /= 2;
2085     switch (function) {
2086     case 2: /* TODO: char inbyte(int waitflag); */
2087         if (env->active_tc.gpr[4] == 0)
2088             env->active_tc.gpr[2] = -1;
2089         /* Fall through */
2090     case 11: /* TODO: char inbyte (void); */
2091         env->active_tc.gpr[2] = -1;
2092         break;
2093     case 3:
2094     case 12:
2095         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2096         break;
2097     case 17:
2098         break;
2099     case 158:
2100         {
2101             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2102             printf("%s", fmt);
2103         }
2104         break;
2105     }
2106 }
2107
2108 void helper_wait(CPUMIPSState *env)
2109 {
2110     env->halted = 1;
2111     cpu_reset_interrupt(env, CPU_INTERRUPT_WAKE);
2112     helper_raise_exception(env, EXCP_HLT);
2113 }
2114
2115 #if !defined(CONFIG_USER_ONLY)
2116
2117 static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
2118                                               target_ulong addr, int is_write,
2119                                               int is_user, uintptr_t retaddr);
2120
2121 #define MMUSUFFIX _mmu
2122 #define ALIGNED_ONLY
2123
2124 #define SHIFT 0
2125 #include "softmmu_template.h"
2126
2127 #define SHIFT 1
2128 #include "softmmu_template.h"
2129
2130 #define SHIFT 2
2131 #include "softmmu_template.h"
2132
2133 #define SHIFT 3
2134 #include "softmmu_template.h"
2135
2136 static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
2137                                 int is_write, int is_user, uintptr_t retaddr)
2138 {
2139     env->CP0_BadVAddr = addr;
2140     do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2141 }
2142
2143 void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
2144               uintptr_t retaddr)
2145 {
2146     int ret;
2147
2148     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
2149     if (ret) {
2150         do_raise_exception_err(env, env->exception_index,
2151                                env->error_code, retaddr);
2152     }
2153 }
2154
2155 void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr,
2156                            int is_write, int is_exec, int unused, int size)
2157 {
2158     if (is_exec)
2159         helper_raise_exception(env, EXCP_IBE);
2160     else
2161         helper_raise_exception(env, EXCP_DBE);
2162 }
2163 #endif /* !CONFIG_USER_ONLY */
2164
2165 /* Complex FPU operations which may need stack space. */
2166
2167 #define FLOAT_TWO32 make_float32(1 << 30)
2168 #define FLOAT_TWO64 make_float64(1ULL << 62)
2169 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2170 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2171
2172 /* convert MIPS rounding mode in FCR31 to IEEE library */
2173 static unsigned int ieee_rm[] = {
2174     float_round_nearest_even,
2175     float_round_to_zero,
2176     float_round_up,
2177     float_round_down
2178 };
2179
2180 #define RESTORE_ROUNDING_MODE \
2181     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
2182
2183 #define RESTORE_FLUSH_MODE \
2184     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0, &env->active_fpu.fp_status);
2185
2186 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2187 {
2188     target_ulong arg1;
2189
2190     switch (reg) {
2191     case 0:
2192         arg1 = (int32_t)env->active_fpu.fcr0;
2193         break;
2194     case 25:
2195         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2196         break;
2197     case 26:
2198         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2199         break;
2200     case 28:
2201         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2202         break;
2203     default:
2204         arg1 = (int32_t)env->active_fpu.fcr31;
2205         break;
2206     }
2207
2208     return arg1;
2209 }
2210
2211 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg)
2212 {
2213     switch(reg) {
2214     case 25:
2215         if (arg1 & 0xffffff00)
2216             return;
2217         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2218                      ((arg1 & 0x1) << 23);
2219         break;
2220     case 26:
2221         if (arg1 & 0x007c0000)
2222             return;
2223         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2224         break;
2225     case 28:
2226         if (arg1 & 0x007c0000)
2227             return;
2228         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2229                      ((arg1 & 0x4) << 22);
2230         break;
2231     case 31:
2232         if (arg1 & 0x007c0000)
2233             return;
2234         env->active_fpu.fcr31 = arg1;
2235         break;
2236     default:
2237         return;
2238     }
2239     /* set rounding mode */
2240     RESTORE_ROUNDING_MODE;
2241     /* set flush-to-zero mode */
2242     RESTORE_FLUSH_MODE;
2243     set_float_exception_flags(0, &env->active_fpu.fp_status);
2244     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2245         do_raise_exception(env, EXCP_FPE, GETPC());
2246 }
2247
2248 static inline int ieee_ex_to_mips(int xcpt)
2249 {
2250     int ret = 0;
2251     if (xcpt) {
2252         if (xcpt & float_flag_invalid) {
2253             ret |= FP_INVALID;
2254         }
2255         if (xcpt & float_flag_overflow) {
2256             ret |= FP_OVERFLOW;
2257         }
2258         if (xcpt & float_flag_underflow) {
2259             ret |= FP_UNDERFLOW;
2260         }
2261         if (xcpt & float_flag_divbyzero) {
2262             ret |= FP_DIV0;
2263         }
2264         if (xcpt & float_flag_inexact) {
2265             ret |= FP_INEXACT;
2266         }
2267     }
2268     return ret;
2269 }
2270
2271 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2272 {
2273     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2274
2275     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2276
2277     if (tmp) {
2278         set_float_exception_flags(0, &env->active_fpu.fp_status);
2279
2280         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2281             do_raise_exception(env, EXCP_FPE, pc);
2282         } else {
2283             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2284         }
2285     }
2286 }
2287
2288 /* Float support.
2289    Single precition routines have a "s" suffix, double precision a
2290    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2291    paired single lower "pl", paired single upper "pu".  */
2292
2293 /* unary operations, modifying fp status  */
2294 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2295 {
2296     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2297     update_fcr31(env, GETPC());
2298     return fdt0;
2299 }
2300
2301 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2302 {
2303     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2304     update_fcr31(env, GETPC());
2305     return fst0;
2306 }
2307
2308 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2309 {
2310     uint64_t fdt2;
2311
2312     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2313     update_fcr31(env, GETPC());
2314     return fdt2;
2315 }
2316
2317 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2318 {
2319     uint64_t fdt2;
2320
2321     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2322     update_fcr31(env, GETPC());
2323     return fdt2;
2324 }
2325
2326 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2327 {
2328     uint64_t fdt2;
2329
2330     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2331     update_fcr31(env, GETPC());
2332     return fdt2;
2333 }
2334
2335 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2336 {
2337     uint64_t dt2;
2338
2339     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2340     if (get_float_exception_flags(&env->active_fpu.fp_status)
2341         & (float_flag_invalid | float_flag_overflow)) {
2342         dt2 = FP_TO_INT64_OVERFLOW;
2343     }
2344     update_fcr31(env, GETPC());
2345     return dt2;
2346 }
2347
2348 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2349 {
2350     uint64_t dt2;
2351
2352     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2353     if (get_float_exception_flags(&env->active_fpu.fp_status)
2354         & (float_flag_invalid | float_flag_overflow)) {
2355         dt2 = FP_TO_INT64_OVERFLOW;
2356     }
2357     update_fcr31(env, GETPC());
2358     return dt2;
2359 }
2360
2361 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2362 {
2363     uint32_t fst2;
2364     uint32_t fsth2;
2365
2366     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2367     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2368     update_fcr31(env, GETPC());
2369     return ((uint64_t)fsth2 << 32) | fst2;
2370 }
2371
2372 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2373 {
2374     uint32_t wt2;
2375     uint32_t wth2;
2376     int excp, excph;
2377
2378     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2379     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2380     if (excp & (float_flag_overflow | float_flag_invalid)) {
2381         wt2 = FP_TO_INT32_OVERFLOW;
2382     }
2383
2384     set_float_exception_flags(0, &env->active_fpu.fp_status);
2385     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2386     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2387     if (excph & (float_flag_overflow | float_flag_invalid)) {
2388         wth2 = FP_TO_INT32_OVERFLOW;
2389     }
2390
2391     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2392     update_fcr31(env, GETPC());
2393
2394     return ((uint64_t)wth2 << 32) | wt2;
2395 }
2396
2397 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2398 {
2399     uint32_t fst2;
2400
2401     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2402     update_fcr31(env, GETPC());
2403     return fst2;
2404 }
2405
2406 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2407 {
2408     uint32_t fst2;
2409
2410     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2411     update_fcr31(env, GETPC());
2412     return fst2;
2413 }
2414
2415 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2416 {
2417     uint32_t fst2;
2418
2419     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2420     update_fcr31(env, GETPC());
2421     return fst2;
2422 }
2423
2424 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2425 {
2426     uint32_t wt2;
2427
2428     wt2 = wt0;
2429     update_fcr31(env, GETPC());
2430     return wt2;
2431 }
2432
2433 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2434 {
2435     uint32_t wt2;
2436
2437     wt2 = wth0;
2438     update_fcr31(env, GETPC());
2439     return wt2;
2440 }
2441
2442 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2443 {
2444     uint32_t wt2;
2445
2446     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2447     update_fcr31(env, GETPC());
2448     if (get_float_exception_flags(&env->active_fpu.fp_status)
2449         & (float_flag_invalid | float_flag_overflow)) {
2450         wt2 = FP_TO_INT32_OVERFLOW;
2451     }
2452     return wt2;
2453 }
2454
2455 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2456 {
2457     uint32_t wt2;
2458
2459     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2460     if (get_float_exception_flags(&env->active_fpu.fp_status)
2461         & (float_flag_invalid | float_flag_overflow)) {
2462         wt2 = FP_TO_INT32_OVERFLOW;
2463     }
2464     update_fcr31(env, GETPC());
2465     return wt2;
2466 }
2467
2468 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2469 {
2470     uint64_t dt2;
2471
2472     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2473     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2474     RESTORE_ROUNDING_MODE;
2475     if (get_float_exception_flags(&env->active_fpu.fp_status)
2476         & (float_flag_invalid | float_flag_overflow)) {
2477         dt2 = FP_TO_INT64_OVERFLOW;
2478     }
2479     update_fcr31(env, GETPC());
2480     return dt2;
2481 }
2482
2483 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2484 {
2485     uint64_t dt2;
2486
2487     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2488     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2489     RESTORE_ROUNDING_MODE;
2490     if (get_float_exception_flags(&env->active_fpu.fp_status)
2491         & (float_flag_invalid | float_flag_overflow)) {
2492         dt2 = FP_TO_INT64_OVERFLOW;
2493     }
2494     update_fcr31(env, GETPC());
2495     return dt2;
2496 }
2497
2498 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2499 {
2500     uint32_t wt2;
2501
2502     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2503     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2504     RESTORE_ROUNDING_MODE;
2505     if (get_float_exception_flags(&env->active_fpu.fp_status)
2506         & (float_flag_invalid | float_flag_overflow)) {
2507         wt2 = FP_TO_INT32_OVERFLOW;
2508     }
2509     update_fcr31(env, GETPC());
2510     return wt2;
2511 }
2512
2513 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2514 {
2515     uint32_t wt2;
2516
2517     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2518     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2519     RESTORE_ROUNDING_MODE;
2520     if (get_float_exception_flags(&env->active_fpu.fp_status)
2521         & (float_flag_invalid | float_flag_overflow)) {
2522         wt2 = FP_TO_INT32_OVERFLOW;
2523     }
2524     update_fcr31(env, GETPC());
2525     return wt2;
2526 }
2527
2528 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2529 {
2530     uint64_t dt2;
2531
2532     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2533     if (get_float_exception_flags(&env->active_fpu.fp_status)
2534         & (float_flag_invalid | float_flag_overflow)) {
2535         dt2 = FP_TO_INT64_OVERFLOW;
2536     }
2537     update_fcr31(env, GETPC());
2538     return dt2;
2539 }
2540
2541 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2542 {
2543     uint64_t dt2;
2544
2545     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2546     if (get_float_exception_flags(&env->active_fpu.fp_status)
2547         & (float_flag_invalid | float_flag_overflow)) {
2548         dt2 = FP_TO_INT64_OVERFLOW;
2549     }
2550     update_fcr31(env, GETPC());
2551     return dt2;
2552 }
2553
2554 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2555 {
2556     uint32_t wt2;
2557
2558     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2559     if (get_float_exception_flags(&env->active_fpu.fp_status)
2560         & (float_flag_invalid | float_flag_overflow)) {
2561         wt2 = FP_TO_INT32_OVERFLOW;
2562     }
2563     update_fcr31(env, GETPC());
2564     return wt2;
2565 }
2566
2567 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2568 {
2569     uint32_t wt2;
2570
2571     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2572     if (get_float_exception_flags(&env->active_fpu.fp_status)
2573         & (float_flag_invalid | float_flag_overflow)) {
2574         wt2 = FP_TO_INT32_OVERFLOW;
2575     }
2576     update_fcr31(env, GETPC());
2577     return wt2;
2578 }
2579
2580 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2581 {
2582     uint64_t dt2;
2583
2584     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2585     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2586     RESTORE_ROUNDING_MODE;
2587     if (get_float_exception_flags(&env->active_fpu.fp_status)
2588         & (float_flag_invalid | float_flag_overflow)) {
2589         dt2 = FP_TO_INT64_OVERFLOW;
2590     }
2591     update_fcr31(env, GETPC());
2592     return dt2;
2593 }
2594
2595 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2596 {
2597     uint64_t dt2;
2598
2599     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2600     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2601     RESTORE_ROUNDING_MODE;
2602     if (get_float_exception_flags(&env->active_fpu.fp_status)
2603         & (float_flag_invalid | float_flag_overflow)) {
2604         dt2 = FP_TO_INT64_OVERFLOW;
2605     }
2606     update_fcr31(env, GETPC());
2607     return dt2;
2608 }
2609
2610 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2611 {
2612     uint32_t wt2;
2613
2614     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2615     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2616     RESTORE_ROUNDING_MODE;
2617     if (get_float_exception_flags(&env->active_fpu.fp_status)
2618         & (float_flag_invalid | float_flag_overflow)) {
2619         wt2 = FP_TO_INT32_OVERFLOW;
2620     }
2621     update_fcr31(env, GETPC());
2622     return wt2;
2623 }
2624
2625 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2626 {
2627     uint32_t wt2;
2628
2629     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2630     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2631     RESTORE_ROUNDING_MODE;
2632     if (get_float_exception_flags(&env->active_fpu.fp_status)
2633         & (float_flag_invalid | float_flag_overflow)) {
2634         wt2 = FP_TO_INT32_OVERFLOW;
2635     }
2636     update_fcr31(env, GETPC());
2637     return wt2;
2638 }
2639
2640 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2641 {
2642     uint64_t dt2;
2643
2644     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2645     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2646     RESTORE_ROUNDING_MODE;
2647     if (get_float_exception_flags(&env->active_fpu.fp_status)
2648         & (float_flag_invalid | float_flag_overflow)) {
2649         dt2 = FP_TO_INT64_OVERFLOW;
2650     }
2651     update_fcr31(env, GETPC());
2652     return dt2;
2653 }
2654
2655 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2656 {
2657     uint64_t dt2;
2658
2659     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2660     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2661     RESTORE_ROUNDING_MODE;
2662     if (get_float_exception_flags(&env->active_fpu.fp_status)
2663         & (float_flag_invalid | float_flag_overflow)) {
2664         dt2 = FP_TO_INT64_OVERFLOW;
2665     }
2666     update_fcr31(env, GETPC());
2667     return dt2;
2668 }
2669
2670 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2671 {
2672     uint32_t wt2;
2673
2674     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2675     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2676     RESTORE_ROUNDING_MODE;
2677     if (get_float_exception_flags(&env->active_fpu.fp_status)
2678         & (float_flag_invalid | float_flag_overflow)) {
2679         wt2 = FP_TO_INT32_OVERFLOW;
2680     }
2681     update_fcr31(env, GETPC());
2682     return wt2;
2683 }
2684
2685 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2686 {
2687     uint32_t wt2;
2688
2689     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2690     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2691     RESTORE_ROUNDING_MODE;
2692     if (get_float_exception_flags(&env->active_fpu.fp_status)
2693         & (float_flag_invalid | float_flag_overflow)) {
2694         wt2 = FP_TO_INT32_OVERFLOW;
2695     }
2696     update_fcr31(env, GETPC());
2697     return wt2;
2698 }
2699
2700 /* unary operations, not modifying fp status  */
2701 #define FLOAT_UNOP(name)                                       \
2702 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2703 {                                                              \
2704     return float64_ ## name(fdt0);                             \
2705 }                                                              \
2706 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2707 {                                                              \
2708     return float32_ ## name(fst0);                             \
2709 }                                                              \
2710 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2711 {                                                              \
2712     uint32_t wt0;                                              \
2713     uint32_t wth0;                                             \
2714                                                                \
2715     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2716     wth0 = float32_ ## name(fdt0 >> 32);                       \
2717     return ((uint64_t)wth0 << 32) | wt0;                       \
2718 }
2719 FLOAT_UNOP(abs)
2720 FLOAT_UNOP(chs)
2721 #undef FLOAT_UNOP
2722
2723 /* MIPS specific unary operations */
2724 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2725 {
2726     uint64_t fdt2;
2727
2728     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2729     update_fcr31(env, GETPC());
2730     return fdt2;
2731 }
2732
2733 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2734 {
2735     uint32_t fst2;
2736
2737     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2738     update_fcr31(env, GETPC());
2739     return fst2;
2740 }
2741
2742 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2743 {
2744     uint64_t fdt2;
2745
2746     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2747     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2748     update_fcr31(env, GETPC());
2749     return fdt2;
2750 }
2751
2752 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2753 {
2754     uint32_t fst2;
2755
2756     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2757     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2758     update_fcr31(env, GETPC());
2759     return fst2;
2760 }
2761
2762 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2763 {
2764     uint64_t fdt2;
2765
2766     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2767     update_fcr31(env, GETPC());
2768     return fdt2;
2769 }
2770
2771 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2772 {
2773     uint32_t fst2;
2774
2775     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2776     update_fcr31(env, GETPC());
2777     return fst2;
2778 }
2779
2780 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2781 {
2782     uint32_t fst2;
2783     uint32_t fsth2;
2784
2785     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2786     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2787     update_fcr31(env, GETPC());
2788     return ((uint64_t)fsth2 << 32) | fst2;
2789 }
2790
2791 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2792 {
2793     uint64_t fdt2;
2794
2795     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2796     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2797     update_fcr31(env, GETPC());
2798     return fdt2;
2799 }
2800
2801 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2802 {
2803     uint32_t fst2;
2804
2805     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2806     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2807     update_fcr31(env, GETPC());
2808     return fst2;
2809 }
2810
2811 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2812 {
2813     uint32_t fst2;
2814     uint32_t fsth2;
2815
2816     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2817     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2818     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2819     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2820     update_fcr31(env, GETPC());
2821     return ((uint64_t)fsth2 << 32) | fst2;
2822 }
2823
2824 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2825
2826 /* binary operations */
2827 #define FLOAT_BINOP(name)                                          \
2828 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
2829                                      uint64_t fdt0, uint64_t fdt1) \
2830 {                                                                  \
2831     uint64_t dt2;                                                  \
2832                                                                    \
2833     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
2834     update_fcr31(env, GETPC());                                    \
2835     return dt2;                                                    \
2836 }                                                                  \
2837                                                                    \
2838 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
2839                                      uint32_t fst0, uint32_t fst1) \
2840 {                                                                  \
2841     uint32_t wt2;                                                  \
2842                                                                    \
2843     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2844     update_fcr31(env, GETPC());                                    \
2845     return wt2;                                                    \
2846 }                                                                  \
2847                                                                    \
2848 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
2849                                       uint64_t fdt0,               \
2850                                       uint64_t fdt1)               \
2851 {                                                                  \
2852     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
2853     uint32_t fsth0 = fdt0 >> 32;                                   \
2854     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
2855     uint32_t fsth1 = fdt1 >> 32;                                   \
2856     uint32_t wt2;                                                  \
2857     uint32_t wth2;                                                 \
2858                                                                    \
2859     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
2860     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
2861     update_fcr31(env, GETPC());                                    \
2862     return ((uint64_t)wth2 << 32) | wt2;                           \
2863 }
2864
2865 FLOAT_BINOP(add)
2866 FLOAT_BINOP(sub)
2867 FLOAT_BINOP(mul)
2868 FLOAT_BINOP(div)
2869 #undef FLOAT_BINOP
2870
2871 /* FMA based operations */
2872 #define FLOAT_FMA(name, type)                                        \
2873 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
2874                                      uint64_t fdt0, uint64_t fdt1,   \
2875                                      uint64_t fdt2)                  \
2876 {                                                                    \
2877     fdt0 = float64_muladd(fdt0, fdt1, fdt2, type,                    \
2878                          &env->active_fpu.fp_status);                \
2879     update_fcr31(env, GETPC());                                      \
2880     return fdt0;                                                     \
2881 }                                                                    \
2882                                                                      \
2883 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
2884                                      uint32_t fst0, uint32_t fst1,   \
2885                                      uint32_t fst2)                  \
2886 {                                                                    \
2887     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2888                          &env->active_fpu.fp_status);                \
2889     update_fcr31(env, GETPC());                                      \
2890     return fst0;                                                     \
2891 }                                                                    \
2892                                                                      \
2893 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
2894                                       uint64_t fdt0, uint64_t fdt1,  \
2895                                       uint64_t fdt2)                 \
2896 {                                                                    \
2897     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
2898     uint32_t fsth0 = fdt0 >> 32;                                     \
2899     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
2900     uint32_t fsth1 = fdt1 >> 32;                                     \
2901     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
2902     uint32_t fsth2 = fdt2 >> 32;                                     \
2903                                                                      \
2904     fst0 = float32_muladd(fst0, fst1, fst2, type,                    \
2905                           &env->active_fpu.fp_status);               \
2906     fsth0 = float32_muladd(fsth0, fsth1, fsth2, type,                \
2907                            &env->active_fpu.fp_status);              \
2908     update_fcr31(env, GETPC());                                      \
2909     return ((uint64_t)fsth0 << 32) | fst0;                           \
2910 }
2911 FLOAT_FMA(madd, 0)
2912 FLOAT_FMA(msub, float_muladd_negate_c)
2913 FLOAT_FMA(nmadd, float_muladd_negate_result)
2914 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2915 #undef FLOAT_FMA
2916
2917 /* MIPS specific binary operations */
2918 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2919 {
2920     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2921     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2922     update_fcr31(env, GETPC());
2923     return fdt2;
2924 }
2925
2926 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2927 {
2928     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2929     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2930     update_fcr31(env, GETPC());
2931     return fst2;
2932 }
2933
2934 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2935 {
2936     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2937     uint32_t fsth0 = fdt0 >> 32;
2938     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2939     uint32_t fsth2 = fdt2 >> 32;
2940
2941     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2942     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2943     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
2944     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
2945     update_fcr31(env, GETPC());
2946     return ((uint64_t)fsth2 << 32) | fst2;
2947 }
2948
2949 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2950 {
2951     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2952     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
2953     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2954     update_fcr31(env, GETPC());
2955     return fdt2;
2956 }
2957
2958 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2959 {
2960     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2961     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2962     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2963     update_fcr31(env, GETPC());
2964     return fst2;
2965 }
2966
2967 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2968 {
2969     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2970     uint32_t fsth0 = fdt0 >> 32;
2971     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2972     uint32_t fsth2 = fdt2 >> 32;
2973
2974     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2975     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2976     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
2977     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
2978     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2979     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2980     update_fcr31(env, GETPC());
2981     return ((uint64_t)fsth2 << 32) | fst2;
2982 }
2983
2984 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
2985 {
2986     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2987     uint32_t fsth0 = fdt0 >> 32;
2988     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2989     uint32_t fsth1 = fdt1 >> 32;
2990     uint32_t fst2;
2991     uint32_t fsth2;
2992
2993     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2994     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2995     update_fcr31(env, GETPC());
2996     return ((uint64_t)fsth2 << 32) | fst2;
2997 }
2998
2999 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3000 {
3001     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3002     uint32_t fsth0 = fdt0 >> 32;
3003     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3004     uint32_t fsth1 = fdt1 >> 32;
3005     uint32_t fst2;
3006     uint32_t fsth2;
3007
3008     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3009     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3010     update_fcr31(env, GETPC());
3011     return ((uint64_t)fsth2 << 32) | fst2;
3012 }
3013
3014 /* compare operations */
3015 #define FOP_COND_D(op, cond)                                   \
3016 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3017                          uint64_t fdt1, int cc)                \
3018 {                                                              \
3019     int c;                                                     \
3020     c = cond;                                                  \
3021     update_fcr31(env, GETPC());                                \
3022     if (c)                                                     \
3023         SET_FP_COND(cc, env->active_fpu);                      \
3024     else                                                       \
3025         CLEAR_FP_COND(cc, env->active_fpu);                    \
3026 }                                                              \
3027 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3028                             uint64_t fdt1, int cc)             \
3029 {                                                              \
3030     int c;                                                     \
3031     fdt0 = float64_abs(fdt0);                                  \
3032     fdt1 = float64_abs(fdt1);                                  \
3033     c = cond;                                                  \
3034     update_fcr31(env, GETPC());                                \
3035     if (c)                                                     \
3036         SET_FP_COND(cc, env->active_fpu);                      \
3037     else                                                       \
3038         CLEAR_FP_COND(cc, env->active_fpu);                    \
3039 }
3040
3041 /* NOTE: the comma operator will make "cond" to eval to false,
3042  * but float64_unordered_quiet() is still called. */
3043 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3044 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3045 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3046 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3047 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3048 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3049 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3050 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3051 /* NOTE: the comma operator will make "cond" to eval to false,
3052  * but float64_unordered() is still called. */
3053 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3054 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3055 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3056 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3057 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3058 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3059 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3060 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3061
3062 #define FOP_COND_S(op, cond)                                   \
3063 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3064                          uint32_t fst1, int cc)                \
3065 {                                                              \
3066     int c;                                                     \
3067     c = cond;                                                  \
3068     update_fcr31(env, GETPC());                                \
3069     if (c)                                                     \
3070         SET_FP_COND(cc, env->active_fpu);                      \
3071     else                                                       \
3072         CLEAR_FP_COND(cc, env->active_fpu);                    \
3073 }                                                              \
3074 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3075                             uint32_t fst1, int cc)             \
3076 {                                                              \
3077     int c;                                                     \
3078     fst0 = float32_abs(fst0);                                  \
3079     fst1 = float32_abs(fst1);                                  \
3080     c = cond;                                                  \
3081     update_fcr31(env, GETPC());                                \
3082     if (c)                                                     \
3083         SET_FP_COND(cc, env->active_fpu);                      \
3084     else                                                       \
3085         CLEAR_FP_COND(cc, env->active_fpu);                    \
3086 }
3087
3088 /* NOTE: the comma operator will make "cond" to eval to false,
3089  * but float32_unordered_quiet() is still called. */
3090 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3091 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3092 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3093 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3094 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3095 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3096 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3097 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3098 /* NOTE: the comma operator will make "cond" to eval to false,
3099  * but float32_unordered() is still called. */
3100 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3101 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3102 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3103 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3104 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3105 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3106 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3107 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3108
3109 #define FOP_COND_PS(op, condl, condh)                           \
3110 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3111                           uint64_t fdt1, int cc)                \
3112 {                                                               \
3113     uint32_t fst0, fsth0, fst1, fsth1;                          \
3114     int ch, cl;                                                 \
3115     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3116     fsth0 = fdt0 >> 32;                                         \
3117     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3118     fsth1 = fdt1 >> 32;                                         \
3119     cl = condl;                                                 \
3120     ch = condh;                                                 \
3121     update_fcr31(env, GETPC());                                 \
3122     if (cl)                                                     \
3123         SET_FP_COND(cc, env->active_fpu);                       \
3124     else                                                        \
3125         CLEAR_FP_COND(cc, env->active_fpu);                     \
3126     if (ch)                                                     \
3127         SET_FP_COND(cc + 1, env->active_fpu);                   \
3128     else                                                        \
3129         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3130 }                                                               \
3131 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3132                              uint64_t fdt1, int cc)             \
3133 {                                                               \
3134     uint32_t fst0, fsth0, fst1, fsth1;                          \
3135     int ch, cl;                                                 \
3136     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3137     fsth0 = float32_abs(fdt0 >> 32);                            \
3138     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3139     fsth1 = float32_abs(fdt1 >> 32);                            \
3140     cl = condl;                                                 \
3141     ch = condh;                                                 \
3142     update_fcr31(env, GETPC());                                 \
3143     if (cl)                                                     \
3144         SET_FP_COND(cc, env->active_fpu);                       \
3145     else                                                        \
3146         CLEAR_FP_COND(cc, env->active_fpu);                     \
3147     if (ch)                                                     \
3148         SET_FP_COND(cc + 1, env->active_fpu);                   \
3149     else                                                        \
3150         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3151 }
3152
3153 /* NOTE: the comma operator will make "cond" to eval to false,
3154  * but float32_unordered_quiet() is still called. */
3155 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3156                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3157 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3158                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3159 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3160                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3161 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3162                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3163 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3164                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3165 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3166                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3167 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3168                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3169 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3170                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3171 /* NOTE: the comma operator will make "cond" to eval to false,
3172  * but float32_unordered() is still called. */
3173 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3174                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3175 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3176                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3177 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3178                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3179 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3180                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3181 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3182                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3183 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3184                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3185 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3186                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3187 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3188                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))