target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "exec.h"
  21
  22 #define MIPS_DEBUG_DISAS
  23
  24 #define GETPC() (__builtin_return_address(0))
  25
  26 /*****************************************************************************/
  27 /* Exceptions processing helpers */
  28 void cpu_loop_exit(void)
  29 {
  30     longjmp(env->jmp_env, 1);
  31 }
  32
  33 void do_raise_exception_err (uint32_t exception, int error_code)
  34 {
  35 #if 1
  36     if (logfile && exception < 0x100)
  37         fprintf(logfile, "%s: %d %d\n", __func__, exception, error_code);
  38 #endif
  39     env->exception_index = exception;
  40     env->error_code = error_code;
  41     T0 = 0;
  42     cpu_loop_exit();
  43 }
  44
  45 void do_raise_exception (uint32_t exception)
  46 {
  47     do_raise_exception_err(exception, 0);
  48 }
  49
  50 void do_restore_state (void *pc_ptr)
  51 {
  52   TranslationBlock *tb;
  53   unsigned long pc = (unsigned long) pc_ptr;
  54
  55   tb = tb_find_pc (pc);
  56   cpu_restore_state (tb, env, pc, NULL);
  57 }
  58
  59 void do_raise_exception_direct_err (uint32_t exception, int error_code)
  60 {
  61     do_restore_state (GETPC ());
  62     do_raise_exception_err (exception, error_code);
  63 }
  64
  65 void do_raise_exception_direct (uint32_t exception)
  66 {
  67     do_raise_exception_direct_err (exception, 0);
  68 }
  69
  70 #define MEMSUFFIX _raw
  71 #include "op_helper_mem.c"
  72 #undef MEMSUFFIX
  73 #if !defined(CONFIG_USER_ONLY)
  74 #define MEMSUFFIX _user
  75 #include "op_helper_mem.c"
  76 #undef MEMSUFFIX
  77 #define MEMSUFFIX _kernel
  78 #include "op_helper_mem.c"
  79 #undef MEMSUFFIX
  80 #endif
  81
  82 #ifdef MIPS_HAS_MIPS64
  83 #if TARGET_LONG_BITS > HOST_LONG_BITS
  84 /* Those might call libgcc functions.  */
  85 void do_dsll (void)
  86 {
  87     T0 = T0 << T1;
  88 }
  89
  90 void do_dsll32 (void)
  91 {
  92     T0 = T0 << (T1 + 32);
  93 }
  94
  95 void do_dsra (void)
  96 {
  97     T0 = (int64_t)T0 >> T1;
  98 }
  99
 100 void do_dsra32 (void)
 101 {
 102     T0 = (int64_t)T0 >> (T1 + 32);
 103 }
 104
 105 void do_dsrl (void)
 106 {
 107     T0 = T0 >> T1;
 108 }
 109
 110 void do_dsrl32 (void)
 111 {
 112     T0 = T0 >> (T1 + 32);
 113 }
 114
 115 void do_drotr (void)
 116 {
 117     target_ulong tmp;
 118
 119     if (T1) {
 120        tmp = T0 << (0x40 - T1);
 121        T0 = (T0 >> T1) | tmp;
 122     } else
 123        T0 = T1;
 124 }
 125
 126 void do_drotr32 (void)
 127 {
 128     target_ulong tmp;
 129
 130     if (T1) {
 131        tmp = T0 << (0x40 - (32 + T1));
 132        T0 = (T0 >> (32 + T1)) | tmp;
 133     } else
 134        T0 = T1;
 135 }
 136
 137 void do_dsllv (void)
 138 {
 139     T0 = T1 << (T0 & 0x3F);
 140 }
 141
 142 void do_dsrav (void)
 143 {
 144     T0 = (int64_t)T1 >> (T0 & 0x3F);
 145 }
 146
 147 void do_dsrlv (void)
 148 {
 149     T0 = T1 >> (T0 & 0x3F);
 150 }
 151
 152 void do_drotrv (void)
 153 {
 154     target_ulong tmp;
 155
 156     T0 &= 0x3F;
 157     if (T0) {
 158        tmp = T1 << (0x40 - T0);
 159        T0 = (T1 >> T0) | tmp;
 160     } else
 161        T0 = T1;
 162 }
 163 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 164 #endif /* MIPS_HAS_MIPS64 */
 165
 166 /* 64 bits arithmetic for 32 bits hosts */
 167 #if TARGET_LONG_BITS > HOST_LONG_BITS
 168 static inline uint64_t get_HILO (void)
 169 {
 170     return (env->HI << 32) | (uint32_t)env->LO;
 171 }
 172
 173 static inline void set_HILO (uint64_t HILO)
 174 {
 175     env->LO = (int32_t)HILO;
 176     env->HI = (int32_t)(HILO >> 32);
 177 }
 178
 179 void do_mult (void)
 180 {
 181     set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 182 }
 183
 184 void do_multu (void)
 185 {
 186     set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 187 }
 188
 189 void do_madd (void)
 190 {
 191     int64_t tmp;
 192
 193     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 194     set_HILO((int64_t)get_HILO() + tmp);
 195 }
 196
 197 void do_maddu (void)
 198 {
 199     uint64_t tmp;
 200
 201     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 202     set_HILO(get_HILO() + tmp);
 203 }
 204
 205 void do_msub (void)
 206 {
 207     int64_t tmp;
 208
 209     tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
 210     set_HILO((int64_t)get_HILO() - tmp);
 211 }
 212
 213 void do_msubu (void)
 214 {
 215     uint64_t tmp;
 216
 217     tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
 218     set_HILO(get_HILO() - tmp);
 219 }
 220 #endif
 221
 222 #ifdef MIPS_HAS_MIPS64
 223 void do_dmult (void)
 224 {
 225     /* XXX */
 226     set_HILO((int64_t)T0 * (int64_t)T1);
 227 }
 228
 229 void do_dmultu (void)
 230 {
 231     /* XXX */
 232     set_HILO((uint64_t)T0 * (uint64_t)T1);
 233 }
 234
 235 void do_ddiv (void)
 236 {
 237     if (T1 != 0) {
 238         env->LO = (int64_t)T0 / (int64_t)T1;
 239         env->HI = (int64_t)T0 % (int64_t)T1;
 240     }
 241 }
 242
 243 void do_ddivu (void)
 244 {
 245     if (T1 != 0) {
 246         env->LO = T0 / T1;
 247         env->HI = T0 % T1;
 248     }
 249 }
 250 #endif
 251
 252 #if defined(CONFIG_USER_ONLY)
 253 void do_mfc0_random (void)
 254 {
 255     cpu_abort(env, "mfc0 random\n");
 256 }
 257
 258 void do_mfc0_count (void)
 259 {
 260     cpu_abort(env, "mfc0 count\n");
 261 }
 262
 263 void cpu_mips_store_count(CPUState *env, uint32_t value)
 264 {
 265     cpu_abort(env, "mtc0 count\n");
 266 }
 267
 268 void cpu_mips_store_compare(CPUState *env, uint32_t value)
 269 {
 270     cpu_abort(env, "mtc0 compare\n");
 271 }
 272
 273 void cpu_mips_update_irq(CPUState *env)
 274 {
 275     cpu_abort(env, "mtc0 status / mtc0 cause\n");
 276 }
 277
 278 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 279 {
 280     cpu_abort(env, "mtc0 status debug\n");
 281 }
 282
 283 void do_mtc0_status_irqraise_debug (void)
 284 {
 285     cpu_abort(env, "mtc0 status irqraise debug\n");
 286 }
 287
 288 void do_tlbwi (void)
 289 {
 290     cpu_abort(env, "tlbwi\n");
 291 }
 292
 293 void do_tlbwr (void)
 294 {
 295     cpu_abort(env, "tlbwr\n");
 296 }
 297
 298 void do_tlbp (void)
 299 {
 300     cpu_abort(env, "tlbp\n");
 301 }
 302
 303 void do_tlbr (void)
 304 {
 305     cpu_abort(env, "tlbr\n");
 306 }
 307
 308 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 309 {
 310     cpu_abort(env, "mips_tlb_flush\n");
 311 }
 312
 313 #else
 314
 315 /* CP0 helpers */
 316 void do_mfc0_random (void)
 317 {
 318     T0 = (int32_t)cpu_mips_get_random(env);
 319 }
 320
 321 void do_mfc0_count (void)
 322 {
 323     T0 = (int32_t)cpu_mips_get_count(env);
 324 }
 325
 326 void do_mtc0_status_debug(uint32_t old, uint32_t val)
 327 {
 328     const uint32_t mask = 0x0000FF00;
 329     fprintf(logfile, "Status %08x => %08x Cause %08x (%08x %08x %08x)\n",
 330             old, val, env->CP0_Cause, old & mask, val & mask,
 331             env->CP0_Cause & mask);
 332 }
 333
 334 void do_mtc0_status_irqraise_debug(void)
 335 {
 336     fprintf(logfile, "Raise pending IRQs\n");
 337 }
 338
 339 #include "softfloat.h"
 340
 341 void fpu_handle_exception(void)
 342 {
 343 #ifdef CONFIG_SOFTFLOAT
 344     int flags = get_float_exception_flags(&env->fp_status);
 345     unsigned int cpuflags = 0, enable, cause = 0;
 346
 347     enable = GET_FP_ENABLE(env->fcr31);
 348
 349     /* determine current flags */
 350     if (flags & float_flag_invalid) {
 351         cpuflags |= FP_INVALID;
 352         cause |= FP_INVALID & enable;
 353     }
 354     if (flags & float_flag_divbyzero) {
 355         cpuflags |= FP_DIV0;
 356         cause |= FP_DIV0 & enable;
 357     }
 358     if (flags & float_flag_overflow) {
 359         cpuflags |= FP_OVERFLOW;
 360         cause |= FP_OVERFLOW & enable;
 361     }
 362     if (flags & float_flag_underflow) {
 363         cpuflags |= FP_UNDERFLOW;
 364         cause |= FP_UNDERFLOW & enable;
 365     }
 366     if (flags & float_flag_inexact) {
 367         cpuflags |= FP_INEXACT;
 368         cause |= FP_INEXACT & enable;
 369     }
 370     SET_FP_FLAGS(env->fcr31, cpuflags);
 371     SET_FP_CAUSE(env->fcr31, cause);
 372 #else
 373     SET_FP_FLAGS(env->fcr31, 0);
 374     SET_FP_CAUSE(env->fcr31, 0);
 375 #endif
 376 }
 377
 378 /* TLB management */
 379 #if defined(MIPS_USES_R4K_TLB)
 380 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 381 {
 382     /* Flush qemu's TLB and discard all shadowed entries.  */
 383     tlb_flush (env, flush_global);
 384     env->tlb_in_use = MIPS_TLB_NB;
 385 }
 386
 387 static void mips_tlb_flush_extra (CPUState *env, int first)
 388 {
 389     /* Discard entries from env->tlb[first] onwards.  */
 390     while (env->tlb_in_use > first) {
 391         invalidate_tlb(env, --env->tlb_in_use, 0);
 392     }
 393 }
 394
 395 static void fill_tlb (int idx)
 396 {
 397     tlb_t *tlb;
 398
 399     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
 400     tlb = &env->tlb[idx];
 401     tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
 402     tlb->ASID = env->CP0_EntryHi & 0xFF;
 403     tlb->PageMask = env->CP0_PageMask;
 404     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
 405     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
 406     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
 407     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
 408     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
 409     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
 410     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
 411     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
 412     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
 413 }
 414
 415 void do_tlbwi (void)
 416 {
 417     /* Discard cached TLB entries.  We could avoid doing this if the
 418        tlbwi is just upgrading access permissions on the current entry;
 419        that might be a further win.  */
 420     mips_tlb_flush_extra (env, MIPS_TLB_NB);
 421
 422     /* Wildly undefined effects for CP0_Index containing a too high value and
 423        MIPS_TLB_NB not being a power of two.  But so does real silicon.  */
 424     invalidate_tlb(env, env->CP0_Index & (MIPS_TLB_NB - 1), 0);
 425     fill_tlb(env->CP0_Index & (MIPS_TLB_NB - 1));
 426 }
 427
 428 void do_tlbwr (void)
 429 {
 430     int r = cpu_mips_get_random(env);
 431
 432     invalidate_tlb(env, r, 1);
 433     fill_tlb(r);
 434 }
 435
 436 void do_tlbp (void)
 437 {
 438     tlb_t *tlb;
 439     target_ulong tag;
 440     uint8_t ASID;
 441     int i;
 442
 443     tag = env->CP0_EntryHi & (int32_t)0xFFFFE000;
 444     ASID = env->CP0_EntryHi & 0xFF;
 445     for (i = 0; i < MIPS_TLB_NB; i++) {
 446         tlb = &env->tlb[i];
 447         /* Check ASID, virtual page number & size */
 448         if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
 449             /* TLB match */
 450             env->CP0_Index = i;
 451             break;
 452         }
 453     }
 454     if (i == MIPS_TLB_NB) {
 455         /* No match.  Discard any shadow entries, if any of them match.  */
 456         for (i = MIPS_TLB_NB; i < env->tlb_in_use; i++) {
 457             tlb = &env->tlb[i];
 458
 459             /* Check ASID, virtual page number & size */
 460             if ((tlb->G == 1 || tlb->ASID == ASID) && tlb->VPN == tag) {
 461                 mips_tlb_flush_extra (env, i);
 462                 break;
 463             }
 464         }
 465
 466         env->CP0_Index |= 0x80000000;
 467     }
 468 }
 469
 470 void do_tlbr (void)
 471 {
 472     tlb_t *tlb;
 473     uint8_t ASID;
 474
 475     ASID = env->CP0_EntryHi & 0xFF;
 476     tlb = &env->tlb[env->CP0_Index & (MIPS_TLB_NB - 1)];
 477
 478     /* If this will change the current ASID, flush qemu's TLB.  */
 479     if (ASID != tlb->ASID)
 480         cpu_mips_tlb_flush (env, 1);
 481
 482     mips_tlb_flush_extra(env, MIPS_TLB_NB);
 483
 484     env->CP0_EntryHi = tlb->VPN | tlb->ASID;
 485     env->CP0_PageMask = tlb->PageMask;
 486     env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
 487                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
 488     env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
 489                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
 490 }
 491 #endif
 492
 493 #endif /* !CONFIG_USER_ONLY */
 494
 495 void dump_ldst (const unsigned char *func)
 496 {
 497     if (loglevel)
 498         fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
 499 }
 500
 501 void dump_sc (void)
 502 {
 503     if (loglevel) {
 504         fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
 505                 T1, T0, env->CP0_LLAddr);
 506     }
 507 }
 508
 509 void debug_eret (void)
 510 {
 511     if (loglevel) {
 512         fprintf(logfile, "ERET: pc " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
 513                 env->PC, env->CP0_EPC);
 514         if (env->CP0_Status & (1 << CP0St_ERL))
 515             fprintf(logfile, " ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
 516         fputs("\n", logfile);
 517     }
 518 }
 519
 520 void do_pmon (int function)
 521 {
 522     function /= 2;
 523     switch (function) {
 524     case 2: /* TODO: char inbyte(int waitflag); */
 525         if (env->gpr[4] == 0)
 526             env->gpr[2] = -1;
 527         /* Fall through */
 528     case 11: /* TODO: char inbyte (void); */
 529         env->gpr[2] = -1;
 530         break;
 531     case 3:
 532     case 12:
 533         printf("%c", (char)(env->gpr[4] & 0xFF));
 534         break;
 535     case 17:
 536         break;
 537     case 158:
 538         {
 539             unsigned char *fmt = (void *)(unsigned long)env->gpr[4];
 540             printf("%s", fmt);
 541         }
 542         break;
 543     }
 544 }
 545
 546 #if !defined(CONFIG_USER_ONLY)
 547
 548 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
 549
 550 #define MMUSUFFIX _mmu
 551 #define ALIGNED_ONLY
 552
 553 #define SHIFT 0
 554 #include "softmmu_template.h"
 555
 556 #define SHIFT 1
 557 #include "softmmu_template.h"
 558
 559 #define SHIFT 2
 560 #include "softmmu_template.h"
 561
 562 #define SHIFT 3
 563 #include "softmmu_template.h"
 564
 565 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
 566 {
 567     env->CP0_BadVAddr = addr;
 568     do_restore_state (retaddr);
 569     do_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
 570 }
 571
 572 void tlb_fill (target_ulong addr, int is_write, int is_user, void *retaddr)
 573 {
 574     TranslationBlock *tb;
 575     CPUState *saved_env;
 576     unsigned long pc;
 577     int ret;
 578
 579     /* XXX: hack to restore env in all cases, even if not called from
 580        generated code */
 581     saved_env = env;
 582     env = cpu_single_env;
 583     ret = cpu_mips_handle_mmu_fault(env, addr, is_write, is_user, 1);
 584     if (ret) {
 585         if (retaddr) {
 586             /* now we have a real cpu fault */
 587             pc = (unsigned long)retaddr;
 588             tb = tb_find_pc(pc);
 589             if (tb) {
 590                 /* the PC is inside the translated code. It means that we have
 591                    a virtual CPU fault */
 592                 cpu_restore_state(tb, env, pc, NULL);
 593             }
 594         }
 595         do_raise_exception_err(env->exception_index, env->error_code);
 596     }
 597     env = saved_env;
 598 }
 599
 600 #endif